1 #ifndef _VMC_REG_REG_H_
2 #define _VMC_REG_REG_H_
4 #define MC_TCAM_VALID_ADDRESS 0x00000000
5 #define MC_TCAM_VALID_OFFSET 0x00000000
6 #define MC_TCAM_VALID_BIT_MSB 0
7 #define MC_TCAM_VALID_BIT_LSB 0
8 #define MC_TCAM_VALID_BIT_MASK 0x00000001
9 #define MC_TCAM_VALID_BIT_GET(x) (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB)
10 #define MC_TCAM_VALID_BIT_SET(x) (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK)
12 #define MC_TCAM_MASK_ADDRESS 0x00000080
13 #define MC_TCAM_MASK_OFFSET 0x00000080
14 #define MC_TCAM_MASK_SIZE_MSB 2
15 #define MC_TCAM_MASK_SIZE_LSB 0
16 #define MC_TCAM_MASK_SIZE_MASK 0x00000007
17 #define MC_TCAM_MASK_SIZE_GET(x) (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB)
18 #define MC_TCAM_MASK_SIZE_SET(x) (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK)
20 #define MC_TCAM_COMPARE_ADDRESS 0x00000100
21 #define MC_TCAM_COMPARE_OFFSET 0x00000100
22 #define MC_TCAM_COMPARE_KEY_MSB 21
23 #define MC_TCAM_COMPARE_KEY_LSB 5
24 #define MC_TCAM_COMPARE_KEY_MASK 0x003fffe0
25 #define MC_TCAM_COMPARE_KEY_GET(x) (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB)
26 #define MC_TCAM_COMPARE_KEY_SET(x) (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK)
28 #define MC_TCAM_TARGET_ADDRESS 0x00000180
29 #define MC_TCAM_TARGET_OFFSET 0x00000180
30 #define MC_TCAM_TARGET_ADDR_MSB 21
31 #define MC_TCAM_TARGET_ADDR_LSB 5
32 #define MC_TCAM_TARGET_ADDR_MASK 0x003fffe0
33 #define MC_TCAM_TARGET_ADDR_GET(x) (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB)
34 #define MC_TCAM_TARGET_ADDR_SET(x) (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK)
36 #define ADDR_ERROR_CONTROL_ADDRESS 0x00000200
37 #define ADDR_ERROR_CONTROL_OFFSET 0x00000200
38 #define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1
39 #define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1
40 #define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002
41 #define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
42 #define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
43 #define ADDR_ERROR_CONTROL_ENABLE_MSB 0
44 #define ADDR_ERROR_CONTROL_ENABLE_LSB 0
45 #define ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001
46 #define ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB)
47 #define ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK)
49 #define ADDR_ERROR_STATUS_ADDRESS 0x00000204
50 #define ADDR_ERROR_STATUS_OFFSET 0x00000204
51 #define ADDR_ERROR_STATUS_WRITE_MSB 25
52 #define ADDR_ERROR_STATUS_WRITE_LSB 25
53 #define ADDR_ERROR_STATUS_WRITE_MASK 0x02000000
54 #define ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB)
55 #define ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK)
56 #define ADDR_ERROR_STATUS_ADDRESS_MSB 24
57 #define ADDR_ERROR_STATUS_ADDRESS_LSB 0
58 #define ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff
59 #define ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB)
60 #define ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK)
65 typedef struct vmc_reg_reg_s {
66 volatile unsigned int mc_tcam_valid[32];
67 volatile unsigned int mc_tcam_mask[32];
68 volatile unsigned int mc_tcam_compare[32];
69 volatile unsigned int mc_tcam_target[32];
70 volatile unsigned int addr_error_control;
71 volatile unsigned int addr_error_status;
74 #endif /* __ASSEMBLER__ */
76 #endif /* _VMC_REG_H_ */