1 #ifndef _MBOX_HOST_REG_REG_H_
2 #define _MBOX_HOST_REG_REG_H_
4 #define HOST_INT_STATUS_ADDRESS 0x00000400
5 #define HOST_INT_STATUS_OFFSET 0x00000400
6 #define HOST_INT_STATUS_ERROR_MSB 7
7 #define HOST_INT_STATUS_ERROR_LSB 7
8 #define HOST_INT_STATUS_ERROR_MASK 0x00000080
9 #define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
10 #define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
11 #define HOST_INT_STATUS_CPU_MSB 6
12 #define HOST_INT_STATUS_CPU_LSB 6
13 #define HOST_INT_STATUS_CPU_MASK 0x00000040
14 #define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
15 #define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
16 #define HOST_INT_STATUS_DRAGON_INT_MSB 5
17 #define HOST_INT_STATUS_DRAGON_INT_LSB 5
18 #define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020
19 #define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB)
20 #define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK)
21 #define HOST_INT_STATUS_COUNTER_MSB 4
22 #define HOST_INT_STATUS_COUNTER_LSB 4
23 #define HOST_INT_STATUS_COUNTER_MASK 0x00000010
24 #define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
25 #define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
26 #define HOST_INT_STATUS_MBOX_DATA_MSB 3
27 #define HOST_INT_STATUS_MBOX_DATA_LSB 0
28 #define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f
29 #define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
30 #define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
32 #define CPU_INT_STATUS_ADDRESS 0x00000401
33 #define CPU_INT_STATUS_OFFSET 0x00000401
34 #define CPU_INT_STATUS_BIT_MSB 7
35 #define CPU_INT_STATUS_BIT_LSB 0
36 #define CPU_INT_STATUS_BIT_MASK 0x000000ff
37 #define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
38 #define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
40 #define ERROR_INT_STATUS_ADDRESS 0x00000402
41 #define ERROR_INT_STATUS_OFFSET 0x00000402
42 #define ERROR_INT_STATUS_SPI_MSB 3
43 #define ERROR_INT_STATUS_SPI_LSB 3
44 #define ERROR_INT_STATUS_SPI_MASK 0x00000008
45 #define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
46 #define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
47 #define ERROR_INT_STATUS_WAKEUP_MSB 2
48 #define ERROR_INT_STATUS_WAKEUP_LSB 2
49 #define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
50 #define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
51 #define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
52 #define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1
53 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
54 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
55 #define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
56 #define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
57 #define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0
58 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
59 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
60 #define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
61 #define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
63 #define COUNTER_INT_STATUS_ADDRESS 0x00000403
64 #define COUNTER_INT_STATUS_OFFSET 0x00000403
65 #define COUNTER_INT_STATUS_COUNTER_MSB 7
66 #define COUNTER_INT_STATUS_COUNTER_LSB 0
67 #define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
68 #define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
69 #define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
71 #define MBOX_FRAME_ADDRESS 0x00000404
72 #define MBOX_FRAME_OFFSET 0x00000404
73 #define MBOX_FRAME_RX_EOM_MSB 7
74 #define MBOX_FRAME_RX_EOM_LSB 4
75 #define MBOX_FRAME_RX_EOM_MASK 0x000000f0
76 #define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
77 #define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
78 #define MBOX_FRAME_RX_SOM_MSB 3
79 #define MBOX_FRAME_RX_SOM_LSB 0
80 #define MBOX_FRAME_RX_SOM_MASK 0x0000000f
81 #define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
82 #define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
84 #define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
85 #define RX_LOOKAHEAD_VALID_OFFSET 0x00000405
86 #define RX_LOOKAHEAD_VALID_MBOX_MSB 3
87 #define RX_LOOKAHEAD_VALID_MBOX_LSB 0
88 #define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f
89 #define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
90 #define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
92 #define RX_LOOKAHEAD0_ADDRESS 0x00000408
93 #define RX_LOOKAHEAD0_OFFSET 0x00000408
94 #define RX_LOOKAHEAD0_DATA_MSB 7
95 #define RX_LOOKAHEAD0_DATA_LSB 0
96 #define RX_LOOKAHEAD0_DATA_MASK 0x000000ff
97 #define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
98 #define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
100 #define RX_LOOKAHEAD1_ADDRESS 0x0000040c
101 #define RX_LOOKAHEAD1_OFFSET 0x0000040c
102 #define RX_LOOKAHEAD1_DATA_MSB 7
103 #define RX_LOOKAHEAD1_DATA_LSB 0
104 #define RX_LOOKAHEAD1_DATA_MASK 0x000000ff
105 #define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
106 #define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
108 #define RX_LOOKAHEAD2_ADDRESS 0x00000410
109 #define RX_LOOKAHEAD2_OFFSET 0x00000410
110 #define RX_LOOKAHEAD2_DATA_MSB 7
111 #define RX_LOOKAHEAD2_DATA_LSB 0
112 #define RX_LOOKAHEAD2_DATA_MASK 0x000000ff
113 #define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
114 #define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
116 #define RX_LOOKAHEAD3_ADDRESS 0x00000414
117 #define RX_LOOKAHEAD3_OFFSET 0x00000414
118 #define RX_LOOKAHEAD3_DATA_MSB 7
119 #define RX_LOOKAHEAD3_DATA_LSB 0
120 #define RX_LOOKAHEAD3_DATA_MASK 0x000000ff
121 #define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
122 #define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
124 #define INT_STATUS_ENABLE_ADDRESS 0x00000418
125 #define INT_STATUS_ENABLE_OFFSET 0x00000418
126 #define INT_STATUS_ENABLE_ERROR_MSB 7
127 #define INT_STATUS_ENABLE_ERROR_LSB 7
128 #define INT_STATUS_ENABLE_ERROR_MASK 0x00000080
129 #define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
130 #define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
131 #define INT_STATUS_ENABLE_CPU_MSB 6
132 #define INT_STATUS_ENABLE_CPU_LSB 6
133 #define INT_STATUS_ENABLE_CPU_MASK 0x00000040
134 #define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
135 #define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
136 #define INT_STATUS_ENABLE_DRAGON_INT_MSB 5
137 #define INT_STATUS_ENABLE_DRAGON_INT_LSB 5
138 #define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020
139 #define INT_STATUS_ENABLE_DRAGON_INT_GET(x) (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB)
140 #define INT_STATUS_ENABLE_DRAGON_INT_SET(x) (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK)
141 #define INT_STATUS_ENABLE_COUNTER_MSB 4
142 #define INT_STATUS_ENABLE_COUNTER_LSB 4
143 #define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
144 #define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
145 #define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
146 #define INT_STATUS_ENABLE_MBOX_DATA_MSB 3
147 #define INT_STATUS_ENABLE_MBOX_DATA_LSB 0
148 #define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
149 #define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
150 #define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
152 #define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
153 #define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419
154 #define CPU_INT_STATUS_ENABLE_BIT_MSB 7
155 #define CPU_INT_STATUS_ENABLE_BIT_LSB 0
156 #define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
157 #define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
158 #define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
160 #define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
161 #define ERROR_STATUS_ENABLE_OFFSET 0x0000041a
162 #define ERROR_STATUS_ENABLE_WAKEUP_MSB 2
163 #define ERROR_STATUS_ENABLE_WAKEUP_LSB 2
164 #define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004
165 #define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
166 #define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
167 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1
168 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
169 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
170 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
171 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
172 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0
173 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
174 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
175 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
176 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
178 #define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
179 #define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b
180 #define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7
181 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
182 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
183 #define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
184 #define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
186 #define COUNT_ADDRESS 0x00000420
187 #define COUNT_OFFSET 0x00000420
188 #define COUNT_VALUE_MSB 7
189 #define COUNT_VALUE_LSB 0
190 #define COUNT_VALUE_MASK 0x000000ff
191 #define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
192 #define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
194 #define COUNT_DEC_ADDRESS 0x00000440
195 #define COUNT_DEC_OFFSET 0x00000440
196 #define COUNT_DEC_VALUE_MSB 7
197 #define COUNT_DEC_VALUE_LSB 0
198 #define COUNT_DEC_VALUE_MASK 0x000000ff
199 #define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
200 #define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
202 #define SCRATCH_ADDRESS 0x00000460
203 #define SCRATCH_OFFSET 0x00000460
204 #define SCRATCH_VALUE_MSB 7
205 #define SCRATCH_VALUE_LSB 0
206 #define SCRATCH_VALUE_MASK 0x000000ff
207 #define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
208 #define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
210 #define FIFO_TIMEOUT_ADDRESS 0x00000468
211 #define FIFO_TIMEOUT_OFFSET 0x00000468
212 #define FIFO_TIMEOUT_VALUE_MSB 7
213 #define FIFO_TIMEOUT_VALUE_LSB 0
214 #define FIFO_TIMEOUT_VALUE_MASK 0x000000ff
215 #define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
216 #define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
218 #define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469
219 #define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469
220 #define FIFO_TIMEOUT_ENABLE_SET_MSB 0
221 #define FIFO_TIMEOUT_ENABLE_SET_LSB 0
222 #define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001
223 #define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
224 #define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
226 #define DISABLE_SLEEP_ADDRESS 0x0000046a
227 #define DISABLE_SLEEP_OFFSET 0x0000046a
228 #define DISABLE_SLEEP_FOR_INT_MSB 1
229 #define DISABLE_SLEEP_FOR_INT_LSB 1
230 #define DISABLE_SLEEP_FOR_INT_MASK 0x00000002
231 #define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
232 #define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
233 #define DISABLE_SLEEP_ON_MSB 0
234 #define DISABLE_SLEEP_ON_LSB 0
235 #define DISABLE_SLEEP_ON_MASK 0x00000001
236 #define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
237 #define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
239 #define LOCAL_BUS_ADDRESS 0x00000470
240 #define LOCAL_BUS_OFFSET 0x00000470
241 #define LOCAL_BUS_STATE_MSB 1
242 #define LOCAL_BUS_STATE_LSB 0
243 #define LOCAL_BUS_STATE_MASK 0x00000003
244 #define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
245 #define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
247 #define INT_WLAN_ADDRESS 0x00000472
248 #define INT_WLAN_OFFSET 0x00000472
249 #define INT_WLAN_VECTOR_MSB 7
250 #define INT_WLAN_VECTOR_LSB 0
251 #define INT_WLAN_VECTOR_MASK 0x000000ff
252 #define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
253 #define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
255 #define WINDOW_DATA_ADDRESS 0x00000474
256 #define WINDOW_DATA_OFFSET 0x00000474
257 #define WINDOW_DATA_DATA_MSB 7
258 #define WINDOW_DATA_DATA_LSB 0
259 #define WINDOW_DATA_DATA_MASK 0x000000ff
260 #define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
261 #define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
263 #define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
264 #define WINDOW_WRITE_ADDR_OFFSET 0x00000478
265 #define WINDOW_WRITE_ADDR_ADDR_MSB 7
266 #define WINDOW_WRITE_ADDR_ADDR_LSB 0
267 #define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff
268 #define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
269 #define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
271 #define WINDOW_READ_ADDR_ADDRESS 0x0000047c
272 #define WINDOW_READ_ADDR_OFFSET 0x0000047c
273 #define WINDOW_READ_ADDR_ADDR_MSB 7
274 #define WINDOW_READ_ADDR_ADDR_LSB 0
275 #define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff
276 #define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
277 #define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
279 #define SPI_CONFIG_ADDRESS 0x00000480
280 #define SPI_CONFIG_OFFSET 0x00000480
281 #define SPI_CONFIG_SPI_RESET_MSB 4
282 #define SPI_CONFIG_SPI_RESET_LSB 4
283 #define SPI_CONFIG_SPI_RESET_MASK 0x00000010
284 #define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB)
285 #define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK)
286 #define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3
287 #define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3
288 #define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008
289 #define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB)
290 #define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK)
291 #define SPI_CONFIG_TEST_MODE_MSB 2
292 #define SPI_CONFIG_TEST_MODE_LSB 2
293 #define SPI_CONFIG_TEST_MODE_MASK 0x00000004
294 #define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB)
295 #define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK)
296 #define SPI_CONFIG_DATA_SIZE_MSB 1
297 #define SPI_CONFIG_DATA_SIZE_LSB 0
298 #define SPI_CONFIG_DATA_SIZE_MASK 0x00000003
299 #define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB)
300 #define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK)
302 #define SPI_STATUS_ADDRESS 0x00000481
303 #define SPI_STATUS_OFFSET 0x00000481
304 #define SPI_STATUS_ADDR_ERR_MSB 3
305 #define SPI_STATUS_ADDR_ERR_LSB 3
306 #define SPI_STATUS_ADDR_ERR_MASK 0x00000008
307 #define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB)
308 #define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK)
309 #define SPI_STATUS_RD_ERR_MSB 2
310 #define SPI_STATUS_RD_ERR_LSB 2
311 #define SPI_STATUS_RD_ERR_MASK 0x00000004
312 #define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB)
313 #define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK)
314 #define SPI_STATUS_WR_ERR_MSB 1
315 #define SPI_STATUS_WR_ERR_LSB 1
316 #define SPI_STATUS_WR_ERR_MASK 0x00000002
317 #define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB)
318 #define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK)
319 #define SPI_STATUS_READY_MSB 0
320 #define SPI_STATUS_READY_LSB 0
321 #define SPI_STATUS_READY_MASK 0x00000001
322 #define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB)
323 #define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK)
325 #define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482
326 #define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482
327 #define NON_ASSOC_SLEEP_EN_BIT_MSB 0
328 #define NON_ASSOC_SLEEP_EN_BIT_LSB 0
329 #define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001
330 #define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
331 #define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
333 #define CIS_WINDOW_ADDRESS 0x00000600
334 #define CIS_WINDOW_OFFSET 0x00000600
335 #define CIS_WINDOW_DATA_MSB 7
336 #define CIS_WINDOW_DATA_LSB 0
337 #define CIS_WINDOW_DATA_MASK 0x000000ff
338 #define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
339 #define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
342 #ifndef __ASSEMBLER__
344 typedef struct mbox_host_reg_reg_s {
345 unsigned char pad0[1024]; /* pad to 0x400 */
346 volatile unsigned char host_int_status;
347 volatile unsigned char cpu_int_status;
348 volatile unsigned char error_int_status;
349 volatile unsigned char counter_int_status;
350 volatile unsigned char mbox_frame;
351 volatile unsigned char rx_lookahead_valid;
352 unsigned char pad1[2]; /* pad to 0x408 */
353 volatile unsigned char rx_lookahead0[4];
354 volatile unsigned char rx_lookahead1[4];
355 volatile unsigned char rx_lookahead2[4];
356 volatile unsigned char rx_lookahead3[4];
357 volatile unsigned char int_status_enable;
358 volatile unsigned char cpu_int_status_enable;
359 volatile unsigned char error_status_enable;
360 volatile unsigned char counter_int_status_enable;
361 unsigned char pad2[4]; /* pad to 0x420 */
362 volatile unsigned char count[8];
363 unsigned char pad3[24]; /* pad to 0x440 */
364 volatile unsigned char count_dec[32];
365 volatile unsigned char scratch[8];
366 volatile unsigned char fifo_timeout;
367 volatile unsigned char fifo_timeout_enable;
368 volatile unsigned char disable_sleep;
369 unsigned char pad4[5]; /* pad to 0x470 */
370 volatile unsigned char local_bus;
371 unsigned char pad5[1]; /* pad to 0x472 */
372 volatile unsigned char int_wlan;
373 unsigned char pad6[1]; /* pad to 0x474 */
374 volatile unsigned char window_data[4];
375 volatile unsigned char window_write_addr[4];
376 volatile unsigned char window_read_addr[4];
377 volatile unsigned char spi_config;
378 volatile unsigned char spi_status;
379 volatile unsigned char non_assoc_sleep_en;
380 unsigned char pad7[381]; /* pad to 0x600 */
381 volatile unsigned char cis_window[512];
382 } mbox_host_reg_reg_t;
384 #endif /* __ASSEMBLER__ */
386 #endif /* _MBOX_HOST_REG_H_ */
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