6 /* Transmission Managment Registers */
7 #define AGNX_TXM_BASE 0x0000
8 #define AGNX_TXM_CTL 0x0000 /* control register */
9 #define AGNX_TXM_ETMF 0x0004 /* enable transmission management functions */
10 #define AGNX_TXM_TXTEMP 0x0008 /* transmission template */
11 #define AGNX_TXM_RETRYSTAID 0x000c /* Retry Station ID */
12 #define AGNX_TXM_TIMESTAMPLO 0x0010 /* Timestamp Lo */
13 #define AGNX_TXM_TIMESTAMPHI 0x0014 /* Timestamp Hi */
14 #define AGNX_TXM_TXDELAY 0x0018 /* tx delay */
15 #define AGNX_TXM_TBTTLO 0x0020 /* tbtt Lo */
16 #define AGNX_TXM_TBTTHI 0x0024 /* tbtt Hi */
17 #define AGNX_TXM_BEAINTER 0x0028 /* Beacon Interval */
18 #define AGNX_TXM_NAV 0x0030 /* NAV */
19 #define AGNX_TXM_CFPMDV 0x0034 /* CFP MDV */
20 #define AGNX_TXM_CFPERCNT 0x0038 /* CFP period count */
21 #define AGNX_TXM_PROBDELAY 0x003c /* probe delay */
22 #define AGNX_TXM_LISINTERCNT 0x0040 /* listen interval count */
23 #define AGNX_TXM_DTIMPERICNT 0x004c /* DTIM period count */
25 #define AGNX_TXM_BEACON_CTL 0x005c /* beacon control */
27 #define AGNX_TXM_SCHEMPCNT 0x007c /* schedule empty count */
28 #define AGNX_TXM_MAXTIMOUT 0x0084 /* max timeout exceed count */
29 #define AGNX_TXM_MAXCFPTIM 0x0088 /* max CF poll timeout count */
30 #define AGNX_TXM_MAXRXTIME 0x008c /* max RX timeout count */
31 #define AGNX_TXM_MAXACKTIM 0x0090 /* max ACK timeout count */
32 #define AGNX_TXM_DIF01 0x00a0 /* DIF 0-1 */
33 #define AGNX_TXM_DIF23 0x00a4 /* DIF 2-3 */
34 #define AGNX_TXM_DIF45 0x00a8 /* DIF 4-5 */
35 #define AGNX_TXM_DIF67 0x00ac /* DIF 6-7 */
36 #define AGNX_TXM_SIFSPIFS 0x00b0 /* SIFS/PIFS */
37 #define AGNX_TXM_TIFSEIFS 0x00b4 /* TIFS/EIFS */
38 #define AGNX_TXM_MAXCCACNTSLOT 0x00b8 /* max CCA count slot */
39 #define AGNX_TXM_SLOTLIMIT 0x00bc /* slot limit/1 msec limit */
40 #define AGNX_TXM_CFPOLLRXTIM 0x00f0 /* CF poll RX timeout count */
41 #define AGNX_TXM_CFACKT11B 0x00f4 /* CF ack timeout limit for 11b */
42 #define AGNX_TXM_CW0 0x0100 /* CW 0 */
43 #define AGNX_TXM_SLBEALIM0 0x0108 /* short/long beacon limit 0 */
44 #define AGNX_TXM_CW1 0x0120 /* CW 1 */
45 #define AGNX_TXM_SLBEALIM1 0x0128 /* short/long beacon limit 1 */
46 #define AGNX_TXM_CW2 0x0140 /* CW 2 */
47 #define AGNX_TXM_SLBEALIM2 0x0148 /* short/long beacon limit 2 */
48 #define AGNX_TXM_CW3 0x0160 /* CW 3 */
49 #define AGNX_TXM_SLBEALIM3 0x0168 /* short/long beacon limit 3 */
50 #define AGNX_TXM_CW4 0x0180 /* CW 4 */
51 #define AGNX_TXM_SLBEALIM4 0x0188 /* short/long beacon limit 4 */
52 #define AGNX_TXM_CW5 0x01a0 /* CW 5 */
53 #define AGNX_TXM_SLBEALIM5 0x01a8 /* short/long beacon limit 5 */
54 #define AGNX_TXM_CW6 0x01c0 /* CW 6 */
55 #define AGNX_TXM_SLBEALIM6 0x01c8 /* short/long beacon limit 6 */
56 #define AGNX_TXM_CW7 0x01e0 /* CW 7 */
57 #define AGNX_TXM_SLBEALIM7 0x01e8 /* short/long beacon limit 7 */
58 #define AGNX_TXM_BEACONTEMP 0x1000 /* beacon template */
59 #define AGNX_TXM_STAPOWTEMP 0x1a00 /* Station Power Template */
61 /* Receive Management Control Registers */
62 #define AGNX_RXM_BASE 0x2000
63 #define AGNX_RXM_REQRATE 0x2000 /* requested rate */
64 #define AGNX_RXM_MACHI 0x2004 /* first 4 bytes of mac address */
65 #define AGNX_RXM_MACLO 0x2008 /* last 2 bytes of mac address */
66 #define AGNX_RXM_BSSIDHI 0x200c /* bssid hi */
67 #define AGNX_RXM_BSSIDLO 0x2010 /* bssid lo */
68 #define AGNX_RXM_HASH_CMD_FLAG 0x2014 /* Flags for the RX Hash Command Default:0 */
69 #define AGNX_RXM_HASH_CMD_HIGH 0x2018 /* The High half of the Hash Command */
70 #define AGNX_RXM_HASH_CMD_LOW 0x201c /* The Low half of the Hash Command */
71 #define AGNX_RXM_ROUTAB 0x2020 /* routing table */
72 #define ROUTAB_SUBTYPE_SHIFT 24
73 #define ROUTAB_TYPE_SHIFT 28
74 #define ROUTAB_STATUS_SHIFT 30
75 #define ROUTAB_RW_SHIFT 31
76 #define ROUTAB_ROUTE_DROP 0xf00000 /* Drop */
77 #define ROUTAB_ROUTE_CPU 0x400000 /* CPU */
78 #define ROUTAB_ROUTE_ENCRY 0x500800 /* Encryption */
79 #define ROUTAB_ROUTE_RFP 0x800000 /* RFP */
81 #define ROUTAB_TYPE_MANAG 0x0 /* Management */
82 #define ROUTAB_TYPE_CTL 0x1 /* Control */
83 #define ROUTAB_TYPE_DATA 0x2 /* Data */
85 #define ROUTAB_SUBTYPE_DATA 0x0
86 #define ROUTAB_SUBTYPE_DATAACK 0x1
87 #define ROUTAB_SUBTYPE_DATAPOLL 0x2
88 #define ROUTAB_SUBTYPE_DATAPOLLACK 0x3
89 #define ROUTAB_SUBTYPE_NULL 0x4 /* NULL */
90 #define ROUTAB_SUBTYPE_NULLACK 0x5
91 #define ROUTAB_SUBTYPE_NULLPOLL 0x6
92 #define ROUTAB_SUBTYPE_NULLPOLLACK 0x7
93 #define ROUTAB_SUBTYPE_QOSDATA 0x8 /* QOS DATA */
94 #define ROUTAB_SUBTYPE_QOSDATAACK 0x9
95 #define ROUTAB_SUBTYPE_QOSDATAPOLL 0xa
96 #define ROUTAB_SUBTYPE_QOSDATAACKPOLL 0xb
97 #define ROUTAB_SUBTYPE_QOSNULL 0xc
98 #define ROUTAB_SUBTYPE_QOSNULLACK 0xd
99 #define ROUTAB_SUBTYPE_QOSNULLPOLL 0xe
100 #define ROUTAB_SUBTYPE_QOSNULLPOLLACK 0xf
101 #define AGNX_RXM_DELAY11 0x2024 /* delay 11(AB) */
102 #define AGNX_RXM_SOF_CNT 0x2028 /* SOF Count */
103 #define AGNX_RXM_FRAG_CNT 0x202c /* Fragment Count*/
104 #define AGNX_RXM_FCS_CNT 0x2030 /* FCS Count */
105 #define AGNX_RXM_BSSID_MISS_CNT 0x2034 /* BSSID Miss Count */
106 #define AGNX_RXM_PDU_ERR_CNT 0x2038 /* PDU Error Count */
107 #define AGNX_RXM_DEST_MISS_CNT 0x203C /* Destination Miss Count */
108 #define AGNX_RXM_DROP_CNT 0x2040 /* Drop Count */
109 #define AGNX_RXM_ABORT_CNT 0x2044 /* Abort Count */
110 #define AGNX_RXM_RELAY_CNT 0x2048 /* Relay Count */
111 #define AGNX_RXM_HASH_MISS_CNT 0x204c /* Hash Miss Count */
112 #define AGNX_RXM_SA_HI 0x2050 /* Address of received packet Hi */
113 #define AGNX_RXM_SA_LO 0x2054 /* Address of received packet Lo */
114 #define AGNX_RXM_HASH_DUMP_LST 0x2100 /* Contains Hash Data */
115 #define AGNX_RXM_HASH_DUMP_MST 0x2104 /* Contains Hash Data */
116 #define AGNX_RXM_HASH_DUMP_DATA 0x2108 /* The Station ID to dump */
119 /* Encryption Managment */
120 #define AGNX_ENCRY_BASE 0x2400
121 #define AGNX_ENCRY_WEPKEY0 0x2440 /* wep key #0 */
122 #define AGNX_ENCRY_WEPKEY1 0x2444 /* wep key #1 */
123 #define AGNX_ENCRY_WEPKEY2 0x2448 /* wep key #2 */
124 #define AGNX_ENCRY_WEPKEY3 0x244c /* wep key #3 */
125 #define AGNX_ENCRY_CCMRECTL 0x2460 /* ccm replay control */
128 /* Band Management Registers */
129 #define AGNX_BM_BASE 0x2c00
130 #define AGNX_BM_BMCTL 0x2c00 /* band management control */
131 #define AGNX_BM_TXWADDR 0x2c18 /* tx workqueue address start */
132 #define AGNX_BM_TXTOPEER 0x2c24 /* transmit to peers */
133 #define AGNX_BM_FPLHP 0x2c2c /* free pool list head pointer */
134 #define AGNX_BM_FPLTP 0x2c30 /* free pool list tail pointer */
135 #define AGNX_BM_FPCNT 0x2c34 /* free pool count */
136 #define AGNX_BM_CIPDUWCNT 0x2c38 /* card interface pdu workqueue count */
137 #define AGNX_BM_SPPDUWCNT 0x2c3c /* sp pdu workqueue count */
138 #define AGNX_BM_RFPPDUWCNT 0x2c40 /* rfp pdu workqueue count */
139 #define AGNX_BM_RHPPDUWCNT 0x2c44 /* rhp pdu workqueue count */
140 #define AGNX_BM_CIWQCTL 0x2c48 /* Card Interface WorkQueue Control */
141 #define AGNX_BM_CPUTXWCTL 0x2c50 /* cpu tx workqueue control */
142 #define AGNX_BM_CPURXWCTL 0x2c58 /* cpu rx workqueue control */
143 #define AGNX_BM_CPULWCTL 0x2c60 /* cpu low workqueue control */
144 #define AGNX_BM_CPUHWCTL 0x2c68 /* cpu high workqueue control */
145 #define AGNX_BM_SPTXWCTL 0x2c70 /* sp tx workqueue control */
146 #define AGNX_BM_SPRXWCTL 0x2c78 /* sp rx workqueue control */
147 #define AGNX_BM_RFPWCTL 0x2c80 /* RFP workqueue control */
148 #define AGNX_BM_MTSM 0x2c90 /* Multicast Transmit Station Mask */
150 /* Card Interface Registers (32bits) */
151 #define AGNX_CIR_BASE 0x3000
152 #define AGNX_CIR_BLKCTL 0x3000 /* block control*/
153 #define AGNX_STAT_TX 0x1
154 #define AGNX_STAT_RX 0x2
155 #define AGNX_STAT_X 0x4
156 /* Below two interrupt flags will be set by our but not CPU or the card */
157 #define AGNX_STAT_TXD 0x10
158 #define AGNX_STAT_TXM 0x20
160 #define AGNX_CIR_ADDRWIN 0x3004 /* Addressable Windows*/
161 #define AGNX_CIR_ENDIAN 0x3008 /* card endianness */
162 #define AGNX_CIR_SERIALITF 0x3020 /* serial interface */
163 #define AGNX_CIR_RXCFG 0x3040 /* receive config */
164 #define ENABLE_RX_INTERRUPT 0x20
165 #define RX_CACHE_LINE 0x8
166 /* the RX fragment length */
167 #define FRAG_LEN_256 0x0 /* 256B */
168 #define FRAG_LEN_512 0x1
169 #define FRAG_LEN_1024 0x2
170 #define FRAG_LEN_2048 0x3
172 #define AGNX_CIR_RXCTL 0x3050 /* receive control */
173 /* memory address, chipside */
174 #define AGNX_CIR_RXCMSTART 0x3054 /* receive client memory start */
175 #define AGNX_CIR_RXCMEND 0x3058 /* receive client memory end */
176 /* memory address, pci */
177 #define AGNX_CIR_RXHOSTADDR 0x3060 /* receive hostside address */
178 /* memory address, chipside */
179 #define AGNX_CIR_RXCLIADDR 0x3064 /* receive clientside address */
180 #define AGNX_CIR_RXDMACTL 0x3068 /* receive dma control */
181 #define AGNX_CIR_TXCFG 0x3080 /* transmit config */
182 #define AGNX_CIR_TXMCTL 0x3090 /* Transmit Management Control */
183 #define ENABLE_TX_INTERRUPT 0x20
184 #define TX_CACHE_LINE 0x8
185 #define AGNX_CIR_TXMSTART 0x3094 /* Transmit Management Start */
186 #define AGNX_CIR_TXMEND 0x3098 /* Transmit Management End */
187 #define AGNX_CIR_TXDCTL 0x30a0 /* transmit data control */
188 /* memeory address, chipset */
189 #define AGNX_CIR_TXDSTART 0x30a4 /* transmit data start */
190 #define AGNX_CIR_TXDEND 0x30a8 /* transmit data end */
191 #define AGNX_CIR_TXMHADDR 0x30b0 /* Transmit Management Hostside Address */
192 #define AGNX_CIR_TXMCADDR 0x30b4 /* Transmit Management Clientside Address */
193 #define AGNX_CIR_TXDMACTL 0x30b8 /* transmit dma control */
196 /* Power Managment Unit */
197 #define AGNX_PM_BASE 0x3c00
198 #define AGNX_PM_PMCTL 0x3c00 /* PM Control*/
199 #define AGNX_PM_MACMSW 0x3c08 /* MAC Manual Slow Work Enable */
200 #define AGNX_PM_RFCTL 0x3c0c /* RF Control */
201 #define AGNX_PM_PHYMW 0x3c14 /* Phy Mannal Work */
202 #define AGNX_PM_SOFTRST 0x3c18 /* PMU Soft Reset */
203 #define AGNX_PM_PLLCTL 0x3c1c /* PMU PLL control*/
204 #define AGNX_PM_TESTPHY 0x3c24 /* PMU Test Phy */
207 /* Interrupt Control interface */
208 #define AGNX_INT_BASE 0x4000
209 #define AGNX_INT_STAT 0x4000 /* interrupt status */
210 #define AGNX_INT_MASK 0x400c /* interrupt mask */
212 #define IRQ_TX_BEACON 0x1 /* TX Beacon */
213 #define IRQ_TX_RETRY 0x8 /* TX Retry Interrupt */
214 #define IRQ_TX_ACTIVITY 0x10 /* TX Activity */
215 #define IRQ_RX_ACTIVITY 0x20 /* RX Activity */
216 /* FIXME I guess that instead RX a none exist staion's packet or
217 the station hasn't been init */
218 #define IRQ_RX_X 0x40
219 #define IRQ_RX_Y 0x80 /* RX ? */
220 #define IRQ_RX_HASHHIT 0x100 /* RX Hash Hit */
221 #define IRQ_RX_FRAME 0x200 /* RX Frame */
222 #define IRQ_ERR_INT 0x400 /* Error Interrupt */
223 #define IRQ_TX_QUE_FULL 0x800 /* TX Workqueue Full */
224 #define IRQ_BANDMAN_ERR 0x10000 /* Bandwidth Management Error */
225 #define IRQ_TX_DISABLE 0x20000 /* TX Disable */
226 #define IRQ_RX_IVASESKEY 0x80000 /* RX Invalid Session Key */
227 #define IRQ_RX_KEYIDMIS 0x100000 /* RX key ID Mismatch */
228 #define IRQ_REP_THHIT 0x200000 /* Replay Threshold Hit */
229 #define IRQ_TIMER1 0x4000000 /* Timer1 */
230 #define IRQ_TIMER_CNT 0x10000000 /* Timer Count */
231 #define IRQ_PHY_FASTINT 0x20000000 /* Phy Fast Interrupt */
232 #define IRQ_PHY_SLOWINT 0x40000000 /* Phy Slow Interrupt */
233 #define IRQ_OTHER 0x80000000 /* Unknow interrupt */
234 #define AGNX_IRQ_ALL 0xffffffff
236 /* System Interface */
237 #define AGNX_SYSITF_BASE 0x4400
238 #define AGNX_SYSITF_SYSMODE 0x4400 /* system mode */
239 #define AGNX_SYSITF_GPIOIN 0x4410 /* GPIO In */
240 /* PIN lines for leds? */
241 #define AGNX_SYSITF_GPIOUT 0x4414 /* GPIO Out */
244 #define AGNX_TIMCTL_TIMER1 0x4800 /* Timer 1 */
245 #define AGNX_TIMCTL_TIM1CTL 0x4808 /* Timer 1 Control */
248 /* Antenna Calibration Interface */
249 #define AGNX_ACI_BASE 0x5000
250 #define AGNX_ACI_MODE 0x5000 /* Mode */
251 #define AGNX_ACI_MEASURE 0x5004 /* Measure */
252 #define AGNX_ACI_SELCHAIN 0x5008 /* Select Chain */
253 #define AGNX_ACI_LEN 0x500c /* Length */
254 #define AGNX_ACI_TIMER1 0x5018 /* Timer 1 */
255 #define AGNX_ACI_TIMER2 0x501c /* Timer 2 */
256 #define AGNX_ACI_OFFSET 0x5020 /* Offset */
257 #define AGNX_ACI_STATUS 0x5030 /* Status */
258 #define CALI_IDLE 0x0
259 #define CALI_DONE 0x1
260 #define CALI_BUSY 0x2
262 #define AGNX_ACI_AICCHA0OVE 0x5034 /* AIC Channel 0 Override */
263 #define AGNX_ACI_AICCHA1OVE 0x5038 /* AIC Channel 1 Override */
265 /* Gain Control Registers */
266 #define AGNX_GCR_BASE 0x9000
267 /* threshold of primary antenna */
268 #define AGNX_GCR_THD0A 0x9000 /* threshold? D0 A */
269 /* low threshold of primary antenna */
270 #define AGNX_GCR_THD0AL 0x9004 /* threshold? D0 A low */
271 /* threshold of secondary antenna */
272 #define AGNX_GCR_THD0B 0x9008 /* threshold? D0_B */
273 #define AGNX_GCR_DUNSAT 0x900c /* d unsaturated */
274 #define AGNX_GCR_DSAT 0x9010 /* d saturated */
275 #define AGNX_GCR_DFIRCAL 0x9014 /* D Fir/Cal */
276 #define AGNX_GCR_DGCTL11A 0x9018 /* d gain control 11a */
277 #define AGNX_GCR_DGCTL11B 0x901c /* d gain control 11b */
278 /* strength of gain */
279 #define AGNX_GCR_GAININIT 0x9020 /* gain initialization */
280 #define AGNX_GCR_THNOSIG 0x9024 /* threhold no signal */
281 #define AGNX_GCR_COARSTEP 0x9028 /* coarse stepping */
282 #define AGNX_GCR_SIFST11A 0x902c /* sifx time 11a */
283 #define AGNX_GCR_SIFST11B 0x9030 /* sifx time 11b */
284 #define AGNX_GCR_CWDETEC 0x9034 /* cw detection */
285 #define AGNX_GCR_0X38 0x9038 /* ???? */
286 #define AGNX_GCR_BOACT 0x903c /* BO Active */
287 #define AGNX_GCR_BOINACT 0x9040 /* BO Inactive */
288 #define AGNX_GCR_BODYNA 0x9044 /* BO dynamic */
289 /* 802.11 mode(a,b,g) */
290 #define AGNX_GCR_DISCOVMOD 0x9048 /* discovery mode */
291 #define AGNX_GCR_NLISTANT 0x904c /* number of listening antenna */
292 #define AGNX_GCR_NACTIANT 0x9050 /* number of active antenna */
293 #define AGNX_GCR_NMEASANT 0x9054 /* number of measuring antenna */
294 #define AGNX_GCR_NCAPTANT 0x9058 /* number of capture antenna */
295 #define AGNX_GCR_THCAP11A 0x905c /* threshold capture 11a */
296 #define AGNX_GCR_THCAP11B 0x9060 /* threshold capture 11b */
297 #define AGNX_GCR_THCAPRX11A 0x9064 /* threshold capture rx 11a */
298 #define AGNX_GCR_THCAPRX11B 0x9068 /* threshold capture rx 11b */
299 #define AGNX_GCR_THLEVDRO 0x906c /* threshold level drop */
300 #define AGNX_GCR_GAINSET0 0x9070 /* Gainset 0 */
301 #define AGNX_GCR_GAINSET1 0x9074 /* Gainset 1 */
302 #define AGNX_GCR_GAINSET2 0x9078 /* Gainset 2 */
303 #define AGNX_GCR_MAXRXTIME11A 0x907c /* maximum rx time 11a */
304 #define AGNX_GCR_MAXRXTIME11B 0x9080 /* maximum rx time 11b */
305 #define AGNX_GCR_CORRTIME 0x9084 /* correction time */
306 /* reset the subsystem, 0 = disable, 1 = enable */
307 #define AGNX_GCR_RSTGCTL 0x9088 /* reset gain control */
308 /* channel receiving */
309 #define AGNX_GCR_RXCHANEL 0x908c /* receive channel */
310 #define AGNX_GCR_NOISE0 0x9090 /* Noise 0 */
311 #define AGNX_GCR_NOISE1 0x9094 /* Noise 1 */
312 #define AGNX_GCR_NOISE2 0x9098 /* Noise 2 */
313 #define AGNX_GCR_SIGHTH 0x909c /* Signal High Threshold */
314 #define AGNX_GCR_SIGLTH 0x90a0 /* Signal Low Threshold */
315 #define AGNX_GCR_CORRDROP 0x90a4 /* correction drop */
316 /* threshold of tertiay antenna */
317 #define AGNX_GCR_THCD 0x90a8 /* threshold? CD */
318 #define AGNX_GCR_THCS 0x90ac /* threshold? CS */
319 #define AGNX_GCR_MAXPOWDIFF 0x90b8 /* maximum power difference */
320 #define AGNX_GCR_TRACNT4 0x90ec /* Transition Count 4 */
321 #define AGNX_GCR_TRACNT5 0x90f0 /* transition count 5 */
322 #define AGNX_GCR_TRACNT6 0x90f4 /* transition count 6 */
323 #define AGNX_GCR_TRACNT7 0x90f8 /* transition coutn 7 */
324 #define AGNX_GCR_TESTBUS 0x911c /* test bus */
325 #define AGNX_GCR_CHAINNUM 0x9120 /* Number of Chains */
326 #define AGNX_GCR_ANTCFG 0x9124 /* Antenna Config */
327 #define AGNX_GCR_THJUMP 0x912c /* threhold jump */
328 #define AGNX_GCR_THPOWER 0x9130 /* threshold power */
329 #define AGNX_GCR_THPOWCLIP 0x9134 /* threshold power clip*/
330 #define AGNX_GCR_FORCECTLCLK 0x9138 /* Force Gain Control Clock */
331 #define AGNX_GCR_GAINSETWRITE 0x913c /* Gainset Write */
332 #define AGNX_GCR_THD0BTFEST 0x9140 /* threshold d0 b tf estimate */
333 #define AGNX_GCR_THRX11BPOWMIN 0x9144 /* threshold rx 11b power minimum */
334 #define AGNX_GCR_0X14c 0x914c /* ?? */
335 #define AGNX_GCR_0X150 0x9150 /* ?? */
336 #define AGNX_GCR_RXOVERIDE 0x9194 /* recieve override */
337 #define AGNX_GCR_WATCHDOG 0x91b0 /* watchdog timeout */
341 #define AGNX_SPI_BASE 0xdc00
342 #define AGNX_SPI_CFG 0xdc00 /* spi configuration */
343 /* Only accept 16 bits */
344 #define AGNX_SPI_WMSW 0xdc04 /* write most significant word */
345 /* Only accept 16 bits */
346 #define AGNX_SPI_WLSW 0xdc08 /* write least significant word */
347 #define AGNX_SPI_CTL 0xdc0c /* spi control */
348 #define AGNX_SPI_RMSW 0xdc10 /* read most significant word */
349 #define AGNX_SPI_RLSW 0xdc14 /* read least significant word */
350 /* SPI Control Mask */
351 #define SPI_READ_CTL 0x4000 /* read control */
352 #define SPI_BUSY_CTL 0x8000 /* busy control */
353 /* RF and synth chips in spi */
354 #define RF_CHIP0 0x400
355 #define RF_CHIP1 0x800
356 #define RF_CHIP2 0x1000
357 #define SYNTH_CHIP 0x2000
359 /* Unknown register */
360 #define AGNX_UNKNOWN_BASE 0x7800
362 /* FIXME MonitorGain */
363 #define AGNX_MONGCR_BASE 0x12000
366 #define AGNX_GAIN_TABLE 0x12400
368 /* The initial FIR coefficient table */
369 #define AGNX_FIR_BASE 0x19804
371 #define AGNX_ENGINE_LOOKUP_TBL 0x800
373 /* eeprom commands */
374 #define EEPROM_CMD_NULL 0x0 /* NULL */
375 #define EEPROM_CMD_WRITE 0x2 /* write */
376 #define EEPROM_CMD_READ 0x3 /* read */
377 #define EEPROM_CMD_STATUSREAD 0x5 /* status register read */
378 #define EEPROM_CMD_WRITEENABLE 0x6 /* write enable */
379 #define EEPROM_CMD_CONFIGURE 0x7 /* configure */
381 #define EEPROM_DATAFORCOFIGURE 0x6 /* ??? */
384 #define EEPROM_ADDR_SUBVID 0x0 /* Sub Vendor ID */
385 #define EEPROM_ADDR_SUBSID 0x2 /* Sub System ID */
386 #define EEPROM_ADDR_MACADDR 0x146 /* MAC Address */
387 #define EEPROM_ADDR_LOTYPE 0x14f /* LO type */
391 u16 address; /* address in EEPROM */
392 u8 cmd; /* command, unknown, status */
393 } __attribute__((__packed__));
395 #define AGNX_EEPROM_COMMAND_SHIFT 5
396 #define AGNX_EEPROM_COMMAND_STAT 0x01
398 void disable_receiver(struct agnx_priv *priv);
399 void enable_receiver(struct agnx_priv *priv);
400 u8 read_from_eeprom(struct agnx_priv *priv, u16 address);
401 void agnx_hw_init(struct agnx_priv *priv);
402 int agnx_hw_reset(struct agnx_priv *priv);
403 int agnx_set_ssid(struct agnx_priv *priv, u8 *ssid, size_t ssid_len);
404 void agnx_set_bssid(struct agnx_priv *priv, const u8 *bssid);
405 void enable_power_saving(struct agnx_priv *priv);
406 void disable_power_saving(struct agnx_priv *priv);
407 void calibrate_antenna_period(unsigned long data);
409 #endif /* AGNX_PHY_H_ */
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