drivers/spi/spi_mpc8xxx.c

   1 /*
   2  * MPC8xxx SPI controller driver.
   3  *
   4  * Maintainer: Kumar Gala
   5  *
   6  * Copyright (C) 2006 Polycom, Inc.
   7  *
   8  * CPM SPI and QE buffer descriptors mode support:
   9  * Copyright (c) 2009  MontaVista Software, Inc.
  10  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17 #include <linux/module.h>
  18 #include <linux/init.h>
  19 #include <linux/types.h>
  20 #include <linux/kernel.h>
  21 #include <linux/bug.h>
  22 #include <linux/errno.h>
  23 #include <linux/err.h>
  24 #include <linux/io.h>
  25 #include <linux/completion.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/delay.h>
  28 #include <linux/irq.h>
  29 #include <linux/device.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/spi/spi_bitbang.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/fsl_devices.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/mm.h>
  36 #include <linux/mutex.h>
  37 #include <linux/of.h>
  38 #include <linux/of_platform.h>
  39 #include <linux/gpio.h>
  40 #include <linux/of_gpio.h>
  41 #include <linux/of_spi.h>
  42
  43 #include <sysdev/fsl_soc.h>
  44 #include <asm/cpm.h>
  45 #include <asm/qe.h>
  46 #include <asm/irq.h>
  47
  48 /* CPM1 and CPM2 are mutually exclusive. */
  49 #ifdef CONFIG_CPM1
  50 #include <asm/cpm1.h>
  51 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0)
  52 #else
  53 #include <asm/cpm2.h>
  54 #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0)
  55 #endif
  56
  57 /* SPI Controller registers */
  58 struct mpc8xxx_spi_reg {
  59         u8 res1[0x20];
  60         __be32 mode;
  61         __be32 event;
  62         __be32 mask;
  63         __be32 command;
  64         __be32 transmit;
  65         __be32 receive;
  66 };
  67
  68 /* SPI Parameter RAM */
  69 struct spi_pram {
  70         __be16  rbase;  /* Rx Buffer descriptor base address */
  71         __be16  tbase;  /* Tx Buffer descriptor base address */
  72         u8      rfcr;   /* Rx function code */
  73         u8      tfcr;   /* Tx function code */
  74         __be16  mrblr;  /* Max receive buffer length */
  75         __be32  rstate; /* Internal */
  76         __be32  rdp;    /* Internal */
  77         __be16  rbptr;  /* Internal */
  78         __be16  rbc;    /* Internal */
  79         __be32  rxtmp;  /* Internal */
  80         __be32  tstate; /* Internal */
  81         __be32  tdp;    /* Internal */
  82         __be16  tbptr;  /* Internal */
  83         __be16  tbc;    /* Internal */
  84         __be32  txtmp;  /* Internal */
  85         __be32  res;    /* Tx temp. */
  86         __be16  rpbase; /* Relocation pointer (CPM1 only) */
  87         __be16  res1;   /* Reserved */
  88 };
  89
  90 /* SPI Controller mode register definitions */
  91 #define SPMODE_LOOP             (1 << 30)
  92 #define SPMODE_CI_INACTIVEHIGH  (1 << 29)
  93 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
  94 #define SPMODE_DIV16            (1 << 27)
  95 #define SPMODE_REV              (1 << 26)
  96 #define SPMODE_MS               (1 << 25)
  97 #define SPMODE_ENABLE           (1 << 24)
  98 #define SPMODE_LEN(x)           ((x) << 20)
  99 #define SPMODE_PM(x)            ((x) << 16)
 100 #define SPMODE_OP               (1 << 14)
 101 #define SPMODE_CG(x)            ((x) << 7)
 102
 103 /*
 104  * Default for SPI Mode:
 105  *      SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
 106  */
 107 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
 108                          SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
 109
 110 /* SPIE register values */
 111 #define SPIE_NE         0x00000200      /* Not empty */
 112 #define SPIE_NF         0x00000100      /* Not full */
 113
 114 /* SPIM register values */
 115 #define SPIM_NE         0x00000200      /* Not empty */
 116 #define SPIM_NF         0x00000100      /* Not full */
 117
 118 #define SPIE_TXB        0x00000200      /* Last char is written to tx fifo */
 119 #define SPIE_RXB        0x00000100      /* Last char is written to rx buf */
 120
 121 /* SPCOM register values */
 122 #define SPCOM_STR       (1 << 23)       /* Start transmit */
 123
 124 #define SPI_PRAM_SIZE   0x100
 125 #define SPI_MRBLR       ((unsigned int)PAGE_SIZE)
 126
 127 /* SPI Controller driver's private data. */
 128 struct mpc8xxx_spi {
 129         struct device *dev;
 130         struct mpc8xxx_spi_reg __iomem *base;
 131
 132         /* rx & tx bufs from the spi_transfer */
 133         const void *tx;
 134         void *rx;
 135
 136         int subblock;
 137         struct spi_pram __iomem *pram;
 138         struct cpm_buf_desc __iomem *tx_bd;
 139         struct cpm_buf_desc __iomem *rx_bd;
 140
 141         struct spi_transfer *xfer_in_progress;
 142
 143         /* dma addresses for CPM transfers */
 144         dma_addr_t tx_dma;
 145         dma_addr_t rx_dma;
 146         bool map_tx_dma;
 147         bool map_rx_dma;
 148
 149         dma_addr_t dma_dummy_tx;
 150         dma_addr_t dma_dummy_rx;
 151
 152         /* functions to deal with different sized buffers */
 153         void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
 154         u32(*get_tx) (struct mpc8xxx_spi *);
 155
 156         unsigned int count;
 157         unsigned int irq;
 158
 159         unsigned nsecs;         /* (clock cycle time)/2 */
 160
 161         u32 spibrg;             /* SPIBRG input clock */
 162         u32 rx_shift;           /* RX data reg shift when in qe mode */
 163         u32 tx_shift;           /* TX data reg shift when in qe mode */
 164
 165         unsigned int flags;
 166 #define SPI_QE_CPU_MODE         (1 << 0) /* QE CPU ("PIO") mode */
 167 #define SPI_CPM_MODE            (1 << 1) /* CPM/QE ("DMA") mode */
 168 #define SPI_CPM1                (1 << 2) /* SPI unit is in CPM1 block */
 169 #define SPI_CPM2                (1 << 3) /* SPI unit is in CPM2 block */
 170 #define SPI_QE                  (1 << 4) /* SPI unit is in QE block */
 171
 172         struct workqueue_struct *workqueue;
 173         struct work_struct work;
 174
 175         struct list_head queue;
 176         spinlock_t lock;
 177
 178         struct completion done;
 179 };
 180
 181 static void *mpc8xxx_dummy_rx;
 182 static DEFINE_MUTEX(mpc8xxx_dummy_rx_lock);
 183 static int mpc8xxx_dummy_rx_refcnt;
 184
 185 struct spi_mpc8xxx_cs {
 186         /* functions to deal with different sized buffers */
 187         void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
 188         u32 (*get_tx) (struct mpc8xxx_spi *);
 189         u32 rx_shift;           /* RX data reg shift when in qe mode */
 190         u32 tx_shift;           /* TX data reg shift when in qe mode */
 191         u32 hw_mode;            /* Holds HW mode register settings */
 192 };
 193
 194 static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
 195 {
 196         out_be32(reg, val);
 197 }
 198
 199 static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
 200 {
 201         return in_be32(reg);
 202 }
 203
 204 #define MPC83XX_SPI_RX_BUF(type)                                          \
 205 static                                                                    \
 206 void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
 207 {                                                                         \
 208         type *rx = mpc8xxx_spi->rx;                                       \
 209         *rx++ = (type)(data >> mpc8xxx_spi->rx_shift);                    \
 210         mpc8xxx_spi->rx = rx;                                             \
 211 }
 212
 213 #define MPC83XX_SPI_TX_BUF(type)                                \
 214 static                                                          \
 215 u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi)  \
 216 {                                                               \
 217         u32 data;                                               \
 218         const type *tx = mpc8xxx_spi->tx;                       \
 219         if (!tx)                                                \
 220                 return 0;                                       \
 221         data = *tx++ << mpc8xxx_spi->tx_shift;                  \
 222         mpc8xxx_spi->tx = tx;                                   \
 223         return data;                                            \
 224 }
 225
 226 MPC83XX_SPI_RX_BUF(u8)
 227 MPC83XX_SPI_RX_BUF(u16)
 228 MPC83XX_SPI_RX_BUF(u32)
 229 MPC83XX_SPI_TX_BUF(u8)
 230 MPC83XX_SPI_TX_BUF(u16)
 231 MPC83XX_SPI_TX_BUF(u32)
 232
 233 static void mpc8xxx_spi_change_mode(struct spi_device *spi)
 234 {
 235         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
 236         struct spi_mpc8xxx_cs *cs = spi->controller_state;
 237         __be32 __iomem *mode = &mspi->base->mode;
 238         unsigned long flags;
 239
 240         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
 241                 return;
 242
 243         /* Turn off IRQs locally to minimize time that SPI is disabled. */
 244         local_irq_save(flags);
 245
 246         /* Turn off SPI unit prior changing mode */
 247         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
 248         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 249
 250         /* When in CPM mode, we need to reinit tx and rx. */
 251         if (mspi->flags & SPI_CPM_MODE) {
 252                 if (mspi->flags & SPI_QE) {
 253                         qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock,
 254                                      QE_CR_PROTOCOL_UNSPECIFIED, 0);
 255                 } else {
 256                         cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX);
 257                         if (mspi->flags & SPI_CPM1) {
 258                                 out_be16(&mspi->pram->rbptr,
 259                                          in_be16(&mspi->pram->rbase));
 260                                 out_be16(&mspi->pram->tbptr,
 261                                          in_be16(&mspi->pram->tbase));
 262                         }
 263                 }
 264         }
 265
 266         local_irq_restore(flags);
 267 }
 268
 269 static void mpc8xxx_spi_chipselect(struct spi_device *spi, int value)
 270 {
 271         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 272         struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data;
 273         bool pol = spi->mode & SPI_CS_HIGH;
 274         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 275
 276         if (value == BITBANG_CS_INACTIVE) {
 277                 if (pdata->cs_control)
 278                         pdata->cs_control(spi, !pol);
 279         }
 280
 281         if (value == BITBANG_CS_ACTIVE) {
 282                 mpc8xxx_spi->rx_shift = cs->rx_shift;
 283                 mpc8xxx_spi->tx_shift = cs->tx_shift;
 284                 mpc8xxx_spi->get_rx = cs->get_rx;
 285                 mpc8xxx_spi->get_tx = cs->get_tx;
 286
 287                 mpc8xxx_spi_change_mode(spi);
 288
 289                 if (pdata->cs_control)
 290                         pdata->cs_control(spi, pol);
 291         }
 292 }
 293
 294 static
 295 int mpc8xxx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 296 {
 297         struct mpc8xxx_spi *mpc8xxx_spi;
 298         u8 bits_per_word, pm;
 299         u32 hz;
 300         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 301
 302         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 303
 304         if (t) {
 305                 bits_per_word = t->bits_per_word;
 306                 hz = t->speed_hz;
 307         } else {
 308                 bits_per_word = 0;
 309                 hz = 0;
 310         }
 311
 312         /* spi_transfer level calls that work per-word */
 313         if (!bits_per_word)
 314                 bits_per_word = spi->bits_per_word;
 315
 316         /* Make sure its a bit width we support [4..16, 32] */
 317         if ((bits_per_word < 4)
 318             || ((bits_per_word > 16) && (bits_per_word != 32)))
 319                 return -EINVAL;
 320
 321         if (!hz)
 322                 hz = spi->max_speed_hz;
 323
 324         cs->rx_shift = 0;
 325         cs->tx_shift = 0;
 326         if (bits_per_word <= 8) {
 327                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
 328                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
 329                 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
 330                         cs->rx_shift = 16;
 331                         cs->tx_shift = 24;
 332                 }
 333         } else if (bits_per_word <= 16) {
 334                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
 335                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
 336                 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
 337                         cs->rx_shift = 16;
 338                         cs->tx_shift = 16;
 339                 }
 340         } else if (bits_per_word <= 32) {
 341                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 342                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 343         } else
 344                 return -EINVAL;
 345
 346         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE &&
 347                         spi->mode & SPI_LSB_FIRST) {
 348                 cs->tx_shift = 0;
 349                 if (bits_per_word <= 8)
 350                         cs->rx_shift = 8;
 351                 else
 352                         cs->rx_shift = 0;
 353         }
 354
 355         mpc8xxx_spi->rx_shift = cs->rx_shift;
 356         mpc8xxx_spi->tx_shift = cs->tx_shift;
 357         mpc8xxx_spi->get_rx = cs->get_rx;
 358         mpc8xxx_spi->get_tx = cs->get_tx;
 359
 360         if (bits_per_word == 32)
 361                 bits_per_word = 0;
 362         else
 363                 bits_per_word = bits_per_word - 1;
 364
 365         /* mask out bits we are going to set */
 366         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 367                                   | SPMODE_PM(0xF));
 368
 369         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 370
 371         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 372                 cs->hw_mode |= SPMODE_DIV16;
 373                 pm = mpc8xxx_spi->spibrg / (hz * 64);
 374
 375                 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
 376                           "Will use %d Hz instead.\n", dev_name(&spi->dev),
 377                           hz, mpc8xxx_spi->spibrg / 1024);
 378                 if (pm > 16)
 379                         pm = 16;
 380         } else
 381                 pm = mpc8xxx_spi->spibrg / (hz * 4);
 382         if (pm)
 383                 pm--;
 384
 385         cs->hw_mode |= SPMODE_PM(pm);
 386
 387         mpc8xxx_spi_change_mode(spi);
 388         return 0;
 389 }
 390
 391 static void mpc8xxx_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi)
 392 {
 393         struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd;
 394         struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd;
 395         unsigned int xfer_len = min(mspi->count, SPI_MRBLR);
 396         unsigned int xfer_ofs;
 397
 398         xfer_ofs = mspi->xfer_in_progress->len - mspi->count;
 399
 400         out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs);
 401         out_be16(&rx_bd->cbd_datlen, 0);
 402         out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP);
 403
 404         out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs);
 405         out_be16(&tx_bd->cbd_datlen, xfer_len);
 406         out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP |
 407                                  BD_SC_LAST);
 408
 409         /* start transfer */
 410         mpc8xxx_spi_write_reg(&mspi->base->command, SPCOM_STR);
 411 }
 412
 413 static int mpc8xxx_spi_cpm_bufs(struct mpc8xxx_spi *mspi,
 414                                 struct spi_transfer *t, bool is_dma_mapped)
 415 {
 416         struct device *dev = mspi->dev;
 417
 418         if (is_dma_mapped) {
 419                 mspi->map_tx_dma = 0;
 420                 mspi->map_rx_dma = 0;
 421         } else {
 422                 mspi->map_tx_dma = 1;
 423                 mspi->map_rx_dma = 1;
 424         }
 425
 426         if (!t->tx_buf) {
 427                 mspi->tx_dma = mspi->dma_dummy_tx;
 428                 mspi->map_tx_dma = 0;
 429         }
 430
 431         if (!t->rx_buf) {
 432                 mspi->rx_dma = mspi->dma_dummy_rx;
 433                 mspi->map_rx_dma = 0;
 434         }
 435
 436         if (mspi->map_tx_dma) {
 437                 void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */
 438
 439                 mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len,
 440                                               DMA_TO_DEVICE);
 441                 if (dma_mapping_error(dev, mspi->tx_dma)) {
 442                         dev_err(dev, "unable to map tx dma\n");
 443                         return -ENOMEM;
 444                 }
 445         } else {
 446                 mspi->tx_dma = t->tx_dma;
 447         }
 448
 449         if (mspi->map_rx_dma) {
 450                 mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len,
 451                                               DMA_FROM_DEVICE);
 452                 if (dma_mapping_error(dev, mspi->rx_dma)) {
 453                         dev_err(dev, "unable to map rx dma\n");
 454                         goto err_rx_dma;
 455                 }
 456         } else {
 457                 mspi->rx_dma = t->rx_dma;
 458         }
 459
 460         /* enable rx ints */
 461         mpc8xxx_spi_write_reg(&mspi->base->mask, SPIE_RXB);
 462
 463         mspi->xfer_in_progress = t;
 464         mspi->count = t->len;
 465
 466         /* start CPM transfers */
 467         mpc8xxx_spi_cpm_bufs_start(mspi);
 468
 469         return 0;
 470
 471 err_rx_dma:
 472         if (mspi->map_tx_dma)
 473                 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
 474         return -ENOMEM;
 475 }
 476
 477 static void mpc8xxx_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi)
 478 {
 479         struct device *dev = mspi->dev;
 480         struct spi_transfer *t = mspi->xfer_in_progress;
 481
 482         if (mspi->map_tx_dma)
 483                 dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE);
 484         if (mspi->map_tx_dma)
 485                 dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE);
 486         mspi->xfer_in_progress = NULL;
 487 }
 488
 489 static int mpc8xxx_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
 490                                 struct spi_transfer *t, unsigned int len)
 491 {
 492         u32 word;
 493
 494         mspi->count = len;
 495
 496         /* enable rx ints */
 497         mpc8xxx_spi_write_reg(&mspi->base->mask, SPIM_NE);
 498
 499         /* transmit word */
 500         word = mspi->get_tx(mspi);
 501         mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
 502
 503         return 0;
 504 }
 505
 506 static int mpc8xxx_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
 507                             bool is_dma_mapped)
 508 {
 509         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 510         unsigned int len = t->len;
 511         u8 bits_per_word;
 512         int ret;
 513
 514         bits_per_word = spi->bits_per_word;
 515         if (t->bits_per_word)
 516                 bits_per_word = t->bits_per_word;
 517
 518         if (bits_per_word > 8) {
 519                 /* invalid length? */
 520                 if (len & 1)
 521                         return -EINVAL;
 522                 len /= 2;
 523         }
 524         if (bits_per_word > 16) {
 525                 /* invalid length? */
 526                 if (len & 1)
 527                         return -EINVAL;
 528                 len /= 2;
 529         }
 530
 531         mpc8xxx_spi->tx = t->tx_buf;
 532         mpc8xxx_spi->rx = t->rx_buf;
 533
 534         INIT_COMPLETION(mpc8xxx_spi->done);
 535
 536         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 537                 ret = mpc8xxx_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
 538         else
 539                 ret = mpc8xxx_spi_cpu_bufs(mpc8xxx_spi, t, len);
 540         if (ret)
 541                 return ret;
 542
 543         wait_for_completion(&mpc8xxx_spi->done);
 544
 545         /* disable rx ints */
 546         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
 547
 548         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 549                 mpc8xxx_spi_cpm_bufs_complete(mpc8xxx_spi);
 550
 551         return mpc8xxx_spi->count;
 552 }
 553
 554 static void mpc8xxx_spi_do_one_msg(struct spi_message *m)
 555 {
 556         struct spi_device *spi = m->spi;
 557         struct spi_transfer *t;
 558         unsigned int cs_change;
 559         const int nsecs = 50;
 560         int status;
 561
 562         cs_change = 1;
 563         status = 0;
 564         list_for_each_entry(t, &m->transfers, transfer_list) {
 565                 if (t->bits_per_word || t->speed_hz) {
 566                         /* Don't allow changes if CS is active */
 567                         status = -EINVAL;
 568
 569                         if (cs_change)
 570                                 status = mpc8xxx_spi_setup_transfer(spi, t);
 571                         if (status < 0)
 572                                 break;
 573                 }
 574
 575                 if (cs_change) {
 576                         mpc8xxx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
 577                         ndelay(nsecs);
 578                 }
 579                 cs_change = t->cs_change;
 580                 if (t->len)
 581                         status = mpc8xxx_spi_bufs(spi, t, m->is_dma_mapped);
 582                 if (status) {
 583                         status = -EMSGSIZE;
 584                         break;
 585                 }
 586                 m->actual_length += t->len;
 587
 588                 if (t->delay_usecs)
 589                         udelay(t->delay_usecs);
 590
 591                 if (cs_change) {
 592                         ndelay(nsecs);
 593                         mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 594                         ndelay(nsecs);
 595                 }
 596         }
 597
 598         m->status = status;
 599         m->complete(m->context);
 600
 601         if (status || !cs_change) {
 602                 ndelay(nsecs);
 603                 mpc8xxx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 604         }
 605
 606         mpc8xxx_spi_setup_transfer(spi, NULL);
 607 }
 608
 609 static void mpc8xxx_spi_work(struct work_struct *work)
 610 {
 611         struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
 612                                                        work);
 613
 614         spin_lock_irq(&mpc8xxx_spi->lock);
 615         while (!list_empty(&mpc8xxx_spi->queue)) {
 616                 struct spi_message *m = container_of(mpc8xxx_spi->queue.next,
 617                                                    struct spi_message, queue);
 618
 619                 list_del_init(&m->queue);
 620                 spin_unlock_irq(&mpc8xxx_spi->lock);
 621
 622                 mpc8xxx_spi_do_one_msg(m);
 623
 624                 spin_lock_irq(&mpc8xxx_spi->lock);
 625         }
 626         spin_unlock_irq(&mpc8xxx_spi->lock);
 627 }
 628
 629 static int mpc8xxx_spi_setup(struct spi_device *spi)
 630 {
 631         struct mpc8xxx_spi *mpc8xxx_spi;
 632         int retval;
 633         u32 hw_mode;
 634         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 635
 636         if (!spi->max_speed_hz)
 637                 return -EINVAL;
 638
 639         if (!cs) {
 640                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 641                 if (!cs)
 642                         return -ENOMEM;
 643                 spi->controller_state = cs;
 644         }
 645         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 646
 647         hw_mode = cs->hw_mode; /* Save orginal settings */
 648         cs->hw_mode = mpc8xxx_spi_read_reg(&mpc8xxx_spi->base->mode);
 649         /* mask out bits we are going to set */
 650         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 651                          | SPMODE_REV | SPMODE_LOOP);
 652
 653         if (spi->mode & SPI_CPHA)
 654                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 655         if (spi->mode & SPI_CPOL)
 656                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 657         if (!(spi->mode & SPI_LSB_FIRST))
 658                 cs->hw_mode |= SPMODE_REV;
 659         if (spi->mode & SPI_LOOP)
 660                 cs->hw_mode |= SPMODE_LOOP;
 661
 662         retval = mpc8xxx_spi_setup_transfer(spi, NULL);
 663         if (retval < 0) {
 664                 cs->hw_mode = hw_mode; /* Restore settings */
 665                 return retval;
 666         }
 667         return 0;
 668 }
 669
 670 static void mpc8xxx_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events)
 671 {
 672         u16 len;
 673
 674         dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__,
 675                 in_be16(&mspi->rx_bd->cbd_datlen), mspi->count);
 676
 677         len = in_be16(&mspi->rx_bd->cbd_datlen);
 678         if (len > mspi->count) {
 679                 WARN_ON(1);
 680                 len = mspi->count;
 681         }
 682
 683         /* Clear the events */
 684         mpc8xxx_spi_write_reg(&mspi->base->event, events);
 685
 686         mspi->count -= len;
 687         if (mspi->count)
 688                 mpc8xxx_spi_cpm_bufs_start(mspi);
 689         else
 690                 complete(&mspi->done);
 691 }
 692
 693 static void mpc8xxx_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 694 {
 695         /* We need handle RX first */
 696         if (events & SPIE_NE) {
 697                 u32 rx_data = mpc8xxx_spi_read_reg(&mspi->base->receive);
 698
 699                 if (mspi->rx)
 700                         mspi->get_rx(rx_data, mspi);
 701         }
 702
 703         if ((events & SPIE_NF) == 0)
 704                 /* spin until TX is done */
 705                 while (((events =
 706                         mpc8xxx_spi_read_reg(&mspi->base->event)) &
 707                                                 SPIE_NF) == 0)
 708                         cpu_relax();
 709
 710         /* Clear the events */
 711         mpc8xxx_spi_write_reg(&mspi->base->event, events);
 712
 713         mspi->count -= 1;
 714         if (mspi->count) {
 715                 u32 word = mspi->get_tx(mspi);
 716
 717                 mpc8xxx_spi_write_reg(&mspi->base->transmit, word);
 718         } else {
 719                 complete(&mspi->done);
 720         }
 721 }
 722
 723 static irqreturn_t mpc8xxx_spi_irq(s32 irq, void *context_data)
 724 {
 725         struct mpc8xxx_spi *mspi = context_data;
 726         irqreturn_t ret = IRQ_NONE;
 727         u32 events;
 728
 729         /* Get interrupt events(tx/rx) */
 730         events = mpc8xxx_spi_read_reg(&mspi->base->event);
 731         if (events)
 732                 ret = IRQ_HANDLED;
 733
 734         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
 735
 736         if (mspi->flags & SPI_CPM_MODE)
 737                 mpc8xxx_spi_cpm_irq(mspi, events);
 738         else
 739                 mpc8xxx_spi_cpu_irq(mspi, events);
 740
 741         return ret;
 742 }
 743
 744 static int mpc8xxx_spi_transfer(struct spi_device *spi,
 745                                 struct spi_message *m)
 746 {
 747         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 748         unsigned long flags;
 749
 750         m->actual_length = 0;
 751         m->status = -EINPROGRESS;
 752
 753         spin_lock_irqsave(&mpc8xxx_spi->lock, flags);
 754         list_add_tail(&m->queue, &mpc8xxx_spi->queue);
 755         queue_work(mpc8xxx_spi->workqueue, &mpc8xxx_spi->work);
 756         spin_unlock_irqrestore(&mpc8xxx_spi->lock, flags);
 757
 758         return 0;
 759 }
 760
 761
 762 static void mpc8xxx_spi_cleanup(struct spi_device *spi)
 763 {
 764         kfree(spi->controller_state);
 765 }
 766
 767 static void *mpc8xxx_spi_alloc_dummy_rx(void)
 768 {
 769         mutex_lock(&mpc8xxx_dummy_rx_lock);
 770
 771         if (!mpc8xxx_dummy_rx)
 772                 mpc8xxx_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL);
 773         if (mpc8xxx_dummy_rx)
 774                 mpc8xxx_dummy_rx_refcnt++;
 775
 776         mutex_unlock(&mpc8xxx_dummy_rx_lock);
 777
 778         return mpc8xxx_dummy_rx;
 779 }
 780
 781 static void mpc8xxx_spi_free_dummy_rx(void)
 782 {
 783         mutex_lock(&mpc8xxx_dummy_rx_lock);
 784
 785         switch (mpc8xxx_dummy_rx_refcnt) {
 786         case 0:
 787                 WARN_ON(1);
 788                 break;
 789         case 1:
 790                 kfree(mpc8xxx_dummy_rx);
 791                 mpc8xxx_dummy_rx = NULL;
 792                 /* fall through */
 793         default:
 794                 mpc8xxx_dummy_rx_refcnt--;
 795                 break;
 796         }
 797
 798         mutex_unlock(&mpc8xxx_dummy_rx_lock);
 799 }
 800
 801 static unsigned long mpc8xxx_spi_cpm_get_pram(struct mpc8xxx_spi *mspi)
 802 {
 803         struct device *dev = mspi->dev;
 804         struct device_node *np = dev_archdata_get_node(&dev->archdata);
 805         const u32 *iprop;
 806         int size;
 807         unsigned long spi_base_ofs;
 808         unsigned long pram_ofs = -ENOMEM;
 809
 810         /* Can't use of_address_to_resource(), QE muram isn't at 0. */
 811         iprop = of_get_property(np, "reg", &size);
 812
 813         /* QE with a fixed pram location? */
 814         if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4)
 815                 return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE);
 816
 817         /* QE but with a dynamic pram location? */
 818         if (mspi->flags & SPI_QE) {
 819                 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
 820                 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock,
 821                                 QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs);
 822                 return pram_ofs;
 823         }
 824
 825         /* CPM1 and CPM2 pram must be at a fixed addr. */
 826         if (!iprop || size != sizeof(*iprop) * 4)
 827                 return -ENOMEM;
 828
 829         spi_base_ofs = cpm_muram_alloc_fixed(iprop[2], 2);
 830         if (IS_ERR_VALUE(spi_base_ofs))
 831                 return -ENOMEM;
 832
 833         if (mspi->flags & SPI_CPM2) {
 834                 pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64);
 835                 if (!IS_ERR_VALUE(pram_ofs)) {
 836                         u16 __iomem *spi_base = cpm_muram_addr(spi_base_ofs);
 837
 838                         out_be16(spi_base, pram_ofs);
 839                 }
 840         } else {
 841                 struct spi_pram __iomem *pram = cpm_muram_addr(spi_base_ofs);
 842                 u16 rpbase = in_be16(&pram->rpbase);
 843
 844                 /* Microcode relocation patch applied? */
 845                 if (rpbase)
 846                         pram_ofs = rpbase;
 847                 else
 848                         return spi_base_ofs;
 849         }
 850
 851         cpm_muram_free(spi_base_ofs);
 852         return pram_ofs;
 853 }
 854
 855 static int mpc8xxx_spi_cpm_init(struct mpc8xxx_spi *mspi)
 856 {
 857         struct device *dev = mspi->dev;
 858         struct device_node *np = dev_archdata_get_node(&dev->archdata);
 859         const u32 *iprop;
 860         int size;
 861         unsigned long pram_ofs;
 862         unsigned long bds_ofs;
 863
 864         if (!(mspi->flags & SPI_CPM_MODE))
 865                 return 0;
 866
 867         if (!mpc8xxx_spi_alloc_dummy_rx())
 868                 return -ENOMEM;
 869
 870         if (mspi->flags & SPI_QE) {
 871                 iprop = of_get_property(np, "cell-index", &size);
 872                 if (iprop && size == sizeof(*iprop))
 873                         mspi->subblock = *iprop;
 874
 875                 switch (mspi->subblock) {
 876                 default:
 877                         dev_warn(dev, "cell-index unspecified, assuming SPI1");
 878                         /* fall through */
 879                 case 0:
 880                         mspi->subblock = QE_CR_SUBBLOCK_SPI1;
 881                         break;
 882                 case 1:
 883                         mspi->subblock = QE_CR_SUBBLOCK_SPI2;
 884                         break;
 885                 }
 886         }
 887
 888         pram_ofs = mpc8xxx_spi_cpm_get_pram(mspi);
 889         if (IS_ERR_VALUE(pram_ofs)) {
 890                 dev_err(dev, "can't allocate spi parameter ram\n");
 891                 goto err_pram;
 892         }
 893
 894         bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) +
 895                                   sizeof(*mspi->rx_bd), 8);
 896         if (IS_ERR_VALUE(bds_ofs)) {
 897                 dev_err(dev, "can't allocate bds\n");
 898                 goto err_bds;
 899         }
 900
 901         mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE,
 902                                             DMA_TO_DEVICE);
 903         if (dma_mapping_error(dev, mspi->dma_dummy_tx)) {
 904                 dev_err(dev, "unable to map dummy tx buffer\n");
 905                 goto err_dummy_tx;
 906         }
 907
 908         mspi->dma_dummy_rx = dma_map_single(dev, mpc8xxx_dummy_rx, SPI_MRBLR,
 909                                             DMA_FROM_DEVICE);
 910         if (dma_mapping_error(dev, mspi->dma_dummy_rx)) {
 911                 dev_err(dev, "unable to map dummy rx buffer\n");
 912                 goto err_dummy_rx;
 913         }
 914
 915         mspi->pram = cpm_muram_addr(pram_ofs);
 916
 917         mspi->tx_bd = cpm_muram_addr(bds_ofs);
 918         mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd));
 919
 920         /* Initialize parameter ram. */
 921         out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd));
 922         out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd));
 923         out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL);
 924         out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL);
 925         out_be16(&mspi->pram->mrblr, SPI_MRBLR);
 926         out_be32(&mspi->pram->rstate, 0);
 927         out_be32(&mspi->pram->rdp, 0);
 928         out_be16(&mspi->pram->rbptr, 0);
 929         out_be16(&mspi->pram->rbc, 0);
 930         out_be32(&mspi->pram->rxtmp, 0);
 931         out_be32(&mspi->pram->tstate, 0);
 932         out_be32(&mspi->pram->tdp, 0);
 933         out_be16(&mspi->pram->tbptr, 0);
 934         out_be16(&mspi->pram->tbc, 0);
 935         out_be32(&mspi->pram->txtmp, 0);
 936
 937         return 0;
 938
 939 err_dummy_rx:
 940         dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
 941 err_dummy_tx:
 942         cpm_muram_free(bds_ofs);
 943 err_bds:
 944         cpm_muram_free(pram_ofs);
 945 err_pram:
 946         mpc8xxx_spi_free_dummy_rx();
 947         return -ENOMEM;
 948 }
 949
 950 static void mpc8xxx_spi_cpm_free(struct mpc8xxx_spi *mspi)
 951 {
 952         struct device *dev = mspi->dev;
 953
 954         dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE);
 955         dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE);
 956         cpm_muram_free(cpm_muram_offset(mspi->tx_bd));
 957         cpm_muram_free(cpm_muram_offset(mspi->pram));
 958         mpc8xxx_spi_free_dummy_rx();
 959 }
 960
 961 static const char *mpc8xxx_spi_strmode(unsigned int flags)
 962 {
 963         if (flags & SPI_QE_CPU_MODE) {
 964                 return "QE CPU";
 965         } else if (flags & SPI_CPM_MODE) {
 966                 if (flags & SPI_QE)
 967                         return "QE";
 968                 else if (flags & SPI_CPM2)
 969                         return "CPM2";
 970                 else
 971                         return "CPM1";
 972         }
 973         return "CPU";
 974 }
 975
 976 static struct spi_master * __devinit
 977 mpc8xxx_spi_probe(struct device *dev, struct resource *mem, unsigned int irq)
 978 {
 979         struct fsl_spi_platform_data *pdata = dev->platform_data;
 980         struct spi_master *master;
 981         struct mpc8xxx_spi *mpc8xxx_spi;
 982         u32 regval;
 983         int ret = 0;
 984
 985         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 986         if (master == NULL) {
 987                 ret = -ENOMEM;
 988                 goto err;
 989         }
 990
 991         dev_set_drvdata(dev, master);
 992
 993         /* the spi->mode bits understood by this driver: */
 994         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
 995                         | SPI_LSB_FIRST | SPI_LOOP;
 996
 997         master->setup = mpc8xxx_spi_setup;
 998         master->transfer = mpc8xxx_spi_transfer;
 999         master->cleanup = mpc8xxx_spi_cleanup;
1000
1001         mpc8xxx_spi = spi_master_get_devdata(master);
1002         mpc8xxx_spi->dev = dev;
1003         mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
1004         mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
1005         mpc8xxx_spi->flags = pdata->flags;
1006         mpc8xxx_spi->spibrg = pdata->sysclk;
1007
1008         ret = mpc8xxx_spi_cpm_init(mpc8xxx_spi);
1009         if (ret)
1010                 goto err_cpm_init;
1011
1012         mpc8xxx_spi->rx_shift = 0;
1013         mpc8xxx_spi->tx_shift = 0;
1014         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
1015                 mpc8xxx_spi->rx_shift = 16;
1016                 mpc8xxx_spi->tx_shift = 24;
1017         }
1018
1019         init_completion(&mpc8xxx_spi->done);
1020
1021         mpc8xxx_spi->base = ioremap(mem->start, mem->end - mem->start + 1);
1022         if (mpc8xxx_spi->base == NULL) {
1023                 ret = -ENOMEM;
1024                 goto err_ioremap;
1025         }
1026
1027         mpc8xxx_spi->irq = irq;
1028
1029         /* Register for SPI Interrupt */
1030         ret = request_irq(mpc8xxx_spi->irq, mpc8xxx_spi_irq,
1031                           0, "mpc8xxx_spi", mpc8xxx_spi);
1032
1033         if (ret != 0)
1034                 goto unmap_io;
1035
1036         master->bus_num = pdata->bus_num;
1037         master->num_chipselect = pdata->max_chipselect;
1038
1039         /* SPI controller initializations */
1040         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, 0);
1041         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mask, 0);
1042         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->command, 0);
1043         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->event, 0xffffffff);
1044
1045         /* Enable SPI interface */
1046         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
1047         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
1048                 regval |= SPMODE_OP;
1049
1050         mpc8xxx_spi_write_reg(&mpc8xxx_spi->base->mode, regval);
1051         spin_lock_init(&mpc8xxx_spi->lock);
1052         init_completion(&mpc8xxx_spi->done);
1053         INIT_WORK(&mpc8xxx_spi->work, mpc8xxx_spi_work);
1054         INIT_LIST_HEAD(&mpc8xxx_spi->queue);
1055
1056         mpc8xxx_spi->workqueue = create_singlethread_workqueue(
1057                 dev_name(master->dev.parent));
1058         if (mpc8xxx_spi->workqueue == NULL) {
1059                 ret = -EBUSY;
1060                 goto free_irq;
1061         }
1062
1063         ret = spi_register_master(master);
1064         if (ret < 0)
1065                 goto unreg_master;
1066
1067         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", mpc8xxx_spi->base,
1068                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
1069
1070         return master;
1071
1072 unreg_master:
1073         destroy_workqueue(mpc8xxx_spi->workqueue);
1074 free_irq:
1075         free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1076 unmap_io:
1077         iounmap(mpc8xxx_spi->base);
1078 err_ioremap:
1079         mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1080 err_cpm_init:
1081         spi_master_put(master);
1082 err:
1083         return ERR_PTR(ret);
1084 }
1085
1086 static int __devexit mpc8xxx_spi_remove(struct device *dev)
1087 {
1088         struct mpc8xxx_spi *mpc8xxx_spi;
1089         struct spi_master *master;
1090
1091         master = dev_get_drvdata(dev);
1092         mpc8xxx_spi = spi_master_get_devdata(master);
1093
1094         flush_workqueue(mpc8xxx_spi->workqueue);
1095         destroy_workqueue(mpc8xxx_spi->workqueue);
1096         spi_unregister_master(master);
1097
1098         free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
1099         iounmap(mpc8xxx_spi->base);
1100         mpc8xxx_spi_cpm_free(mpc8xxx_spi);
1101
1102         return 0;
1103 }
1104
1105 struct mpc8xxx_spi_probe_info {
1106         struct fsl_spi_platform_data pdata;
1107         int *gpios;
1108         bool *alow_flags;
1109 };
1110
1111 static struct mpc8xxx_spi_probe_info *
1112 to_of_pinfo(struct fsl_spi_platform_data *pdata)
1113 {
1114         return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
1115 }
1116
1117 static void mpc8xxx_spi_cs_control(struct spi_device *spi, bool on)
1118 {
1119         struct device *dev = spi->dev.parent;
1120         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
1121         u16 cs = spi->chip_select;
1122         int gpio = pinfo->gpios[cs];
1123         bool alow = pinfo->alow_flags[cs];
1124
1125         gpio_set_value(gpio, on ^ alow);
1126 }
1127
1128 static int of_mpc8xxx_spi_get_chipselects(struct device *dev)
1129 {
1130         struct device_node *np = dev_archdata_get_node(&dev->archdata);
1131         struct fsl_spi_platform_data *pdata = dev->platform_data;
1132         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1133         unsigned int ngpios;
1134         int i = 0;
1135         int ret;
1136
1137         ngpios = of_gpio_count(np);
1138         if (!ngpios) {
1139                 /*
1140                  * SPI w/o chip-select line. One SPI device is still permitted
1141                  * though.
1142                  */
1143                 pdata->max_chipselect = 1;
1144                 return 0;
1145         }
1146
1147         pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
1148         if (!pinfo->gpios)
1149                 return -ENOMEM;
1150         memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
1151
1152         pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
1153                                     GFP_KERNEL);
1154         if (!pinfo->alow_flags) {
1155                 ret = -ENOMEM;
1156                 goto err_alloc_flags;
1157         }
1158
1159         for (; i < ngpios; i++) {
1160                 int gpio;
1161                 enum of_gpio_flags flags;
1162
1163                 gpio = of_get_gpio_flags(np, i, &flags);
1164                 if (!gpio_is_valid(gpio)) {
1165                         dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
1166                         ret = gpio;
1167                         goto err_loop;
1168                 }
1169
1170                 ret = gpio_request(gpio, dev_name(dev));
1171                 if (ret) {
1172                         dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
1173                         goto err_loop;
1174                 }
1175
1176                 pinfo->gpios[i] = gpio;
1177                 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
1178
1179                 ret = gpio_direction_output(pinfo->gpios[i],
1180                                             pinfo->alow_flags[i]);
1181                 if (ret) {
1182                         dev_err(dev, "can't set output direction for gpio "
1183                                 "#%d: %d\n", i, ret);
1184                         goto err_loop;
1185                 }
1186         }
1187
1188         pdata->max_chipselect = ngpios;
1189         pdata->cs_control = mpc8xxx_spi_cs_control;
1190
1191         return 0;
1192
1193 err_loop:
1194         while (i >= 0) {
1195                 if (gpio_is_valid(pinfo->gpios[i]))
1196                         gpio_free(pinfo->gpios[i]);
1197                 i--;
1198         }
1199
1200         kfree(pinfo->alow_flags);
1201         pinfo->alow_flags = NULL;
1202 err_alloc_flags:
1203         kfree(pinfo->gpios);
1204         pinfo->gpios = NULL;
1205         return ret;
1206 }
1207
1208 static int of_mpc8xxx_spi_free_chipselects(struct device *dev)
1209 {
1210         struct fsl_spi_platform_data *pdata = dev->platform_data;
1211         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
1212         int i;
1213
1214         if (!pinfo->gpios)
1215                 return 0;
1216
1217         for (i = 0; i < pdata->max_chipselect; i++) {
1218                 if (gpio_is_valid(pinfo->gpios[i]))
1219                         gpio_free(pinfo->gpios[i]);
1220         }
1221
1222         kfree(pinfo->gpios);
1223         kfree(pinfo->alow_flags);
1224         return 0;
1225 }
1226
1227 static int __devinit of_mpc8xxx_spi_probe(struct of_device *ofdev,
1228                                           const struct of_device_id *ofid)
1229 {
1230         struct device *dev = &ofdev->dev;
1231         struct device_node *np = ofdev->node;
1232         struct mpc8xxx_spi_probe_info *pinfo;
1233         struct fsl_spi_platform_data *pdata;
1234         struct spi_master *master;
1235         struct resource mem;
1236         struct resource irq;
1237         const void *prop;
1238         int ret = -ENOMEM;
1239
1240         pinfo = kzalloc(sizeof(*pinfo), GFP_KERNEL);
1241         if (!pinfo)
1242                 return -ENOMEM;
1243
1244         pdata = &pinfo->pdata;
1245         dev->platform_data = pdata;
1246
1247         /* Allocate bus num dynamically. */
1248         pdata->bus_num = -1;
1249
1250         /* SPI controller is either clocked from QE or SoC clock. */
1251         pdata->sysclk = get_brgfreq();
1252         if (pdata->sysclk == -1) {
1253                 pdata->sysclk = fsl_get_sys_freq();
1254                 if (pdata->sysclk == -1) {
1255                         ret = -ENODEV;
1256                         goto err_clk;
1257                 }
1258         }
1259
1260         prop = of_get_property(np, "mode", NULL);
1261         if (prop && !strcmp(prop, "cpu-qe"))
1262                 pdata->flags = SPI_QE_CPU_MODE;
1263         else if (prop && !strcmp(prop, "qe"))
1264                 pdata->flags = SPI_CPM_MODE | SPI_QE;
1265         else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
1266                 pdata->flags = SPI_CPM_MODE | SPI_CPM2;
1267         else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
1268                 pdata->flags = SPI_CPM_MODE | SPI_CPM1;
1269
1270         ret = of_mpc8xxx_spi_get_chipselects(dev);
1271         if (ret)
1272                 goto err;
1273
1274         ret = of_address_to_resource(np, 0, &mem);
1275         if (ret)
1276                 goto err;
1277
1278         ret = of_irq_to_resource(np, 0, &irq);
1279         if (!ret) {
1280                 ret = -EINVAL;
1281                 goto err;
1282         }
1283
1284         master = mpc8xxx_spi_probe(dev, &mem, irq.start);
1285         if (IS_ERR(master)) {
1286                 ret = PTR_ERR(master);
1287                 goto err;
1288         }
1289
1290         of_register_spi_devices(master, np);
1291
1292         return 0;
1293
1294 err:
1295         of_mpc8xxx_spi_free_chipselects(dev);
1296 err_clk:
1297         kfree(pinfo);
1298         return ret;
1299 }
1300
1301 static int __devexit of_mpc8xxx_spi_remove(struct of_device *ofdev)
1302 {
1303         int ret;
1304
1305         ret = mpc8xxx_spi_remove(&ofdev->dev);
1306         if (ret)
1307                 return ret;
1308         of_mpc8xxx_spi_free_chipselects(&ofdev->dev);
1309         return 0;
1310 }
1311
1312 static const struct of_device_id of_mpc8xxx_spi_match[] = {
1313         { .compatible = "fsl,spi" },
1314         {},
1315 };
1316 MODULE_DEVICE_TABLE(of, of_mpc8xxx_spi_match);
1317
1318 static struct of_platform_driver of_mpc8xxx_spi_driver = {
1319         .name           = "mpc8xxx_spi",
1320         .match_table    = of_mpc8xxx_spi_match,
1321         .probe          = of_mpc8xxx_spi_probe,
1322         .remove         = __devexit_p(of_mpc8xxx_spi_remove),
1323 };
1324
1325 #ifdef CONFIG_MPC832x_RDB
1326 /*
1327  *                              XXX XXX XXX
1328  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
1329  * only. The driver should go away soon, since newer MPC8323E-RDB's device
1330  * tree can work with OpenFirmware driver. But for now we support old trees
1331  * as well.
1332  */
1333 static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev)
1334 {
1335         struct resource *mem;
1336         unsigned int irq;
1337         struct spi_master *master;
1338
1339         if (!pdev->dev.platform_data)
1340                 return -EINVAL;
1341
1342         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1343         if (!mem)
1344                 return -EINVAL;
1345
1346         irq = platform_get_irq(pdev, 0);
1347         if (!irq)
1348                 return -EINVAL;
1349
1350         master = mpc8xxx_spi_probe(&pdev->dev, mem, irq);
1351         if (IS_ERR(master))
1352                 return PTR_ERR(master);
1353         return 0;
1354 }
1355
1356 static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev)
1357 {
1358         return mpc8xxx_spi_remove(&pdev->dev);
1359 }
1360
1361 MODULE_ALIAS("platform:mpc8xxx_spi");
1362 static struct platform_driver mpc8xxx_spi_driver = {
1363         .probe = plat_mpc8xxx_spi_probe,
1364         .remove = __exit_p(plat_mpc8xxx_spi_remove),
1365         .driver = {
1366                 .name = "mpc8xxx_spi",
1367                 .owner = THIS_MODULE,
1368         },
1369 };
1370
1371 static bool legacy_driver_failed;
1372
1373 static void __init legacy_driver_register(void)
1374 {
1375         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
1376 }
1377
1378 static void __exit legacy_driver_unregister(void)
1379 {
1380         if (legacy_driver_failed)
1381                 return;
1382         platform_driver_unregister(&mpc8xxx_spi_driver);
1383 }
1384 #else
1385 static void __init legacy_driver_register(void) {}
1386 static void __exit legacy_driver_unregister(void) {}
1387 #endif /* CONFIG_MPC832x_RDB */
1388
1389 static int __init mpc8xxx_spi_init(void)
1390 {
1391         legacy_driver_register();
1392         return of_register_platform_driver(&of_mpc8xxx_spi_driver);
1393 }
1394
1395 static void __exit mpc8xxx_spi_exit(void)
1396 {
1397         of_unregister_platform_driver(&of_mpc8xxx_spi_driver);
1398         legacy_driver_unregister();
1399 }
1400
1401 module_init(mpc8xxx_spi_init);
1402 module_exit(mpc8xxx_spi_exit);
1403
1404 MODULE_AUTHOR("Kumar Gala");
1405 MODULE_DESCRIPTION("Simple MPC8xxx SPI Driver");
1406 MODULE_LICENSE("GPL");