drivers/spi/spi-topcliff-pch.c

   1 /*
   2  * SPI bus driver for the Topcliff PCH used by Intel SoCs
   3  *
   4  * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/pci.h>
  22 #include <linux/wait.h>
  23 #include <linux/spi/spi.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sched.h>
  26 #include <linux/spi/spidev.h>
  27 #include <linux/module.h>
  28 #include <linux/device.h>
  29 #include <linux/platform_device.h>
  30
  31 #include <linux/dmaengine.h>
  32 #include <linux/pch_dma.h>
  33
  34 /* Register offsets */
  35 #define PCH_SPCR                0x00    /* SPI control register */
  36 #define PCH_SPBRR               0x04    /* SPI baud rate register */
  37 #define PCH_SPSR                0x08    /* SPI status register */
  38 #define PCH_SPDWR               0x0C    /* SPI write data register */
  39 #define PCH_SPDRR               0x10    /* SPI read data register */
  40 #define PCH_SSNXCR              0x18    /* SSN Expand Control Register */
  41 #define PCH_SRST                0x1C    /* SPI reset register */
  42 #define PCH_ADDRESS_SIZE        0x20
  43
  44 #define PCH_SPSR_TFD            0x000007C0
  45 #define PCH_SPSR_RFD            0x0000F800
  46
  47 #define PCH_READABLE(x)         (((x) & PCH_SPSR_RFD)>>11)
  48 #define PCH_WRITABLE(x)         (((x) & PCH_SPSR_TFD)>>6)
  49
  50 #define PCH_RX_THOLD            7
  51 #define PCH_RX_THOLD_MAX        15
  52
  53 #define PCH_MAX_BAUDRATE        5000000
  54 #define PCH_MAX_FIFO_DEPTH      16
  55
  56 #define STATUS_RUNNING          1
  57 #define STATUS_EXITING          2
  58 #define PCH_SLEEP_TIME          10
  59
  60 #define SSN_LOW                 0x02U
  61 #define SSN_NO_CONTROL          0x00U
  62 #define PCH_MAX_CS              0xFF
  63 #define PCI_DEVICE_ID_GE_SPI    0x8816
  64
  65 #define SPCR_SPE_BIT            (1 << 0)
  66 #define SPCR_MSTR_BIT           (1 << 1)
  67 #define SPCR_LSBF_BIT           (1 << 4)
  68 #define SPCR_CPHA_BIT           (1 << 5)
  69 #define SPCR_CPOL_BIT           (1 << 6)
  70 #define SPCR_TFIE_BIT           (1 << 8)
  71 #define SPCR_RFIE_BIT           (1 << 9)
  72 #define SPCR_FIE_BIT            (1 << 10)
  73 #define SPCR_ORIE_BIT           (1 << 11)
  74 #define SPCR_MDFIE_BIT          (1 << 12)
  75 #define SPCR_FICLR_BIT          (1 << 24)
  76 #define SPSR_TFI_BIT            (1 << 0)
  77 #define SPSR_RFI_BIT            (1 << 1)
  78 #define SPSR_FI_BIT             (1 << 2)
  79 #define SPSR_ORF_BIT            (1 << 3)
  80 #define SPBRR_SIZE_BIT          (1 << 10)
  81
  82 #define PCH_ALL                 (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
  83                                 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
  84
  85 #define SPCR_RFIC_FIELD         20
  86 #define SPCR_TFIC_FIELD         16
  87
  88 #define MASK_SPBRR_SPBR_BITS    ((1 << 10) - 1)
  89 #define MASK_RFIC_SPCR_BITS     (0xf << SPCR_RFIC_FIELD)
  90 #define MASK_TFIC_SPCR_BITS     (0xf << SPCR_TFIC_FIELD)
  91
  92 #define PCH_CLOCK_HZ            50000000
  93 #define PCH_MAX_SPBR            1023
  94
  95 /* Definition for ML7213 by OKI SEMICONDUCTOR */
  96 #define PCI_VENDOR_ID_ROHM              0x10DB
  97 #define PCI_DEVICE_ID_ML7213_SPI        0x802c
  98 #define PCI_DEVICE_ID_ML7223_SPI        0x800F
  99
 100 /*
 101  * Set the number of SPI instance max
 102  * Intel EG20T PCH :            1ch
 103  * OKI SEMICONDUCTOR ML7213 IOH :       2ch
 104  * OKI SEMICONDUCTOR ML7223 IOH :       1ch
 105 */
 106 #define PCH_SPI_MAX_DEV                 2
 107
 108 #define PCH_BUF_SIZE            4096
 109 #define PCH_DMA_TRANS_SIZE      12
 110
 111 static int use_dma = 1;
 112
 113 struct pch_spi_dma_ctrl {
 114         struct dma_async_tx_descriptor  *desc_tx;
 115         struct dma_async_tx_descriptor  *desc_rx;
 116         struct pch_dma_slave            param_tx;
 117         struct pch_dma_slave            param_rx;
 118         struct dma_chan         *chan_tx;
 119         struct dma_chan         *chan_rx;
 120         struct scatterlist              *sg_tx_p;
 121         struct scatterlist              *sg_rx_p;
 122         struct scatterlist              sg_tx;
 123         struct scatterlist              sg_rx;
 124         int                             nent;
 125         void                            *tx_buf_virt;
 126         void                            *rx_buf_virt;
 127         dma_addr_t                      tx_buf_dma;
 128         dma_addr_t                      rx_buf_dma;
 129 };
 130 /**
 131  * struct pch_spi_data - Holds the SPI channel specific details
 132  * @io_remap_addr:              The remapped PCI base address
 133  * @master:                     Pointer to the SPI master structure
 134  * @work:                       Reference to work queue handler
 135  * @wk:                         Workqueue for carrying out execution of the
 136  *                              requests
 137  * @wait:                       Wait queue for waking up upon receiving an
 138  *                              interrupt.
 139  * @transfer_complete:          Status of SPI Transfer
 140  * @bcurrent_msg_processing:    Status flag for message processing
 141  * @lock:                       Lock for protecting this structure
 142  * @queue:                      SPI Message queue
 143  * @status:                     Status of the SPI driver
 144  * @bpw_len:                    Length of data to be transferred in bits per
 145  *                              word
 146  * @transfer_active:            Flag showing active transfer
 147  * @tx_index:                   Transmit data count; for bookkeeping during
 148  *                              transfer
 149  * @rx_index:                   Receive data count; for bookkeeping during
 150  *                              transfer
 151  * @tx_buff:                    Buffer for data to be transmitted
 152  * @rx_index:                   Buffer for Received data
 153  * @n_curnt_chip:               The chip number that this SPI driver currently
 154  *                              operates on
 155  * @current_chip:               Reference to the current chip that this SPI
 156  *                              driver currently operates on
 157  * @current_msg:                The current message that this SPI driver is
 158  *                              handling
 159  * @cur_trans:                  The current transfer that this SPI driver is
 160  *                              handling
 161  * @board_dat:                  Reference to the SPI device data structure
 162  * @plat_dev:                   platform_device structure
 163  * @ch:                         SPI channel number
 164  * @irq_reg_sts:                Status of IRQ registration
 165  */
 166 struct pch_spi_data {
 167         void __iomem *io_remap_addr;
 168         unsigned long io_base_addr;
 169         struct spi_master *master;
 170         struct work_struct work;
 171         struct workqueue_struct *wk;
 172         wait_queue_head_t wait;
 173         u8 transfer_complete;
 174         u8 bcurrent_msg_processing;
 175         spinlock_t lock;
 176         struct list_head queue;
 177         u8 status;
 178         u32 bpw_len;
 179         u8 transfer_active;
 180         u32 tx_index;
 181         u32 rx_index;
 182         u16 *pkt_tx_buff;
 183         u16 *pkt_rx_buff;
 184         u8 n_curnt_chip;
 185         struct spi_device *current_chip;
 186         struct spi_message *current_msg;
 187         struct spi_transfer *cur_trans;
 188         struct pch_spi_board_data *board_dat;
 189         struct platform_device  *plat_dev;
 190         int ch;
 191         struct pch_spi_dma_ctrl dma;
 192         int use_dma;
 193         u8 irq_reg_sts;
 194 };
 195
 196 /**
 197  * struct pch_spi_board_data - Holds the SPI device specific details
 198  * @pdev:               Pointer to the PCI device
 199  * @suspend_sts:        Status of suspend
 200  * @num:                The number of SPI device instance
 201  */
 202 struct pch_spi_board_data {
 203         struct pci_dev *pdev;
 204         u8 suspend_sts;
 205         int num;
 206 };
 207
 208 struct pch_pd_dev_save {
 209         int num;
 210         struct platform_device *pd_save[PCH_SPI_MAX_DEV];
 211         struct pch_spi_board_data *board_dat;
 212 };
 213
 214 static struct pci_device_id pch_spi_pcidev_id[] = {
 215         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),    1, },
 216         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
 217         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
 218         { }
 219 };
 220
 221 /**
 222  * pch_spi_writereg() - Performs  register writes
 223  * @master:     Pointer to struct spi_master.
 224  * @idx:        Register offset.
 225  * @val:        Value to be written to register.
 226  */
 227 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
 228 {
 229         struct pch_spi_data *data = spi_master_get_devdata(master);
 230         iowrite32(val, (data->io_remap_addr + idx));
 231 }
 232
 233 /**
 234  * pch_spi_readreg() - Performs register reads
 235  * @master:     Pointer to struct spi_master.
 236  * @idx:        Register offset.
 237  */
 238 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
 239 {
 240         struct pch_spi_data *data = spi_master_get_devdata(master);
 241         return ioread32(data->io_remap_addr + idx);
 242 }
 243
 244 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
 245                                       u32 set, u32 clr)
 246 {
 247         u32 tmp = pch_spi_readreg(master, idx);
 248         tmp = (tmp & ~clr) | set;
 249         pch_spi_writereg(master, idx, tmp);
 250 }
 251
 252 static void pch_spi_set_master_mode(struct spi_master *master)
 253 {
 254         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
 255 }
 256
 257 /**
 258  * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
 259  * @master:     Pointer to struct spi_master.
 260  */
 261 static void pch_spi_clear_fifo(struct spi_master *master)
 262 {
 263         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
 264         pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
 265 }
 266
 267 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
 268                                 void __iomem *io_remap_addr)
 269 {
 270         u32 n_read, tx_index, rx_index, bpw_len;
 271         u16 *pkt_rx_buffer, *pkt_tx_buff;
 272         int read_cnt;
 273         u32 reg_spcr_val;
 274         void __iomem *spsr;
 275         void __iomem *spdrr;
 276         void __iomem *spdwr;
 277
 278         spsr = io_remap_addr + PCH_SPSR;
 279         iowrite32(reg_spsr_val, spsr);
 280
 281         if (data->transfer_active) {
 282                 rx_index = data->rx_index;
 283                 tx_index = data->tx_index;
 284                 bpw_len = data->bpw_len;
 285                 pkt_rx_buffer = data->pkt_rx_buff;
 286                 pkt_tx_buff = data->pkt_tx_buff;
 287
 288                 spdrr = io_remap_addr + PCH_SPDRR;
 289                 spdwr = io_remap_addr + PCH_SPDWR;
 290
 291                 n_read = PCH_READABLE(reg_spsr_val);
 292
 293                 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
 294                         pkt_rx_buffer[rx_index++] = ioread32(spdrr);
 295                         if (tx_index < bpw_len)
 296                                 iowrite32(pkt_tx_buff[tx_index++], spdwr);
 297                 }
 298
 299                 /* disable RFI if not needed */
 300                 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
 301                         reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
 302                         reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
 303
 304                         /* reset rx threshold */
 305                         reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
 306                         reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
 307
 308                         iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
 309                 }
 310
 311                 /* update counts */
 312                 data->tx_index = tx_index;
 313                 data->rx_index = rx_index;
 314
 315         }
 316
 317         /* if transfer complete interrupt */
 318         if (reg_spsr_val & SPSR_FI_BIT) {
 319                 if (tx_index < bpw_len)
 320                         dev_err(&data->master->dev,
 321                                 "%s : Transfer is not completed", __func__);
 322                 /* disable interrupts */
 323                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
 324
 325                 /* transfer is completed;inform pch_spi_process_messages */
 326                 data->transfer_complete = true;
 327                 data->transfer_active = false;
 328                 wake_up(&data->wait);
 329         }
 330 }
 331
 332 /**
 333  * pch_spi_handler() - Interrupt handler
 334  * @irq:        The interrupt number.
 335  * @dev_id:     Pointer to struct pch_spi_board_data.
 336  */
 337 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
 338 {
 339         u32 reg_spsr_val;
 340         void __iomem *spsr;
 341         void __iomem *io_remap_addr;
 342         irqreturn_t ret = IRQ_NONE;
 343         struct pch_spi_data *data = dev_id;
 344         struct pch_spi_board_data *board_dat = data->board_dat;
 345
 346         if (board_dat->suspend_sts) {
 347                 dev_dbg(&board_dat->pdev->dev,
 348                         "%s returning due to suspend\n", __func__);
 349                 return IRQ_NONE;
 350         }
 351         if (data->use_dma)
 352                 return IRQ_NONE;
 353
 354         io_remap_addr = data->io_remap_addr;
 355         spsr = io_remap_addr + PCH_SPSR;
 356
 357         reg_spsr_val = ioread32(spsr);
 358
 359         if (reg_spsr_val & SPSR_ORF_BIT)
 360                 dev_err(&board_dat->pdev->dev, "%s Over run error", __func__);
 361
 362         /* Check if the interrupt is for SPI device */
 363         if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
 364                 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
 365                 ret = IRQ_HANDLED;
 366         }
 367
 368         dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
 369                 __func__, ret);
 370
 371         return ret;
 372 }
 373
 374 /**
 375  * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
 376  * @master:     Pointer to struct spi_master.
 377  * @speed_hz:   Baud rate.
 378  */
 379 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
 380 {
 381         u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
 382
 383         /* if baud rate is less than we can support limit it */
 384         if (n_spbr > PCH_MAX_SPBR)
 385                 n_spbr = PCH_MAX_SPBR;
 386
 387         pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
 388 }
 389
 390 /**
 391  * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
 392  * @master:             Pointer to struct spi_master.
 393  * @bits_per_word:      Bits per word for SPI transfer.
 394  */
 395 static void pch_spi_set_bits_per_word(struct spi_master *master,
 396                                       u8 bits_per_word)
 397 {
 398         if (bits_per_word == 8)
 399                 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
 400         else
 401                 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
 402 }
 403
 404 /**
 405  * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
 406  * @spi:        Pointer to struct spi_device.
 407  */
 408 static void pch_spi_setup_transfer(struct spi_device *spi)
 409 {
 410         u32 flags = 0;
 411
 412         dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
 413                 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
 414                 spi->max_speed_hz);
 415         pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
 416
 417         /* set bits per word */
 418         pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
 419
 420         if (!(spi->mode & SPI_LSB_FIRST))
 421                 flags |= SPCR_LSBF_BIT;
 422         if (spi->mode & SPI_CPOL)
 423                 flags |= SPCR_CPOL_BIT;
 424         if (spi->mode & SPI_CPHA)
 425                 flags |= SPCR_CPHA_BIT;
 426         pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
 427                            (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
 428
 429         /* Clear the FIFO by toggling  FICLR to 1 and back to 0 */
 430         pch_spi_clear_fifo(spi->master);
 431 }
 432
 433 /**
 434  * pch_spi_reset() - Clears SPI registers
 435  * @master:     Pointer to struct spi_master.
 436  */
 437 static void pch_spi_reset(struct spi_master *master)
 438 {
 439         /* write 1 to reset SPI */
 440         pch_spi_writereg(master, PCH_SRST, 0x1);
 441
 442         /* clear reset */
 443         pch_spi_writereg(master, PCH_SRST, 0x0);
 444 }
 445
 446 static int pch_spi_setup(struct spi_device *pspi)
 447 {
 448         /* check bits per word */
 449         if (pspi->bits_per_word == 0) {
 450                 pspi->bits_per_word = 8;
 451                 dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__);
 452         }
 453
 454         if ((pspi->bits_per_word != 8) && (pspi->bits_per_word != 16)) {
 455                 dev_err(&pspi->dev, "%s Invalid bits per word\n", __func__);
 456                 return -EINVAL;
 457         }
 458
 459         /* Check baud rate setting */
 460         /* if baud rate of chip is greater than
 461            max we can support,return error */
 462         if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE)
 463                 pspi->max_speed_hz = PCH_MAX_BAUDRATE;
 464
 465         dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__,
 466                 (pspi->mode) & (SPI_CPOL | SPI_CPHA));
 467
 468         return 0;
 469 }
 470
 471 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
 472 {
 473
 474         struct spi_transfer *transfer;
 475         struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
 476         int retval;
 477         unsigned long flags;
 478
 479         /* validate spi message and baud rate */
 480         if (unlikely(list_empty(&pmsg->transfers) == 1)) {
 481                 dev_err(&pspi->dev, "%s list empty\n", __func__);
 482                 retval = -EINVAL;
 483                 goto err_out;
 484         }
 485
 486         if (unlikely(pspi->max_speed_hz == 0)) {
 487                 dev_err(&pspi->dev, "%s pch_spi_tranfer maxspeed=%d\n",
 488                         __func__, pspi->max_speed_hz);
 489                 retval = -EINVAL;
 490                 goto err_out;
 491         }
 492
 493         dev_dbg(&pspi->dev, "%s Transfer List not empty. "
 494                 "Transfer Speed is set.\n", __func__);
 495
 496         spin_lock_irqsave(&data->lock, flags);
 497         /* validate Tx/Rx buffers and Transfer length */
 498         list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
 499                 if (!transfer->tx_buf && !transfer->rx_buf) {
 500                         dev_err(&pspi->dev,
 501                                 "%s Tx and Rx buffer NULL\n", __func__);
 502                         retval = -EINVAL;
 503                         goto err_return_spinlock;
 504                 }
 505
 506                 if (!transfer->len) {
 507                         dev_err(&pspi->dev, "%s Transfer length invalid\n",
 508                                 __func__);
 509                         retval = -EINVAL;
 510                         goto err_return_spinlock;
 511                 }
 512
 513                 dev_dbg(&pspi->dev, "%s Tx/Rx buffer valid. Transfer length"
 514                         " valid\n", __func__);
 515
 516                 /* if baud rate has been specified validate the same */
 517                 if (transfer->speed_hz > PCH_MAX_BAUDRATE)
 518                         transfer->speed_hz = PCH_MAX_BAUDRATE;
 519
 520                 /* if bits per word has been specified validate the same */
 521                 if (transfer->bits_per_word) {
 522                         if ((transfer->bits_per_word != 8)
 523                             && (transfer->bits_per_word != 16)) {
 524                                 retval = -EINVAL;
 525                                 dev_err(&pspi->dev,
 526                                         "%s Invalid bits per word\n", __func__);
 527                                 goto err_return_spinlock;
 528                         }
 529                 }
 530         }
 531         spin_unlock_irqrestore(&data->lock, flags);
 532
 533         /* We won't process any messages if we have been asked to terminate */
 534         if (data->status == STATUS_EXITING) {
 535                 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
 536                 retval = -ESHUTDOWN;
 537                 goto err_out;
 538         }
 539
 540         /* If suspended ,return -EINVAL */
 541         if (data->board_dat->suspend_sts) {
 542                 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
 543                 retval = -EINVAL;
 544                 goto err_out;
 545         }
 546
 547         /* set status of message */
 548         pmsg->actual_length = 0;
 549         dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
 550
 551         pmsg->status = -EINPROGRESS;
 552         spin_lock_irqsave(&data->lock, flags);
 553         /* add message to queue */
 554         list_add_tail(&pmsg->queue, &data->queue);
 555         spin_unlock_irqrestore(&data->lock, flags);
 556
 557         dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
 558
 559         /* schedule work queue to run */
 560         queue_work(data->wk, &data->work);
 561         dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
 562
 563         retval = 0;
 564
 565 err_out:
 566         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
 567         return retval;
 568 err_return_spinlock:
 569         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
 570         spin_unlock_irqrestore(&data->lock, flags);
 571         return retval;
 572 }
 573
 574 static inline void pch_spi_select_chip(struct pch_spi_data *data,
 575                                        struct spi_device *pspi)
 576 {
 577         if (data->current_chip != NULL) {
 578                 if (pspi->chip_select != data->n_curnt_chip) {
 579                         dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
 580                         data->current_chip = NULL;
 581                 }
 582         }
 583
 584         data->current_chip = pspi;
 585
 586         data->n_curnt_chip = data->current_chip->chip_select;
 587
 588         dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
 589         pch_spi_setup_transfer(pspi);
 590 }
 591
 592 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
 593 {
 594         int size;
 595         u32 n_writes;
 596         int j;
 597         struct spi_message *pmsg;
 598         const u8 *tx_buf;
 599         const u16 *tx_sbuf;
 600
 601         /* set baud rate if needed */
 602         if (data->cur_trans->speed_hz) {
 603                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
 604                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
 605         }
 606
 607         /* set bits per word if needed */
 608         if (data->cur_trans->bits_per_word &&
 609             (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
 610                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
 611                 pch_spi_set_bits_per_word(data->master,
 612                                           data->cur_trans->bits_per_word);
 613                 *bpw = data->cur_trans->bits_per_word;
 614         } else {
 615                 *bpw = data->current_msg->spi->bits_per_word;
 616         }
 617
 618         /* reset Tx/Rx index */
 619         data->tx_index = 0;
 620         data->rx_index = 0;
 621
 622         data->bpw_len = data->cur_trans->len / (*bpw / 8);
 623
 624         /* find alloc size */
 625         size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
 626
 627         /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
 628         data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
 629         if (data->pkt_tx_buff != NULL) {
 630                 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
 631                 if (!data->pkt_rx_buff)
 632                         kfree(data->pkt_tx_buff);
 633         }
 634
 635         if (!data->pkt_rx_buff) {
 636                 /* flush queue and set status of all transfers to -ENOMEM */
 637                 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__);
 638                 list_for_each_entry(pmsg, data->queue.next, queue) {
 639                         pmsg->status = -ENOMEM;
 640
 641                         if (pmsg->complete != 0)
 642                                 pmsg->complete(pmsg->context);
 643
 644                         /* delete from queue */
 645                         list_del_init(&pmsg->queue);
 646                 }
 647                 return;
 648         }
 649
 650         /* copy Tx Data */
 651         if (data->cur_trans->tx_buf != NULL) {
 652                 if (*bpw == 8) {
 653                         tx_buf = data->cur_trans->tx_buf;
 654                         for (j = 0; j < data->bpw_len; j++)
 655                                 data->pkt_tx_buff[j] = *tx_buf++;
 656                 } else {
 657                         tx_sbuf = data->cur_trans->tx_buf;
 658                         for (j = 0; j < data->bpw_len; j++)
 659                                 data->pkt_tx_buff[j] = *tx_sbuf++;
 660                 }
 661         }
 662
 663         /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
 664         n_writes = data->bpw_len;
 665         if (n_writes > PCH_MAX_FIFO_DEPTH)
 666                 n_writes = PCH_MAX_FIFO_DEPTH;
 667
 668         dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
 669                 "0x2 to SSNXCR\n", __func__);
 670         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
 671
 672         for (j = 0; j < n_writes; j++)
 673                 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
 674
 675         /* update tx_index */
 676         data->tx_index = j;
 677
 678         /* reset transfer complete flag */
 679         data->transfer_complete = false;
 680         data->transfer_active = true;
 681 }
 682
 683 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
 684 {
 685         struct spi_message *pmsg;
 686         dev_dbg(&data->master->dev, "%s called\n", __func__);
 687         /* Invoke complete callback
 688          * [To the spi core..indicating end of transfer] */
 689         data->current_msg->status = 0;
 690
 691         if (data->current_msg->complete != 0) {
 692                 dev_dbg(&data->master->dev,
 693                         "%s:Invoking callback of SPI core\n", __func__);
 694                 data->current_msg->complete(data->current_msg->context);
 695         }
 696
 697         /* update status in global variable */
 698         data->bcurrent_msg_processing = false;
 699
 700         dev_dbg(&data->master->dev,
 701                 "%s:data->bcurrent_msg_processing = false\n", __func__);
 702
 703         data->current_msg = NULL;
 704         data->cur_trans = NULL;
 705
 706         /* check if we have items in list and not suspending
 707          * return 1 if list empty */
 708         if ((list_empty(&data->queue) == 0) &&
 709             (!data->board_dat->suspend_sts) &&
 710             (data->status != STATUS_EXITING)) {
 711                 /* We have some more work to do (either there is more tranint
 712                  * bpw;sfer requests in the current message or there are
 713                  *more messages)
 714                  */
 715                 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
 716                 queue_work(data->wk, &data->work);
 717         } else if (data->board_dat->suspend_sts ||
 718                    data->status == STATUS_EXITING) {
 719                 dev_dbg(&data->master->dev,
 720                         "%s suspend/remove initiated, flushing queue\n",
 721                         __func__);
 722                 list_for_each_entry(pmsg, data->queue.next, queue) {
 723                         pmsg->status = -EIO;
 724
 725                         if (pmsg->complete)
 726                                 pmsg->complete(pmsg->context);
 727
 728                         /* delete from queue */
 729                         list_del_init(&pmsg->queue);
 730                 }
 731         }
 732 }
 733
 734 static void pch_spi_set_ir(struct pch_spi_data *data)
 735 {
 736         /* enable interrupts, set threshold, enable SPI */
 737         if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
 738                 /* set receive threshold to PCH_RX_THOLD */
 739                 pch_spi_setclr_reg(data->master, PCH_SPCR,
 740                                    PCH_RX_THOLD << SPCR_RFIC_FIELD |
 741                                    SPCR_FIE_BIT | SPCR_RFIE_BIT |
 742                                    SPCR_ORIE_BIT | SPCR_SPE_BIT,
 743                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
 744         else
 745                 /* set receive threshold to maximum */
 746                 pch_spi_setclr_reg(data->master, PCH_SPCR,
 747                                    PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
 748                                    SPCR_FIE_BIT | SPCR_ORIE_BIT |
 749                                    SPCR_SPE_BIT,
 750                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
 751
 752         /* Wait until the transfer completes; go to sleep after
 753                                  initiating the transfer. */
 754         dev_dbg(&data->master->dev,
 755                 "%s:waiting for transfer to get over\n", __func__);
 756
 757         wait_event_interruptible(data->wait, data->transfer_complete);
 758
 759         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
 760         dev_dbg(&data->master->dev,
 761                 "%s:no more control over SSN-writing 0 to SSNXCR.", __func__);
 762
 763         /* clear all interrupts */
 764         pch_spi_writereg(data->master, PCH_SPSR,
 765                          pch_spi_readreg(data->master, PCH_SPSR));
 766         /* Disable interrupts and SPI transfer */
 767         pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
 768         /* clear FIFO */
 769         pch_spi_clear_fifo(data->master);
 770 }
 771
 772 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
 773 {
 774         int j;
 775         u8 *rx_buf;
 776         u16 *rx_sbuf;
 777
 778         /* copy Rx Data */
 779         if (!data->cur_trans->rx_buf)
 780                 return;
 781
 782         if (bpw == 8) {
 783                 rx_buf = data->cur_trans->rx_buf;
 784                 for (j = 0; j < data->bpw_len; j++)
 785                         *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
 786         } else {
 787                 rx_sbuf = data->cur_trans->rx_buf;
 788                 for (j = 0; j < data->bpw_len; j++)
 789                         *rx_sbuf++ = data->pkt_rx_buff[j];
 790         }
 791 }
 792
 793 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
 794 {
 795         int j;
 796         u8 *rx_buf;
 797         u16 *rx_sbuf;
 798         const u8 *rx_dma_buf;
 799         const u16 *rx_dma_sbuf;
 800
 801         /* copy Rx Data */
 802         if (!data->cur_trans->rx_buf)
 803                 return;
 804
 805         if (bpw == 8) {
 806                 rx_buf = data->cur_trans->rx_buf;
 807                 rx_dma_buf = data->dma.rx_buf_virt;
 808                 for (j = 0; j < data->bpw_len; j++)
 809                         *rx_buf++ = *rx_dma_buf++ & 0xFF;
 810         } else {
 811                 rx_sbuf = data->cur_trans->rx_buf;
 812                 rx_dma_sbuf = data->dma.rx_buf_virt;
 813                 for (j = 0; j < data->bpw_len; j++)
 814                         *rx_sbuf++ = *rx_dma_sbuf++;
 815         }
 816 }
 817
 818 static void pch_spi_start_transfer(struct pch_spi_data *data)
 819 {
 820         struct pch_spi_dma_ctrl *dma;
 821         unsigned long flags;
 822
 823         dma = &data->dma;
 824
 825         spin_lock_irqsave(&data->lock, flags);
 826
 827         /* disable interrupts, SPI set enable */
 828         pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
 829
 830         spin_unlock_irqrestore(&data->lock, flags);
 831
 832         /* Wait until the transfer completes; go to sleep after
 833                                  initiating the transfer. */
 834         dev_dbg(&data->master->dev,
 835                 "%s:waiting for transfer to get over\n", __func__);
 836         wait_event_interruptible(data->wait, data->transfer_complete);
 837
 838         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
 839                             DMA_FROM_DEVICE);
 840
 841         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
 842                             DMA_FROM_DEVICE);
 843         memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
 844
 845         async_tx_ack(dma->desc_rx);
 846         async_tx_ack(dma->desc_tx);
 847         kfree(dma->sg_tx_p);
 848         kfree(dma->sg_rx_p);
 849
 850         spin_lock_irqsave(&data->lock, flags);
 851         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
 852         dev_dbg(&data->master->dev,
 853                 "%s:no more control over SSN-writing 0 to SSNXCR.", __func__);
 854
 855         /* clear fifo threshold, disable interrupts, disable SPI transfer */
 856         pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
 857                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
 858                            SPCR_SPE_BIT);
 859         /* clear all interrupts */
 860         pch_spi_writereg(data->master, PCH_SPSR,
 861                          pch_spi_readreg(data->master, PCH_SPSR));
 862         /* clear FIFO */
 863         pch_spi_clear_fifo(data->master);
 864
 865         spin_unlock_irqrestore(&data->lock, flags);
 866 }
 867
 868 static void pch_dma_rx_complete(void *arg)
 869 {
 870         struct pch_spi_data *data = arg;
 871
 872         /* transfer is completed;inform pch_spi_process_messages_dma */
 873         data->transfer_complete = true;
 874         wake_up_interruptible(&data->wait);
 875 }
 876
 877 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
 878 {
 879         struct pch_dma_slave *param = slave;
 880
 881         if ((chan->chan_id == param->chan_id) &&
 882             (param->dma_dev == chan->device->dev)) {
 883                 chan->private = param;
 884                 return true;
 885         } else {
 886                 return false;
 887         }
 888 }
 889
 890 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
 891 {
 892         dma_cap_mask_t mask;
 893         struct dma_chan *chan;
 894         struct pci_dev *dma_dev;
 895         struct pch_dma_slave *param;
 896         struct pch_spi_dma_ctrl *dma;
 897         unsigned int width;
 898
 899         if (bpw == 8)
 900                 width = PCH_DMA_WIDTH_1_BYTE;
 901         else
 902                 width = PCH_DMA_WIDTH_2_BYTES;
 903
 904         dma = &data->dma;
 905         dma_cap_zero(mask);
 906         dma_cap_set(DMA_SLAVE, mask);
 907
 908         /* Get DMA's dev information */
 909         dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(12, 0));
 910
 911         /* Set Tx DMA */
 912         param = &dma->param_tx;
 913         param->dma_dev = &dma_dev->dev;
 914         param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */
 915         param->tx_reg = data->io_base_addr + PCH_SPDWR;
 916         param->width = width;
 917         chan = dma_request_channel(mask, pch_spi_filter, param);
 918         if (!chan) {
 919                 dev_err(&data->master->dev,
 920                         "ERROR: dma_request_channel FAILS(Tx)\n");
 921                 data->use_dma = 0;
 922                 return;
 923         }
 924         dma->chan_tx = chan;
 925
 926         /* Set Rx DMA */
 927         param = &dma->param_rx;
 928         param->dma_dev = &dma_dev->dev;
 929         param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */
 930         param->rx_reg = data->io_base_addr + PCH_SPDRR;
 931         param->width = width;
 932         chan = dma_request_channel(mask, pch_spi_filter, param);
 933         if (!chan) {
 934                 dev_err(&data->master->dev,
 935                         "ERROR: dma_request_channel FAILS(Rx)\n");
 936                 dma_release_channel(dma->chan_tx);
 937                 dma->chan_tx = NULL;
 938                 data->use_dma = 0;
 939                 return;
 940         }
 941         dma->chan_rx = chan;
 942 }
 943
 944 static void pch_spi_release_dma(struct pch_spi_data *data)
 945 {
 946         struct pch_spi_dma_ctrl *dma;
 947
 948         dma = &data->dma;
 949         if (dma->chan_tx) {
 950                 dma_release_channel(dma->chan_tx);
 951                 dma->chan_tx = NULL;
 952         }
 953         if (dma->chan_rx) {
 954                 dma_release_channel(dma->chan_rx);
 955                 dma->chan_rx = NULL;
 956         }
 957         return;
 958 }
 959
 960 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
 961 {
 962         const u8 *tx_buf;
 963         const u16 *tx_sbuf;
 964         u8 *tx_dma_buf;
 965         u16 *tx_dma_sbuf;
 966         struct scatterlist *sg;
 967         struct dma_async_tx_descriptor *desc_tx;
 968         struct dma_async_tx_descriptor *desc_rx;
 969         int num;
 970         int i;
 971         int size;
 972         int rem;
 973         unsigned long flags;
 974         struct pch_spi_dma_ctrl *dma;
 975
 976         dma = &data->dma;
 977
 978         /* set baud rate if needed */
 979         if (data->cur_trans->speed_hz) {
 980                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
 981                 spin_lock_irqsave(&data->lock, flags);
 982                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
 983                 spin_unlock_irqrestore(&data->lock, flags);
 984         }
 985
 986         /* set bits per word if needed */
 987         if (data->cur_trans->bits_per_word &&
 988             (data->current_msg->spi->bits_per_word !=
 989              data->cur_trans->bits_per_word)) {
 990                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
 991                 spin_lock_irqsave(&data->lock, flags);
 992                 pch_spi_set_bits_per_word(data->master,
 993                                           data->cur_trans->bits_per_word);
 994                 spin_unlock_irqrestore(&data->lock, flags);
 995                 *bpw = data->cur_trans->bits_per_word;
 996         } else {
 997                 *bpw = data->current_msg->spi->bits_per_word;
 998         }
 999         data->bpw_len = data->cur_trans->len / (*bpw / 8);
1000
1001         /* copy Tx Data */
1002         if (data->cur_trans->tx_buf != NULL) {
1003                 if (*bpw == 8) {
1004                         tx_buf = data->cur_trans->tx_buf;
1005                         tx_dma_buf = dma->tx_buf_virt;
1006                         for (i = 0; i < data->bpw_len; i++)
1007                                 *tx_dma_buf++ = *tx_buf++;
1008                 } else {
1009                         tx_sbuf = data->cur_trans->tx_buf;
1010                         tx_dma_sbuf = dma->tx_buf_virt;
1011                         for (i = 0; i < data->bpw_len; i++)
1012                                 *tx_dma_sbuf++ = *tx_sbuf++;
1013                 }
1014         }
1015         if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
1016                 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1017                 size = PCH_DMA_TRANS_SIZE;
1018                 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
1019         } else {
1020                 num = 1;
1021                 size = data->bpw_len;
1022                 rem = data->bpw_len;
1023         }
1024         dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1025                 __func__, num, size, rem);
1026         spin_lock_irqsave(&data->lock, flags);
1027
1028         /* set receive fifo threshold and transmit fifo threshold */
1029         pch_spi_setclr_reg(data->master, PCH_SPCR,
1030                            ((size - 1) << SPCR_RFIC_FIELD) |
1031                            ((PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE) <<
1032                             SPCR_TFIC_FIELD),
1033                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1034
1035         spin_unlock_irqrestore(&data->lock, flags);
1036
1037         /* RX */
1038         dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1039         sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1040         /* offset, length setting */
1041         sg = dma->sg_rx_p;
1042         for (i = 0; i < num; i++, sg++) {
1043                 if (i == 0) {
1044                         sg->offset = 0;
1045                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1046                                     sg->offset);
1047                         sg_dma_len(sg) = rem;
1048                 } else {
1049                         sg->offset = rem + size * (i - 1);
1050                         sg->offset = sg->offset * (*bpw / 8);
1051                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1052                                     sg->offset);
1053                         sg_dma_len(sg) = size;
1054                 }
1055                 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1056         }
1057         sg = dma->sg_rx_p;
1058         desc_rx = dma->chan_rx->device->device_prep_slave_sg(dma->chan_rx, sg,
1059                                         num, DMA_FROM_DEVICE,
1060                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1061         if (!desc_rx) {
1062                 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1063                         __func__);
1064                 return;
1065         }
1066         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1067         desc_rx->callback = pch_dma_rx_complete;
1068         desc_rx->callback_param = data;
1069         dma->nent = num;
1070         dma->desc_rx = desc_rx;
1071
1072         /* TX */
1073         dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1074         sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1075         /* offset, length setting */
1076         sg = dma->sg_tx_p;
1077         for (i = 0; i < num; i++, sg++) {
1078                 if (i == 0) {
1079                         sg->offset = 0;
1080                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1081                                     sg->offset);
1082                         sg_dma_len(sg) = rem;
1083                 } else {
1084                         sg->offset = rem + size * (i - 1);
1085                         sg->offset = sg->offset * (*bpw / 8);
1086                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1087                                     sg->offset);
1088                         sg_dma_len(sg) = size;
1089                 }
1090                 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1091         }
1092         sg = dma->sg_tx_p;
1093         desc_tx = dma->chan_tx->device->device_prep_slave_sg(dma->chan_tx,
1094                                         sg, num, DMA_TO_DEVICE,
1095                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1096         if (!desc_tx) {
1097                 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1098                         __func__);
1099                 return;
1100         }
1101         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1102         desc_tx->callback = NULL;
1103         desc_tx->callback_param = data;
1104         dma->nent = num;
1105         dma->desc_tx = desc_tx;
1106
1107         dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
1108                 "0x2 to SSNXCR\n", __func__);
1109
1110         spin_lock_irqsave(&data->lock, flags);
1111         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1112         desc_rx->tx_submit(desc_rx);
1113         desc_tx->tx_submit(desc_tx);
1114         spin_unlock_irqrestore(&data->lock, flags);
1115
1116         /* reset transfer complete flag */
1117         data->transfer_complete = false;
1118 }
1119
1120 static void pch_spi_process_messages(struct work_struct *pwork)
1121 {
1122         struct spi_message *pmsg;
1123         struct pch_spi_data *data;
1124         int bpw;
1125
1126         data = container_of(pwork, struct pch_spi_data, work);
1127         dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1128
1129         spin_lock(&data->lock);
1130         /* check if suspend has been initiated;if yes flush queue */
1131         if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1132                 dev_dbg(&data->master->dev, "%s suspend/remove initiated,"
1133                         "flushing queue\n", __func__);
1134                 list_for_each_entry(pmsg, data->queue.next, queue) {
1135                         pmsg->status = -EIO;
1136
1137                         if (pmsg->complete != 0) {
1138                                 spin_unlock(&data->lock);
1139                                 pmsg->complete(pmsg->context);
1140                                 spin_lock(&data->lock);
1141                         }
1142
1143                         /* delete from queue */
1144                         list_del_init(&pmsg->queue);
1145                 }
1146
1147                 spin_unlock(&data->lock);
1148                 return;
1149         }
1150
1151         data->bcurrent_msg_processing = true;
1152         dev_dbg(&data->master->dev,
1153                 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1154
1155         /* Get the message from the queue and delete it from there. */
1156         data->current_msg = list_entry(data->queue.next, struct spi_message,
1157                                         queue);
1158
1159         list_del_init(&data->current_msg->queue);
1160
1161         data->current_msg->status = 0;
1162
1163         pch_spi_select_chip(data, data->current_msg->spi);
1164
1165         spin_unlock(&data->lock);
1166
1167         if (data->use_dma)
1168                 pch_spi_request_dma(data,
1169                                     data->current_msg->spi->bits_per_word);
1170         do {
1171                 /* If we are already processing a message get the next
1172                 transfer structure from the message otherwise retrieve
1173                 the 1st transfer request from the message. */
1174                 spin_lock(&data->lock);
1175                 if (data->cur_trans == NULL) {
1176                         data->cur_trans =
1177                                 list_entry(data->current_msg->transfers.next,
1178                                            struct spi_transfer, transfer_list);
1179                         dev_dbg(&data->master->dev, "%s "
1180                                 ":Getting 1st transfer message\n", __func__);
1181                 } else {
1182                         data->cur_trans =
1183                                 list_entry(data->cur_trans->transfer_list.next,
1184                                            struct spi_transfer, transfer_list);
1185                         dev_dbg(&data->master->dev, "%s "
1186                                 ":Getting next transfer message\n", __func__);
1187                 }
1188                 spin_unlock(&data->lock);
1189
1190                 if (data->use_dma) {
1191                         pch_spi_handle_dma(data, &bpw);
1192                         pch_spi_start_transfer(data);
1193                         pch_spi_copy_rx_data_for_dma(data, bpw);
1194                 } else {
1195                         pch_spi_set_tx(data, &bpw);
1196                         pch_spi_set_ir(data);
1197                         pch_spi_copy_rx_data(data, bpw);
1198                         kfree(data->pkt_rx_buff);
1199                         data->pkt_rx_buff = NULL;
1200                         kfree(data->pkt_tx_buff);
1201                         data->pkt_tx_buff = NULL;
1202                 }
1203                 /* increment message count */
1204                 data->current_msg->actual_length += data->cur_trans->len;
1205
1206                 dev_dbg(&data->master->dev,
1207                         "%s:data->current_msg->actual_length=%d\n",
1208                         __func__, data->current_msg->actual_length);
1209
1210                 /* check for delay */
1211                 if (data->cur_trans->delay_usecs) {
1212                         dev_dbg(&data->master->dev, "%s:"
1213                                 "delay in usec=%d\n", __func__,
1214                                 data->cur_trans->delay_usecs);
1215                         udelay(data->cur_trans->delay_usecs);
1216                 }
1217
1218                 spin_lock(&data->lock);
1219
1220                 /* No more transfer in this message. */
1221                 if ((data->cur_trans->transfer_list.next) ==
1222                     &(data->current_msg->transfers)) {
1223                         pch_spi_nomore_transfer(data);
1224                 }
1225
1226                 spin_unlock(&data->lock);
1227
1228         } while (data->cur_trans != NULL);
1229
1230         if (data->use_dma)
1231                 pch_spi_release_dma(data);
1232 }
1233
1234 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1235                                    struct pch_spi_data *data)
1236 {
1237         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1238
1239         /* free workqueue */
1240         if (data->wk != NULL) {
1241                 destroy_workqueue(data->wk);
1242                 data->wk = NULL;
1243                 dev_dbg(&board_dat->pdev->dev,
1244                         "%s destroy_workqueue invoked successfully\n",
1245                         __func__);
1246         }
1247 }
1248
1249 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1250                                  struct pch_spi_data *data)
1251 {
1252         int retval = 0;
1253
1254         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1255
1256         /* create workqueue */
1257         data->wk = create_singlethread_workqueue(KBUILD_MODNAME);
1258         if (!data->wk) {
1259                 dev_err(&board_dat->pdev->dev,
1260                         "%s create_singlet hread_workqueue failed\n", __func__);
1261                 retval = -EBUSY;
1262                 goto err_return;
1263         }
1264
1265         /* reset PCH SPI h/w */
1266         pch_spi_reset(data->master);
1267         dev_dbg(&board_dat->pdev->dev,
1268                 "%s pch_spi_reset invoked successfully\n", __func__);
1269
1270         dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1271
1272 err_return:
1273         if (retval != 0) {
1274                 dev_err(&board_dat->pdev->dev,
1275                         "%s FAIL:invoking pch_spi_free_resources\n", __func__);
1276                 pch_spi_free_resources(board_dat, data);
1277         }
1278
1279         dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
1280
1281         return retval;
1282 }
1283
1284 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1285                              struct pch_spi_data *data)
1286 {
1287         struct pch_spi_dma_ctrl *dma;
1288
1289         dma = &data->dma;
1290         if (dma->tx_buf_dma)
1291                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1292                                   dma->tx_buf_virt, dma->tx_buf_dma);
1293         if (dma->rx_buf_dma)
1294                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1295                                   dma->rx_buf_virt, dma->rx_buf_dma);
1296         return;
1297 }
1298
1299 static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1300                               struct pch_spi_data *data)
1301 {
1302         struct pch_spi_dma_ctrl *dma;
1303
1304         dma = &data->dma;
1305         /* Get Consistent memory for Tx DMA */
1306         dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1307                                 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1308         /* Get Consistent memory for Rx DMA */
1309         dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1310                                 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1311 }
1312
1313 static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
1314 {
1315         int ret;
1316         struct spi_master *master;
1317         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1318         struct pch_spi_data *data;
1319
1320         dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1321
1322         master = spi_alloc_master(&board_dat->pdev->dev,
1323                                   sizeof(struct pch_spi_data));
1324         if (!master) {
1325                 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1326                         plat_dev->id);
1327                 return -ENOMEM;
1328         }
1329
1330         data = spi_master_get_devdata(master);
1331         data->master = master;
1332
1333         platform_set_drvdata(plat_dev, data);
1334
1335         /* baseaddress + address offset) */
1336         data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1337                                          PCH_ADDRESS_SIZE * plat_dev->id;
1338         data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0) +
1339                                          PCH_ADDRESS_SIZE * plat_dev->id;
1340         if (!data->io_remap_addr) {
1341                 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1342                 ret = -ENOMEM;
1343                 goto err_pci_iomap;
1344         }
1345
1346         dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1347                 plat_dev->id, data->io_remap_addr);
1348
1349         /* initialize members of SPI master */
1350         master->bus_num = -1;
1351         master->num_chipselect = PCH_MAX_CS;
1352         master->setup = pch_spi_setup;
1353         master->transfer = pch_spi_transfer;
1354
1355         data->board_dat = board_dat;
1356         data->plat_dev = plat_dev;
1357         data->n_curnt_chip = 255;
1358         data->status = STATUS_RUNNING;
1359         data->ch = plat_dev->id;
1360         data->use_dma = use_dma;
1361
1362         INIT_LIST_HEAD(&data->queue);
1363         spin_lock_init(&data->lock);
1364         INIT_WORK(&data->work, pch_spi_process_messages);
1365         init_waitqueue_head(&data->wait);
1366
1367         ret = pch_spi_get_resources(board_dat, data);
1368         if (ret) {
1369                 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1370                 goto err_spi_get_resources;
1371         }
1372
1373         ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1374                           IRQF_SHARED, KBUILD_MODNAME, data);
1375         if (ret) {
1376                 dev_err(&plat_dev->dev,
1377                         "%s request_irq failed\n", __func__);
1378                 goto err_request_irq;
1379         }
1380         data->irq_reg_sts = true;
1381
1382         pch_spi_set_master_mode(master);
1383
1384         ret = spi_register_master(master);
1385         if (ret != 0) {
1386                 dev_err(&plat_dev->dev,
1387                         "%s spi_register_master FAILED\n", __func__);
1388                 goto err_spi_register_master;
1389         }
1390
1391         if (use_dma) {
1392                 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1393                 pch_alloc_dma_buf(board_dat, data);
1394         }
1395
1396         return 0;
1397
1398 err_spi_register_master:
1399         free_irq(board_dat->pdev->irq, board_dat);
1400 err_request_irq:
1401         pch_spi_free_resources(board_dat, data);
1402 err_spi_get_resources:
1403         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1404 err_pci_iomap:
1405         spi_master_put(master);
1406
1407         return ret;
1408 }
1409
1410 static int __devexit pch_spi_pd_remove(struct platform_device *plat_dev)
1411 {
1412         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1413         struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1414         int count;
1415         unsigned long flags;
1416
1417         dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1418                 __func__, plat_dev->id, board_dat->pdev->irq);
1419
1420         if (use_dma)
1421                 pch_free_dma_buf(board_dat, data);
1422
1423         /* check for any pending messages; no action is taken if the queue
1424          * is still full; but at least we tried.  Unload anyway */
1425         count = 500;
1426         spin_lock_irqsave(&data->lock, flags);
1427         data->status = STATUS_EXITING;
1428         while ((list_empty(&data->queue) == 0) && --count) {
1429                 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1430                         __func__);
1431                 spin_unlock_irqrestore(&data->lock, flags);
1432                 msleep(PCH_SLEEP_TIME);
1433                 spin_lock_irqsave(&data->lock, flags);
1434         }
1435         spin_unlock_irqrestore(&data->lock, flags);
1436
1437         pch_spi_free_resources(board_dat, data);
1438         /* disable interrupts & free IRQ */
1439         if (data->irq_reg_sts) {
1440                 /* disable interrupts */
1441                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1442                 data->irq_reg_sts = false;
1443                 free_irq(board_dat->pdev->irq, data);
1444         }
1445
1446         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1447         spi_unregister_master(data->master);
1448         spi_master_put(data->master);
1449         platform_set_drvdata(plat_dev, NULL);
1450
1451         return 0;
1452 }
1453 #ifdef CONFIG_PM
1454 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1455                               pm_message_t state)
1456 {
1457         u8 count;
1458         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1459         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1460
1461         dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1462
1463         if (!board_dat) {
1464                 dev_err(&pd_dev->dev,
1465                         "%s pci_get_drvdata returned NULL\n", __func__);
1466                 return -EFAULT;
1467         }
1468
1469         /* check if the current message is processed:
1470            Only after thats done the transfer will be suspended */
1471         count = 255;
1472         while ((--count) > 0) {
1473                 if (!(data->bcurrent_msg_processing))
1474                         break;
1475                 msleep(PCH_SLEEP_TIME);
1476         }
1477
1478         /* Free IRQ */
1479         if (data->irq_reg_sts) {
1480                 /* disable all interrupts */
1481                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1482                 pch_spi_reset(data->master);
1483                 free_irq(board_dat->pdev->irq, data);
1484
1485                 data->irq_reg_sts = false;
1486                 dev_dbg(&pd_dev->dev,
1487                         "%s free_irq invoked successfully.\n", __func__);
1488         }
1489
1490         return 0;
1491 }
1492
1493 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1494 {
1495         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1496         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1497         int retval;
1498
1499         if (!board_dat) {
1500                 dev_err(&pd_dev->dev,
1501                         "%s pci_get_drvdata returned NULL\n", __func__);
1502                 return -EFAULT;
1503         }
1504
1505         if (!data->irq_reg_sts) {
1506                 /* register IRQ */
1507                 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1508                                      IRQF_SHARED, KBUILD_MODNAME, data);
1509                 if (retval < 0) {
1510                         dev_err(&pd_dev->dev,
1511                                 "%s request_irq failed\n", __func__);
1512                         return retval;
1513                 }
1514
1515                 /* reset PCH SPI h/w */
1516                 pch_spi_reset(data->master);
1517                 pch_spi_set_master_mode(data->master);
1518                 data->irq_reg_sts = true;
1519         }
1520         return 0;
1521 }
1522 #else
1523 #define pch_spi_pd_suspend NULL
1524 #define pch_spi_pd_resume NULL
1525 #endif
1526
1527 static struct platform_driver pch_spi_pd_driver = {
1528         .driver = {
1529                 .name = "pch-spi",
1530                 .owner = THIS_MODULE,
1531         },
1532         .probe = pch_spi_pd_probe,
1533         .remove = __devexit_p(pch_spi_pd_remove),
1534         .suspend = pch_spi_pd_suspend,
1535         .resume = pch_spi_pd_resume
1536 };
1537
1538 static int __devinit pch_spi_probe(struct pci_dev *pdev,
1539                                    const struct pci_device_id *id)
1540 {
1541         struct pch_spi_board_data *board_dat;
1542         struct platform_device *pd_dev = NULL;
1543         int retval;
1544         int i;
1545         struct pch_pd_dev_save *pd_dev_save;
1546
1547         pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL);
1548         if (!pd_dev_save) {
1549                 dev_err(&pdev->dev, "%s Can't allocate pd_dev_sav\n", __func__);
1550                 return -ENOMEM;
1551         }
1552
1553         board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
1554         if (!board_dat) {
1555                 dev_err(&pdev->dev, "%s Can't allocate board_dat\n", __func__);
1556                 retval = -ENOMEM;
1557                 goto err_no_mem;
1558         }
1559
1560         retval = pci_request_regions(pdev, KBUILD_MODNAME);
1561         if (retval) {
1562                 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1563                 goto pci_request_regions;
1564         }
1565
1566         board_dat->pdev = pdev;
1567         board_dat->num = id->driver_data;
1568         pd_dev_save->num = id->driver_data;
1569         pd_dev_save->board_dat = board_dat;
1570
1571         retval = pci_enable_device(pdev);
1572         if (retval) {
1573                 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1574                 goto pci_enable_device;
1575         }
1576
1577         for (i = 0; i < board_dat->num; i++) {
1578                 pd_dev = platform_device_alloc("pch-spi", i);
1579                 if (!pd_dev) {
1580                         dev_err(&pdev->dev, "platform_device_alloc failed\n");
1581                         goto err_platform_device;
1582                 }
1583                 pd_dev_save->pd_save[i] = pd_dev;
1584                 pd_dev->dev.parent = &pdev->dev;
1585
1586                 retval = platform_device_add_data(pd_dev, board_dat,
1587                                                   sizeof(*board_dat));
1588                 if (retval) {
1589                         dev_err(&pdev->dev,
1590                                 "platform_device_add_data failed\n");
1591                         platform_device_put(pd_dev);
1592                         goto err_platform_device;
1593                 }
1594
1595                 retval = platform_device_add(pd_dev);
1596                 if (retval) {
1597                         dev_err(&pdev->dev, "platform_device_add failed\n");
1598                         platform_device_put(pd_dev);
1599                         goto err_platform_device;
1600                 }
1601         }
1602
1603         pci_set_drvdata(pdev, pd_dev_save);
1604
1605         return 0;
1606
1607 err_platform_device:
1608         pci_disable_device(pdev);
1609 pci_enable_device:
1610         pci_release_regions(pdev);
1611 pci_request_regions:
1612         kfree(board_dat);
1613 err_no_mem:
1614         kfree(pd_dev_save);
1615
1616         return retval;
1617 }
1618
1619 static void __devexit pch_spi_remove(struct pci_dev *pdev)
1620 {
1621         int i;
1622         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1623
1624         dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1625
1626         for (i = 0; i < pd_dev_save->num; i++)
1627                 platform_device_unregister(pd_dev_save->pd_save[i]);
1628
1629         pci_disable_device(pdev);
1630         pci_release_regions(pdev);
1631         kfree(pd_dev_save->board_dat);
1632         kfree(pd_dev_save);
1633 }
1634
1635 #ifdef CONFIG_PM
1636 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1637 {
1638         int retval;
1639         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1640
1641         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1642
1643         pd_dev_save->board_dat->suspend_sts = true;
1644
1645         /* save config space */
1646         retval = pci_save_state(pdev);
1647         if (retval == 0) {
1648                 pci_enable_wake(pdev, PCI_D3hot, 0);
1649                 pci_disable_device(pdev);
1650                 pci_set_power_state(pdev, PCI_D3hot);
1651         } else {
1652                 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1653         }
1654
1655         return retval;
1656 }
1657
1658 static int pch_spi_resume(struct pci_dev *pdev)
1659 {
1660         int retval;
1661         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1662         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1663
1664         pci_set_power_state(pdev, PCI_D0);
1665         pci_restore_state(pdev);
1666
1667         retval = pci_enable_device(pdev);
1668         if (retval < 0) {
1669                 dev_err(&pdev->dev,
1670                         "%s pci_enable_device failed\n", __func__);
1671         } else {
1672                 pci_enable_wake(pdev, PCI_D3hot, 0);
1673
1674                 /* set suspend status to false */
1675                 pd_dev_save->board_dat->suspend_sts = false;
1676         }
1677
1678         return retval;
1679 }
1680 #else
1681 #define pch_spi_suspend NULL
1682 #define pch_spi_resume NULL
1683
1684 #endif
1685
1686 static struct pci_driver pch_spi_pcidev = {
1687         .name = "pch_spi",
1688         .id_table = pch_spi_pcidev_id,
1689         .probe = pch_spi_probe,
1690         .remove = pch_spi_remove,
1691         .suspend = pch_spi_suspend,
1692         .resume = pch_spi_resume,
1693 };
1694
1695 static int __init pch_spi_init(void)
1696 {
1697         int ret;
1698         ret = platform_driver_register(&pch_spi_pd_driver);
1699         if (ret)
1700                 return ret;
1701
1702         ret = pci_register_driver(&pch_spi_pcidev);
1703         if (ret)
1704                 return ret;
1705
1706         return 0;
1707 }
1708 module_init(pch_spi_init);
1709
1710 static void __exit pch_spi_exit(void)
1711 {
1712         pci_unregister_driver(&pch_spi_pcidev);
1713         platform_driver_unregister(&pch_spi_pd_driver);
1714 }
1715 module_exit(pch_spi_exit);
1716
1717 module_param(use_dma, int, 0644);
1718 MODULE_PARM_DESC(use_dma,
1719                  "to use DMA for data transfers pass 1 else 0; default 1");
1720
1721 MODULE_LICENSE("GPL");
1722 MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7xxx IOH SPI Driver");