drivers/spi/spi-topcliff-pch.c

   1 /*
   2  * SPI bus driver for the Topcliff PCH used by Intel SoCs
   3  *
   4  * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/pci.h>
  22 #include <linux/wait.h>
  23 #include <linux/spi/spi.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sched.h>
  26 #include <linux/spi/spidev.h>
  27 #include <linux/module.h>
  28 #include <linux/device.h>
  29 #include <linux/platform_device.h>
  30
  31 #include <linux/dmaengine.h>
  32 #include <linux/pch_dma.h>
  33
  34 /* Register offsets */
  35 #define PCH_SPCR                0x00    /* SPI control register */
  36 #define PCH_SPBRR               0x04    /* SPI baud rate register */
  37 #define PCH_SPSR                0x08    /* SPI status register */
  38 #define PCH_SPDWR               0x0C    /* SPI write data register */
  39 #define PCH_SPDRR               0x10    /* SPI read data register */
  40 #define PCH_SSNXCR              0x18    /* SSN Expand Control Register */
  41 #define PCH_SRST                0x1C    /* SPI reset register */
  42 #define PCH_ADDRESS_SIZE        0x20
  43
  44 #define PCH_SPSR_TFD            0x000007C0
  45 #define PCH_SPSR_RFD            0x0000F800
  46
  47 #define PCH_READABLE(x)         (((x) & PCH_SPSR_RFD)>>11)
  48 #define PCH_WRITABLE(x)         (((x) & PCH_SPSR_TFD)>>6)
  49
  50 #define PCH_RX_THOLD            7
  51 #define PCH_RX_THOLD_MAX        15
  52
  53 #define PCH_MAX_BAUDRATE        5000000
  54 #define PCH_MAX_FIFO_DEPTH      16
  55
  56 #define STATUS_RUNNING          1
  57 #define STATUS_EXITING          2
  58 #define PCH_SLEEP_TIME          10
  59
  60 #define SSN_LOW                 0x02U
  61 #define SSN_HIGH                0x03U
  62 #define SSN_NO_CONTROL          0x00U
  63 #define PCH_MAX_CS              0xFF
  64 #define PCI_DEVICE_ID_GE_SPI    0x8816
  65
  66 #define SPCR_SPE_BIT            (1 << 0)
  67 #define SPCR_MSTR_BIT           (1 << 1)
  68 #define SPCR_LSBF_BIT           (1 << 4)
  69 #define SPCR_CPHA_BIT           (1 << 5)
  70 #define SPCR_CPOL_BIT           (1 << 6)
  71 #define SPCR_TFIE_BIT           (1 << 8)
  72 #define SPCR_RFIE_BIT           (1 << 9)
  73 #define SPCR_FIE_BIT            (1 << 10)
  74 #define SPCR_ORIE_BIT           (1 << 11)
  75 #define SPCR_MDFIE_BIT          (1 << 12)
  76 #define SPCR_FICLR_BIT          (1 << 24)
  77 #define SPSR_TFI_BIT            (1 << 0)
  78 #define SPSR_RFI_BIT            (1 << 1)
  79 #define SPSR_FI_BIT             (1 << 2)
  80 #define SPSR_ORF_BIT            (1 << 3)
  81 #define SPBRR_SIZE_BIT          (1 << 10)
  82
  83 #define PCH_ALL                 (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\
  84                                 SPCR_ORIE_BIT|SPCR_MDFIE_BIT)
  85
  86 #define SPCR_RFIC_FIELD         20
  87 #define SPCR_TFIC_FIELD         16
  88
  89 #define MASK_SPBRR_SPBR_BITS    ((1 << 10) - 1)
  90 #define MASK_RFIC_SPCR_BITS     (0xf << SPCR_RFIC_FIELD)
  91 #define MASK_TFIC_SPCR_BITS     (0xf << SPCR_TFIC_FIELD)
  92
  93 #define PCH_CLOCK_HZ            50000000
  94 #define PCH_MAX_SPBR            1023
  95
  96 /* Definition for ML7213 by OKI SEMICONDUCTOR */
  97 #define PCI_VENDOR_ID_ROHM              0x10DB
  98 #define PCI_DEVICE_ID_ML7213_SPI        0x802c
  99 #define PCI_DEVICE_ID_ML7223_SPI        0x800F
 100
 101 /*
 102  * Set the number of SPI instance max
 103  * Intel EG20T PCH :            1ch
 104  * OKI SEMICONDUCTOR ML7213 IOH :       2ch
 105  * OKI SEMICONDUCTOR ML7223 IOH :       1ch
 106 */
 107 #define PCH_SPI_MAX_DEV                 2
 108
 109 #define PCH_BUF_SIZE            4096
 110 #define PCH_DMA_TRANS_SIZE      12
 111
 112 static int use_dma = 1;
 113
 114 struct pch_spi_dma_ctrl {
 115         struct dma_async_tx_descriptor  *desc_tx;
 116         struct dma_async_tx_descriptor  *desc_rx;
 117         struct pch_dma_slave            param_tx;
 118         struct pch_dma_slave            param_rx;
 119         struct dma_chan         *chan_tx;
 120         struct dma_chan         *chan_rx;
 121         struct scatterlist              *sg_tx_p;
 122         struct scatterlist              *sg_rx_p;
 123         struct scatterlist              sg_tx;
 124         struct scatterlist              sg_rx;
 125         int                             nent;
 126         void                            *tx_buf_virt;
 127         void                            *rx_buf_virt;
 128         dma_addr_t                      tx_buf_dma;
 129         dma_addr_t                      rx_buf_dma;
 130 };
 131 /**
 132  * struct pch_spi_data - Holds the SPI channel specific details
 133  * @io_remap_addr:              The remapped PCI base address
 134  * @master:                     Pointer to the SPI master structure
 135  * @work:                       Reference to work queue handler
 136  * @wk:                         Workqueue for carrying out execution of the
 137  *                              requests
 138  * @wait:                       Wait queue for waking up upon receiving an
 139  *                              interrupt.
 140  * @transfer_complete:          Status of SPI Transfer
 141  * @bcurrent_msg_processing:    Status flag for message processing
 142  * @lock:                       Lock for protecting this structure
 143  * @queue:                      SPI Message queue
 144  * @status:                     Status of the SPI driver
 145  * @bpw_len:                    Length of data to be transferred in bits per
 146  *                              word
 147  * @transfer_active:            Flag showing active transfer
 148  * @tx_index:                   Transmit data count; for bookkeeping during
 149  *                              transfer
 150  * @rx_index:                   Receive data count; for bookkeeping during
 151  *                              transfer
 152  * @tx_buff:                    Buffer for data to be transmitted
 153  * @rx_index:                   Buffer for Received data
 154  * @n_curnt_chip:               The chip number that this SPI driver currently
 155  *                              operates on
 156  * @current_chip:               Reference to the current chip that this SPI
 157  *                              driver currently operates on
 158  * @current_msg:                The current message that this SPI driver is
 159  *                              handling
 160  * @cur_trans:                  The current transfer that this SPI driver is
 161  *                              handling
 162  * @board_dat:                  Reference to the SPI device data structure
 163  * @plat_dev:                   platform_device structure
 164  * @ch:                         SPI channel number
 165  * @irq_reg_sts:                Status of IRQ registration
 166  */
 167 struct pch_spi_data {
 168         void __iomem *io_remap_addr;
 169         unsigned long io_base_addr;
 170         struct spi_master *master;
 171         struct work_struct work;
 172         struct workqueue_struct *wk;
 173         wait_queue_head_t wait;
 174         u8 transfer_complete;
 175         u8 bcurrent_msg_processing;
 176         spinlock_t lock;
 177         struct list_head queue;
 178         u8 status;
 179         u32 bpw_len;
 180         u8 transfer_active;
 181         u32 tx_index;
 182         u32 rx_index;
 183         u16 *pkt_tx_buff;
 184         u16 *pkt_rx_buff;
 185         u8 n_curnt_chip;
 186         struct spi_device *current_chip;
 187         struct spi_message *current_msg;
 188         struct spi_transfer *cur_trans;
 189         struct pch_spi_board_data *board_dat;
 190         struct platform_device  *plat_dev;
 191         int ch;
 192         struct pch_spi_dma_ctrl dma;
 193         int use_dma;
 194         u8 irq_reg_sts;
 195 };
 196
 197 /**
 198  * struct pch_spi_board_data - Holds the SPI device specific details
 199  * @pdev:               Pointer to the PCI device
 200  * @suspend_sts:        Status of suspend
 201  * @num:                The number of SPI device instance
 202  */
 203 struct pch_spi_board_data {
 204         struct pci_dev *pdev;
 205         u8 suspend_sts;
 206         int num;
 207 };
 208
 209 struct pch_pd_dev_save {
 210         int num;
 211         struct platform_device *pd_save[PCH_SPI_MAX_DEV];
 212         struct pch_spi_board_data *board_dat;
 213 };
 214
 215 static struct pci_device_id pch_spi_pcidev_id[] = {
 216         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI),    1, },
 217         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, },
 218         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, },
 219         { }
 220 };
 221
 222 /**
 223  * pch_spi_writereg() - Performs  register writes
 224  * @master:     Pointer to struct spi_master.
 225  * @idx:        Register offset.
 226  * @val:        Value to be written to register.
 227  */
 228 static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val)
 229 {
 230         struct pch_spi_data *data = spi_master_get_devdata(master);
 231         iowrite32(val, (data->io_remap_addr + idx));
 232 }
 233
 234 /**
 235  * pch_spi_readreg() - Performs register reads
 236  * @master:     Pointer to struct spi_master.
 237  * @idx:        Register offset.
 238  */
 239 static inline u32 pch_spi_readreg(struct spi_master *master, int idx)
 240 {
 241         struct pch_spi_data *data = spi_master_get_devdata(master);
 242         return ioread32(data->io_remap_addr + idx);
 243 }
 244
 245 static inline void pch_spi_setclr_reg(struct spi_master *master, int idx,
 246                                       u32 set, u32 clr)
 247 {
 248         u32 tmp = pch_spi_readreg(master, idx);
 249         tmp = (tmp & ~clr) | set;
 250         pch_spi_writereg(master, idx, tmp);
 251 }
 252
 253 static void pch_spi_set_master_mode(struct spi_master *master)
 254 {
 255         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0);
 256 }
 257
 258 /**
 259  * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs
 260  * @master:     Pointer to struct spi_master.
 261  */
 262 static void pch_spi_clear_fifo(struct spi_master *master)
 263 {
 264         pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0);
 265         pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT);
 266 }
 267
 268 static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val,
 269                                 void __iomem *io_remap_addr)
 270 {
 271         u32 n_read, tx_index, rx_index, bpw_len;
 272         u16 *pkt_rx_buffer, *pkt_tx_buff;
 273         int read_cnt;
 274         u32 reg_spcr_val;
 275         void __iomem *spsr;
 276         void __iomem *spdrr;
 277         void __iomem *spdwr;
 278
 279         spsr = io_remap_addr + PCH_SPSR;
 280         iowrite32(reg_spsr_val, spsr);
 281
 282         if (data->transfer_active) {
 283                 rx_index = data->rx_index;
 284                 tx_index = data->tx_index;
 285                 bpw_len = data->bpw_len;
 286                 pkt_rx_buffer = data->pkt_rx_buff;
 287                 pkt_tx_buff = data->pkt_tx_buff;
 288
 289                 spdrr = io_remap_addr + PCH_SPDRR;
 290                 spdwr = io_remap_addr + PCH_SPDWR;
 291
 292                 n_read = PCH_READABLE(reg_spsr_val);
 293
 294                 for (read_cnt = 0; (read_cnt < n_read); read_cnt++) {
 295                         pkt_rx_buffer[rx_index++] = ioread32(spdrr);
 296                         if (tx_index < bpw_len)
 297                                 iowrite32(pkt_tx_buff[tx_index++], spdwr);
 298                 }
 299
 300                 /* disable RFI if not needed */
 301                 if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) {
 302                         reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR);
 303                         reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */
 304
 305                         /* reset rx threshold */
 306                         reg_spcr_val &= ~MASK_RFIC_SPCR_BITS;
 307                         reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD);
 308
 309                         iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR));
 310                 }
 311
 312                 /* update counts */
 313                 data->tx_index = tx_index;
 314                 data->rx_index = rx_index;
 315
 316         }
 317
 318         /* if transfer complete interrupt */
 319         if (reg_spsr_val & SPSR_FI_BIT) {
 320                 if ((tx_index == bpw_len) && (rx_index == tx_index)) {
 321                         /* disable interrupts */
 322                         pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
 323
 324                         /* transfer is completed;
 325                            inform pch_spi_process_messages */
 326                         data->transfer_complete = true;
 327                         data->transfer_active = false;
 328                         wake_up(&data->wait);
 329                 } else {
 330                         dev_err(&data->master->dev,
 331                                 "%s : Transfer is not completed", __func__);
 332                 }
 333         }
 334 }
 335
 336 /**
 337  * pch_spi_handler() - Interrupt handler
 338  * @irq:        The interrupt number.
 339  * @dev_id:     Pointer to struct pch_spi_board_data.
 340  */
 341 static irqreturn_t pch_spi_handler(int irq, void *dev_id)
 342 {
 343         u32 reg_spsr_val;
 344         void __iomem *spsr;
 345         void __iomem *io_remap_addr;
 346         irqreturn_t ret = IRQ_NONE;
 347         struct pch_spi_data *data = dev_id;
 348         struct pch_spi_board_data *board_dat = data->board_dat;
 349
 350         if (board_dat->suspend_sts) {
 351                 dev_dbg(&board_dat->pdev->dev,
 352                         "%s returning due to suspend\n", __func__);
 353                 return IRQ_NONE;
 354         }
 355
 356         io_remap_addr = data->io_remap_addr;
 357         spsr = io_remap_addr + PCH_SPSR;
 358
 359         reg_spsr_val = ioread32(spsr);
 360
 361         if (reg_spsr_val & SPSR_ORF_BIT) {
 362                 dev_err(&board_dat->pdev->dev, "%s Over run error\n", __func__);
 363                 if (data->current_msg->complete != 0) {
 364                         data->transfer_complete = true;
 365                         data->current_msg->status = -EIO;
 366                         data->current_msg->complete(data->current_msg->context);
 367                         data->bcurrent_msg_processing = false;
 368                         data->current_msg = NULL;
 369                         data->cur_trans = NULL;
 370                 }
 371         }
 372
 373         if (data->use_dma)
 374                 return IRQ_NONE;
 375
 376         /* Check if the interrupt is for SPI device */
 377         if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) {
 378                 pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr);
 379                 ret = IRQ_HANDLED;
 380         }
 381
 382         dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n",
 383                 __func__, ret);
 384
 385         return ret;
 386 }
 387
 388 /**
 389  * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR
 390  * @master:     Pointer to struct spi_master.
 391  * @speed_hz:   Baud rate.
 392  */
 393 static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz)
 394 {
 395         u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2);
 396
 397         /* if baud rate is less than we can support limit it */
 398         if (n_spbr > PCH_MAX_SPBR)
 399                 n_spbr = PCH_MAX_SPBR;
 400
 401         pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS);
 402 }
 403
 404 /**
 405  * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR
 406  * @master:             Pointer to struct spi_master.
 407  * @bits_per_word:      Bits per word for SPI transfer.
 408  */
 409 static void pch_spi_set_bits_per_word(struct spi_master *master,
 410                                       u8 bits_per_word)
 411 {
 412         if (bits_per_word == 8)
 413                 pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT);
 414         else
 415                 pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0);
 416 }
 417
 418 /**
 419  * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer
 420  * @spi:        Pointer to struct spi_device.
 421  */
 422 static void pch_spi_setup_transfer(struct spi_device *spi)
 423 {
 424         u32 flags = 0;
 425
 426         dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n",
 427                 __func__, pch_spi_readreg(spi->master, PCH_SPBRR),
 428                 spi->max_speed_hz);
 429         pch_spi_set_baud_rate(spi->master, spi->max_speed_hz);
 430
 431         /* set bits per word */
 432         pch_spi_set_bits_per_word(spi->master, spi->bits_per_word);
 433
 434         if (!(spi->mode & SPI_LSB_FIRST))
 435                 flags |= SPCR_LSBF_BIT;
 436         if (spi->mode & SPI_CPOL)
 437                 flags |= SPCR_CPOL_BIT;
 438         if (spi->mode & SPI_CPHA)
 439                 flags |= SPCR_CPHA_BIT;
 440         pch_spi_setclr_reg(spi->master, PCH_SPCR, flags,
 441                            (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT));
 442
 443         /* Clear the FIFO by toggling  FICLR to 1 and back to 0 */
 444         pch_spi_clear_fifo(spi->master);
 445 }
 446
 447 /**
 448  * pch_spi_reset() - Clears SPI registers
 449  * @master:     Pointer to struct spi_master.
 450  */
 451 static void pch_spi_reset(struct spi_master *master)
 452 {
 453         /* write 1 to reset SPI */
 454         pch_spi_writereg(master, PCH_SRST, 0x1);
 455
 456         /* clear reset */
 457         pch_spi_writereg(master, PCH_SRST, 0x0);
 458 }
 459
 460 static int pch_spi_setup(struct spi_device *pspi)
 461 {
 462         /* check bits per word */
 463         if (pspi->bits_per_word == 0) {
 464                 pspi->bits_per_word = 8;
 465                 dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__);
 466         }
 467
 468         if ((pspi->bits_per_word != 8) && (pspi->bits_per_word != 16)) {
 469                 dev_err(&pspi->dev, "%s Invalid bits per word\n", __func__);
 470                 return -EINVAL;
 471         }
 472
 473         /* Check baud rate setting */
 474         /* if baud rate of chip is greater than
 475            max we can support,return error */
 476         if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE)
 477                 pspi->max_speed_hz = PCH_MAX_BAUDRATE;
 478
 479         dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__,
 480                 (pspi->mode) & (SPI_CPOL | SPI_CPHA));
 481
 482         return 0;
 483 }
 484
 485 static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg)
 486 {
 487
 488         struct spi_transfer *transfer;
 489         struct pch_spi_data *data = spi_master_get_devdata(pspi->master);
 490         int retval;
 491         unsigned long flags;
 492
 493         /* validate spi message and baud rate */
 494         if (unlikely(list_empty(&pmsg->transfers) == 1)) {
 495                 dev_err(&pspi->dev, "%s list empty\n", __func__);
 496                 retval = -EINVAL;
 497                 goto err_out;
 498         }
 499
 500         if (unlikely(pspi->max_speed_hz == 0)) {
 501                 dev_err(&pspi->dev, "%s pch_spi_tranfer maxspeed=%d\n",
 502                         __func__, pspi->max_speed_hz);
 503                 retval = -EINVAL;
 504                 goto err_out;
 505         }
 506
 507         dev_dbg(&pspi->dev, "%s Transfer List not empty. "
 508                 "Transfer Speed is set.\n", __func__);
 509
 510         spin_lock_irqsave(&data->lock, flags);
 511         /* validate Tx/Rx buffers and Transfer length */
 512         list_for_each_entry(transfer, &pmsg->transfers, transfer_list) {
 513                 if (!transfer->tx_buf && !transfer->rx_buf) {
 514                         dev_err(&pspi->dev,
 515                                 "%s Tx and Rx buffer NULL\n", __func__);
 516                         retval = -EINVAL;
 517                         goto err_return_spinlock;
 518                 }
 519
 520                 if (!transfer->len) {
 521                         dev_err(&pspi->dev, "%s Transfer length invalid\n",
 522                                 __func__);
 523                         retval = -EINVAL;
 524                         goto err_return_spinlock;
 525                 }
 526
 527                 dev_dbg(&pspi->dev, "%s Tx/Rx buffer valid. Transfer length"
 528                         " valid\n", __func__);
 529
 530                 /* if baud rate has been specified validate the same */
 531                 if (transfer->speed_hz > PCH_MAX_BAUDRATE)
 532                         transfer->speed_hz = PCH_MAX_BAUDRATE;
 533
 534                 /* if bits per word has been specified validate the same */
 535                 if (transfer->bits_per_word) {
 536                         if ((transfer->bits_per_word != 8)
 537                             && (transfer->bits_per_word != 16)) {
 538                                 retval = -EINVAL;
 539                                 dev_err(&pspi->dev,
 540                                         "%s Invalid bits per word\n", __func__);
 541                                 goto err_return_spinlock;
 542                         }
 543                 }
 544         }
 545         spin_unlock_irqrestore(&data->lock, flags);
 546
 547         /* We won't process any messages if we have been asked to terminate */
 548         if (data->status == STATUS_EXITING) {
 549                 dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__);
 550                 retval = -ESHUTDOWN;
 551                 goto err_out;
 552         }
 553
 554         /* If suspended ,return -EINVAL */
 555         if (data->board_dat->suspend_sts) {
 556                 dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__);
 557                 retval = -EINVAL;
 558                 goto err_out;
 559         }
 560
 561         /* set status of message */
 562         pmsg->actual_length = 0;
 563         dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status);
 564
 565         pmsg->status = -EINPROGRESS;
 566         spin_lock_irqsave(&data->lock, flags);
 567         /* add message to queue */
 568         list_add_tail(&pmsg->queue, &data->queue);
 569         spin_unlock_irqrestore(&data->lock, flags);
 570
 571         dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__);
 572
 573         /* schedule work queue to run */
 574         queue_work(data->wk, &data->work);
 575         dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__);
 576
 577         retval = 0;
 578
 579 err_out:
 580         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
 581         return retval;
 582 err_return_spinlock:
 583         dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval);
 584         spin_unlock_irqrestore(&data->lock, flags);
 585         return retval;
 586 }
 587
 588 static inline void pch_spi_select_chip(struct pch_spi_data *data,
 589                                        struct spi_device *pspi)
 590 {
 591         if (data->current_chip != NULL) {
 592                 if (pspi->chip_select != data->n_curnt_chip) {
 593                         dev_dbg(&pspi->dev, "%s : different slave\n", __func__);
 594                         data->current_chip = NULL;
 595                 }
 596         }
 597
 598         data->current_chip = pspi;
 599
 600         data->n_curnt_chip = data->current_chip->chip_select;
 601
 602         dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__);
 603         pch_spi_setup_transfer(pspi);
 604 }
 605
 606 static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw)
 607 {
 608         int size;
 609         u32 n_writes;
 610         int j;
 611         struct spi_message *pmsg;
 612         const u8 *tx_buf;
 613         const u16 *tx_sbuf;
 614
 615         /* set baud rate if needed */
 616         if (data->cur_trans->speed_hz) {
 617                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
 618                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
 619         }
 620
 621         /* set bits per word if needed */
 622         if (data->cur_trans->bits_per_word &&
 623             (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) {
 624                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
 625                 pch_spi_set_bits_per_word(data->master,
 626                                           data->cur_trans->bits_per_word);
 627                 *bpw = data->cur_trans->bits_per_word;
 628         } else {
 629                 *bpw = data->current_msg->spi->bits_per_word;
 630         }
 631
 632         /* reset Tx/Rx index */
 633         data->tx_index = 0;
 634         data->rx_index = 0;
 635
 636         data->bpw_len = data->cur_trans->len / (*bpw / 8);
 637
 638         /* find alloc size */
 639         size = data->cur_trans->len * sizeof(*data->pkt_tx_buff);
 640
 641         /* allocate memory for pkt_tx_buff & pkt_rx_buffer */
 642         data->pkt_tx_buff = kzalloc(size, GFP_KERNEL);
 643         if (data->pkt_tx_buff != NULL) {
 644                 data->pkt_rx_buff = kzalloc(size, GFP_KERNEL);
 645                 if (!data->pkt_rx_buff)
 646                         kfree(data->pkt_tx_buff);
 647         }
 648
 649         if (!data->pkt_rx_buff) {
 650                 /* flush queue and set status of all transfers to -ENOMEM */
 651                 dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__);
 652                 list_for_each_entry(pmsg, data->queue.next, queue) {
 653                         pmsg->status = -ENOMEM;
 654
 655                         if (pmsg->complete != 0)
 656                                 pmsg->complete(pmsg->context);
 657
 658                         /* delete from queue */
 659                         list_del_init(&pmsg->queue);
 660                 }
 661                 return;
 662         }
 663
 664         /* copy Tx Data */
 665         if (data->cur_trans->tx_buf != NULL) {
 666                 if (*bpw == 8) {
 667                         tx_buf = data->cur_trans->tx_buf;
 668                         for (j = 0; j < data->bpw_len; j++)
 669                                 data->pkt_tx_buff[j] = *tx_buf++;
 670                 } else {
 671                         tx_sbuf = data->cur_trans->tx_buf;
 672                         for (j = 0; j < data->bpw_len; j++)
 673                                 data->pkt_tx_buff[j] = *tx_sbuf++;
 674                 }
 675         }
 676
 677         /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */
 678         n_writes = data->bpw_len;
 679         if (n_writes > PCH_MAX_FIFO_DEPTH)
 680                 n_writes = PCH_MAX_FIFO_DEPTH;
 681
 682         dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
 683                 "0x2 to SSNXCR\n", __func__);
 684         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
 685
 686         for (j = 0; j < n_writes; j++)
 687                 pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]);
 688
 689         /* update tx_index */
 690         data->tx_index = j;
 691
 692         /* reset transfer complete flag */
 693         data->transfer_complete = false;
 694         data->transfer_active = true;
 695 }
 696
 697 static void pch_spi_nomore_transfer(struct pch_spi_data *data)
 698 {
 699         struct spi_message *pmsg;
 700         dev_dbg(&data->master->dev, "%s called\n", __func__);
 701         /* Invoke complete callback
 702          * [To the spi core..indicating end of transfer] */
 703         data->current_msg->status = 0;
 704
 705         if (data->current_msg->complete != 0) {
 706                 dev_dbg(&data->master->dev,
 707                         "%s:Invoking callback of SPI core\n", __func__);
 708                 data->current_msg->complete(data->current_msg->context);
 709         }
 710
 711         /* update status in global variable */
 712         data->bcurrent_msg_processing = false;
 713
 714         dev_dbg(&data->master->dev,
 715                 "%s:data->bcurrent_msg_processing = false\n", __func__);
 716
 717         data->current_msg = NULL;
 718         data->cur_trans = NULL;
 719
 720         /* check if we have items in list and not suspending
 721          * return 1 if list empty */
 722         if ((list_empty(&data->queue) == 0) &&
 723             (!data->board_dat->suspend_sts) &&
 724             (data->status != STATUS_EXITING)) {
 725                 /* We have some more work to do (either there is more tranint
 726                  * bpw;sfer requests in the current message or there are
 727                  *more messages)
 728                  */
 729                 dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__);
 730                 queue_work(data->wk, &data->work);
 731         } else if (data->board_dat->suspend_sts ||
 732                    data->status == STATUS_EXITING) {
 733                 dev_dbg(&data->master->dev,
 734                         "%s suspend/remove initiated, flushing queue\n",
 735                         __func__);
 736                 list_for_each_entry(pmsg, data->queue.next, queue) {
 737                         pmsg->status = -EIO;
 738
 739                         if (pmsg->complete)
 740                                 pmsg->complete(pmsg->context);
 741
 742                         /* delete from queue */
 743                         list_del_init(&pmsg->queue);
 744                 }
 745         }
 746 }
 747
 748 static void pch_spi_set_ir(struct pch_spi_data *data)
 749 {
 750         /* enable interrupts, set threshold, enable SPI */
 751         if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH)
 752                 /* set receive threshold to PCH_RX_THOLD */
 753                 pch_spi_setclr_reg(data->master, PCH_SPCR,
 754                                    PCH_RX_THOLD << SPCR_RFIC_FIELD |
 755                                    SPCR_FIE_BIT | SPCR_RFIE_BIT |
 756                                    SPCR_ORIE_BIT | SPCR_SPE_BIT,
 757                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
 758         else
 759                 /* set receive threshold to maximum */
 760                 pch_spi_setclr_reg(data->master, PCH_SPCR,
 761                                    PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD |
 762                                    SPCR_FIE_BIT | SPCR_ORIE_BIT |
 763                                    SPCR_SPE_BIT,
 764                                    MASK_RFIC_SPCR_BITS | PCH_ALL);
 765
 766         /* Wait until the transfer completes; go to sleep after
 767                                  initiating the transfer. */
 768         dev_dbg(&data->master->dev,
 769                 "%s:waiting for transfer to get over\n", __func__);
 770
 771         wait_event_interruptible(data->wait, data->transfer_complete);
 772
 773         /* clear all interrupts */
 774         pch_spi_writereg(data->master, PCH_SPSR,
 775                          pch_spi_readreg(data->master, PCH_SPSR));
 776         /* Disable interrupts and SPI transfer */
 777         pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT);
 778         /* clear FIFO */
 779         pch_spi_clear_fifo(data->master);
 780 }
 781
 782 static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw)
 783 {
 784         int j;
 785         u8 *rx_buf;
 786         u16 *rx_sbuf;
 787
 788         /* copy Rx Data */
 789         if (!data->cur_trans->rx_buf)
 790                 return;
 791
 792         if (bpw == 8) {
 793                 rx_buf = data->cur_trans->rx_buf;
 794                 for (j = 0; j < data->bpw_len; j++)
 795                         *rx_buf++ = data->pkt_rx_buff[j] & 0xFF;
 796         } else {
 797                 rx_sbuf = data->cur_trans->rx_buf;
 798                 for (j = 0; j < data->bpw_len; j++)
 799                         *rx_sbuf++ = data->pkt_rx_buff[j];
 800         }
 801 }
 802
 803 static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw)
 804 {
 805         int j;
 806         u8 *rx_buf;
 807         u16 *rx_sbuf;
 808         const u8 *rx_dma_buf;
 809         const u16 *rx_dma_sbuf;
 810
 811         /* copy Rx Data */
 812         if (!data->cur_trans->rx_buf)
 813                 return;
 814
 815         if (bpw == 8) {
 816                 rx_buf = data->cur_trans->rx_buf;
 817                 rx_dma_buf = data->dma.rx_buf_virt;
 818                 for (j = 0; j < data->bpw_len; j++)
 819                         *rx_buf++ = *rx_dma_buf++ & 0xFF;
 820         } else {
 821                 rx_sbuf = data->cur_trans->rx_buf;
 822                 rx_dma_sbuf = data->dma.rx_buf_virt;
 823                 for (j = 0; j < data->bpw_len; j++)
 824                         *rx_sbuf++ = *rx_dma_sbuf++;
 825         }
 826 }
 827
 828 static int pch_spi_start_transfer(struct pch_spi_data *data)
 829 {
 830         struct pch_spi_dma_ctrl *dma;
 831         unsigned long flags;
 832         int rtn;
 833
 834         dma = &data->dma;
 835
 836         spin_lock_irqsave(&data->lock, flags);
 837
 838         /* disable interrupts, SPI set enable */
 839         pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL);
 840
 841         spin_unlock_irqrestore(&data->lock, flags);
 842
 843         /* Wait until the transfer completes; go to sleep after
 844                                  initiating the transfer. */
 845         dev_dbg(&data->master->dev,
 846                 "%s:waiting for transfer to get over\n", __func__);
 847         rtn = wait_event_interruptible_timeout(data->wait,
 848                                                data->transfer_complete,
 849                                                msecs_to_jiffies(2 * HZ));
 850
 851         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent,
 852                             DMA_FROM_DEVICE);
 853
 854         dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent,
 855                             DMA_FROM_DEVICE);
 856         memset(data->dma.tx_buf_virt, 0, PAGE_SIZE);
 857
 858         async_tx_ack(dma->desc_rx);
 859         async_tx_ack(dma->desc_tx);
 860         kfree(dma->sg_tx_p);
 861         kfree(dma->sg_rx_p);
 862
 863         spin_lock_irqsave(&data->lock, flags);
 864
 865         /* clear fifo threshold, disable interrupts, disable SPI transfer */
 866         pch_spi_setclr_reg(data->master, PCH_SPCR, 0,
 867                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL |
 868                            SPCR_SPE_BIT);
 869         /* clear all interrupts */
 870         pch_spi_writereg(data->master, PCH_SPSR,
 871                          pch_spi_readreg(data->master, PCH_SPSR));
 872         /* clear FIFO */
 873         pch_spi_clear_fifo(data->master);
 874
 875         spin_unlock_irqrestore(&data->lock, flags);
 876
 877         return rtn;
 878 }
 879
 880 static void pch_dma_rx_complete(void *arg)
 881 {
 882         struct pch_spi_data *data = arg;
 883
 884         /* transfer is completed;inform pch_spi_process_messages_dma */
 885         data->transfer_complete = true;
 886         wake_up_interruptible(&data->wait);
 887 }
 888
 889 static bool pch_spi_filter(struct dma_chan *chan, void *slave)
 890 {
 891         struct pch_dma_slave *param = slave;
 892
 893         if ((chan->chan_id == param->chan_id) &&
 894             (param->dma_dev == chan->device->dev)) {
 895                 chan->private = param;
 896                 return true;
 897         } else {
 898                 return false;
 899         }
 900 }
 901
 902 static void pch_spi_request_dma(struct pch_spi_data *data, int bpw)
 903 {
 904         dma_cap_mask_t mask;
 905         struct dma_chan *chan;
 906         struct pci_dev *dma_dev;
 907         struct pch_dma_slave *param;
 908         struct pch_spi_dma_ctrl *dma;
 909         unsigned int width;
 910
 911         if (bpw == 8)
 912                 width = PCH_DMA_WIDTH_1_BYTE;
 913         else
 914                 width = PCH_DMA_WIDTH_2_BYTES;
 915
 916         dma = &data->dma;
 917         dma_cap_zero(mask);
 918         dma_cap_set(DMA_SLAVE, mask);
 919
 920         /* Get DMA's dev information */
 921         dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(12, 0));
 922
 923         /* Set Tx DMA */
 924         param = &dma->param_tx;
 925         param->dma_dev = &dma_dev->dev;
 926         param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */
 927         param->tx_reg = data->io_base_addr + PCH_SPDWR;
 928         param->width = width;
 929         chan = dma_request_channel(mask, pch_spi_filter, param);
 930         if (!chan) {
 931                 dev_err(&data->master->dev,
 932                         "ERROR: dma_request_channel FAILS(Tx)\n");
 933                 data->use_dma = 0;
 934                 return;
 935         }
 936         dma->chan_tx = chan;
 937
 938         /* Set Rx DMA */
 939         param = &dma->param_rx;
 940         param->dma_dev = &dma_dev->dev;
 941         param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */
 942         param->rx_reg = data->io_base_addr + PCH_SPDRR;
 943         param->width = width;
 944         chan = dma_request_channel(mask, pch_spi_filter, param);
 945         if (!chan) {
 946                 dev_err(&data->master->dev,
 947                         "ERROR: dma_request_channel FAILS(Rx)\n");
 948                 dma_release_channel(dma->chan_tx);
 949                 dma->chan_tx = NULL;
 950                 data->use_dma = 0;
 951                 return;
 952         }
 953         dma->chan_rx = chan;
 954 }
 955
 956 static void pch_spi_release_dma(struct pch_spi_data *data)
 957 {
 958         struct pch_spi_dma_ctrl *dma;
 959
 960         dma = &data->dma;
 961         if (dma->chan_tx) {
 962                 dma_release_channel(dma->chan_tx);
 963                 dma->chan_tx = NULL;
 964         }
 965         if (dma->chan_rx) {
 966                 dma_release_channel(dma->chan_rx);
 967                 dma->chan_rx = NULL;
 968         }
 969         return;
 970 }
 971
 972 static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw)
 973 {
 974         const u8 *tx_buf;
 975         const u16 *tx_sbuf;
 976         u8 *tx_dma_buf;
 977         u16 *tx_dma_sbuf;
 978         struct scatterlist *sg;
 979         struct dma_async_tx_descriptor *desc_tx;
 980         struct dma_async_tx_descriptor *desc_rx;
 981         int num;
 982         int i;
 983         int size;
 984         int rem;
 985         unsigned long flags;
 986         struct pch_spi_dma_ctrl *dma;
 987
 988         dma = &data->dma;
 989
 990         /* set baud rate if needed */
 991         if (data->cur_trans->speed_hz) {
 992                 dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__);
 993                 spin_lock_irqsave(&data->lock, flags);
 994                 pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz);
 995                 spin_unlock_irqrestore(&data->lock, flags);
 996         }
 997
 998         /* set bits per word if needed */
 999         if (data->cur_trans->bits_per_word &&
1000             (data->current_msg->spi->bits_per_word !=
1001              data->cur_trans->bits_per_word)) {
1002                 dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__);
1003                 spin_lock_irqsave(&data->lock, flags);
1004                 pch_spi_set_bits_per_word(data->master,
1005                                           data->cur_trans->bits_per_word);
1006                 spin_unlock_irqrestore(&data->lock, flags);
1007                 *bpw = data->cur_trans->bits_per_word;
1008         } else {
1009                 *bpw = data->current_msg->spi->bits_per_word;
1010         }
1011         data->bpw_len = data->cur_trans->len / (*bpw / 8);
1012
1013         /* copy Tx Data */
1014         if (data->cur_trans->tx_buf != NULL) {
1015                 if (*bpw == 8) {
1016                         tx_buf = data->cur_trans->tx_buf;
1017                         tx_dma_buf = dma->tx_buf_virt;
1018                         for (i = 0; i < data->bpw_len; i++)
1019                                 *tx_dma_buf++ = *tx_buf++;
1020                 } else {
1021                         tx_sbuf = data->cur_trans->tx_buf;
1022                         tx_dma_sbuf = dma->tx_buf_virt;
1023                         for (i = 0; i < data->bpw_len; i++)
1024                                 *tx_dma_sbuf++ = *tx_sbuf++;
1025                 }
1026         }
1027         if (data->bpw_len > PCH_DMA_TRANS_SIZE) {
1028                 num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1;
1029                 size = PCH_DMA_TRANS_SIZE;
1030                 rem = data->bpw_len % PCH_DMA_TRANS_SIZE;
1031         } else {
1032                 num = 1;
1033                 size = data->bpw_len;
1034                 rem = data->bpw_len;
1035         }
1036         dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n",
1037                 __func__, num, size, rem);
1038         spin_lock_irqsave(&data->lock, flags);
1039
1040         /* set receive fifo threshold and transmit fifo threshold */
1041         pch_spi_setclr_reg(data->master, PCH_SPCR,
1042                            ((size - 1) << SPCR_RFIC_FIELD) |
1043                            ((PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE) <<
1044                             SPCR_TFIC_FIELD),
1045                            MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS);
1046
1047         spin_unlock_irqrestore(&data->lock, flags);
1048
1049         /* RX */
1050         dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1051         sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */
1052         /* offset, length setting */
1053         sg = dma->sg_rx_p;
1054         for (i = 0; i < num; i++, sg++) {
1055                 if (i == 0) {
1056                         sg->offset = 0;
1057                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem,
1058                                     sg->offset);
1059                         sg_dma_len(sg) = rem;
1060                 } else {
1061                         sg->offset = rem + size * (i - 1);
1062                         sg->offset = sg->offset * (*bpw / 8);
1063                         sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size,
1064                                     sg->offset);
1065                         sg_dma_len(sg) = size;
1066                 }
1067                 sg_dma_address(sg) = dma->rx_buf_dma + sg->offset;
1068         }
1069         sg = dma->sg_rx_p;
1070         desc_rx = dma->chan_rx->device->device_prep_slave_sg(dma->chan_rx, sg,
1071                                         num, DMA_FROM_DEVICE,
1072                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1073         if (!desc_rx) {
1074                 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1075                         __func__);
1076                 return;
1077         }
1078         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE);
1079         desc_rx->callback = pch_dma_rx_complete;
1080         desc_rx->callback_param = data;
1081         dma->nent = num;
1082         dma->desc_rx = desc_rx;
1083
1084         /* TX */
1085         dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1086         sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */
1087         /* offset, length setting */
1088         sg = dma->sg_tx_p;
1089         for (i = 0; i < num; i++, sg++) {
1090                 if (i == 0) {
1091                         sg->offset = 0;
1092                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem,
1093                                     sg->offset);
1094                         sg_dma_len(sg) = rem;
1095                 } else {
1096                         sg->offset = rem + size * (i - 1);
1097                         sg->offset = sg->offset * (*bpw / 8);
1098                         sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size,
1099                                     sg->offset);
1100                         sg_dma_len(sg) = size;
1101                 }
1102                 sg_dma_address(sg) = dma->tx_buf_dma + sg->offset;
1103         }
1104         sg = dma->sg_tx_p;
1105         desc_tx = dma->chan_tx->device->device_prep_slave_sg(dma->chan_tx,
1106                                         sg, num, DMA_TO_DEVICE,
1107                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1108         if (!desc_tx) {
1109                 dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n",
1110                         __func__);
1111                 return;
1112         }
1113         dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE);
1114         desc_tx->callback = NULL;
1115         desc_tx->callback_param = data;
1116         dma->nent = num;
1117         dma->desc_tx = desc_tx;
1118
1119         dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing "
1120                 "0x2 to SSNXCR\n", __func__);
1121
1122         spin_lock_irqsave(&data->lock, flags);
1123         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW);
1124         desc_rx->tx_submit(desc_rx);
1125         desc_tx->tx_submit(desc_tx);
1126         spin_unlock_irqrestore(&data->lock, flags);
1127
1128         /* reset transfer complete flag */
1129         data->transfer_complete = false;
1130 }
1131
1132 static void pch_spi_process_messages(struct work_struct *pwork)
1133 {
1134         struct spi_message *pmsg;
1135         struct pch_spi_data *data;
1136         int bpw;
1137
1138         data = container_of(pwork, struct pch_spi_data, work);
1139         dev_dbg(&data->master->dev, "%s data initialized\n", __func__);
1140
1141         spin_lock(&data->lock);
1142         /* check if suspend has been initiated;if yes flush queue */
1143         if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) {
1144                 dev_dbg(&data->master->dev, "%s suspend/remove initiated,"
1145                         "flushing queue\n", __func__);
1146                 list_for_each_entry(pmsg, data->queue.next, queue) {
1147                         pmsg->status = -EIO;
1148
1149                         if (pmsg->complete != 0) {
1150                                 spin_unlock(&data->lock);
1151                                 pmsg->complete(pmsg->context);
1152                                 spin_lock(&data->lock);
1153                         }
1154
1155                         /* delete from queue */
1156                         list_del_init(&pmsg->queue);
1157                 }
1158
1159                 spin_unlock(&data->lock);
1160                 return;
1161         }
1162
1163         data->bcurrent_msg_processing = true;
1164         dev_dbg(&data->master->dev,
1165                 "%s Set data->bcurrent_msg_processing= true\n", __func__);
1166
1167         /* Get the message from the queue and delete it from there. */
1168         data->current_msg = list_entry(data->queue.next, struct spi_message,
1169                                         queue);
1170
1171         list_del_init(&data->current_msg->queue);
1172
1173         data->current_msg->status = 0;
1174
1175         pch_spi_select_chip(data, data->current_msg->spi);
1176
1177         spin_unlock(&data->lock);
1178
1179         if (data->use_dma)
1180                 pch_spi_request_dma(data,
1181                                     data->current_msg->spi->bits_per_word);
1182         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL);
1183         do {
1184                 /* If we are already processing a message get the next
1185                 transfer structure from the message otherwise retrieve
1186                 the 1st transfer request from the message. */
1187                 spin_lock(&data->lock);
1188                 if (data->cur_trans == NULL) {
1189                         data->cur_trans =
1190                                 list_entry(data->current_msg->transfers.next,
1191                                            struct spi_transfer, transfer_list);
1192                         dev_dbg(&data->master->dev, "%s "
1193                                 ":Getting 1st transfer message\n", __func__);
1194                 } else {
1195                         data->cur_trans =
1196                                 list_entry(data->cur_trans->transfer_list.next,
1197                                            struct spi_transfer, transfer_list);
1198                         dev_dbg(&data->master->dev, "%s "
1199                                 ":Getting next transfer message\n", __func__);
1200                 }
1201                 spin_unlock(&data->lock);
1202
1203                 if (data->use_dma) {
1204                         pch_spi_handle_dma(data, &bpw);
1205                         if (!pch_spi_start_transfer(data))
1206                                 goto out;
1207                         pch_spi_copy_rx_data_for_dma(data, bpw);
1208                 } else {
1209                         pch_spi_set_tx(data, &bpw);
1210                         pch_spi_set_ir(data);
1211                         pch_spi_copy_rx_data(data, bpw);
1212                         kfree(data->pkt_rx_buff);
1213                         data->pkt_rx_buff = NULL;
1214                         kfree(data->pkt_tx_buff);
1215                         data->pkt_tx_buff = NULL;
1216                 }
1217                 /* increment message count */
1218                 data->current_msg->actual_length += data->cur_trans->len;
1219
1220                 dev_dbg(&data->master->dev,
1221                         "%s:data->current_msg->actual_length=%d\n",
1222                         __func__, data->current_msg->actual_length);
1223
1224                 /* check for delay */
1225                 if (data->cur_trans->delay_usecs) {
1226                         dev_dbg(&data->master->dev, "%s:"
1227                                 "delay in usec=%d\n", __func__,
1228                                 data->cur_trans->delay_usecs);
1229                         udelay(data->cur_trans->delay_usecs);
1230                 }
1231
1232                 spin_lock(&data->lock);
1233
1234                 /* No more transfer in this message. */
1235                 if ((data->cur_trans->transfer_list.next) ==
1236                     &(data->current_msg->transfers)) {
1237                         pch_spi_nomore_transfer(data);
1238                 }
1239
1240                 spin_unlock(&data->lock);
1241
1242         } while (data->cur_trans != NULL);
1243
1244 out:
1245         pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH);
1246         if (data->use_dma)
1247                 pch_spi_release_dma(data);
1248 }
1249
1250 static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
1251                                    struct pch_spi_data *data)
1252 {
1253         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1254
1255         /* free workqueue */
1256         if (data->wk != NULL) {
1257                 destroy_workqueue(data->wk);
1258                 data->wk = NULL;
1259                 dev_dbg(&board_dat->pdev->dev,
1260                         "%s destroy_workqueue invoked successfully\n",
1261                         __func__);
1262         }
1263 }
1264
1265 static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
1266                                  struct pch_spi_data *data)
1267 {
1268         int retval = 0;
1269
1270         dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
1271
1272         /* create workqueue */
1273         data->wk = create_singlethread_workqueue(KBUILD_MODNAME);
1274         if (!data->wk) {
1275                 dev_err(&board_dat->pdev->dev,
1276                         "%s create_singlet hread_workqueue failed\n", __func__);
1277                 retval = -EBUSY;
1278                 goto err_return;
1279         }
1280
1281         /* reset PCH SPI h/w */
1282         pch_spi_reset(data->master);
1283         dev_dbg(&board_dat->pdev->dev,
1284                 "%s pch_spi_reset invoked successfully\n", __func__);
1285
1286         dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
1287
1288 err_return:
1289         if (retval != 0) {
1290                 dev_err(&board_dat->pdev->dev,
1291                         "%s FAIL:invoking pch_spi_free_resources\n", __func__);
1292                 pch_spi_free_resources(board_dat, data);
1293         }
1294
1295         dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
1296
1297         return retval;
1298 }
1299
1300 static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
1301                              struct pch_spi_data *data)
1302 {
1303         struct pch_spi_dma_ctrl *dma;
1304
1305         dma = &data->dma;
1306         if (dma->tx_buf_dma)
1307                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1308                                   dma->tx_buf_virt, dma->tx_buf_dma);
1309         if (dma->rx_buf_dma)
1310                 dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE,
1311                                   dma->rx_buf_virt, dma->rx_buf_dma);
1312         return;
1313 }
1314
1315 static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat,
1316                               struct pch_spi_data *data)
1317 {
1318         struct pch_spi_dma_ctrl *dma;
1319
1320         dma = &data->dma;
1321         /* Get Consistent memory for Tx DMA */
1322         dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1323                                 PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL);
1324         /* Get Consistent memory for Rx DMA */
1325         dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev,
1326                                 PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL);
1327 }
1328
1329 static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
1330 {
1331         int ret;
1332         struct spi_master *master;
1333         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1334         struct pch_spi_data *data;
1335
1336         dev_dbg(&plat_dev->dev, "%s:debug\n", __func__);
1337
1338         master = spi_alloc_master(&board_dat->pdev->dev,
1339                                   sizeof(struct pch_spi_data));
1340         if (!master) {
1341                 dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n",
1342                         plat_dev->id);
1343                 return -ENOMEM;
1344         }
1345
1346         data = spi_master_get_devdata(master);
1347         data->master = master;
1348
1349         platform_set_drvdata(plat_dev, data);
1350
1351         /* baseaddress + address offset) */
1352         data->io_base_addr = pci_resource_start(board_dat->pdev, 1) +
1353                                          PCH_ADDRESS_SIZE * plat_dev->id;
1354         data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0) +
1355                                          PCH_ADDRESS_SIZE * plat_dev->id;
1356         if (!data->io_remap_addr) {
1357                 dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__);
1358                 ret = -ENOMEM;
1359                 goto err_pci_iomap;
1360         }
1361
1362         dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n",
1363                 plat_dev->id, data->io_remap_addr);
1364
1365         /* initialize members of SPI master */
1366         master->bus_num = -1;
1367         master->num_chipselect = PCH_MAX_CS;
1368         master->setup = pch_spi_setup;
1369         master->transfer = pch_spi_transfer;
1370
1371         data->board_dat = board_dat;
1372         data->plat_dev = plat_dev;
1373         data->n_curnt_chip = 255;
1374         data->status = STATUS_RUNNING;
1375         data->ch = plat_dev->id;
1376         data->use_dma = use_dma;
1377
1378         INIT_LIST_HEAD(&data->queue);
1379         spin_lock_init(&data->lock);
1380         INIT_WORK(&data->work, pch_spi_process_messages);
1381         init_waitqueue_head(&data->wait);
1382
1383         ret = pch_spi_get_resources(board_dat, data);
1384         if (ret) {
1385                 dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret);
1386                 goto err_spi_get_resources;
1387         }
1388
1389         ret = request_irq(board_dat->pdev->irq, pch_spi_handler,
1390                           IRQF_SHARED, KBUILD_MODNAME, data);
1391         if (ret) {
1392                 dev_err(&plat_dev->dev,
1393                         "%s request_irq failed\n", __func__);
1394                 goto err_request_irq;
1395         }
1396         data->irq_reg_sts = true;
1397
1398         pch_spi_set_master_mode(master);
1399
1400         ret = spi_register_master(master);
1401         if (ret != 0) {
1402                 dev_err(&plat_dev->dev,
1403                         "%s spi_register_master FAILED\n", __func__);
1404                 goto err_spi_register_master;
1405         }
1406
1407         if (use_dma) {
1408                 dev_info(&plat_dev->dev, "Use DMA for data transfers\n");
1409                 pch_alloc_dma_buf(board_dat, data);
1410         }
1411
1412         return 0;
1413
1414 err_spi_register_master:
1415         free_irq(board_dat->pdev->irq, board_dat);
1416 err_request_irq:
1417         pch_spi_free_resources(board_dat, data);
1418 err_spi_get_resources:
1419         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1420 err_pci_iomap:
1421         spi_master_put(master);
1422
1423         return ret;
1424 }
1425
1426 static int __devexit pch_spi_pd_remove(struct platform_device *plat_dev)
1427 {
1428         struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev);
1429         struct pch_spi_data *data = platform_get_drvdata(plat_dev);
1430         int count;
1431         unsigned long flags;
1432
1433         dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n",
1434                 __func__, plat_dev->id, board_dat->pdev->irq);
1435
1436         if (use_dma)
1437                 pch_free_dma_buf(board_dat, data);
1438
1439         /* check for any pending messages; no action is taken if the queue
1440          * is still full; but at least we tried.  Unload anyway */
1441         count = 500;
1442         spin_lock_irqsave(&data->lock, flags);
1443         data->status = STATUS_EXITING;
1444         while ((list_empty(&data->queue) == 0) && --count) {
1445                 dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n",
1446                         __func__);
1447                 spin_unlock_irqrestore(&data->lock, flags);
1448                 msleep(PCH_SLEEP_TIME);
1449                 spin_lock_irqsave(&data->lock, flags);
1450         }
1451         spin_unlock_irqrestore(&data->lock, flags);
1452
1453         pch_spi_free_resources(board_dat, data);
1454         /* disable interrupts & free IRQ */
1455         if (data->irq_reg_sts) {
1456                 /* disable interrupts */
1457                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1458                 data->irq_reg_sts = false;
1459                 free_irq(board_dat->pdev->irq, data);
1460         }
1461
1462         pci_iounmap(board_dat->pdev, data->io_remap_addr);
1463         spi_unregister_master(data->master);
1464         spi_master_put(data->master);
1465         platform_set_drvdata(plat_dev, NULL);
1466
1467         return 0;
1468 }
1469 #ifdef CONFIG_PM
1470 static int pch_spi_pd_suspend(struct platform_device *pd_dev,
1471                               pm_message_t state)
1472 {
1473         u8 count;
1474         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1475         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1476
1477         dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__);
1478
1479         if (!board_dat) {
1480                 dev_err(&pd_dev->dev,
1481                         "%s pci_get_drvdata returned NULL\n", __func__);
1482                 return -EFAULT;
1483         }
1484
1485         /* check if the current message is processed:
1486            Only after thats done the transfer will be suspended */
1487         count = 255;
1488         while ((--count) > 0) {
1489                 if (!(data->bcurrent_msg_processing))
1490                         break;
1491                 msleep(PCH_SLEEP_TIME);
1492         }
1493
1494         /* Free IRQ */
1495         if (data->irq_reg_sts) {
1496                 /* disable all interrupts */
1497                 pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL);
1498                 pch_spi_reset(data->master);
1499                 free_irq(board_dat->pdev->irq, data);
1500
1501                 data->irq_reg_sts = false;
1502                 dev_dbg(&pd_dev->dev,
1503                         "%s free_irq invoked successfully.\n", __func__);
1504         }
1505
1506         return 0;
1507 }
1508
1509 static int pch_spi_pd_resume(struct platform_device *pd_dev)
1510 {
1511         struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev);
1512         struct pch_spi_data *data = platform_get_drvdata(pd_dev);
1513         int retval;
1514
1515         if (!board_dat) {
1516                 dev_err(&pd_dev->dev,
1517                         "%s pci_get_drvdata returned NULL\n", __func__);
1518                 return -EFAULT;
1519         }
1520
1521         if (!data->irq_reg_sts) {
1522                 /* register IRQ */
1523                 retval = request_irq(board_dat->pdev->irq, pch_spi_handler,
1524                                      IRQF_SHARED, KBUILD_MODNAME, data);
1525                 if (retval < 0) {
1526                         dev_err(&pd_dev->dev,
1527                                 "%s request_irq failed\n", __func__);
1528                         return retval;
1529                 }
1530
1531                 /* reset PCH SPI h/w */
1532                 pch_spi_reset(data->master);
1533                 pch_spi_set_master_mode(data->master);
1534                 data->irq_reg_sts = true;
1535         }
1536         return 0;
1537 }
1538 #else
1539 #define pch_spi_pd_suspend NULL
1540 #define pch_spi_pd_resume NULL
1541 #endif
1542
1543 static struct platform_driver pch_spi_pd_driver = {
1544         .driver = {
1545                 .name = "pch-spi",
1546                 .owner = THIS_MODULE,
1547         },
1548         .probe = pch_spi_pd_probe,
1549         .remove = __devexit_p(pch_spi_pd_remove),
1550         .suspend = pch_spi_pd_suspend,
1551         .resume = pch_spi_pd_resume
1552 };
1553
1554 static int __devinit pch_spi_probe(struct pci_dev *pdev,
1555                                    const struct pci_device_id *id)
1556 {
1557         struct pch_spi_board_data *board_dat;
1558         struct platform_device *pd_dev = NULL;
1559         int retval;
1560         int i;
1561         struct pch_pd_dev_save *pd_dev_save;
1562
1563         pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL);
1564         if (!pd_dev_save) {
1565                 dev_err(&pdev->dev, "%s Can't allocate pd_dev_sav\n", __func__);
1566                 return -ENOMEM;
1567         }
1568
1569         board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL);
1570         if (!board_dat) {
1571                 dev_err(&pdev->dev, "%s Can't allocate board_dat\n", __func__);
1572                 retval = -ENOMEM;
1573                 goto err_no_mem;
1574         }
1575
1576         retval = pci_request_regions(pdev, KBUILD_MODNAME);
1577         if (retval) {
1578                 dev_err(&pdev->dev, "%s request_region failed\n", __func__);
1579                 goto pci_request_regions;
1580         }
1581
1582         board_dat->pdev = pdev;
1583         board_dat->num = id->driver_data;
1584         pd_dev_save->num = id->driver_data;
1585         pd_dev_save->board_dat = board_dat;
1586
1587         retval = pci_enable_device(pdev);
1588         if (retval) {
1589                 dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__);
1590                 goto pci_enable_device;
1591         }
1592
1593         for (i = 0; i < board_dat->num; i++) {
1594                 pd_dev = platform_device_alloc("pch-spi", i);
1595                 if (!pd_dev) {
1596                         dev_err(&pdev->dev, "platform_device_alloc failed\n");
1597                         goto err_platform_device;
1598                 }
1599                 pd_dev_save->pd_save[i] = pd_dev;
1600                 pd_dev->dev.parent = &pdev->dev;
1601
1602                 retval = platform_device_add_data(pd_dev, board_dat,
1603                                                   sizeof(*board_dat));
1604                 if (retval) {
1605                         dev_err(&pdev->dev,
1606                                 "platform_device_add_data failed\n");
1607                         platform_device_put(pd_dev);
1608                         goto err_platform_device;
1609                 }
1610
1611                 retval = platform_device_add(pd_dev);
1612                 if (retval) {
1613                         dev_err(&pdev->dev, "platform_device_add failed\n");
1614                         platform_device_put(pd_dev);
1615                         goto err_platform_device;
1616                 }
1617         }
1618
1619         pci_set_drvdata(pdev, pd_dev_save);
1620
1621         return 0;
1622
1623 err_platform_device:
1624         pci_disable_device(pdev);
1625 pci_enable_device:
1626         pci_release_regions(pdev);
1627 pci_request_regions:
1628         kfree(board_dat);
1629 err_no_mem:
1630         kfree(pd_dev_save);
1631
1632         return retval;
1633 }
1634
1635 static void __devexit pch_spi_remove(struct pci_dev *pdev)
1636 {
1637         int i;
1638         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1639
1640         dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev);
1641
1642         for (i = 0; i < pd_dev_save->num; i++)
1643                 platform_device_unregister(pd_dev_save->pd_save[i]);
1644
1645         pci_disable_device(pdev);
1646         pci_release_regions(pdev);
1647         kfree(pd_dev_save->board_dat);
1648         kfree(pd_dev_save);
1649 }
1650
1651 #ifdef CONFIG_PM
1652 static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state)
1653 {
1654         int retval;
1655         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1656
1657         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1658
1659         pd_dev_save->board_dat->suspend_sts = true;
1660
1661         /* save config space */
1662         retval = pci_save_state(pdev);
1663         if (retval == 0) {
1664                 pci_enable_wake(pdev, PCI_D3hot, 0);
1665                 pci_disable_device(pdev);
1666                 pci_set_power_state(pdev, PCI_D3hot);
1667         } else {
1668                 dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__);
1669         }
1670
1671         return retval;
1672 }
1673
1674 static int pch_spi_resume(struct pci_dev *pdev)
1675 {
1676         int retval;
1677         struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev);
1678         dev_dbg(&pdev->dev, "%s ENTRY\n", __func__);
1679
1680         pci_set_power_state(pdev, PCI_D0);
1681         pci_restore_state(pdev);
1682
1683         retval = pci_enable_device(pdev);
1684         if (retval < 0) {
1685                 dev_err(&pdev->dev,
1686                         "%s pci_enable_device failed\n", __func__);
1687         } else {
1688                 pci_enable_wake(pdev, PCI_D3hot, 0);
1689
1690                 /* set suspend status to false */
1691                 pd_dev_save->board_dat->suspend_sts = false;
1692         }
1693
1694         return retval;
1695 }
1696 #else
1697 #define pch_spi_suspend NULL
1698 #define pch_spi_resume NULL
1699
1700 #endif
1701
1702 static struct pci_driver pch_spi_pcidev = {
1703         .name = "pch_spi",
1704         .id_table = pch_spi_pcidev_id,
1705         .probe = pch_spi_probe,
1706         .remove = pch_spi_remove,
1707         .suspend = pch_spi_suspend,
1708         .resume = pch_spi_resume,
1709 };
1710
1711 static int __init pch_spi_init(void)
1712 {
1713         int ret;
1714         ret = platform_driver_register(&pch_spi_pd_driver);
1715         if (ret)
1716                 return ret;
1717
1718         ret = pci_register_driver(&pch_spi_pcidev);
1719         if (ret)
1720                 return ret;
1721
1722         return 0;
1723 }
1724 module_init(pch_spi_init);
1725
1726 static void __exit pch_spi_exit(void)
1727 {
1728         pci_unregister_driver(&pch_spi_pcidev);
1729         platform_driver_unregister(&pch_spi_pd_driver);
1730 }
1731 module_exit(pch_spi_exit);
1732
1733 module_param(use_dma, int, 0644);
1734 MODULE_PARM_DESC(use_dma,
1735                  "to use DMA for data transfers pass 1 else 0; default 1");
1736
1737 MODULE_LICENSE("GPL");
1738 MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7xxx IOH SPI Driver");