drivers/spi/spi-imx.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright (C) 2008 Juergen Beisert
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the
  16  * Free Software Foundation
  17  * 51 Franklin Street, Fifth Floor
  18  * Boston, MA  02110-1301, USA.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/completion.h>
  23 #include <linux/delay.h>
  24 #include <linux/err.h>
  25 #include <linux/gpio.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/irq.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/slab.h>
  34 #include <linux/spi/spi.h>
  35 #include <linux/spi/spi_bitbang.h>
  36 #include <linux/types.h>
  37
  38 #include <mach/spi.h>
  39
  40 #define DRIVER_NAME "spi_imx"
  41
  42 #define MXC_CSPIRXDATA          0x00
  43 #define MXC_CSPITXDATA          0x04
  44 #define MXC_CSPICTRL            0x08
  45 #define MXC_CSPIINT             0x0c
  46 #define MXC_RESET               0x1c
  47
  48 #define MX3_CSPISTAT            0x14
  49 #define MX3_CSPISTAT_RR         (1 << 3)
  50
  51 /* generic defines to abstract from the different register layouts */
  52 #define MXC_INT_RR      (1 << 0) /* Receive data ready interrupt */
  53 #define MXC_INT_TE      (1 << 1) /* Transmit FIFO empty interrupt */
  54
  55 struct spi_imx_config {
  56         unsigned int speed_hz;
  57         unsigned int bpw;
  58         unsigned int mode;
  59         u8 cs;
  60 };
  61
  62 enum spi_imx_devtype {
  63         SPI_IMX_VER_IMX1,
  64         SPI_IMX_VER_0_0,
  65         SPI_IMX_VER_0_4,
  66         SPI_IMX_VER_0_5,
  67         SPI_IMX_VER_0_7,
  68         SPI_IMX_VER_2_3,
  69 };
  70
  71 struct spi_imx_data;
  72
  73 struct spi_imx_devtype_data {
  74         void (*intctrl)(struct spi_imx_data *, int);
  75         int (*config)(struct spi_imx_data *, struct spi_imx_config *);
  76         void (*trigger)(struct spi_imx_data *);
  77         int (*rx_available)(struct spi_imx_data *);
  78         void (*reset)(struct spi_imx_data *);
  79         unsigned int fifosize;
  80 };
  81
  82 struct spi_imx_data {
  83         struct spi_bitbang bitbang;
  84
  85         struct completion xfer_done;
  86         void *base;
  87         int irq;
  88         struct clk *clk;
  89         unsigned long spi_clk;
  90         int *chipselect;
  91
  92         unsigned int count;
  93         void (*tx)(struct spi_imx_data *);
  94         void (*rx)(struct spi_imx_data *);
  95         void *rx_buf;
  96         const void *tx_buf;
  97         unsigned int txfifo; /* number of words pushed in tx FIFO */
  98
  99         struct spi_imx_devtype_data *devtype_data;
 100 };
 101
 102 #define MXC_SPI_BUF_RX(type)                                            \
 103 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)         \
 104 {                                                                       \
 105         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);       \
 106                                                                         \
 107         if (spi_imx->rx_buf) {                                          \
 108                 *(type *)spi_imx->rx_buf = val;                         \
 109                 spi_imx->rx_buf += sizeof(type);                        \
 110         }                                                               \
 111 }
 112
 113 #define MXC_SPI_BUF_TX(type)                                            \
 114 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)         \
 115 {                                                                       \
 116         type val = 0;                                                   \
 117                                                                         \
 118         if (spi_imx->tx_buf) {                                          \
 119                 val = *(type *)spi_imx->tx_buf;                         \
 120                 spi_imx->tx_buf += sizeof(type);                        \
 121         }                                                               \
 122                                                                         \
 123         spi_imx->count -= sizeof(type);                                 \
 124                                                                         \
 125         writel(val, spi_imx->base + MXC_CSPITXDATA);                    \
 126 }
 127
 128 MXC_SPI_BUF_RX(u8)
 129 MXC_SPI_BUF_TX(u8)
 130 MXC_SPI_BUF_RX(u16)
 131 MXC_SPI_BUF_TX(u16)
 132 MXC_SPI_BUF_RX(u32)
 133 MXC_SPI_BUF_TX(u32)
 134
 135 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
 136  * (which is currently not the case in this driver)
 137  */
 138 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
 139         256, 384, 512, 768, 1024};
 140
 141 /* MX21, MX27 */
 142 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
 143                 unsigned int fspi)
 144 {
 145         int i, max;
 146
 147         if (cpu_is_mx21())
 148                 max = 18;
 149         else
 150                 max = 16;
 151
 152         for (i = 2; i < max; i++)
 153                 if (fspi * mxc_clkdivs[i] >= fin)
 154                         return i;
 155
 156         return max;
 157 }
 158
 159 /* MX1, MX31, MX35, MX51 CSPI */
 160 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 161                 unsigned int fspi)
 162 {
 163         int i, div = 4;
 164
 165         for (i = 0; i < 7; i++) {
 166                 if (fspi * div >= fin)
 167                         return i;
 168                 div <<= 1;
 169         }
 170
 171         return 7;
 172 }
 173
 174 #define MX51_ECSPI_CTRL         0x08
 175 #define MX51_ECSPI_CTRL_ENABLE          (1 <<  0)
 176 #define MX51_ECSPI_CTRL_XCH             (1 <<  2)
 177 #define MX51_ECSPI_CTRL_MODE_MASK       (0xf << 4)
 178 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET  8
 179 #define MX51_ECSPI_CTRL_PREDIV_OFFSET   12
 180 #define MX51_ECSPI_CTRL_CS(cs)          ((cs) << 18)
 181 #define MX51_ECSPI_CTRL_BL_OFFSET       20
 182
 183 #define MX51_ECSPI_CONFIG       0x0c
 184 #define MX51_ECSPI_CONFIG_SCLKPHA(cs)   (1 << ((cs) +  0))
 185 #define MX51_ECSPI_CONFIG_SCLKPOL(cs)   (1 << ((cs) +  4))
 186 #define MX51_ECSPI_CONFIG_SBBCTRL(cs)   (1 << ((cs) +  8))
 187 #define MX51_ECSPI_CONFIG_SSBPOL(cs)    (1 << ((cs) + 12))
 188
 189 #define MX51_ECSPI_INT          0x10
 190 #define MX51_ECSPI_INT_TEEN             (1 <<  0)
 191 #define MX51_ECSPI_INT_RREN             (1 <<  3)
 192
 193 #define MX51_ECSPI_STAT         0x18
 194 #define MX51_ECSPI_STAT_RR              (1 <<  3)
 195
 196 /* MX51 eCSPI */
 197 static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi)
 198 {
 199         /*
 200          * there are two 4-bit dividers, the pre-divider divides by
 201          * $pre, the post-divider by 2^$post
 202          */
 203         unsigned int pre, post;
 204
 205         if (unlikely(fspi > fin))
 206                 return 0;
 207
 208         post = fls(fin) - fls(fspi);
 209         if (fin > fspi << post)
 210                 post++;
 211
 212         /* now we have: (fin <= fspi << post) with post being minimal */
 213
 214         post = max(4U, post) - 4;
 215         if (unlikely(post > 0xf)) {
 216                 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
 217                                 __func__, fspi, fin);
 218                 return 0xff;
 219         }
 220
 221         pre = DIV_ROUND_UP(fin, fspi << post) - 1;
 222
 223         pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
 224                         __func__, fin, fspi, post, pre);
 225         return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
 226                 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
 227 }
 228
 229 static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
 230 {
 231         unsigned val = 0;
 232
 233         if (enable & MXC_INT_TE)
 234                 val |= MX51_ECSPI_INT_TEEN;
 235
 236         if (enable & MXC_INT_RR)
 237                 val |= MX51_ECSPI_INT_RREN;
 238
 239         writel(val, spi_imx->base + MX51_ECSPI_INT);
 240 }
 241
 242 static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
 243 {
 244         u32 reg;
 245
 246         reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
 247         reg |= MX51_ECSPI_CTRL_XCH;
 248         writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
 249 }
 250
 251 static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
 252                 struct spi_imx_config *config)
 253 {
 254         u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
 255
 256         /*
 257          * The hardware seems to have a race condition when changing modes. The
 258          * current assumption is that the selection of the channel arrives
 259          * earlier in the hardware than the mode bits when they are written at
 260          * the same time.
 261          * So set master mode for all channels as we do not support slave mode.
 262          */
 263         ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
 264
 265         /* set clock speed */
 266         ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz);
 267
 268         /* set chip select to use */
 269         ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
 270
 271         ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
 272
 273         cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
 274
 275         if (config->mode & SPI_CPHA)
 276                 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
 277
 278         if (config->mode & SPI_CPOL)
 279                 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
 280
 281         if (config->mode & SPI_CS_HIGH)
 282                 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
 283
 284         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 285         writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
 286
 287         return 0;
 288 }
 289
 290 static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
 291 {
 292         return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
 293 }
 294
 295 static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
 296 {
 297         /* drain receive buffer */
 298         while (mx51_ecspi_rx_available(spi_imx))
 299                 readl(spi_imx->base + MXC_CSPIRXDATA);
 300 }
 301
 302 #define MX31_INTREG_TEEN        (1 << 0)
 303 #define MX31_INTREG_RREN        (1 << 3)
 304
 305 #define MX31_CSPICTRL_ENABLE    (1 << 0)
 306 #define MX31_CSPICTRL_MASTER    (1 << 1)
 307 #define MX31_CSPICTRL_XCH       (1 << 2)
 308 #define MX31_CSPICTRL_POL       (1 << 4)
 309 #define MX31_CSPICTRL_PHA       (1 << 5)
 310 #define MX31_CSPICTRL_SSCTL     (1 << 6)
 311 #define MX31_CSPICTRL_SSPOL     (1 << 7)
 312 #define MX31_CSPICTRL_BC_SHIFT  8
 313 #define MX35_CSPICTRL_BL_SHIFT  20
 314 #define MX31_CSPICTRL_CS_SHIFT  24
 315 #define MX35_CSPICTRL_CS_SHIFT  12
 316 #define MX31_CSPICTRL_DR_SHIFT  16
 317
 318 #define MX31_CSPISTATUS         0x14
 319 #define MX31_STATUS_RR          (1 << 3)
 320
 321 /* These functions also work for the i.MX35, but be aware that
 322  * the i.MX35 has a slightly different register layout for bits
 323  * we do not use here.
 324  */
 325 static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
 326 {
 327         unsigned int val = 0;
 328
 329         if (enable & MXC_INT_TE)
 330                 val |= MX31_INTREG_TEEN;
 331         if (enable & MXC_INT_RR)
 332                 val |= MX31_INTREG_RREN;
 333
 334         writel(val, spi_imx->base + MXC_CSPIINT);
 335 }
 336
 337 static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
 338 {
 339         unsigned int reg;
 340
 341         reg = readl(spi_imx->base + MXC_CSPICTRL);
 342         reg |= MX31_CSPICTRL_XCH;
 343         writel(reg, spi_imx->base + MXC_CSPICTRL);
 344 }
 345
 346 static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
 347                 struct spi_imx_config *config)
 348 {
 349         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
 350         int cs = spi_imx->chipselect[config->cs];
 351
 352         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
 353                 MX31_CSPICTRL_DR_SHIFT;
 354
 355         reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
 356
 357         if (config->mode & SPI_CPHA)
 358                 reg |= MX31_CSPICTRL_PHA;
 359         if (config->mode & SPI_CPOL)
 360                 reg |= MX31_CSPICTRL_POL;
 361         if (config->mode & SPI_CS_HIGH)
 362                 reg |= MX31_CSPICTRL_SSPOL;
 363         if (cs < 0)
 364                 reg |= (cs + 32) << MX31_CSPICTRL_CS_SHIFT;
 365
 366         writel(reg, spi_imx->base + MXC_CSPICTRL);
 367
 368         return 0;
 369 }
 370
 371 static int __maybe_unused spi_imx0_7_config(struct spi_imx_data *spi_imx,
 372                 struct spi_imx_config *config)
 373 {
 374         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
 375         int cs = spi_imx->chipselect[config->cs];
 376
 377         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
 378                 MX31_CSPICTRL_DR_SHIFT;
 379
 380         reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
 381         reg |= MX31_CSPICTRL_SSCTL;
 382
 383         if (config->mode & SPI_CPHA)
 384                 reg |= MX31_CSPICTRL_PHA;
 385         if (config->mode & SPI_CPOL)
 386                 reg |= MX31_CSPICTRL_POL;
 387         if (config->mode & SPI_CS_HIGH)
 388                 reg |= MX31_CSPICTRL_SSPOL;
 389         if (cs < 0)
 390                 reg |= (cs + 32) << MX35_CSPICTRL_CS_SHIFT;
 391
 392         writel(reg, spi_imx->base + MXC_CSPICTRL);
 393
 394         return 0;
 395 }
 396
 397 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
 398 {
 399         return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
 400 }
 401
 402 static void __maybe_unused spi_imx0_4_reset(struct spi_imx_data *spi_imx)
 403 {
 404         /* drain receive buffer */
 405         while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
 406                 readl(spi_imx->base + MXC_CSPIRXDATA);
 407 }
 408
 409 #define MX21_INTREG_RR          (1 << 4)
 410 #define MX21_INTREG_TEEN        (1 << 9)
 411 #define MX21_INTREG_RREN        (1 << 13)
 412
 413 #define MX21_CSPICTRL_POL       (1 << 5)
 414 #define MX21_CSPICTRL_PHA       (1 << 6)
 415 #define MX21_CSPICTRL_SSPOL     (1 << 8)
 416 #define MX21_CSPICTRL_XCH       (1 << 9)
 417 #define MX21_CSPICTRL_ENABLE    (1 << 10)
 418 #define MX21_CSPICTRL_MASTER    (1 << 11)
 419 #define MX21_CSPICTRL_DR_SHIFT  14
 420 #define MX21_CSPICTRL_CS_SHIFT  19
 421
 422 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
 423 {
 424         unsigned int val = 0;
 425
 426         if (enable & MXC_INT_TE)
 427                 val |= MX21_INTREG_TEEN;
 428         if (enable & MXC_INT_RR)
 429                 val |= MX21_INTREG_RREN;
 430
 431         writel(val, spi_imx->base + MXC_CSPIINT);
 432 }
 433
 434 static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
 435 {
 436         unsigned int reg;
 437
 438         reg = readl(spi_imx->base + MXC_CSPICTRL);
 439         reg |= MX21_CSPICTRL_XCH;
 440         writel(reg, spi_imx->base + MXC_CSPICTRL);
 441 }
 442
 443 static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
 444                 struct spi_imx_config *config)
 445 {
 446         unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
 447         int cs = spi_imx->chipselect[config->cs];
 448
 449         reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) <<
 450                 MX21_CSPICTRL_DR_SHIFT;
 451         reg |= config->bpw - 1;
 452
 453         if (config->mode & SPI_CPHA)
 454                 reg |= MX21_CSPICTRL_PHA;
 455         if (config->mode & SPI_CPOL)
 456                 reg |= MX21_CSPICTRL_POL;
 457         if (config->mode & SPI_CS_HIGH)
 458                 reg |= MX21_CSPICTRL_SSPOL;
 459         if (cs < 0)
 460                 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
 461
 462         writel(reg, spi_imx->base + MXC_CSPICTRL);
 463
 464         return 0;
 465 }
 466
 467 static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
 468 {
 469         return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
 470 }
 471
 472 static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
 473 {
 474         writel(1, spi_imx->base + MXC_RESET);
 475 }
 476
 477 #define MX1_INTREG_RR           (1 << 3)
 478 #define MX1_INTREG_TEEN         (1 << 8)
 479 #define MX1_INTREG_RREN         (1 << 11)
 480
 481 #define MX1_CSPICTRL_POL        (1 << 4)
 482 #define MX1_CSPICTRL_PHA        (1 << 5)
 483 #define MX1_CSPICTRL_XCH        (1 << 8)
 484 #define MX1_CSPICTRL_ENABLE     (1 << 9)
 485 #define MX1_CSPICTRL_MASTER     (1 << 10)
 486 #define MX1_CSPICTRL_DR_SHIFT   13
 487
 488 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
 489 {
 490         unsigned int val = 0;
 491
 492         if (enable & MXC_INT_TE)
 493                 val |= MX1_INTREG_TEEN;
 494         if (enable & MXC_INT_RR)
 495                 val |= MX1_INTREG_RREN;
 496
 497         writel(val, spi_imx->base + MXC_CSPIINT);
 498 }
 499
 500 static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
 501 {
 502         unsigned int reg;
 503
 504         reg = readl(spi_imx->base + MXC_CSPICTRL);
 505         reg |= MX1_CSPICTRL_XCH;
 506         writel(reg, spi_imx->base + MXC_CSPICTRL);
 507 }
 508
 509 static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
 510                 struct spi_imx_config *config)
 511 {
 512         unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
 513
 514         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
 515                 MX1_CSPICTRL_DR_SHIFT;
 516         reg |= config->bpw - 1;
 517
 518         if (config->mode & SPI_CPHA)
 519                 reg |= MX1_CSPICTRL_PHA;
 520         if (config->mode & SPI_CPOL)
 521                 reg |= MX1_CSPICTRL_POL;
 522
 523         writel(reg, spi_imx->base + MXC_CSPICTRL);
 524
 525         return 0;
 526 }
 527
 528 static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
 529 {
 530         return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
 531 }
 532
 533 static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
 534 {
 535         writel(1, spi_imx->base + MXC_RESET);
 536 }
 537
 538 /*
 539  * These version numbers are taken from the Freescale driver.  Unfortunately it
 540  * doesn't support i.MX1, so this entry doesn't match the scheme. :-(
 541  */
 542 static struct spi_imx_devtype_data spi_imx_devtype_data[] = {
 543 #ifdef CONFIG_SPI_IMX_VER_IMX1
 544         [SPI_IMX_VER_IMX1] = {
 545                 .intctrl = mx1_intctrl,
 546                 .config = mx1_config,
 547                 .trigger = mx1_trigger,
 548                 .rx_available = mx1_rx_available,
 549                 .reset = mx1_reset,
 550                 .fifosize = 8,
 551         },
 552 #endif
 553 #ifdef CONFIG_SPI_IMX_VER_0_0
 554         [SPI_IMX_VER_0_0] = {
 555                 .intctrl = mx21_intctrl,
 556                 .config = mx21_config,
 557                 .trigger = mx21_trigger,
 558                 .rx_available = mx21_rx_available,
 559                 .reset = mx21_reset,
 560                 .fifosize = 8,
 561         },
 562 #endif
 563 #ifdef CONFIG_SPI_IMX_VER_0_4
 564         [SPI_IMX_VER_0_4] = {
 565                 .intctrl = mx31_intctrl,
 566                 .config = spi_imx0_4_config,
 567                 .trigger = mx31_trigger,
 568                 .rx_available = mx31_rx_available,
 569                 .reset = spi_imx0_4_reset,
 570                 .fifosize = 8,
 571         },
 572 #endif
 573 #ifdef CONFIG_SPI_IMX_VER_0_7
 574         [SPI_IMX_VER_0_7] = {
 575                 .intctrl = mx31_intctrl,
 576                 .config = spi_imx0_7_config,
 577                 .trigger = mx31_trigger,
 578                 .rx_available = mx31_rx_available,
 579                 .reset = spi_imx0_4_reset,
 580                 .fifosize = 8,
 581         },
 582 #endif
 583 #ifdef CONFIG_SPI_IMX_VER_2_3
 584         [SPI_IMX_VER_2_3] = {
 585                 .intctrl = mx51_ecspi_intctrl,
 586                 .config = mx51_ecspi_config,
 587                 .trigger = mx51_ecspi_trigger,
 588                 .rx_available = mx51_ecspi_rx_available,
 589                 .reset = mx51_ecspi_reset,
 590                 .fifosize = 64,
 591         },
 592 #endif
 593 };
 594
 595 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
 596 {
 597         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 598         int gpio = spi_imx->chipselect[spi->chip_select];
 599         int active = is_active != BITBANG_CS_INACTIVE;
 600         int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
 601
 602         if (gpio < 0)
 603                 return;
 604
 605         gpio_set_value(gpio, dev_is_lowactive ^ active);
 606 }
 607
 608 static void spi_imx_push(struct spi_imx_data *spi_imx)
 609 {
 610         while (spi_imx->txfifo < spi_imx->devtype_data->fifosize) {
 611                 if (!spi_imx->count)
 612                         break;
 613                 spi_imx->tx(spi_imx);
 614                 spi_imx->txfifo++;
 615         }
 616
 617         spi_imx->devtype_data->trigger(spi_imx);
 618 }
 619
 620 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
 621 {
 622         struct spi_imx_data *spi_imx = dev_id;
 623
 624         while (spi_imx->devtype_data->rx_available(spi_imx)) {
 625                 spi_imx->rx(spi_imx);
 626                 spi_imx->txfifo--;
 627         }
 628
 629         if (spi_imx->count) {
 630                 spi_imx_push(spi_imx);
 631                 return IRQ_HANDLED;
 632         }
 633
 634         if (spi_imx->txfifo) {
 635                 /* No data left to push, but still waiting for rx data,
 636                  * enable receive data available interrupt.
 637                  */
 638                 spi_imx->devtype_data->intctrl(
 639                                 spi_imx, MXC_INT_RR);
 640                 return IRQ_HANDLED;
 641         }
 642
 643         spi_imx->devtype_data->intctrl(spi_imx, 0);
 644         complete(&spi_imx->xfer_done);
 645
 646         return IRQ_HANDLED;
 647 }
 648
 649 static int spi_imx_setupxfer(struct spi_device *spi,
 650                                  struct spi_transfer *t)
 651 {
 652         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 653         struct spi_imx_config config;
 654
 655         config.bpw = t ? t->bits_per_word : spi->bits_per_word;
 656         config.speed_hz  = t ? t->speed_hz : spi->max_speed_hz;
 657         config.mode = spi->mode;
 658         config.cs = spi->chip_select;
 659
 660         if (!config.speed_hz)
 661                 config.speed_hz = spi->max_speed_hz;
 662         if (!config.bpw)
 663                 config.bpw = spi->bits_per_word;
 664         if (!config.speed_hz)
 665                 config.speed_hz = spi->max_speed_hz;
 666
 667         /* Initialize the functions for transfer */
 668         if (config.bpw <= 8) {
 669                 spi_imx->rx = spi_imx_buf_rx_u8;
 670                 spi_imx->tx = spi_imx_buf_tx_u8;
 671         } else if (config.bpw <= 16) {
 672                 spi_imx->rx = spi_imx_buf_rx_u16;
 673                 spi_imx->tx = spi_imx_buf_tx_u16;
 674         } else if (config.bpw <= 32) {
 675                 spi_imx->rx = spi_imx_buf_rx_u32;
 676                 spi_imx->tx = spi_imx_buf_tx_u32;
 677         } else
 678                 BUG();
 679
 680         spi_imx->devtype_data->config(spi_imx, &config);
 681
 682         return 0;
 683 }
 684
 685 static int spi_imx_transfer(struct spi_device *spi,
 686                                 struct spi_transfer *transfer)
 687 {
 688         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 689
 690         spi_imx->tx_buf = transfer->tx_buf;
 691         spi_imx->rx_buf = transfer->rx_buf;
 692         spi_imx->count = transfer->len;
 693         spi_imx->txfifo = 0;
 694
 695         init_completion(&spi_imx->xfer_done);
 696
 697         spi_imx_push(spi_imx);
 698
 699         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
 700
 701         wait_for_completion(&spi_imx->xfer_done);
 702
 703         return transfer->len;
 704 }
 705
 706 static int spi_imx_setup(struct spi_device *spi)
 707 {
 708         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 709         int gpio = spi_imx->chipselect[spi->chip_select];
 710
 711         dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
 712                  spi->mode, spi->bits_per_word, spi->max_speed_hz);
 713
 714         if (gpio >= 0)
 715                 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
 716
 717         spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
 718
 719         return 0;
 720 }
 721
 722 static void spi_imx_cleanup(struct spi_device *spi)
 723 {
 724 }
 725
 726 static struct platform_device_id spi_imx_devtype[] = {
 727         {
 728                 .name = "imx1-cspi",
 729                 .driver_data = SPI_IMX_VER_IMX1,
 730         }, {
 731                 .name = "imx21-cspi",
 732                 .driver_data = SPI_IMX_VER_0_0,
 733         }, {
 734                 .name = "imx25-cspi",
 735                 .driver_data = SPI_IMX_VER_0_7,
 736         }, {
 737                 .name = "imx27-cspi",
 738                 .driver_data = SPI_IMX_VER_0_0,
 739         }, {
 740                 .name = "imx31-cspi",
 741                 .driver_data = SPI_IMX_VER_0_4,
 742         }, {
 743                 .name = "imx35-cspi",
 744                 .driver_data = SPI_IMX_VER_0_7,
 745         }, {
 746                 .name = "imx51-cspi",
 747                 .driver_data = SPI_IMX_VER_0_7,
 748         }, {
 749                 .name = "imx51-ecspi",
 750                 .driver_data = SPI_IMX_VER_2_3,
 751         }, {
 752                 .name = "imx53-cspi",
 753                 .driver_data = SPI_IMX_VER_0_7,
 754         }, {
 755                 .name = "imx53-ecspi",
 756                 .driver_data = SPI_IMX_VER_2_3,
 757         }, {
 758                 /* sentinel */
 759         }
 760 };
 761
 762 static int __devinit spi_imx_probe(struct platform_device *pdev)
 763 {
 764         struct spi_imx_master *mxc_platform_info;
 765         struct spi_master *master;
 766         struct spi_imx_data *spi_imx;
 767         struct resource *res;
 768         int i, ret;
 769
 770         mxc_platform_info = dev_get_platdata(&pdev->dev);
 771         if (!mxc_platform_info) {
 772                 dev_err(&pdev->dev, "can't get the platform data\n");
 773                 return -EINVAL;
 774         }
 775
 776         master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
 777         if (!master)
 778                 return -ENOMEM;
 779
 780         platform_set_drvdata(pdev, master);
 781
 782         master->bus_num = pdev->id;
 783         master->num_chipselect = mxc_platform_info->num_chipselect;
 784
 785         spi_imx = spi_master_get_devdata(master);
 786         spi_imx->bitbang.master = spi_master_get(master);
 787         spi_imx->chipselect = mxc_platform_info->chipselect;
 788
 789         for (i = 0; i < master->num_chipselect; i++) {
 790                 if (spi_imx->chipselect[i] < 0)
 791                         continue;
 792                 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
 793                 if (ret) {
 794                         while (i > 0) {
 795                                 i--;
 796                                 if (spi_imx->chipselect[i] >= 0)
 797                                         gpio_free(spi_imx->chipselect[i]);
 798                         }
 799                         dev_err(&pdev->dev, "can't get cs gpios\n");
 800                         goto out_master_put;
 801                 }
 802         }
 803
 804         spi_imx->bitbang.chipselect = spi_imx_chipselect;
 805         spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
 806         spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
 807         spi_imx->bitbang.master->setup = spi_imx_setup;
 808         spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
 809         spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 810
 811         init_completion(&spi_imx->xfer_done);
 812
 813         spi_imx->devtype_data =
 814                 &spi_imx_devtype_data[pdev->id_entry->driver_data];
 815
 816         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 817         if (!res) {
 818                 dev_err(&pdev->dev, "can't get platform resource\n");
 819                 ret = -ENOMEM;
 820                 goto out_gpio_free;
 821         }
 822
 823         if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
 824                 dev_err(&pdev->dev, "request_mem_region failed\n");
 825                 ret = -EBUSY;
 826                 goto out_gpio_free;
 827         }
 828
 829         spi_imx->base = ioremap(res->start, resource_size(res));
 830         if (!spi_imx->base) {
 831                 ret = -EINVAL;
 832                 goto out_release_mem;
 833         }
 834
 835         spi_imx->irq = platform_get_irq(pdev, 0);
 836         if (spi_imx->irq < 0) {
 837                 ret = -EINVAL;
 838                 goto out_iounmap;
 839         }
 840
 841         ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
 842         if (ret) {
 843                 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
 844                 goto out_iounmap;
 845         }
 846
 847         spi_imx->clk = clk_get(&pdev->dev, NULL);
 848         if (IS_ERR(spi_imx->clk)) {
 849                 dev_err(&pdev->dev, "unable to get clock\n");
 850                 ret = PTR_ERR(spi_imx->clk);
 851                 goto out_free_irq;
 852         }
 853
 854         clk_enable(spi_imx->clk);
 855         spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
 856
 857         spi_imx->devtype_data->reset(spi_imx);
 858
 859         spi_imx->devtype_data->intctrl(spi_imx, 0);
 860
 861         ret = spi_bitbang_start(&spi_imx->bitbang);
 862         if (ret) {
 863                 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
 864                 goto out_clk_put;
 865         }
 866
 867         dev_info(&pdev->dev, "probed\n");
 868
 869         return ret;
 870
 871 out_clk_put:
 872         clk_disable(spi_imx->clk);
 873         clk_put(spi_imx->clk);
 874 out_free_irq:
 875         free_irq(spi_imx->irq, spi_imx);
 876 out_iounmap:
 877         iounmap(spi_imx->base);
 878 out_release_mem:
 879         release_mem_region(res->start, resource_size(res));
 880 out_gpio_free:
 881         for (i = 0; i < master->num_chipselect; i++)
 882                 if (spi_imx->chipselect[i] >= 0)
 883                         gpio_free(spi_imx->chipselect[i]);
 884 out_master_put:
 885         spi_master_put(master);
 886         kfree(master);
 887         platform_set_drvdata(pdev, NULL);
 888         return ret;
 889 }
 890
 891 static int __devexit spi_imx_remove(struct platform_device *pdev)
 892 {
 893         struct spi_master *master = platform_get_drvdata(pdev);
 894         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 895         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
 896         int i;
 897
 898         spi_bitbang_stop(&spi_imx->bitbang);
 899
 900         writel(0, spi_imx->base + MXC_CSPICTRL);
 901         clk_disable(spi_imx->clk);
 902         clk_put(spi_imx->clk);
 903         free_irq(spi_imx->irq, spi_imx);
 904         iounmap(spi_imx->base);
 905
 906         for (i = 0; i < master->num_chipselect; i++)
 907                 if (spi_imx->chipselect[i] >= 0)
 908                         gpio_free(spi_imx->chipselect[i]);
 909
 910         spi_master_put(master);
 911
 912         release_mem_region(res->start, resource_size(res));
 913
 914         platform_set_drvdata(pdev, NULL);
 915
 916         return 0;
 917 }
 918
 919 static struct platform_driver spi_imx_driver = {
 920         .driver = {
 921                    .name = DRIVER_NAME,
 922                    .owner = THIS_MODULE,
 923                    },
 924         .id_table = spi_imx_devtype,
 925         .probe = spi_imx_probe,
 926         .remove = __devexit_p(spi_imx_remove),
 927 };
 928
 929 static int __init spi_imx_init(void)
 930 {
 931         return platform_driver_register(&spi_imx_driver);
 932 }
 933
 934 static void __exit spi_imx_exit(void)
 935 {
 936         platform_driver_unregister(&spi_imx_driver);
 937 }
 938
 939 module_init(spi_imx_init);
 940 module_exit(spi_imx_exit);
 941
 942 MODULE_DESCRIPTION("SPI Master Controller driver");
 943 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
 944 MODULE_LICENSE("GPL");