2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
21 #include <linux/clk.h>
22 #include <linux/completion.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/gpio.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/platform_device.h>
33 #include <linux/slab.h>
34 #include <linux/spi/spi.h>
35 #include <linux/spi/spi_bitbang.h>
36 #include <linux/types.h>
40 #define DRIVER_NAME "spi_imx"
42 #define MXC_CSPIRXDATA 0x00
43 #define MXC_CSPITXDATA 0x04
44 #define MXC_CSPICTRL 0x08
45 #define MXC_CSPIINT 0x0c
46 #define MXC_RESET 0x1c
48 /* generic defines to abstract from the different register layouts */
49 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
50 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
52 struct spi_imx_config {
53 unsigned int speed_hz;
59 enum spi_imx_devtype {
64 IMX35_CSPI, /* CSPI on all i.mx except above */
65 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
70 struct spi_imx_devtype_data {
71 void (*intctrl)(struct spi_imx_data *, int);
72 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
73 void (*trigger)(struct spi_imx_data *);
74 int (*rx_available)(struct spi_imx_data *);
75 void (*reset)(struct spi_imx_data *);
76 enum spi_imx_devtype devtype;
80 struct spi_bitbang bitbang;
82 struct completion xfer_done;
86 unsigned long spi_clk;
89 void (*tx)(struct spi_imx_data *);
90 void (*rx)(struct spi_imx_data *);
93 unsigned int txfifo; /* number of words pushed in tx FIFO */
95 struct spi_imx_devtype_data *devtype_data;
99 static inline int is_imx27_cspi(struct spi_imx_data *d)
101 return d->devtype_data->devtype == IMX27_CSPI;
104 static inline int is_imx35_cspi(struct spi_imx_data *d)
106 return d->devtype_data->devtype == IMX35_CSPI;
109 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
111 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
114 #define MXC_SPI_BUF_RX(type) \
115 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
117 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
119 if (spi_imx->rx_buf) { \
120 *(type *)spi_imx->rx_buf = val; \
121 spi_imx->rx_buf += sizeof(type); \
125 #define MXC_SPI_BUF_TX(type) \
126 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
130 if (spi_imx->tx_buf) { \
131 val = *(type *)spi_imx->tx_buf; \
132 spi_imx->tx_buf += sizeof(type); \
135 spi_imx->count -= sizeof(type); \
137 writel(val, spi_imx->base + MXC_CSPITXDATA); \
147 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
148 * (which is currently not the case in this driver)
150 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
151 256, 384, 512, 768, 1024};
154 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
155 unsigned int fspi, unsigned int max)
159 for (i = 2; i < max; i++)
160 if (fspi * mxc_clkdivs[i] >= fin)
166 /* MX1, MX31, MX35, MX51 CSPI */
167 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
172 for (i = 0; i < 7; i++) {
173 if (fspi * div >= fin)
181 #define MX51_ECSPI_CTRL 0x08
182 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
183 #define MX51_ECSPI_CTRL_XCH (1 << 2)
184 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
185 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
186 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
187 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
188 #define MX51_ECSPI_CTRL_BL_OFFSET 20
190 #define MX51_ECSPI_CONFIG 0x0c
191 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
192 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
193 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
194 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
196 #define MX51_ECSPI_INT 0x10
197 #define MX51_ECSPI_INT_TEEN (1 << 0)
198 #define MX51_ECSPI_INT_RREN (1 << 3)
200 #define MX51_ECSPI_STAT 0x18
201 #define MX51_ECSPI_STAT_RR (1 << 3)
204 static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi)
207 * there are two 4-bit dividers, the pre-divider divides by
208 * $pre, the post-divider by 2^$post
210 unsigned int pre, post;
212 if (unlikely(fspi > fin))
215 post = fls(fin) - fls(fspi);
216 if (fin > fspi << post)
219 /* now we have: (fin <= fspi << post) with post being minimal */
221 post = max(4U, post) - 4;
222 if (unlikely(post > 0xf)) {
223 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
224 __func__, fspi, fin);
228 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
230 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
231 __func__, fin, fspi, post, pre);
232 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
233 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
236 static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
240 if (enable & MXC_INT_TE)
241 val |= MX51_ECSPI_INT_TEEN;
243 if (enable & MXC_INT_RR)
244 val |= MX51_ECSPI_INT_RREN;
246 writel(val, spi_imx->base + MX51_ECSPI_INT);
249 static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
253 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
254 reg |= MX51_ECSPI_CTRL_XCH;
255 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
258 static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
259 struct spi_imx_config *config)
261 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
264 * The hardware seems to have a race condition when changing modes. The
265 * current assumption is that the selection of the channel arrives
266 * earlier in the hardware than the mode bits when they are written at
268 * So set master mode for all channels as we do not support slave mode.
270 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
272 /* set clock speed */
273 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz);
275 /* set chip select to use */
276 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
278 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
280 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
282 if (config->mode & SPI_CPHA)
283 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
285 if (config->mode & SPI_CPOL)
286 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
288 if (config->mode & SPI_CS_HIGH)
289 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
291 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
292 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
297 static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
299 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
302 static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
304 /* drain receive buffer */
305 while (mx51_ecspi_rx_available(spi_imx))
306 readl(spi_imx->base + MXC_CSPIRXDATA);
309 #define MX31_INTREG_TEEN (1 << 0)
310 #define MX31_INTREG_RREN (1 << 3)
312 #define MX31_CSPICTRL_ENABLE (1 << 0)
313 #define MX31_CSPICTRL_MASTER (1 << 1)
314 #define MX31_CSPICTRL_XCH (1 << 2)
315 #define MX31_CSPICTRL_POL (1 << 4)
316 #define MX31_CSPICTRL_PHA (1 << 5)
317 #define MX31_CSPICTRL_SSCTL (1 << 6)
318 #define MX31_CSPICTRL_SSPOL (1 << 7)
319 #define MX31_CSPICTRL_BC_SHIFT 8
320 #define MX35_CSPICTRL_BL_SHIFT 20
321 #define MX31_CSPICTRL_CS_SHIFT 24
322 #define MX35_CSPICTRL_CS_SHIFT 12
323 #define MX31_CSPICTRL_DR_SHIFT 16
325 #define MX31_CSPISTATUS 0x14
326 #define MX31_STATUS_RR (1 << 3)
328 /* These functions also work for the i.MX35, but be aware that
329 * the i.MX35 has a slightly different register layout for bits
330 * we do not use here.
332 static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
334 unsigned int val = 0;
336 if (enable & MXC_INT_TE)
337 val |= MX31_INTREG_TEEN;
338 if (enable & MXC_INT_RR)
339 val |= MX31_INTREG_RREN;
341 writel(val, spi_imx->base + MXC_CSPIINT);
344 static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
348 reg = readl(spi_imx->base + MXC_CSPICTRL);
349 reg |= MX31_CSPICTRL_XCH;
350 writel(reg, spi_imx->base + MXC_CSPICTRL);
353 static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
354 struct spi_imx_config *config)
356 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
357 int cs = spi_imx->chipselect[config->cs];
359 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
360 MX31_CSPICTRL_DR_SHIFT;
362 if (is_imx35_cspi(spi_imx)) {
363 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
364 reg |= MX31_CSPICTRL_SSCTL;
366 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
369 if (config->mode & SPI_CPHA)
370 reg |= MX31_CSPICTRL_PHA;
371 if (config->mode & SPI_CPOL)
372 reg |= MX31_CSPICTRL_POL;
373 if (config->mode & SPI_CS_HIGH)
374 reg |= MX31_CSPICTRL_SSPOL;
377 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
378 MX31_CSPICTRL_CS_SHIFT);
380 writel(reg, spi_imx->base + MXC_CSPICTRL);
385 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
387 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
390 static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
392 /* drain receive buffer */
393 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
394 readl(spi_imx->base + MXC_CSPIRXDATA);
397 #define MX21_INTREG_RR (1 << 4)
398 #define MX21_INTREG_TEEN (1 << 9)
399 #define MX21_INTREG_RREN (1 << 13)
401 #define MX21_CSPICTRL_POL (1 << 5)
402 #define MX21_CSPICTRL_PHA (1 << 6)
403 #define MX21_CSPICTRL_SSPOL (1 << 8)
404 #define MX21_CSPICTRL_XCH (1 << 9)
405 #define MX21_CSPICTRL_ENABLE (1 << 10)
406 #define MX21_CSPICTRL_MASTER (1 << 11)
407 #define MX21_CSPICTRL_DR_SHIFT 14
408 #define MX21_CSPICTRL_CS_SHIFT 19
410 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
412 unsigned int val = 0;
414 if (enable & MXC_INT_TE)
415 val |= MX21_INTREG_TEEN;
416 if (enable & MXC_INT_RR)
417 val |= MX21_INTREG_RREN;
419 writel(val, spi_imx->base + MXC_CSPIINT);
422 static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
426 reg = readl(spi_imx->base + MXC_CSPICTRL);
427 reg |= MX21_CSPICTRL_XCH;
428 writel(reg, spi_imx->base + MXC_CSPICTRL);
431 static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
432 struct spi_imx_config *config)
434 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
435 int cs = spi_imx->chipselect[config->cs];
436 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
438 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
439 MX21_CSPICTRL_DR_SHIFT;
440 reg |= config->bpw - 1;
442 if (config->mode & SPI_CPHA)
443 reg |= MX21_CSPICTRL_PHA;
444 if (config->mode & SPI_CPOL)
445 reg |= MX21_CSPICTRL_POL;
446 if (config->mode & SPI_CS_HIGH)
447 reg |= MX21_CSPICTRL_SSPOL;
449 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
451 writel(reg, spi_imx->base + MXC_CSPICTRL);
456 static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
458 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
461 static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
463 writel(1, spi_imx->base + MXC_RESET);
466 #define MX1_INTREG_RR (1 << 3)
467 #define MX1_INTREG_TEEN (1 << 8)
468 #define MX1_INTREG_RREN (1 << 11)
470 #define MX1_CSPICTRL_POL (1 << 4)
471 #define MX1_CSPICTRL_PHA (1 << 5)
472 #define MX1_CSPICTRL_XCH (1 << 8)
473 #define MX1_CSPICTRL_ENABLE (1 << 9)
474 #define MX1_CSPICTRL_MASTER (1 << 10)
475 #define MX1_CSPICTRL_DR_SHIFT 13
477 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
479 unsigned int val = 0;
481 if (enable & MXC_INT_TE)
482 val |= MX1_INTREG_TEEN;
483 if (enable & MXC_INT_RR)
484 val |= MX1_INTREG_RREN;
486 writel(val, spi_imx->base + MXC_CSPIINT);
489 static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
493 reg = readl(spi_imx->base + MXC_CSPICTRL);
494 reg |= MX1_CSPICTRL_XCH;
495 writel(reg, spi_imx->base + MXC_CSPICTRL);
498 static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
499 struct spi_imx_config *config)
501 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
503 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
504 MX1_CSPICTRL_DR_SHIFT;
505 reg |= config->bpw - 1;
507 if (config->mode & SPI_CPHA)
508 reg |= MX1_CSPICTRL_PHA;
509 if (config->mode & SPI_CPOL)
510 reg |= MX1_CSPICTRL_POL;
512 writel(reg, spi_imx->base + MXC_CSPICTRL);
517 static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
519 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
522 static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
524 writel(1, spi_imx->base + MXC_RESET);
527 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
528 .intctrl = mx1_intctrl,
529 .config = mx1_config,
530 .trigger = mx1_trigger,
531 .rx_available = mx1_rx_available,
533 .devtype = IMX1_CSPI,
536 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
537 .intctrl = mx21_intctrl,
538 .config = mx21_config,
539 .trigger = mx21_trigger,
540 .rx_available = mx21_rx_available,
542 .devtype = IMX21_CSPI,
545 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
546 /* i.mx27 cspi shares the functions with i.mx21 one */
547 .intctrl = mx21_intctrl,
548 .config = mx21_config,
549 .trigger = mx21_trigger,
550 .rx_available = mx21_rx_available,
552 .devtype = IMX27_CSPI,
555 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
556 .intctrl = mx31_intctrl,
557 .config = mx31_config,
558 .trigger = mx31_trigger,
559 .rx_available = mx31_rx_available,
561 .devtype = IMX31_CSPI,
564 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
565 /* i.mx35 and later cspi shares the functions with i.mx31 one */
566 .intctrl = mx31_intctrl,
567 .config = mx31_config,
568 .trigger = mx31_trigger,
569 .rx_available = mx31_rx_available,
571 .devtype = IMX35_CSPI,
574 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
575 .intctrl = mx51_ecspi_intctrl,
576 .config = mx51_ecspi_config,
577 .trigger = mx51_ecspi_trigger,
578 .rx_available = mx51_ecspi_rx_available,
579 .reset = mx51_ecspi_reset,
580 .devtype = IMX51_ECSPI,
583 static struct platform_device_id spi_imx_devtype[] = {
586 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
588 .name = "imx21-cspi",
589 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
591 .name = "imx27-cspi",
592 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
594 .name = "imx31-cspi",
595 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
597 .name = "imx35-cspi",
598 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
600 .name = "imx51-ecspi",
601 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
607 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
609 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
610 int gpio = spi_imx->chipselect[spi->chip_select];
611 int active = is_active != BITBANG_CS_INACTIVE;
612 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
617 gpio_set_value(gpio, dev_is_lowactive ^ active);
620 static void spi_imx_push(struct spi_imx_data *spi_imx)
622 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
625 spi_imx->tx(spi_imx);
629 spi_imx->devtype_data->trigger(spi_imx);
632 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
634 struct spi_imx_data *spi_imx = dev_id;
636 while (spi_imx->devtype_data->rx_available(spi_imx)) {
637 spi_imx->rx(spi_imx);
641 if (spi_imx->count) {
642 spi_imx_push(spi_imx);
646 if (spi_imx->txfifo) {
647 /* No data left to push, but still waiting for rx data,
648 * enable receive data available interrupt.
650 spi_imx->devtype_data->intctrl(
651 spi_imx, MXC_INT_RR);
655 spi_imx->devtype_data->intctrl(spi_imx, 0);
656 complete(&spi_imx->xfer_done);
661 static int spi_imx_setupxfer(struct spi_device *spi,
662 struct spi_transfer *t)
664 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
665 struct spi_imx_config config;
667 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
668 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
669 config.mode = spi->mode;
670 config.cs = spi->chip_select;
672 if (!config.speed_hz)
673 config.speed_hz = spi->max_speed_hz;
675 config.bpw = spi->bits_per_word;
676 if (!config.speed_hz)
677 config.speed_hz = spi->max_speed_hz;
679 /* Initialize the functions for transfer */
680 if (config.bpw <= 8) {
681 spi_imx->rx = spi_imx_buf_rx_u8;
682 spi_imx->tx = spi_imx_buf_tx_u8;
683 } else if (config.bpw <= 16) {
684 spi_imx->rx = spi_imx_buf_rx_u16;
685 spi_imx->tx = spi_imx_buf_tx_u16;
686 } else if (config.bpw <= 32) {
687 spi_imx->rx = spi_imx_buf_rx_u32;
688 spi_imx->tx = spi_imx_buf_tx_u32;
692 spi_imx->devtype_data->config(spi_imx, &config);
697 static int spi_imx_transfer(struct spi_device *spi,
698 struct spi_transfer *transfer)
700 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
702 spi_imx->tx_buf = transfer->tx_buf;
703 spi_imx->rx_buf = transfer->rx_buf;
704 spi_imx->count = transfer->len;
707 init_completion(&spi_imx->xfer_done);
709 spi_imx_push(spi_imx);
711 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
713 wait_for_completion(&spi_imx->xfer_done);
715 return transfer->len;
718 static int spi_imx_setup(struct spi_device *spi)
720 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
721 int gpio = spi_imx->chipselect[spi->chip_select];
723 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
724 spi->mode, spi->bits_per_word, spi->max_speed_hz);
727 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
729 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
734 static void spi_imx_cleanup(struct spi_device *spi)
738 static int __devinit spi_imx_probe(struct platform_device *pdev)
740 struct spi_imx_master *mxc_platform_info;
741 struct spi_master *master;
742 struct spi_imx_data *spi_imx;
743 struct resource *res;
746 mxc_platform_info = dev_get_platdata(&pdev->dev);
747 if (!mxc_platform_info) {
748 dev_err(&pdev->dev, "can't get the platform data\n");
752 num_cs = mxc_platform_info->num_chipselect;
753 master = spi_alloc_master(&pdev->dev,
754 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
758 platform_set_drvdata(pdev, master);
760 master->bus_num = pdev->id;
761 master->num_chipselect = num_cs;
763 spi_imx = spi_master_get_devdata(master);
764 spi_imx->bitbang.master = spi_master_get(master);
766 for (i = 0; i < master->num_chipselect; i++) {
767 spi_imx->chipselect[i] = mxc_platform_info->chipselect[i];
768 if (spi_imx->chipselect[i] < 0)
770 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
774 if (spi_imx->chipselect[i] >= 0)
775 gpio_free(spi_imx->chipselect[i]);
777 dev_err(&pdev->dev, "can't get cs gpios\n");
782 spi_imx->bitbang.chipselect = spi_imx_chipselect;
783 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
784 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
785 spi_imx->bitbang.master->setup = spi_imx_setup;
786 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
787 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
789 init_completion(&spi_imx->xfer_done);
791 spi_imx->devtype_data =
792 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
794 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
796 dev_err(&pdev->dev, "can't get platform resource\n");
801 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
802 dev_err(&pdev->dev, "request_mem_region failed\n");
807 spi_imx->base = ioremap(res->start, resource_size(res));
808 if (!spi_imx->base) {
810 goto out_release_mem;
813 spi_imx->irq = platform_get_irq(pdev, 0);
814 if (spi_imx->irq < 0) {
819 ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
821 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
825 spi_imx->clk = clk_get(&pdev->dev, NULL);
826 if (IS_ERR(spi_imx->clk)) {
827 dev_err(&pdev->dev, "unable to get clock\n");
828 ret = PTR_ERR(spi_imx->clk);
832 clk_enable(spi_imx->clk);
833 spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
835 spi_imx->devtype_data->reset(spi_imx);
837 spi_imx->devtype_data->intctrl(spi_imx, 0);
839 ret = spi_bitbang_start(&spi_imx->bitbang);
841 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
845 dev_info(&pdev->dev, "probed\n");
850 clk_disable(spi_imx->clk);
851 clk_put(spi_imx->clk);
853 free_irq(spi_imx->irq, spi_imx);
855 iounmap(spi_imx->base);
857 release_mem_region(res->start, resource_size(res));
859 for (i = 0; i < master->num_chipselect; i++)
860 if (spi_imx->chipselect[i] >= 0)
861 gpio_free(spi_imx->chipselect[i]);
863 spi_master_put(master);
865 platform_set_drvdata(pdev, NULL);
869 static int __devexit spi_imx_remove(struct platform_device *pdev)
871 struct spi_master *master = platform_get_drvdata(pdev);
872 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
873 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
876 spi_bitbang_stop(&spi_imx->bitbang);
878 writel(0, spi_imx->base + MXC_CSPICTRL);
879 clk_disable(spi_imx->clk);
880 clk_put(spi_imx->clk);
881 free_irq(spi_imx->irq, spi_imx);
882 iounmap(spi_imx->base);
884 for (i = 0; i < master->num_chipselect; i++)
885 if (spi_imx->chipselect[i] >= 0)
886 gpio_free(spi_imx->chipselect[i]);
888 spi_master_put(master);
890 release_mem_region(res->start, resource_size(res));
892 platform_set_drvdata(pdev, NULL);
897 static struct platform_driver spi_imx_driver = {
900 .owner = THIS_MODULE,
902 .id_table = spi_imx_devtype,
903 .probe = spi_imx_probe,
904 .remove = __devexit_p(spi_imx_remove),
907 static int __init spi_imx_init(void)
909 return platform_driver_register(&spi_imx_driver);
912 static void __exit spi_imx_exit(void)
914 platform_driver_unregister(&spi_imx_driver);
917 module_init(spi_imx_init);
918 module_exit(spi_imx_exit);
920 MODULE_DESCRIPTION("SPI Master Controller driver");
921 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
922 MODULE_LICENSE("GPL");