drivers/spi/spi-dw-mid.c

   1 /*
   2  * Special handling for DW core on Intel MID platform
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/slab.h>
  24 #include <linux/spi/spi.h>
  25
  26 #include "spi-dw.h"
  27
  28 #ifdef CONFIG_SPI_DW_MID_DMA
  29 #include <linux/intel_mid_dma.h>
  30 #include <linux/pci.h>
  31
  32 struct mid_dma {
  33         struct intel_mid_dma_slave      dmas_tx;
  34         struct intel_mid_dma_slave      dmas_rx;
  35 };
  36
  37 static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
  38 {
  39         struct dw_spi *dws = param;
  40
  41         return dws->dmac && (&dws->dmac->dev == chan->device->dev);
  42 }
  43
  44 static int mid_spi_dma_init(struct dw_spi *dws)
  45 {
  46         struct mid_dma *dw_dma = dws->dma_priv;
  47         struct intel_mid_dma_slave *rxs, *txs;
  48         dma_cap_mask_t mask;
  49
  50         /*
  51          * Get pci device for DMA controller, currently it could only
  52          * be the DMA controller of either Moorestown or Medfield
  53          */
  54         dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0813, NULL);
  55         if (!dws->dmac)
  56                 dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
  57
  58         dma_cap_zero(mask);
  59         dma_cap_set(DMA_SLAVE, mask);
  60
  61         /* 1. Init rx channel */
  62         dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
  63         if (!dws->rxchan)
  64                 goto err_exit;
  65         rxs = &dw_dma->dmas_rx;
  66         rxs->hs_mode = LNW_DMA_HW_HS;
  67         rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
  68         dws->rxchan->private = rxs;
  69
  70         /* 2. Init tx channel */
  71         dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
  72         if (!dws->txchan)
  73                 goto free_rxchan;
  74         txs = &dw_dma->dmas_tx;
  75         txs->hs_mode = LNW_DMA_HW_HS;
  76         txs->cfg_mode = LNW_DMA_MEM_TO_PER;
  77         dws->txchan->private = txs;
  78
  79         dws->dma_inited = 1;
  80         return 0;
  81
  82 free_rxchan:
  83         dma_release_channel(dws->rxchan);
  84 err_exit:
  85         return -1;
  86
  87 }
  88
  89 static void mid_spi_dma_exit(struct dw_spi *dws)
  90 {
  91         if (!dws->dma_inited)
  92                 return;
  93
  94         dmaengine_terminate_all(dws->txchan);
  95         dma_release_channel(dws->txchan);
  96
  97         dmaengine_terminate_all(dws->rxchan);
  98         dma_release_channel(dws->rxchan);
  99 }
 100
 101 /*
 102  * dws->dma_chan_done is cleared before the dma transfer starts,
 103  * callback for rx/tx channel will each increment it by 1.
 104  * Reaching 2 means the whole spi transaction is done.
 105  */
 106 static void dw_spi_dma_done(void *arg)
 107 {
 108         struct dw_spi *dws = arg;
 109
 110         if (++dws->dma_chan_done != 2)
 111                 return;
 112         dw_spi_xfer_done(dws);
 113 }
 114
 115 static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
 116 {
 117         struct dma_async_tx_descriptor *txdesc = NULL, *rxdesc = NULL;
 118         struct dma_chan *txchan, *rxchan;
 119         struct dma_slave_config txconf, rxconf;
 120         u16 dma_ctrl = 0;
 121
 122         /* 1. setup DMA related registers */
 123         if (cs_change) {
 124                 spi_enable_chip(dws, 0);
 125                 dw_writew(dws, DW_SPI_DMARDLR, 0xf);
 126                 dw_writew(dws, DW_SPI_DMATDLR, 0x10);
 127                 if (dws->tx_dma)
 128                         dma_ctrl |= 0x2;
 129                 if (dws->rx_dma)
 130                         dma_ctrl |= 0x1;
 131                 dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
 132                 spi_enable_chip(dws, 1);
 133         }
 134
 135         dws->dma_chan_done = 0;
 136         txchan = dws->txchan;
 137         rxchan = dws->rxchan;
 138
 139         /* 2. Prepare the TX dma transfer */
 140         txconf.direction = DMA_TO_DEVICE;
 141         txconf.dst_addr = dws->dma_addr;
 142         txconf.dst_maxburst = LNW_DMA_MSIZE_16;
 143         txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 144         txconf.dst_addr_width = dws->dma_width;
 145
 146         txchan->device->device_control(txchan, DMA_SLAVE_CONFIG,
 147                                        (unsigned long) &txconf);
 148
 149         memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
 150         dws->tx_sgl.dma_address = dws->tx_dma;
 151         dws->tx_sgl.length = dws->len;
 152
 153         txdesc = txchan->device->device_prep_slave_sg(txchan,
 154                                 &dws->tx_sgl,
 155                                 1,
 156                                 DMA_TO_DEVICE,
 157                                 DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP);
 158         txdesc->callback = dw_spi_dma_done;
 159         txdesc->callback_param = dws;
 160
 161         /* 3. Prepare the RX dma transfer */
 162         rxconf.direction = DMA_FROM_DEVICE;
 163         rxconf.src_addr = dws->dma_addr;
 164         rxconf.src_maxburst = LNW_DMA_MSIZE_16;
 165         rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 166         rxconf.src_addr_width = dws->dma_width;
 167
 168         rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG,
 169                                        (unsigned long) &rxconf);
 170
 171         memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
 172         dws->rx_sgl.dma_address = dws->rx_dma;
 173         dws->rx_sgl.length = dws->len;
 174
 175         rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
 176                                 &dws->rx_sgl,
 177                                 1,
 178                                 DMA_FROM_DEVICE,
 179                                 DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP);
 180         rxdesc->callback = dw_spi_dma_done;
 181         rxdesc->callback_param = dws;
 182
 183         /* rx must be started before tx due to spi instinct */
 184         rxdesc->tx_submit(rxdesc);
 185         txdesc->tx_submit(txdesc);
 186         return 0;
 187 }
 188
 189 static struct dw_spi_dma_ops mid_dma_ops = {
 190         .dma_init       = mid_spi_dma_init,
 191         .dma_exit       = mid_spi_dma_exit,
 192         .dma_transfer   = mid_spi_dma_transfer,
 193 };
 194 #endif
 195
 196 /* Some specific info for SPI0 controller on Moorestown */
 197
 198 /* HW info for MRST CLk Control Unit, one 32b reg */
 199 #define MRST_SPI_CLK_BASE       100000000       /* 100m */
 200 #define MRST_CLK_SPI0_REG       0xff11d86c
 201 #define CLK_SPI_BDIV_OFFSET     0
 202 #define CLK_SPI_BDIV_MASK       0x00000007
 203 #define CLK_SPI_CDIV_OFFSET     9
 204 #define CLK_SPI_CDIV_MASK       0x00000e00
 205 #define CLK_SPI_DISABLE_OFFSET  8
 206
 207 int dw_spi_mid_init(struct dw_spi *dws)
 208 {
 209         void __iomem *clk_reg;
 210         u32 clk_cdiv;
 211
 212         clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16);
 213         if (!clk_reg)
 214                 return -ENOMEM;
 215
 216         /* get SPI controller operating freq info */
 217         clk_cdiv  = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
 218         dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
 219         iounmap(clk_reg);
 220
 221         dws->num_cs = 16;
 222         dws->fifo_len = 40;     /* FIFO has 40 words buffer */
 223
 224 #ifdef CONFIG_SPI_DW_MID_DMA
 225         dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
 226         if (!dws->dma_priv)
 227                 return -ENOMEM;
 228         dws->dma_ops = &mid_dma_ops;
 229 #endif
 230         return 0;
 231 }