drivers/spi/omap2_mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrjölä <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/module.h>
  28 #include <linux/device.h>
  29 #include <linux/delay.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/io.h>
  35
  36 #include <linux/spi/spi.h>
  37
  38 #include <mach/dma.h>
  39 #include <mach/clock.h>
  40
  41
  42 #define OMAP2_MCSPI_MAX_FREQ            48000000
  43
  44 #define OMAP2_MCSPI_REVISION            0x00
  45 #define OMAP2_MCSPI_SYSCONFIG           0x10
  46 #define OMAP2_MCSPI_SYSSTATUS           0x14
  47 #define OMAP2_MCSPI_IRQSTATUS           0x18
  48 #define OMAP2_MCSPI_IRQENABLE           0x1c
  49 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  50 #define OMAP2_MCSPI_SYST                0x24
  51 #define OMAP2_MCSPI_MODULCTRL           0x28
  52
  53 /* per-channel banks, 0x14 bytes each, first is: */
  54 #define OMAP2_MCSPI_CHCONF0             0x2c
  55 #define OMAP2_MCSPI_CHSTAT0             0x30
  56 #define OMAP2_MCSPI_CHCTRL0             0x34
  57 #define OMAP2_MCSPI_TX0                 0x38
  58 #define OMAP2_MCSPI_RX0                 0x3c
  59
  60 /* per-register bitmasks: */
  61
  62 #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
  63 #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
  64 #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE  (1 << 0)
  65 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
  66
  67 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
  68
  69 #define OMAP2_MCSPI_MODULCTRL_SINGLE    (1 << 0)
  70 #define OMAP2_MCSPI_MODULCTRL_MS        (1 << 2)
  71 #define OMAP2_MCSPI_MODULCTRL_STEST     (1 << 3)
  72
  73 #define OMAP2_MCSPI_CHCONF_PHA          (1 << 0)
  74 #define OMAP2_MCSPI_CHCONF_POL          (1 << 1)
  75 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  76 #define OMAP2_MCSPI_CHCONF_EPOL         (1 << 6)
  77 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  78 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  (0x01 << 12)
  79 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  (0x02 << 12)
  80 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  81 #define OMAP2_MCSPI_CHCONF_DMAW         (1 << 14)
  82 #define OMAP2_MCSPI_CHCONF_DMAR         (1 << 15)
  83 #define OMAP2_MCSPI_CHCONF_DPE0         (1 << 16)
  84 #define OMAP2_MCSPI_CHCONF_DPE1         (1 << 17)
  85 #define OMAP2_MCSPI_CHCONF_IS           (1 << 18)
  86 #define OMAP2_MCSPI_CHCONF_TURBO        (1 << 19)
  87 #define OMAP2_MCSPI_CHCONF_FORCE        (1 << 20)
  88
  89 #define OMAP2_MCSPI_CHSTAT_RXS          (1 << 0)
  90 #define OMAP2_MCSPI_CHSTAT_TXS          (1 << 1)
  91 #define OMAP2_MCSPI_CHSTAT_EOT          (1 << 2)
  92
  93 #define OMAP2_MCSPI_CHCTRL_EN           (1 << 0)
  94
  95 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN   (1 << 0)
  96
  97 /* We have 2 DMA channels per CS, one for RX and one for TX */
  98 struct omap2_mcspi_dma {
  99         int dma_tx_channel;
 100         int dma_rx_channel;
 101
 102         int dma_tx_sync_dev;
 103         int dma_rx_sync_dev;
 104
 105         struct completion dma_tx_completion;
 106         struct completion dma_rx_completion;
 107 };
 108
 109 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 110  * cache operations; better heuristics consider wordsize and bitrate.
 111  */
 112 #define DMA_MIN_BYTES                   8
 113
 114
 115 struct omap2_mcspi {
 116         struct work_struct      work;
 117         /* lock protects queue and registers */
 118         spinlock_t              lock;
 119         struct list_head        msg_queue;
 120         struct spi_master       *master;
 121         struct clk              *ick;
 122         struct clk              *fck;
 123         /* Virtual base address of the controller */
 124         void __iomem            *base;
 125         unsigned long           phys;
 126         /* SPI1 has 4 channels, while SPI2 has 2 */
 127         struct omap2_mcspi_dma  *dma_channels;
 128 };
 129
 130 struct omap2_mcspi_cs {
 131         void __iomem            *base;
 132         unsigned long           phys;
 133         int                     word_len;
 134 };
 135
 136 static struct workqueue_struct *omap2_mcspi_wq;
 137
 138 #define MOD_REG_BIT(val, mask, set) do { \
 139         if (set) \
 140                 val |= mask; \
 141         else \
 142                 val &= ~mask; \
 143 } while (0)
 144
 145 static inline void mcspi_write_reg(struct spi_master *master,
 146                 int idx, u32 val)
 147 {
 148         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 149
 150         __raw_writel(val, mcspi->base + idx);
 151 }
 152
 153 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 154 {
 155         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 156
 157         return __raw_readl(mcspi->base + idx);
 158 }
 159
 160 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 161                 int idx, u32 val)
 162 {
 163         struct omap2_mcspi_cs   *cs = spi->controller_state;
 164
 165         __raw_writel(val, cs->base +  idx);
 166 }
 167
 168 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 169 {
 170         struct omap2_mcspi_cs   *cs = spi->controller_state;
 171
 172         return __raw_readl(cs->base + idx);
 173 }
 174
 175 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 176                 int is_read, int enable)
 177 {
 178         u32 l, rw;
 179
 180         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 181
 182         if (is_read) /* 1 is read, 0 write */
 183                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 184         else
 185                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 186
 187         MOD_REG_BIT(l, rw, enable);
 188         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
 189 }
 190
 191 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 192 {
 193         u32 l;
 194
 195         l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
 196         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
 197 }
 198
 199 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 200 {
 201         u32 l;
 202
 203         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 204         MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
 205         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
 206 }
 207
 208 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 209 {
 210         u32 l;
 211
 212         /* setup when switching from (reset default) slave mode
 213          * to single-channel master mode
 214          */
 215         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 216         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
 217         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
 218         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
 219         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 220 }
 221
 222 static unsigned
 223 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 224 {
 225         struct omap2_mcspi      *mcspi;
 226         struct omap2_mcspi_cs   *cs = spi->controller_state;
 227         struct omap2_mcspi_dma  *mcspi_dma;
 228         unsigned int            count, c;
 229         unsigned long           base, tx_reg, rx_reg;
 230         int                     word_len, data_type, element_count;
 231         u8                      * rx;
 232         const u8                * tx;
 233
 234         mcspi = spi_master_get_devdata(spi->master);
 235         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 236
 237         count = xfer->len;
 238         c = count;
 239         word_len = cs->word_len;
 240
 241         base = cs->phys;
 242         tx_reg = base + OMAP2_MCSPI_TX0;
 243         rx_reg = base + OMAP2_MCSPI_RX0;
 244         rx = xfer->rx_buf;
 245         tx = xfer->tx_buf;
 246
 247         if (word_len <= 8) {
 248                 data_type = OMAP_DMA_DATA_TYPE_S8;
 249                 element_count = count;
 250         } else if (word_len <= 16) {
 251                 data_type = OMAP_DMA_DATA_TYPE_S16;
 252                 element_count = count >> 1;
 253         } else /* word_len <= 32 */ {
 254                 data_type = OMAP_DMA_DATA_TYPE_S32;
 255                 element_count = count >> 2;
 256         }
 257
 258         if (tx != NULL) {
 259                 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
 260                                 data_type, element_count, 1,
 261                                 OMAP_DMA_SYNC_ELEMENT,
 262                                 mcspi_dma->dma_tx_sync_dev, 0);
 263
 264                 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
 265                                 OMAP_DMA_AMODE_CONSTANT,
 266                                 tx_reg, 0, 0);
 267
 268                 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
 269                                 OMAP_DMA_AMODE_POST_INC,
 270                                 xfer->tx_dma, 0, 0);
 271         }
 272
 273         if (rx != NULL) {
 274                 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
 275                                 data_type, element_count - 1, 1,
 276                                 OMAP_DMA_SYNC_ELEMENT,
 277                                 mcspi_dma->dma_rx_sync_dev, 1);
 278
 279                 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
 280                                 OMAP_DMA_AMODE_CONSTANT,
 281                                 rx_reg, 0, 0);
 282
 283                 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
 284                                 OMAP_DMA_AMODE_POST_INC,
 285                                 xfer->rx_dma, 0, 0);
 286         }
 287
 288         if (tx != NULL) {
 289                 omap_start_dma(mcspi_dma->dma_tx_channel);
 290                 omap2_mcspi_set_dma_req(spi, 0, 1);
 291         }
 292
 293         if (rx != NULL) {
 294                 omap_start_dma(mcspi_dma->dma_rx_channel);
 295                 omap2_mcspi_set_dma_req(spi, 1, 1);
 296         }
 297
 298         if (tx != NULL) {
 299                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 300                 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
 301         }
 302
 303         if (rx != NULL) {
 304                 wait_for_completion(&mcspi_dma->dma_rx_completion);
 305                 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
 306                 omap2_mcspi_set_enable(spi, 0);
 307                 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
 308                                 & OMAP2_MCSPI_CHSTAT_RXS)) {
 309                         u32 w;
 310
 311                         w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
 312                         if (word_len <= 8)
 313                                 ((u8 *)xfer->rx_buf)[element_count - 1] = w;
 314                         else if (word_len <= 16)
 315                                 ((u16 *)xfer->rx_buf)[element_count - 1] = w;
 316                         else /* word_len <= 32 */
 317                                 ((u32 *)xfer->rx_buf)[element_count - 1] = w;
 318                 } else {
 319                         dev_err(&spi->dev, "DMA RX last word empty");
 320                         count -= (word_len <= 8)  ? 1 :
 321                                  (word_len <= 16) ? 2 :
 322                                /* word_len <= 32 */ 4;
 323                 }
 324                 omap2_mcspi_set_enable(spi, 1);
 325         }
 326         return count;
 327 }
 328
 329 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 330 {
 331         unsigned long timeout;
 332
 333         timeout = jiffies + msecs_to_jiffies(1000);
 334         while (!(__raw_readl(reg) & bit)) {
 335                 if (time_after(jiffies, timeout))
 336                         return -1;
 337                 cpu_relax();
 338         }
 339         return 0;
 340 }
 341
 342 static unsigned
 343 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 344 {
 345         struct omap2_mcspi      *mcspi;
 346         struct omap2_mcspi_cs   *cs = spi->controller_state;
 347         unsigned int            count, c;
 348         u32                     l;
 349         void __iomem            *base = cs->base;
 350         void __iomem            *tx_reg;
 351         void __iomem            *rx_reg;
 352         void __iomem            *chstat_reg;
 353         int                     word_len;
 354
 355         mcspi = spi_master_get_devdata(spi->master);
 356         count = xfer->len;
 357         c = count;
 358         word_len = cs->word_len;
 359
 360         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 361         l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 362
 363         /* We store the pre-calculated register addresses on stack to speed
 364          * up the transfer loop. */
 365         tx_reg          = base + OMAP2_MCSPI_TX0;
 366         rx_reg          = base + OMAP2_MCSPI_RX0;
 367         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 368
 369         if (word_len <= 8) {
 370                 u8              *rx;
 371                 const u8        *tx;
 372
 373                 rx = xfer->rx_buf;
 374                 tx = xfer->tx_buf;
 375
 376                 do {
 377                         c -= 1;
 378                         if (tx != NULL) {
 379                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 380                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 381                                         dev_err(&spi->dev, "TXS timed out\n");
 382                                         goto out;
 383                                 }
 384 #ifdef VERBOSE
 385                                 dev_dbg(&spi->dev, "write-%d %02x\n",
 386                                                 word_len, *tx);
 387 #endif
 388                                 __raw_writel(*tx++, tx_reg);
 389                         }
 390                         if (rx != NULL) {
 391                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 392                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 393                                         dev_err(&spi->dev, "RXS timed out\n");
 394                                         goto out;
 395                                 }
 396                                 /* prevent last RX_ONLY read from triggering
 397                                  * more word i/o: switch to rx+tx
 398                                  */
 399                                 if (c == 0 && tx == NULL)
 400                                         mcspi_write_cs_reg(spi,
 401                                                         OMAP2_MCSPI_CHCONF0, l);
 402                                 *rx++ = __raw_readl(rx_reg);
 403 #ifdef VERBOSE
 404                                 dev_dbg(&spi->dev, "read-%d %02x\n",
 405                                                 word_len, *(rx - 1));
 406 #endif
 407                         }
 408                 } while (c);
 409         } else if (word_len <= 16) {
 410                 u16             *rx;
 411                 const u16       *tx;
 412
 413                 rx = xfer->rx_buf;
 414                 tx = xfer->tx_buf;
 415                 do {
 416                         c -= 2;
 417                         if (tx != NULL) {
 418                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 419                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 420                                         dev_err(&spi->dev, "TXS timed out\n");
 421                                         goto out;
 422                                 }
 423 #ifdef VERBOSE
 424                                 dev_dbg(&spi->dev, "write-%d %04x\n",
 425                                                 word_len, *tx);
 426 #endif
 427                                 __raw_writel(*tx++, tx_reg);
 428                         }
 429                         if (rx != NULL) {
 430                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 431                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 432                                         dev_err(&spi->dev, "RXS timed out\n");
 433                                         goto out;
 434                                 }
 435                                 /* prevent last RX_ONLY read from triggering
 436                                  * more word i/o: switch to rx+tx
 437                                  */
 438                                 if (c == 0 && tx == NULL)
 439                                         mcspi_write_cs_reg(spi,
 440                                                         OMAP2_MCSPI_CHCONF0, l);
 441                                 *rx++ = __raw_readl(rx_reg);
 442 #ifdef VERBOSE
 443                                 dev_dbg(&spi->dev, "read-%d %04x\n",
 444                                                 word_len, *(rx - 1));
 445 #endif
 446                         }
 447                 } while (c);
 448         } else if (word_len <= 32) {
 449                 u32             *rx;
 450                 const u32       *tx;
 451
 452                 rx = xfer->rx_buf;
 453                 tx = xfer->tx_buf;
 454                 do {
 455                         c -= 4;
 456                         if (tx != NULL) {
 457                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 458                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 459                                         dev_err(&spi->dev, "TXS timed out\n");
 460                                         goto out;
 461                                 }
 462 #ifdef VERBOSE
 463                                 dev_dbg(&spi->dev, "write-%d %04x\n",
 464                                                 word_len, *tx);
 465 #endif
 466                                 __raw_writel(*tx++, tx_reg);
 467                         }
 468                         if (rx != NULL) {
 469                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 470                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 471                                         dev_err(&spi->dev, "RXS timed out\n");
 472                                         goto out;
 473                                 }
 474                                 /* prevent last RX_ONLY read from triggering
 475                                  * more word i/o: switch to rx+tx
 476                                  */
 477                                 if (c == 0 && tx == NULL)
 478                                         mcspi_write_cs_reg(spi,
 479                                                         OMAP2_MCSPI_CHCONF0, l);
 480                                 *rx++ = __raw_readl(rx_reg);
 481 #ifdef VERBOSE
 482                                 dev_dbg(&spi->dev, "read-%d %04x\n",
 483                                                 word_len, *(rx - 1));
 484 #endif
 485                         }
 486                 } while (c);
 487         }
 488
 489         /* for TX_ONLY mode, be sure all words have shifted out */
 490         if (xfer->rx_buf == NULL) {
 491                 if (mcspi_wait_for_reg_bit(chstat_reg,
 492                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 493                         dev_err(&spi->dev, "TXS timed out\n");
 494                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 495                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 496                         dev_err(&spi->dev, "EOT timed out\n");
 497         }
 498 out:
 499         return count - c;
 500 }
 501
 502 /* called only when no transfer is active to this device */
 503 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 504                 struct spi_transfer *t)
 505 {
 506         struct omap2_mcspi_cs *cs = spi->controller_state;
 507         struct omap2_mcspi *mcspi;
 508         u32 l = 0, div = 0;
 509         u8 word_len = spi->bits_per_word;
 510
 511         mcspi = spi_master_get_devdata(spi->master);
 512
 513         if (t != NULL && t->bits_per_word)
 514                 word_len = t->bits_per_word;
 515
 516         cs->word_len = word_len;
 517
 518         if (spi->max_speed_hz) {
 519                 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
 520                                         > spi->max_speed_hz)
 521                         div++;
 522         } else
 523                 div = 15;
 524
 525         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 526
 527         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 528          * REVISIT: this controller could support SPI_3WIRE mode.
 529          */
 530         l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
 531         l |= OMAP2_MCSPI_CHCONF_DPE0;
 532
 533         /* wordlength */
 534         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 535         l |= (word_len - 1) << 7;
 536
 537         /* set chipselect polarity; manage with FORCE */
 538         if (!(spi->mode & SPI_CS_HIGH))
 539                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 540         else
 541                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 542
 543         /* set clock divisor */
 544         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 545         l |= div << 2;
 546
 547         /* set SPI mode 0..3 */
 548         if (spi->mode & SPI_CPOL)
 549                 l |= OMAP2_MCSPI_CHCONF_POL;
 550         else
 551                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 552         if (spi->mode & SPI_CPHA)
 553                 l |= OMAP2_MCSPI_CHCONF_PHA;
 554         else
 555                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 556
 557         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
 558
 559         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 560                         OMAP2_MCSPI_MAX_FREQ / (1 << div),
 561                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 562                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 563
 564         return 0;
 565 }
 566
 567 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
 568 {
 569         struct spi_device       *spi = data;
 570         struct omap2_mcspi      *mcspi;
 571         struct omap2_mcspi_dma  *mcspi_dma;
 572
 573         mcspi = spi_master_get_devdata(spi->master);
 574         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 575
 576         complete(&mcspi_dma->dma_rx_completion);
 577
 578         /* We must disable the DMA RX request */
 579         omap2_mcspi_set_dma_req(spi, 1, 0);
 580 }
 581
 582 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
 583 {
 584         struct spi_device       *spi = data;
 585         struct omap2_mcspi      *mcspi;
 586         struct omap2_mcspi_dma  *mcspi_dma;
 587
 588         mcspi = spi_master_get_devdata(spi->master);
 589         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 590
 591         complete(&mcspi_dma->dma_tx_completion);
 592
 593         /* We must disable the DMA TX request */
 594         omap2_mcspi_set_dma_req(spi, 0, 0);
 595 }
 596
 597 static int omap2_mcspi_request_dma(struct spi_device *spi)
 598 {
 599         struct spi_master       *master = spi->master;
 600         struct omap2_mcspi      *mcspi;
 601         struct omap2_mcspi_dma  *mcspi_dma;
 602
 603         mcspi = spi_master_get_devdata(master);
 604         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 605
 606         if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
 607                         omap2_mcspi_dma_rx_callback, spi,
 608                         &mcspi_dma->dma_rx_channel)) {
 609                 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
 610                 return -EAGAIN;
 611         }
 612
 613         if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
 614                         omap2_mcspi_dma_tx_callback, spi,
 615                         &mcspi_dma->dma_tx_channel)) {
 616                 omap_free_dma(mcspi_dma->dma_rx_channel);
 617                 mcspi_dma->dma_rx_channel = -1;
 618                 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
 619                 return -EAGAIN;
 620         }
 621
 622         init_completion(&mcspi_dma->dma_rx_completion);
 623         init_completion(&mcspi_dma->dma_tx_completion);
 624
 625         return 0;
 626 }
 627
 628 static int omap2_mcspi_setup(struct spi_device *spi)
 629 {
 630         int                     ret;
 631         struct omap2_mcspi      *mcspi;
 632         struct omap2_mcspi_dma  *mcspi_dma;
 633         struct omap2_mcspi_cs   *cs = spi->controller_state;
 634
 635         if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
 636                 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
 637                         spi->bits_per_word);
 638                 return -EINVAL;
 639         }
 640
 641         mcspi = spi_master_get_devdata(spi->master);
 642         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 643
 644         if (!cs) {
 645                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 646                 if (!cs)
 647                         return -ENOMEM;
 648                 cs->base = mcspi->base + spi->chip_select * 0x14;
 649                 cs->phys = mcspi->phys + spi->chip_select * 0x14;
 650                 spi->controller_state = cs;
 651         }
 652
 653         if (mcspi_dma->dma_rx_channel == -1
 654                         || mcspi_dma->dma_tx_channel == -1) {
 655                 ret = omap2_mcspi_request_dma(spi);
 656                 if (ret < 0)
 657                         return ret;
 658         }
 659
 660         clk_enable(mcspi->ick);
 661         clk_enable(mcspi->fck);
 662         ret = omap2_mcspi_setup_transfer(spi, NULL);
 663         clk_disable(mcspi->fck);
 664         clk_disable(mcspi->ick);
 665
 666         return ret;
 667 }
 668
 669 static void omap2_mcspi_cleanup(struct spi_device *spi)
 670 {
 671         struct omap2_mcspi      *mcspi;
 672         struct omap2_mcspi_dma  *mcspi_dma;
 673
 674         mcspi = spi_master_get_devdata(spi->master);
 675         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 676
 677         kfree(spi->controller_state);
 678
 679         if (mcspi_dma->dma_rx_channel != -1) {
 680                 omap_free_dma(mcspi_dma->dma_rx_channel);
 681                 mcspi_dma->dma_rx_channel = -1;
 682         }
 683         if (mcspi_dma->dma_tx_channel != -1) {
 684                 omap_free_dma(mcspi_dma->dma_tx_channel);
 685                 mcspi_dma->dma_tx_channel = -1;
 686         }
 687 }
 688
 689 static void omap2_mcspi_work(struct work_struct *work)
 690 {
 691         struct omap2_mcspi      *mcspi;
 692
 693         mcspi = container_of(work, struct omap2_mcspi, work);
 694         spin_lock_irq(&mcspi->lock);
 695
 696         clk_enable(mcspi->ick);
 697         clk_enable(mcspi->fck);
 698
 699         /* We only enable one channel at a time -- the one whose message is
 700          * at the head of the queue -- although this controller would gladly
 701          * arbitrate among multiple channels.  This corresponds to "single
 702          * channel" master mode.  As a side effect, we need to manage the
 703          * chipselect with the FORCE bit ... CS != channel enable.
 704          */
 705         while (!list_empty(&mcspi->msg_queue)) {
 706                 struct spi_message              *m;
 707                 struct spi_device               *spi;
 708                 struct spi_transfer             *t = NULL;
 709                 int                             cs_active = 0;
 710                 struct omap2_mcspi_cs           *cs;
 711                 int                             par_override = 0;
 712                 int                             status = 0;
 713                 u32                             chconf;
 714
 715                 m = container_of(mcspi->msg_queue.next, struct spi_message,
 716                                  queue);
 717
 718                 list_del_init(&m->queue);
 719                 spin_unlock_irq(&mcspi->lock);
 720
 721                 spi = m->spi;
 722                 cs = spi->controller_state;
 723
 724                 omap2_mcspi_set_enable(spi, 1);
 725                 list_for_each_entry(t, &m->transfers, transfer_list) {
 726                         if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 727                                 status = -EINVAL;
 728                                 break;
 729                         }
 730                         if (par_override || t->speed_hz || t->bits_per_word) {
 731                                 par_override = 1;
 732                                 status = omap2_mcspi_setup_transfer(spi, t);
 733                                 if (status < 0)
 734                                         break;
 735                                 if (!t->speed_hz && !t->bits_per_word)
 736                                         par_override = 0;
 737                         }
 738
 739                         if (!cs_active) {
 740                                 omap2_mcspi_force_cs(spi, 1);
 741                                 cs_active = 1;
 742                         }
 743
 744                         chconf = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 745                         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 746                         if (t->tx_buf == NULL)
 747                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
 748                         else if (t->rx_buf == NULL)
 749                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
 750                         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, chconf);
 751
 752                         if (t->len) {
 753                                 unsigned        count;
 754
 755                                 /* RX_ONLY mode needs dummy data in TX reg */
 756                                 if (t->tx_buf == NULL)
 757                                         __raw_writel(0, cs->base
 758                                                         + OMAP2_MCSPI_TX0);
 759
 760                                 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
 761                                         count = omap2_mcspi_txrx_dma(spi, t);
 762                                 else
 763                                         count = omap2_mcspi_txrx_pio(spi, t);
 764                                 m->actual_length += count;
 765
 766                                 if (count != t->len) {
 767                                         status = -EIO;
 768                                         break;
 769                                 }
 770                         }
 771
 772                         if (t->delay_usecs)
 773                                 udelay(t->delay_usecs);
 774
 775                         /* ignore the "leave it on after last xfer" hint */
 776                         if (t->cs_change) {
 777                                 omap2_mcspi_force_cs(spi, 0);
 778                                 cs_active = 0;
 779                         }
 780                 }
 781
 782                 /* Restore defaults if they were overriden */
 783                 if (par_override) {
 784                         par_override = 0;
 785                         status = omap2_mcspi_setup_transfer(spi, NULL);
 786                 }
 787
 788                 if (cs_active)
 789                         omap2_mcspi_force_cs(spi, 0);
 790
 791                 omap2_mcspi_set_enable(spi, 0);
 792
 793                 m->status = status;
 794                 m->complete(m->context);
 795
 796                 spin_lock_irq(&mcspi->lock);
 797         }
 798
 799         clk_disable(mcspi->fck);
 800         clk_disable(mcspi->ick);
 801
 802         spin_unlock_irq(&mcspi->lock);
 803 }
 804
 805 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
 806 {
 807         struct omap2_mcspi      *mcspi;
 808         unsigned long           flags;
 809         struct spi_transfer     *t;
 810
 811         m->actual_length = 0;
 812         m->status = 0;
 813
 814         /* reject invalid messages and transfers */
 815         if (list_empty(&m->transfers) || !m->complete)
 816                 return -EINVAL;
 817         list_for_each_entry(t, &m->transfers, transfer_list) {
 818                 const void      *tx_buf = t->tx_buf;
 819                 void            *rx_buf = t->rx_buf;
 820                 unsigned        len = t->len;
 821
 822                 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
 823                                 || (len && !(rx_buf || tx_buf))
 824                                 || (t->bits_per_word &&
 825                                         (  t->bits_per_word < 4
 826                                         || t->bits_per_word > 32))) {
 827                         dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
 828                                         t->speed_hz,
 829                                         len,
 830                                         tx_buf ? "tx" : "",
 831                                         rx_buf ? "rx" : "",
 832                                         t->bits_per_word);
 833                         return -EINVAL;
 834                 }
 835                 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
 836                         dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
 837                                         t->speed_hz,
 838                                         OMAP2_MCSPI_MAX_FREQ/(1<<16));
 839                         return -EINVAL;
 840                 }
 841
 842                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
 843                         continue;
 844
 845                 /* Do DMA mapping "early" for better error reporting and
 846                  * dcache use.  Note that if dma_unmap_single() ever starts
 847                  * to do real work on ARM, we'd need to clean up mappings
 848                  * for previous transfers on *ALL* exits of this loop...
 849                  */
 850                 if (tx_buf != NULL) {
 851                         t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
 852                                         len, DMA_TO_DEVICE);
 853                         if (dma_mapping_error(&spi->dev, t->tx_dma)) {
 854                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
 855                                                 'T', len);
 856                                 return -EINVAL;
 857                         }
 858                 }
 859                 if (rx_buf != NULL) {
 860                         t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
 861                                         DMA_FROM_DEVICE);
 862                         if (dma_mapping_error(&spi->dev, t->rx_dma)) {
 863                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
 864                                                 'R', len);
 865                                 if (tx_buf != NULL)
 866                                         dma_unmap_single(NULL, t->tx_dma,
 867                                                         len, DMA_TO_DEVICE);
 868                                 return -EINVAL;
 869                         }
 870                 }
 871         }
 872
 873         mcspi = spi_master_get_devdata(spi->master);
 874
 875         spin_lock_irqsave(&mcspi->lock, flags);
 876         list_add_tail(&m->queue, &mcspi->msg_queue);
 877         queue_work(omap2_mcspi_wq, &mcspi->work);
 878         spin_unlock_irqrestore(&mcspi->lock, flags);
 879
 880         return 0;
 881 }
 882
 883 static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
 884 {
 885         struct spi_master       *master = mcspi->master;
 886         u32                     tmp;
 887
 888         clk_enable(mcspi->ick);
 889         clk_enable(mcspi->fck);
 890
 891         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
 892                         OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
 893         do {
 894                 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
 895         } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
 896
 897         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
 898                         OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
 899                         OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
 900                         OMAP2_MCSPI_SYSCONFIG_SMARTIDLE);
 901
 902         mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
 903                         OMAP2_MCSPI_WAKEUPENABLE_WKEN);
 904
 905         omap2_mcspi_set_master_mode(master);
 906
 907         clk_disable(mcspi->fck);
 908         clk_disable(mcspi->ick);
 909         return 0;
 910 }
 911
 912 static u8 __initdata spi1_rxdma_id [] = {
 913         OMAP24XX_DMA_SPI1_RX0,
 914         OMAP24XX_DMA_SPI1_RX1,
 915         OMAP24XX_DMA_SPI1_RX2,
 916         OMAP24XX_DMA_SPI1_RX3,
 917 };
 918
 919 static u8 __initdata spi1_txdma_id [] = {
 920         OMAP24XX_DMA_SPI1_TX0,
 921         OMAP24XX_DMA_SPI1_TX1,
 922         OMAP24XX_DMA_SPI1_TX2,
 923         OMAP24XX_DMA_SPI1_TX3,
 924 };
 925
 926 static u8 __initdata spi2_rxdma_id[] = {
 927         OMAP24XX_DMA_SPI2_RX0,
 928         OMAP24XX_DMA_SPI2_RX1,
 929 };
 930
 931 static u8 __initdata spi2_txdma_id[] = {
 932         OMAP24XX_DMA_SPI2_TX0,
 933         OMAP24XX_DMA_SPI2_TX1,
 934 };
 935
 936 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
 937 static u8 __initdata spi3_rxdma_id[] = {
 938         OMAP24XX_DMA_SPI3_RX0,
 939         OMAP24XX_DMA_SPI3_RX1,
 940 };
 941
 942 static u8 __initdata spi3_txdma_id[] = {
 943         OMAP24XX_DMA_SPI3_TX0,
 944         OMAP24XX_DMA_SPI3_TX1,
 945 };
 946 #endif
 947
 948 #ifdef CONFIG_ARCH_OMAP3
 949 static u8 __initdata spi4_rxdma_id[] = {
 950         OMAP34XX_DMA_SPI4_RX0,
 951 };
 952
 953 static u8 __initdata spi4_txdma_id[] = {
 954         OMAP34XX_DMA_SPI4_TX0,
 955 };
 956 #endif
 957
 958 static int __init omap2_mcspi_probe(struct platform_device *pdev)
 959 {
 960         struct spi_master       *master;
 961         struct omap2_mcspi      *mcspi;
 962         struct resource         *r;
 963         int                     status = 0, i;
 964         const u8                *rxdma_id, *txdma_id;
 965         unsigned                num_chipselect;
 966
 967         switch (pdev->id) {
 968         case 1:
 969                 rxdma_id = spi1_rxdma_id;
 970                 txdma_id = spi1_txdma_id;
 971                 num_chipselect = 4;
 972                 break;
 973         case 2:
 974                 rxdma_id = spi2_rxdma_id;
 975                 txdma_id = spi2_txdma_id;
 976                 num_chipselect = 2;
 977                 break;
 978 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
 979         case 3:
 980                 rxdma_id = spi3_rxdma_id;
 981                 txdma_id = spi3_txdma_id;
 982                 num_chipselect = 2;
 983                 break;
 984 #endif
 985 #ifdef CONFIG_ARCH_OMAP3
 986         case 4:
 987                 rxdma_id = spi4_rxdma_id;
 988                 txdma_id = spi4_txdma_id;
 989                 num_chipselect = 1;
 990                 break;
 991 #endif
 992         default:
 993                 return -EINVAL;
 994         }
 995
 996         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
 997         if (master == NULL) {
 998                 dev_dbg(&pdev->dev, "master allocation failed\n");
 999                 return -ENOMEM;
1000         }
1001
1002         /* the spi->mode bits understood by this driver: */
1003         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1004
1005         if (pdev->id != -1)
1006                 master->bus_num = pdev->id;
1007
1008         master->setup = omap2_mcspi_setup;
1009         master->transfer = omap2_mcspi_transfer;
1010         master->cleanup = omap2_mcspi_cleanup;
1011         master->num_chipselect = num_chipselect;
1012
1013         dev_set_drvdata(&pdev->dev, master);
1014
1015         mcspi = spi_master_get_devdata(master);
1016         mcspi->master = master;
1017
1018         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1019         if (r == NULL) {
1020                 status = -ENODEV;
1021                 goto err1;
1022         }
1023         if (!request_mem_region(r->start, (r->end - r->start) + 1,
1024                         dev_name(&pdev->dev))) {
1025                 status = -EBUSY;
1026                 goto err1;
1027         }
1028
1029         mcspi->phys = r->start;
1030         mcspi->base = ioremap(r->start, r->end - r->start + 1);
1031         if (!mcspi->base) {
1032                 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1033                 status = -ENOMEM;
1034                 goto err1aa;
1035         }
1036
1037         INIT_WORK(&mcspi->work, omap2_mcspi_work);
1038
1039         spin_lock_init(&mcspi->lock);
1040         INIT_LIST_HEAD(&mcspi->msg_queue);
1041
1042         mcspi->ick = clk_get(&pdev->dev, "ick");
1043         if (IS_ERR(mcspi->ick)) {
1044                 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1045                 status = PTR_ERR(mcspi->ick);
1046                 goto err1a;
1047         }
1048         mcspi->fck = clk_get(&pdev->dev, "fck");
1049         if (IS_ERR(mcspi->fck)) {
1050                 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1051                 status = PTR_ERR(mcspi->fck);
1052                 goto err2;
1053         }
1054
1055         mcspi->dma_channels = kcalloc(master->num_chipselect,
1056                         sizeof(struct omap2_mcspi_dma),
1057                         GFP_KERNEL);
1058
1059         if (mcspi->dma_channels == NULL)
1060                 goto err3;
1061
1062         for (i = 0; i < num_chipselect; i++) {
1063                 mcspi->dma_channels[i].dma_rx_channel = -1;
1064                 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
1065                 mcspi->dma_channels[i].dma_tx_channel = -1;
1066                 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
1067         }
1068
1069         if (omap2_mcspi_reset(mcspi) < 0)
1070                 goto err4;
1071
1072         status = spi_register_master(master);
1073         if (status < 0)
1074                 goto err4;
1075
1076         return status;
1077
1078 err4:
1079         kfree(mcspi->dma_channels);
1080 err3:
1081         clk_put(mcspi->fck);
1082 err2:
1083         clk_put(mcspi->ick);
1084 err1a:
1085         iounmap(mcspi->base);
1086 err1aa:
1087         release_mem_region(r->start, (r->end - r->start) + 1);
1088 err1:
1089         spi_master_put(master);
1090         return status;
1091 }
1092
1093 static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1094 {
1095         struct spi_master       *master;
1096         struct omap2_mcspi      *mcspi;
1097         struct omap2_mcspi_dma  *dma_channels;
1098         struct resource         *r;
1099         void __iomem *base;
1100
1101         master = dev_get_drvdata(&pdev->dev);
1102         mcspi = spi_master_get_devdata(master);
1103         dma_channels = mcspi->dma_channels;
1104
1105         clk_put(mcspi->fck);
1106         clk_put(mcspi->ick);
1107
1108         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1109         release_mem_region(r->start, (r->end - r->start) + 1);
1110
1111         base = mcspi->base;
1112         spi_unregister_master(master);
1113         iounmap(base);
1114         kfree(dma_channels);
1115
1116         return 0;
1117 }
1118
1119 /* work with hotplug and coldplug */
1120 MODULE_ALIAS("platform:omap2_mcspi");
1121
1122 static struct platform_driver omap2_mcspi_driver = {
1123         .driver = {
1124                 .name =         "omap2_mcspi",
1125                 .owner =        THIS_MODULE,
1126         },
1127         .remove =       __exit_p(omap2_mcspi_remove),
1128 };
1129
1130
1131 static int __init omap2_mcspi_init(void)
1132 {
1133         omap2_mcspi_wq = create_singlethread_workqueue(
1134                                 omap2_mcspi_driver.driver.name);
1135         if (omap2_mcspi_wq == NULL)
1136                 return -1;
1137         return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1138 }
1139 subsys_initcall(omap2_mcspi_init);
1140
1141 static void __exit omap2_mcspi_exit(void)
1142 {
1143         platform_driver_unregister(&omap2_mcspi_driver);
1144
1145         destroy_workqueue(omap2_mcspi_wq);
1146 }
1147 module_exit(omap2_mcspi_exit);
1148
1149 MODULE_LICENSE("GPL");