drivers/spi/dw_spi.c

   1 /*
   2  * dw_spi.c - Designware SPI core controller driver (refer pxa2xx_spi.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/highmem.h>
  23 #include <linux/delay.h>
  24 #include <linux/slab.h>
  25 #include <linux/spi/spi.h>
  26
  27 #include "dw_spi.h"
  28
  29 #ifdef CONFIG_DEBUG_FS
  30 #include <linux/debugfs.h>
  31 #endif
  32
  33 #define START_STATE     ((void *)0)
  34 #define RUNNING_STATE   ((void *)1)
  35 #define DONE_STATE      ((void *)2)
  36 #define ERROR_STATE     ((void *)-1)
  37
  38 #define QUEUE_RUNNING   0
  39 #define QUEUE_STOPPED   1
  40
  41 #define MRST_SPI_DEASSERT       0
  42 #define MRST_SPI_ASSERT         1
  43
  44 /* Slave spi_dev related */
  45 struct chip_data {
  46         u16 cr0;
  47         u8 cs;                  /* chip select pin */
  48         u8 n_bytes;             /* current is a 1/2/4 byte op */
  49         u8 tmode;               /* TR/TO/RO/EEPROM */
  50         u8 type;                /* SPI/SSP/MicroWire */
  51
  52         u8 poll_mode;           /* 1 means use poll mode */
  53
  54         u32 dma_width;
  55         u32 rx_threshold;
  56         u32 tx_threshold;
  57         u8 enable_dma;
  58         u8 bits_per_word;
  59         u16 clk_div;            /* baud rate divider */
  60         u32 speed_hz;           /* baud rate */
  61         int (*write)(struct dw_spi *dws);
  62         int (*read)(struct dw_spi *dws);
  63         void (*cs_control)(u32 command);
  64 };
  65
  66 #ifdef CONFIG_DEBUG_FS
  67 static int spi_show_regs_open(struct inode *inode, struct file *file)
  68 {
  69         file->private_data = inode->i_private;
  70         return 0;
  71 }
  72
  73 #define SPI_REGS_BUFSIZE        1024
  74 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,
  75                                 size_t count, loff_t *ppos)
  76 {
  77         struct dw_spi *dws;
  78         char *buf;
  79         u32 len = 0;
  80         ssize_t ret;
  81
  82         dws = file->private_data;
  83
  84         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
  85         if (!buf)
  86                 return 0;
  87
  88         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  89                         "MRST SPI0 registers:\n");
  90         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  91                         "=================================\n");
  92         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  93                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
  94         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  95                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
  96         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  97                         "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
  98         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
  99                         "SER: \t\t0x%08x\n", dw_readl(dws, ser));
 100         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 101                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
 102         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 103                         "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
 104         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 105                         "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
 106         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 107                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
 108         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 109                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
 110         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 111                         "SR: \t\t0x%08x\n", dw_readl(dws, sr));
 112         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 113                         "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
 114         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 115                         "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
 116         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 117                         "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
 118         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 119                         "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
 120         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 121                         "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
 122         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 123                         "=================================\n");
 124
 125         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 126         kfree(buf);
 127         return ret;
 128 }
 129
 130 static const struct file_operations mrst_spi_regs_ops = {
 131         .owner          = THIS_MODULE,
 132         .open           = spi_show_regs_open,
 133         .read           = spi_show_regs,
 134         .llseek         = default_llseek,
 135 };
 136
 137 static int mrst_spi_debugfs_init(struct dw_spi *dws)
 138 {
 139         dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
 140         if (!dws->debugfs)
 141                 return -ENOMEM;
 142
 143         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 144                 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
 145         return 0;
 146 }
 147
 148 static void mrst_spi_debugfs_remove(struct dw_spi *dws)
 149 {
 150         if (dws->debugfs)
 151                 debugfs_remove_recursive(dws->debugfs);
 152 }
 153
 154 #else
 155 static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
 156 {
 157         return 0;
 158 }
 159
 160 static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
 161 {
 162 }
 163 #endif /* CONFIG_DEBUG_FS */
 164
 165 static void wait_till_not_busy(struct dw_spi *dws)
 166 {
 167         unsigned long end = jiffies + 1 + usecs_to_jiffies(5000);
 168
 169         while (time_before(jiffies, end)) {
 170                 if (!(dw_readw(dws, sr) & SR_BUSY))
 171                         return;
 172                 cpu_relax();
 173         }
 174         dev_err(&dws->master->dev,
 175                 "DW SPI: Status keeps busy for 5000us after a read/write!\n");
 176 }
 177
 178 static void flush(struct dw_spi *dws)
 179 {
 180         while (dw_readw(dws, sr) & SR_RF_NOT_EMPT) {
 181                 dw_readw(dws, dr);
 182                 cpu_relax();
 183         }
 184
 185         wait_till_not_busy(dws);
 186 }
 187
 188 static int null_writer(struct dw_spi *dws)
 189 {
 190         u8 n_bytes = dws->n_bytes;
 191
 192         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 193                 || (dws->tx == dws->tx_end))
 194                 return 0;
 195         dw_writew(dws, dr, 0);
 196         dws->tx += n_bytes;
 197
 198         wait_till_not_busy(dws);
 199         return 1;
 200 }
 201
 202 static int null_reader(struct dw_spi *dws)
 203 {
 204         u8 n_bytes = dws->n_bytes;
 205
 206         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 207                 && (dws->rx < dws->rx_end)) {
 208                 dw_readw(dws, dr);
 209                 dws->rx += n_bytes;
 210         }
 211         wait_till_not_busy(dws);
 212         return dws->rx == dws->rx_end;
 213 }
 214
 215 static int u8_writer(struct dw_spi *dws)
 216 {
 217         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 218                 || (dws->tx == dws->tx_end))
 219                 return 0;
 220
 221         dw_writew(dws, dr, *(u8 *)(dws->tx));
 222         ++dws->tx;
 223
 224         wait_till_not_busy(dws);
 225         return 1;
 226 }
 227
 228 static int u8_reader(struct dw_spi *dws)
 229 {
 230         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 231                 && (dws->rx < dws->rx_end)) {
 232                 *(u8 *)(dws->rx) = dw_readw(dws, dr);
 233                 ++dws->rx;
 234         }
 235
 236         wait_till_not_busy(dws);
 237         return dws->rx == dws->rx_end;
 238 }
 239
 240 static int u16_writer(struct dw_spi *dws)
 241 {
 242         if (!(dw_readw(dws, sr) & SR_TF_NOT_FULL)
 243                 || (dws->tx == dws->tx_end))
 244                 return 0;
 245
 246         dw_writew(dws, dr, *(u16 *)(dws->tx));
 247         dws->tx += 2;
 248
 249         wait_till_not_busy(dws);
 250         return 1;
 251 }
 252
 253 static int u16_reader(struct dw_spi *dws)
 254 {
 255         u16 temp;
 256
 257         while ((dw_readw(dws, sr) & SR_RF_NOT_EMPT)
 258                 && (dws->rx < dws->rx_end)) {
 259                 temp = dw_readw(dws, dr);
 260                 *(u16 *)(dws->rx) = temp;
 261                 dws->rx += 2;
 262         }
 263
 264         wait_till_not_busy(dws);
 265         return dws->rx == dws->rx_end;
 266 }
 267
 268 static void *next_transfer(struct dw_spi *dws)
 269 {
 270         struct spi_message *msg = dws->cur_msg;
 271         struct spi_transfer *trans = dws->cur_transfer;
 272
 273         /* Move to next transfer */
 274         if (trans->transfer_list.next != &msg->transfers) {
 275                 dws->cur_transfer =
 276                         list_entry(trans->transfer_list.next,
 277                                         struct spi_transfer,
 278                                         transfer_list);
 279                 return RUNNING_STATE;
 280         } else
 281                 return DONE_STATE;
 282 }
 283
 284 /*
 285  * Note: first step is the protocol driver prepares
 286  * a dma-capable memory, and this func just need translate
 287  * the virt addr to physical
 288  */
 289 static int map_dma_buffers(struct dw_spi *dws)
 290 {
 291         if (!dws->cur_msg->is_dma_mapped
 292                 || !dws->dma_inited
 293                 || !dws->cur_chip->enable_dma
 294                 || !dws->dma_ops)
 295                 return 0;
 296
 297         if (dws->cur_transfer->tx_dma)
 298                 dws->tx_dma = dws->cur_transfer->tx_dma;
 299
 300         if (dws->cur_transfer->rx_dma)
 301                 dws->rx_dma = dws->cur_transfer->rx_dma;
 302
 303         return 1;
 304 }
 305
 306 /* Caller already set message->status; dma and pio irqs are blocked */
 307 static void giveback(struct dw_spi *dws)
 308 {
 309         struct spi_transfer *last_transfer;
 310         unsigned long flags;
 311         struct spi_message *msg;
 312
 313         spin_lock_irqsave(&dws->lock, flags);
 314         msg = dws->cur_msg;
 315         dws->cur_msg = NULL;
 316         dws->cur_transfer = NULL;
 317         dws->prev_chip = dws->cur_chip;
 318         dws->cur_chip = NULL;
 319         dws->dma_mapped = 0;
 320         queue_work(dws->workqueue, &dws->pump_messages);
 321         spin_unlock_irqrestore(&dws->lock, flags);
 322
 323         last_transfer = list_entry(msg->transfers.prev,
 324                                         struct spi_transfer,
 325                                         transfer_list);
 326
 327         if (!last_transfer->cs_change && dws->cs_control)
 328                 dws->cs_control(MRST_SPI_DEASSERT);
 329
 330         msg->state = NULL;
 331         if (msg->complete)
 332                 msg->complete(msg->context);
 333 }
 334
 335 static void int_error_stop(struct dw_spi *dws, const char *msg)
 336 {
 337         /* Stop and reset hw */
 338         flush(dws);
 339         spi_enable_chip(dws, 0);
 340
 341         dev_err(&dws->master->dev, "%s\n", msg);
 342         dws->cur_msg->state = ERROR_STATE;
 343         tasklet_schedule(&dws->pump_transfers);
 344 }
 345
 346 void dw_spi_xfer_done(struct dw_spi *dws)
 347 {
 348         /* Update total byte transferred return count actual bytes read */
 349         dws->cur_msg->actual_length += dws->len;
 350
 351         /* Move to next transfer */
 352         dws->cur_msg->state = next_transfer(dws);
 353
 354         /* Handle end of message */
 355         if (dws->cur_msg->state == DONE_STATE) {
 356                 dws->cur_msg->status = 0;
 357                 giveback(dws);
 358         } else
 359                 tasklet_schedule(&dws->pump_transfers);
 360 }
 361 EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
 362
 363 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 364 {
 365         u16 irq_status, irq_mask = 0x3f;
 366         u32 int_level = dws->fifo_len / 2;
 367         u32 left;
 368
 369         irq_status = dw_readw(dws, isr) & irq_mask;
 370         /* Error handling */
 371         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 372                 dw_readw(dws, txoicr);
 373                 dw_readw(dws, rxoicr);
 374                 dw_readw(dws, rxuicr);
 375                 int_error_stop(dws, "interrupt_transfer: fifo overrun");
 376                 return IRQ_HANDLED;
 377         }
 378
 379         if (irq_status & SPI_INT_TXEI) {
 380                 spi_mask_intr(dws, SPI_INT_TXEI);
 381
 382                 left = (dws->tx_end - dws->tx) / dws->n_bytes;
 383                 left = (left > int_level) ? int_level : left;
 384
 385                 while (left--)
 386                         dws->write(dws);
 387                 dws->read(dws);
 388
 389                 /* Re-enable the IRQ if there is still data left to tx */
 390                 if (dws->tx_end > dws->tx)
 391                         spi_umask_intr(dws, SPI_INT_TXEI);
 392                 else
 393                         dw_spi_xfer_done(dws);
 394         }
 395
 396         return IRQ_HANDLED;
 397 }
 398
 399 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 400 {
 401         struct dw_spi *dws = dev_id;
 402         u16 irq_status, irq_mask = 0x3f;
 403
 404         irq_status = dw_readw(dws, isr) & irq_mask;
 405         if (!irq_status)
 406                 return IRQ_NONE;
 407
 408         if (!dws->cur_msg) {
 409                 spi_mask_intr(dws, SPI_INT_TXEI);
 410                 /* Never fail */
 411                 return IRQ_HANDLED;
 412         }
 413
 414         return dws->transfer_handler(dws);
 415 }
 416
 417 /* Must be called inside pump_transfers() */
 418 static void poll_transfer(struct dw_spi *dws)
 419 {
 420         while (dws->write(dws))
 421                 dws->read(dws);
 422         /*
 423          * There is a possibility that the last word of a transaction
 424          * will be lost if data is not ready. Re-read to solve this issue.
 425          */
 426         dws->read(dws);
 427
 428         dw_spi_xfer_done(dws);
 429 }
 430
 431 static void pump_transfers(unsigned long data)
 432 {
 433         struct dw_spi *dws = (struct dw_spi *)data;
 434         struct spi_message *message = NULL;
 435         struct spi_transfer *transfer = NULL;
 436         struct spi_transfer *previous = NULL;
 437         struct spi_device *spi = NULL;
 438         struct chip_data *chip = NULL;
 439         u8 bits = 0;
 440         u8 imask = 0;
 441         u8 cs_change = 0;
 442         u16 txint_level = 0;
 443         u16 clk_div = 0;
 444         u32 speed = 0;
 445         u32 cr0 = 0;
 446
 447         /* Get current state information */
 448         message = dws->cur_msg;
 449         transfer = dws->cur_transfer;
 450         chip = dws->cur_chip;
 451         spi = message->spi;
 452
 453         if (unlikely(!chip->clk_div))
 454                 chip->clk_div = dws->max_freq / chip->speed_hz;
 455
 456         if (message->state == ERROR_STATE) {
 457                 message->status = -EIO;
 458                 goto early_exit;
 459         }
 460
 461         /* Handle end of message */
 462         if (message->state == DONE_STATE) {
 463                 message->status = 0;
 464                 goto early_exit;
 465         }
 466
 467         /* Delay if requested at end of transfer*/
 468         if (message->state == RUNNING_STATE) {
 469                 previous = list_entry(transfer->transfer_list.prev,
 470                                         struct spi_transfer,
 471                                         transfer_list);
 472                 if (previous->delay_usecs)
 473                         udelay(previous->delay_usecs);
 474         }
 475
 476         dws->n_bytes = chip->n_bytes;
 477         dws->dma_width = chip->dma_width;
 478         dws->cs_control = chip->cs_control;
 479
 480         dws->rx_dma = transfer->rx_dma;
 481         dws->tx_dma = transfer->tx_dma;
 482         dws->tx = (void *)transfer->tx_buf;
 483         dws->tx_end = dws->tx + transfer->len;
 484         dws->rx = transfer->rx_buf;
 485         dws->rx_end = dws->rx + transfer->len;
 486         dws->write = dws->tx ? chip->write : null_writer;
 487         dws->read = dws->rx ? chip->read : null_reader;
 488         dws->cs_change = transfer->cs_change;
 489         dws->len = dws->cur_transfer->len;
 490         if (chip != dws->prev_chip)
 491                 cs_change = 1;
 492
 493         cr0 = chip->cr0;
 494
 495         /* Handle per transfer options for bpw and speed */
 496         if (transfer->speed_hz) {
 497                 speed = chip->speed_hz;
 498
 499                 if (transfer->speed_hz != speed) {
 500                         speed = transfer->speed_hz;
 501                         if (speed > dws->max_freq) {
 502                                 printk(KERN_ERR "MRST SPI0: unsupported"
 503                                         "freq: %dHz\n", speed);
 504                                 message->status = -EIO;
 505                                 goto early_exit;
 506                         }
 507
 508                         /* clk_div doesn't support odd number */
 509                         clk_div = dws->max_freq / speed;
 510                         clk_div = (clk_div + 1) & 0xfffe;
 511
 512                         chip->speed_hz = speed;
 513                         chip->clk_div = clk_div;
 514                 }
 515         }
 516         if (transfer->bits_per_word) {
 517                 bits = transfer->bits_per_word;
 518
 519                 switch (bits) {
 520                 case 8:
 521                         dws->n_bytes = 1;
 522                         dws->dma_width = 1;
 523                         dws->read = (dws->read != null_reader) ?
 524                                         u8_reader : null_reader;
 525                         dws->write = (dws->write != null_writer) ?
 526                                         u8_writer : null_writer;
 527                         break;
 528                 case 16:
 529                         dws->n_bytes = 2;
 530                         dws->dma_width = 2;
 531                         dws->read = (dws->read != null_reader) ?
 532                                         u16_reader : null_reader;
 533                         dws->write = (dws->write != null_writer) ?
 534                                         u16_writer : null_writer;
 535                         break;
 536                 default:
 537                         printk(KERN_ERR "MRST SPI0: unsupported bits:"
 538                                 "%db\n", bits);
 539                         message->status = -EIO;
 540                         goto early_exit;
 541                 }
 542
 543                 cr0 = (bits - 1)
 544                         | (chip->type << SPI_FRF_OFFSET)
 545                         | (spi->mode << SPI_MODE_OFFSET)
 546                         | (chip->tmode << SPI_TMOD_OFFSET);
 547         }
 548         message->state = RUNNING_STATE;
 549
 550         /*
 551          * Adjust transfer mode if necessary. Requires platform dependent
 552          * chipselect mechanism.
 553          */
 554         if (dws->cs_control) {
 555                 if (dws->rx && dws->tx)
 556                         chip->tmode = SPI_TMOD_TR;
 557                 else if (dws->rx)
 558                         chip->tmode = SPI_TMOD_RO;
 559                 else
 560                         chip->tmode = SPI_TMOD_TO;
 561
 562                 cr0 &= ~SPI_TMOD_MASK;
 563                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 564         }
 565
 566         /* Check if current transfer is a DMA transaction */
 567         dws->dma_mapped = map_dma_buffers(dws);
 568
 569         /*
 570          * Interrupt mode
 571          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 572          */
 573         if (!dws->dma_mapped && !chip->poll_mode) {
 574                 int templen = dws->len / dws->n_bytes;
 575                 txint_level = dws->fifo_len / 2;
 576                 txint_level = (templen > txint_level) ? txint_level : templen;
 577
 578                 imask |= SPI_INT_TXEI;
 579                 dws->transfer_handler = interrupt_transfer;
 580         }
 581
 582         /*
 583          * Reprogram registers only if
 584          *      1. chip select changes
 585          *      2. clk_div is changed
 586          *      3. control value changes
 587          */
 588         if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
 589                 spi_enable_chip(dws, 0);
 590
 591                 if (dw_readw(dws, ctrl0) != cr0)
 592                         dw_writew(dws, ctrl0, cr0);
 593
 594                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
 595                 spi_chip_sel(dws, spi->chip_select);
 596
 597                 /* Set the interrupt mask, for poll mode just disable all int */
 598                 spi_mask_intr(dws, 0xff);
 599                 if (imask)
 600                         spi_umask_intr(dws, imask);
 601                 if (txint_level)
 602                         dw_writew(dws, txfltr, txint_level);
 603
 604                 spi_enable_chip(dws, 1);
 605                 if (cs_change)
 606                         dws->prev_chip = chip;
 607         }
 608
 609         if (dws->dma_mapped)
 610                 dws->dma_ops->dma_transfer(dws, cs_change);
 611
 612         if (chip->poll_mode)
 613                 poll_transfer(dws);
 614
 615         return;
 616
 617 early_exit:
 618         giveback(dws);
 619         return;
 620 }
 621
 622 static void pump_messages(struct work_struct *work)
 623 {
 624         struct dw_spi *dws =
 625                 container_of(work, struct dw_spi, pump_messages);
 626         unsigned long flags;
 627
 628         /* Lock queue and check for queue work */
 629         spin_lock_irqsave(&dws->lock, flags);
 630         if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
 631                 dws->busy = 0;
 632                 spin_unlock_irqrestore(&dws->lock, flags);
 633                 return;
 634         }
 635
 636         /* Make sure we are not already running a message */
 637         if (dws->cur_msg) {
 638                 spin_unlock_irqrestore(&dws->lock, flags);
 639                 return;
 640         }
 641
 642         /* Extract head of queue */
 643         dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
 644         list_del_init(&dws->cur_msg->queue);
 645
 646         /* Initial message state*/
 647         dws->cur_msg->state = START_STATE;
 648         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
 649                                                 struct spi_transfer,
 650                                                 transfer_list);
 651         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
 652
 653         /* Mark as busy and launch transfers */
 654         tasklet_schedule(&dws->pump_transfers);
 655
 656         dws->busy = 1;
 657         spin_unlock_irqrestore(&dws->lock, flags);
 658 }
 659
 660 /* spi_device use this to queue in their spi_msg */
 661 static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 662 {
 663         struct dw_spi *dws = spi_master_get_devdata(spi->master);
 664         unsigned long flags;
 665
 666         spin_lock_irqsave(&dws->lock, flags);
 667
 668         if (dws->run == QUEUE_STOPPED) {
 669                 spin_unlock_irqrestore(&dws->lock, flags);
 670                 return -ESHUTDOWN;
 671         }
 672
 673         msg->actual_length = 0;
 674         msg->status = -EINPROGRESS;
 675         msg->state = START_STATE;
 676
 677         list_add_tail(&msg->queue, &dws->queue);
 678
 679         if (dws->run == QUEUE_RUNNING && !dws->busy) {
 680
 681                 if (dws->cur_transfer || dws->cur_msg)
 682                         queue_work(dws->workqueue,
 683                                         &dws->pump_messages);
 684                 else {
 685                         /* If no other data transaction in air, just go */
 686                         spin_unlock_irqrestore(&dws->lock, flags);
 687                         pump_messages(&dws->pump_messages);
 688                         return 0;
 689                 }
 690         }
 691
 692         spin_unlock_irqrestore(&dws->lock, flags);
 693         return 0;
 694 }
 695
 696 /* This may be called twice for each spi dev */
 697 static int dw_spi_setup(struct spi_device *spi)
 698 {
 699         struct dw_spi_chip *chip_info = NULL;
 700         struct chip_data *chip;
 701
 702         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 703                 return -EINVAL;
 704
 705         /* Only alloc on first setup */
 706         chip = spi_get_ctldata(spi);
 707         if (!chip) {
 708                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 709                 if (!chip)
 710                         return -ENOMEM;
 711         }
 712
 713         /*
 714          * Protocol drivers may change the chip settings, so...
 715          * if chip_info exists, use it
 716          */
 717         chip_info = spi->controller_data;
 718
 719         /* chip_info doesn't always exist */
 720         if (chip_info) {
 721                 if (chip_info->cs_control)
 722                         chip->cs_control = chip_info->cs_control;
 723
 724                 chip->poll_mode = chip_info->poll_mode;
 725                 chip->type = chip_info->type;
 726
 727                 chip->rx_threshold = 0;
 728                 chip->tx_threshold = 0;
 729
 730                 chip->enable_dma = chip_info->enable_dma;
 731         }
 732
 733         if (spi->bits_per_word <= 8) {
 734                 chip->n_bytes = 1;
 735                 chip->dma_width = 1;
 736                 chip->read = u8_reader;
 737                 chip->write = u8_writer;
 738         } else if (spi->bits_per_word <= 16) {
 739                 chip->n_bytes = 2;
 740                 chip->dma_width = 2;
 741                 chip->read = u16_reader;
 742                 chip->write = u16_writer;
 743         } else {
 744                 /* Never take >16b case for MRST SPIC */
 745                 dev_err(&spi->dev, "invalid wordsize\n");
 746                 return -EINVAL;
 747         }
 748         chip->bits_per_word = spi->bits_per_word;
 749
 750         if (!spi->max_speed_hz) {
 751                 dev_err(&spi->dev, "No max speed HZ parameter\n");
 752                 return -EINVAL;
 753         }
 754         chip->speed_hz = spi->max_speed_hz;
 755
 756         chip->tmode = 0; /* Tx & Rx */
 757         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 758         chip->cr0 = (chip->bits_per_word - 1)
 759                         | (chip->type << SPI_FRF_OFFSET)
 760                         | (spi->mode  << SPI_MODE_OFFSET)
 761                         | (chip->tmode << SPI_TMOD_OFFSET);
 762
 763         spi_set_ctldata(spi, chip);
 764         return 0;
 765 }
 766
 767 static void dw_spi_cleanup(struct spi_device *spi)
 768 {
 769         struct chip_data *chip = spi_get_ctldata(spi);
 770         kfree(chip);
 771 }
 772
 773 static int __devinit init_queue(struct dw_spi *dws)
 774 {
 775         INIT_LIST_HEAD(&dws->queue);
 776         spin_lock_init(&dws->lock);
 777
 778         dws->run = QUEUE_STOPPED;
 779         dws->busy = 0;
 780
 781         tasklet_init(&dws->pump_transfers,
 782                         pump_transfers, (unsigned long)dws);
 783
 784         INIT_WORK(&dws->pump_messages, pump_messages);
 785         dws->workqueue = create_singlethread_workqueue(
 786                                         dev_name(dws->master->dev.parent));
 787         if (dws->workqueue == NULL)
 788                 return -EBUSY;
 789
 790         return 0;
 791 }
 792
 793 static int start_queue(struct dw_spi *dws)
 794 {
 795         unsigned long flags;
 796
 797         spin_lock_irqsave(&dws->lock, flags);
 798
 799         if (dws->run == QUEUE_RUNNING || dws->busy) {
 800                 spin_unlock_irqrestore(&dws->lock, flags);
 801                 return -EBUSY;
 802         }
 803
 804         dws->run = QUEUE_RUNNING;
 805         dws->cur_msg = NULL;
 806         dws->cur_transfer = NULL;
 807         dws->cur_chip = NULL;
 808         dws->prev_chip = NULL;
 809         spin_unlock_irqrestore(&dws->lock, flags);
 810
 811         queue_work(dws->workqueue, &dws->pump_messages);
 812
 813         return 0;
 814 }
 815
 816 static int stop_queue(struct dw_spi *dws)
 817 {
 818         unsigned long flags;
 819         unsigned limit = 50;
 820         int status = 0;
 821
 822         spin_lock_irqsave(&dws->lock, flags);
 823         dws->run = QUEUE_STOPPED;
 824         while ((!list_empty(&dws->queue) || dws->busy) && limit--) {
 825                 spin_unlock_irqrestore(&dws->lock, flags);
 826                 msleep(10);
 827                 spin_lock_irqsave(&dws->lock, flags);
 828         }
 829
 830         if (!list_empty(&dws->queue) || dws->busy)
 831                 status = -EBUSY;
 832         spin_unlock_irqrestore(&dws->lock, flags);
 833
 834         return status;
 835 }
 836
 837 static int destroy_queue(struct dw_spi *dws)
 838 {
 839         int status;
 840
 841         status = stop_queue(dws);
 842         if (status != 0)
 843                 return status;
 844         destroy_workqueue(dws->workqueue);
 845         return 0;
 846 }
 847
 848 /* Restart the controller, disable all interrupts, clean rx fifo */
 849 static void spi_hw_init(struct dw_spi *dws)
 850 {
 851         spi_enable_chip(dws, 0);
 852         spi_mask_intr(dws, 0xff);
 853         spi_enable_chip(dws, 1);
 854         flush(dws);
 855
 856         /*
 857          * Try to detect the FIFO depth if not set by interface driver,
 858          * the depth could be from 2 to 256 from HW spec
 859          */
 860         if (!dws->fifo_len) {
 861                 u32 fifo;
 862                 for (fifo = 2; fifo <= 257; fifo++) {
 863                         dw_writew(dws, txfltr, fifo);
 864                         if (fifo != dw_readw(dws, txfltr))
 865                                 break;
 866                 }
 867
 868                 dws->fifo_len = (fifo == 257) ? 0 : fifo;
 869                 dw_writew(dws, txfltr, 0);
 870         }
 871 }
 872
 873 int __devinit dw_spi_add_host(struct dw_spi *dws)
 874 {
 875         struct spi_master *master;
 876         int ret;
 877
 878         BUG_ON(dws == NULL);
 879
 880         master = spi_alloc_master(dws->parent_dev, 0);
 881         if (!master) {
 882                 ret = -ENOMEM;
 883                 goto exit;
 884         }
 885
 886         dws->master = master;
 887         dws->type = SSI_MOTO_SPI;
 888         dws->prev_chip = NULL;
 889         dws->dma_inited = 0;
 890         dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
 891
 892         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
 893                         "dw_spi", dws);
 894         if (ret < 0) {
 895                 dev_err(&master->dev, "can not get IRQ\n");
 896                 goto err_free_master;
 897         }
 898
 899         master->mode_bits = SPI_CPOL | SPI_CPHA;
 900         master->bus_num = dws->bus_num;
 901         master->num_chipselect = dws->num_cs;
 902         master->cleanup = dw_spi_cleanup;
 903         master->setup = dw_spi_setup;
 904         master->transfer = dw_spi_transfer;
 905
 906         /* Basic HW init */
 907         spi_hw_init(dws);
 908
 909         if (dws->dma_ops && dws->dma_ops->dma_init) {
 910                 ret = dws->dma_ops->dma_init(dws);
 911                 if (ret) {
 912                         dev_warn(&master->dev, "DMA init failed\n");
 913                         dws->dma_inited = 0;
 914                 }
 915         }
 916
 917         /* Initial and start queue */
 918         ret = init_queue(dws);
 919         if (ret) {
 920                 dev_err(&master->dev, "problem initializing queue\n");
 921                 goto err_diable_hw;
 922         }
 923         ret = start_queue(dws);
 924         if (ret) {
 925                 dev_err(&master->dev, "problem starting queue\n");
 926                 goto err_diable_hw;
 927         }
 928
 929         spi_master_set_devdata(master, dws);
 930         ret = spi_register_master(master);
 931         if (ret) {
 932                 dev_err(&master->dev, "problem registering spi master\n");
 933                 goto err_queue_alloc;
 934         }
 935
 936         mrst_spi_debugfs_init(dws);
 937         return 0;
 938
 939 err_queue_alloc:
 940         destroy_queue(dws);
 941         if (dws->dma_ops && dws->dma_ops->dma_exit)
 942                 dws->dma_ops->dma_exit(dws);
 943 err_diable_hw:
 944         spi_enable_chip(dws, 0);
 945         free_irq(dws->irq, dws);
 946 err_free_master:
 947         spi_master_put(master);
 948 exit:
 949         return ret;
 950 }
 951 EXPORT_SYMBOL_GPL(dw_spi_add_host);
 952
 953 void __devexit dw_spi_remove_host(struct dw_spi *dws)
 954 {
 955         int status = 0;
 956
 957         if (!dws)
 958                 return;
 959         mrst_spi_debugfs_remove(dws);
 960
 961         /* Remove the queue */
 962         status = destroy_queue(dws);
 963         if (status != 0)
 964                 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
 965                         "complete, message memory not freed\n");
 966
 967         if (dws->dma_ops && dws->dma_ops->dma_exit)
 968                 dws->dma_ops->dma_exit(dws);
 969         spi_enable_chip(dws, 0);
 970         /* Disable clk */
 971         spi_set_clk(dws, 0);
 972         free_irq(dws->irq, dws);
 973
 974         /* Disconnect from the SPI framework */
 975         spi_unregister_master(dws->master);
 976 }
 977 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
 978
 979 int dw_spi_suspend_host(struct dw_spi *dws)
 980 {
 981         int ret = 0;
 982
 983         ret = stop_queue(dws);
 984         if (ret)
 985                 return ret;
 986         spi_enable_chip(dws, 0);
 987         spi_set_clk(dws, 0);
 988         return ret;
 989 }
 990 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
 991
 992 int dw_spi_resume_host(struct dw_spi *dws)
 993 {
 994         int ret;
 995
 996         spi_hw_init(dws);
 997         ret = start_queue(dws);
 998         if (ret)
 999                 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
1000         return ret;
1001 }
1002 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
1003
1004 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
1005 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
1006 MODULE_LICENSE("GPL v2");