pandora: update defconfig
[pandora-kernel.git] / drivers / sh / clk-cpg.c
1 #include <linux/clk.h>
2 #include <linux/compiler.h>
3 #include <linux/slab.h>
4 #include <linux/io.h>
5 #include <linux/sh_clk.h>
6
7 static int sh_clk_mstp32_enable(struct clk *clk)
8 {
9         __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
10                      clk->enable_reg);
11         return 0;
12 }
13
14 static void sh_clk_mstp32_disable(struct clk *clk)
15 {
16         __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
17                      clk->enable_reg);
18 }
19
20 static struct clk_ops sh_clk_mstp32_clk_ops = {
21         .enable         = sh_clk_mstp32_enable,
22         .disable        = sh_clk_mstp32_disable,
23         .recalc         = followparent_recalc,
24 };
25
26 int __init sh_clk_mstp32_register(struct clk *clks, int nr)
27 {
28         struct clk *clkp;
29         int ret = 0;
30         int k;
31
32         for (k = 0; !ret && (k < nr); k++) {
33                 clkp = clks + k;
34                 clkp->ops = &sh_clk_mstp32_clk_ops;
35                 ret |= clk_register(clkp);
36         }
37
38         return ret;
39 }
40
41 static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
42 {
43         return clk_rate_table_round(clk, clk->freq_table, rate);
44 }
45
46 static int sh_clk_div6_divisors[64] = {
47         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
48         17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
49         33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
50         49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
51 };
52
53 static struct clk_div_mult_table sh_clk_div6_table = {
54         .divisors = sh_clk_div6_divisors,
55         .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
56 };
57
58 static unsigned long sh_clk_div6_recalc(struct clk *clk)
59 {
60         struct clk_div_mult_table *table = &sh_clk_div6_table;
61         unsigned int idx;
62
63         clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
64                              table, NULL);
65
66         idx = __raw_readl(clk->enable_reg) & 0x003f;
67
68         return clk->freq_table[idx].frequency;
69 }
70
71 static int sh_clk_div6_set_rate(struct clk *clk,
72                                 unsigned long rate, int algo_id)
73 {
74         unsigned long value;
75         int idx;
76
77         idx = clk_rate_table_find(clk, clk->freq_table, rate);
78         if (idx < 0)
79                 return idx;
80
81         value = __raw_readl(clk->enable_reg);
82         value &= ~0x3f;
83         value |= idx;
84         __raw_writel(value, clk->enable_reg);
85         return 0;
86 }
87
88 static int sh_clk_div6_enable(struct clk *clk)
89 {
90         unsigned long value;
91         int ret;
92
93         ret = sh_clk_div6_set_rate(clk, clk->rate, 0);
94         if (ret == 0) {
95                 value = __raw_readl(clk->enable_reg);
96                 value &= ~0x100; /* clear stop bit to enable clock */
97                 __raw_writel(value, clk->enable_reg);
98         }
99         return ret;
100 }
101
102 static void sh_clk_div6_disable(struct clk *clk)
103 {
104         unsigned long value;
105
106         value = __raw_readl(clk->enable_reg);
107         value |= 0x100; /* stop clock */
108         value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
109         __raw_writel(value, clk->enable_reg);
110 }
111
112 static struct clk_ops sh_clk_div6_clk_ops = {
113         .recalc         = sh_clk_div6_recalc,
114         .round_rate     = sh_clk_div_round_rate,
115         .set_rate       = sh_clk_div6_set_rate,
116         .enable         = sh_clk_div6_enable,
117         .disable        = sh_clk_div6_disable,
118 };
119
120 int __init sh_clk_div6_register(struct clk *clks, int nr)
121 {
122         struct clk *clkp;
123         void *freq_table;
124         int nr_divs = sh_clk_div6_table.nr_divisors;
125         int freq_table_size = sizeof(struct cpufreq_frequency_table);
126         int ret = 0;
127         int k;
128
129         freq_table_size *= (nr_divs + 1);
130         freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
131         if (!freq_table) {
132                 pr_err("sh_clk_div6_register: unable to alloc memory\n");
133                 return -ENOMEM;
134         }
135
136         for (k = 0; !ret && (k < nr); k++) {
137                 clkp = clks + k;
138
139                 clkp->ops = &sh_clk_div6_clk_ops;
140                 clkp->id = -1;
141                 clkp->freq_table = freq_table + (k * freq_table_size);
142                 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
143
144                 ret = clk_register(clkp);
145         }
146
147         return ret;
148 }
149
150 static unsigned long sh_clk_div4_recalc(struct clk *clk)
151 {
152         struct clk_div4_table *d4t = clk->priv;
153         struct clk_div_mult_table *table = d4t->div_mult_table;
154         unsigned int idx;
155
156         clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
157                              table, &clk->arch_flags);
158
159         idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f;
160
161         return clk->freq_table[idx].frequency;
162 }
163
164 static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
165 {
166         struct clk_div4_table *d4t = clk->priv;
167         struct clk_div_mult_table *table = d4t->div_mult_table;
168         u32 value;
169         int ret;
170
171         /* we really need a better way to determine parent index, but for
172          * now assume internal parent comes with CLK_ENABLE_ON_INIT set,
173          * no CLK_ENABLE_ON_INIT means external clock...
174          */
175
176         if (parent->flags & CLK_ENABLE_ON_INIT)
177                 value = __raw_readl(clk->enable_reg) & ~(1 << 7);
178         else
179                 value = __raw_readl(clk->enable_reg) | (1 << 7);
180
181         ret = clk_reparent(clk, parent);
182         if (ret < 0)
183                 return ret;
184
185         __raw_writel(value, clk->enable_reg);
186
187         /* Rebiuld the frequency table */
188         clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
189                              table, &clk->arch_flags);
190
191         return 0;
192 }
193
194 static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id)
195 {
196         struct clk_div4_table *d4t = clk->priv;
197         unsigned long value;
198         int idx = clk_rate_table_find(clk, clk->freq_table, rate);
199         if (idx < 0)
200                 return idx;
201
202         value = __raw_readl(clk->enable_reg);
203         value &= ~(0xf << clk->enable_bit);
204         value |= (idx << clk->enable_bit);
205         __raw_writel(value, clk->enable_reg);
206
207         if (d4t->kick)
208                 d4t->kick(clk);
209
210         return 0;
211 }
212
213 static int sh_clk_div4_enable(struct clk *clk)
214 {
215         __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg);
216         return 0;
217 }
218
219 static void sh_clk_div4_disable(struct clk *clk)
220 {
221         __raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg);
222 }
223
224 static struct clk_ops sh_clk_div4_clk_ops = {
225         .recalc         = sh_clk_div4_recalc,
226         .set_rate       = sh_clk_div4_set_rate,
227         .round_rate     = sh_clk_div_round_rate,
228 };
229
230 static struct clk_ops sh_clk_div4_enable_clk_ops = {
231         .recalc         = sh_clk_div4_recalc,
232         .set_rate       = sh_clk_div4_set_rate,
233         .round_rate     = sh_clk_div_round_rate,
234         .enable         = sh_clk_div4_enable,
235         .disable        = sh_clk_div4_disable,
236 };
237
238 static struct clk_ops sh_clk_div4_reparent_clk_ops = {
239         .recalc         = sh_clk_div4_recalc,
240         .set_rate       = sh_clk_div4_set_rate,
241         .round_rate     = sh_clk_div_round_rate,
242         .enable         = sh_clk_div4_enable,
243         .disable        = sh_clk_div4_disable,
244         .set_parent     = sh_clk_div4_set_parent,
245 };
246
247 static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
248                         struct clk_div4_table *table, struct clk_ops *ops)
249 {
250         struct clk *clkp;
251         void *freq_table;
252         int nr_divs = table->div_mult_table->nr_divisors;
253         int freq_table_size = sizeof(struct cpufreq_frequency_table);
254         int ret = 0;
255         int k;
256
257         freq_table_size *= (nr_divs + 1);
258         freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
259         if (!freq_table) {
260                 pr_err("sh_clk_div4_register: unable to alloc memory\n");
261                 return -ENOMEM;
262         }
263
264         for (k = 0; !ret && (k < nr); k++) {
265                 clkp = clks + k;
266
267                 clkp->ops = ops;
268                 clkp->id = -1;
269                 clkp->priv = table;
270
271                 clkp->freq_table = freq_table + (k * freq_table_size);
272                 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
273
274                 ret = clk_register(clkp);
275         }
276
277         return ret;
278 }
279
280 int __init sh_clk_div4_register(struct clk *clks, int nr,
281                                 struct clk_div4_table *table)
282 {
283         return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops);
284 }
285
286 int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
287                                 struct clk_div4_table *table)
288 {
289         return sh_clk_div4_register_ops(clks, nr, table,
290                                         &sh_clk_div4_enable_clk_ops);
291 }
292
293 int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
294                                 struct clk_div4_table *table)
295 {
296         return sh_clk_div4_register_ops(clks, nr, table,
297                                         &sh_clk_div4_reparent_clk_ops);
298 }