drivers/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #include <linux/serial_reg.h>
  18 #include <linux/pci.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24
  25 #include <linux/dmaengine.h>
  26 #include <linux/pch_dma.h>
  27
  28 enum {
  29         PCH_UART_HANDLED_RX_INT_SHIFT,
  30         PCH_UART_HANDLED_TX_INT_SHIFT,
  31         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  32         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  33         PCH_UART_HANDLED_MS_INT_SHIFT,
  34 };
  35
  36 enum {
  37         PCH_UART_8LINE,
  38         PCH_UART_2LINE,
  39 };
  40
  41 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  42
  43 #define PCH_UART_NR_GE_256FIFO          1
  44 #define PCH_UART_NR_GE_64FIFO           3
  45 #define PCH_UART_NR_GE  (PCH_UART_NR_GE_256FIFO+PCH_UART_NR_GE_64FIFO)
  46 #define PCH_UART_NR     PCH_UART_NR_GE
  47
  48 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  49 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  50 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  51                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  52 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  53                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  54 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  55
  56 #define PCH_UART_RBR            0x00
  57 #define PCH_UART_THR            0x00
  58
  59 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  60                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  61 #define PCH_UART_IER_ERBFI      0x00000001
  62 #define PCH_UART_IER_ETBEI      0x00000002
  63 #define PCH_UART_IER_ELSI       0x00000004
  64 #define PCH_UART_IER_EDSSI      0x00000008
  65
  66 #define PCH_UART_IIR_IP                 0x00000001
  67 #define PCH_UART_IIR_IID                0x00000006
  68 #define PCH_UART_IIR_MSI                0x00000000
  69 #define PCH_UART_IIR_TRI                0x00000002
  70 #define PCH_UART_IIR_RRI                0x00000004
  71 #define PCH_UART_IIR_REI                0x00000006
  72 #define PCH_UART_IIR_TOI                0x00000008
  73 #define PCH_UART_IIR_FIFO256            0x00000020
  74 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  75 #define PCH_UART_IIR_FE                 0x000000C0
  76
  77 #define PCH_UART_FCR_FIFOE              0x00000001
  78 #define PCH_UART_FCR_RFR                0x00000002
  79 #define PCH_UART_FCR_TFR                0x00000004
  80 #define PCH_UART_FCR_DMS                0x00000008
  81 #define PCH_UART_FCR_FIFO256            0x00000020
  82 #define PCH_UART_FCR_RFTL               0x000000C0
  83
  84 #define PCH_UART_FCR_RFTL1              0x00000000
  85 #define PCH_UART_FCR_RFTL64             0x00000040
  86 #define PCH_UART_FCR_RFTL128            0x00000080
  87 #define PCH_UART_FCR_RFTL224            0x000000C0
  88 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  89 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
  90 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
  91 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
  92 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
  93 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
  94 #define PCH_UART_FCR_RFTL_SHIFT         6
  95
  96 #define PCH_UART_LCR_WLS        0x00000003
  97 #define PCH_UART_LCR_STB        0x00000004
  98 #define PCH_UART_LCR_PEN        0x00000008
  99 #define PCH_UART_LCR_EPS        0x00000010
 100 #define PCH_UART_LCR_SP         0x00000020
 101 #define PCH_UART_LCR_SB         0x00000040
 102 #define PCH_UART_LCR_DLAB       0x00000080
 103 #define PCH_UART_LCR_NP         0x00000000
 104 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 105 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 106 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 107 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 108                                 PCH_UART_LCR_SP)
 109
 110 #define PCH_UART_LCR_5BIT       0x00000000
 111 #define PCH_UART_LCR_6BIT       0x00000001
 112 #define PCH_UART_LCR_7BIT       0x00000002
 113 #define PCH_UART_LCR_8BIT       0x00000003
 114
 115 #define PCH_UART_MCR_DTR        0x00000001
 116 #define PCH_UART_MCR_RTS        0x00000002
 117 #define PCH_UART_MCR_OUT        0x0000000C
 118 #define PCH_UART_MCR_LOOP       0x00000010
 119 #define PCH_UART_MCR_AFE        0x00000020
 120
 121 #define PCH_UART_LSR_DR         0x00000001
 122 #define PCH_UART_LSR_ERR        (1<<7)
 123
 124 #define PCH_UART_MSR_DCTS       0x00000001
 125 #define PCH_UART_MSR_DDSR       0x00000002
 126 #define PCH_UART_MSR_TERI       0x00000004
 127 #define PCH_UART_MSR_DDCD       0x00000008
 128 #define PCH_UART_MSR_CTS        0x00000010
 129 #define PCH_UART_MSR_DSR        0x00000020
 130 #define PCH_UART_MSR_RI         0x00000040
 131 #define PCH_UART_MSR_DCD        0x00000080
 132 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 133                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 134
 135 #define PCH_UART_DLL            0x00
 136 #define PCH_UART_DLM            0x01
 137
 138 #define DIV_ROUND(a, b) (((a) + ((b)/2)) / (b))
 139
 140 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 141 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 142 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 143 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 144 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 145
 146 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 147 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 148 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 149 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 150 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 151 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 152 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 153 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 154 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 155 #define PCH_UART_HAL_STB1               0
 156 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 157
 158 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 159 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 160 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 161                                         PCH_UART_HAL_CLR_RX_FIFO)
 162
 163 #define PCH_UART_HAL_DMA_MODE0          0
 164 #define PCH_UART_HAL_FIFO_DIS           0
 165 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 166 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 167                                         PCH_UART_FCR_FIFO256)
 168 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 169 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 170 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 171 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 172 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 173 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 174 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 175 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 176 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 177 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 178 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 179 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 180 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 181 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 182
 183 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 184 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 185 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 186 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 187 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 188
 189 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 190 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 191 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 192 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 193 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 194
 195 struct pch_uart_buffer {
 196         unsigned char *buf;
 197         int size;
 198 };
 199
 200 struct eg20t_port {
 201         struct uart_port port;
 202         int port_type;
 203         void __iomem *membase;
 204         resource_size_t mapbase;
 205         unsigned int iobase;
 206         struct pci_dev *pdev;
 207         int fifo_size;
 208         int base_baud;
 209         int start_tx;
 210         int start_rx;
 211         int tx_empty;
 212         int int_dis_flag;
 213         int trigger;
 214         int trigger_level;
 215         struct pch_uart_buffer rxbuf;
 216         unsigned int dmsr;
 217         unsigned int fcr;
 218         unsigned int use_dma;
 219         unsigned int use_dma_flag;
 220         struct dma_async_tx_descriptor  *desc_tx;
 221         struct dma_async_tx_descriptor  *desc_rx;
 222         struct pch_dma_slave            param_tx;
 223         struct pch_dma_slave            param_rx;
 224         struct dma_chan                 *chan_tx;
 225         struct dma_chan                 *chan_rx;
 226         struct scatterlist              sg_tx;
 227         struct scatterlist              sg_rx;
 228         int                             tx_dma_use;
 229         void                            *rx_buf_virt;
 230         dma_addr_t                      rx_buf_dma;
 231 };
 232
 233 static unsigned int default_baud = 9600;
 234 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 235 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 236 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 237 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 238
 239 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
 240                                  int base_baud)
 241 {
 242         struct eg20t_port *priv = pci_get_drvdata(pdev);
 243
 244         priv->trigger_level = 1;
 245         priv->fcr = 0;
 246 }
 247
 248 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
 249 {
 250         unsigned int msr = ioread8(base + UART_MSR);
 251         priv->dmsr |= msr & PCH_UART_MSR_DELTA;
 252
 253         return msr;
 254 }
 255
 256 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 257                                           unsigned int flag)
 258 {
 259         u8 ier = ioread8(priv->membase + UART_IER);
 260         ier |= flag & PCH_UART_IER_MASK;
 261         iowrite8(ier, priv->membase + UART_IER);
 262 }
 263
 264 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 265                                            unsigned int flag)
 266 {
 267         u8 ier = ioread8(priv->membase + UART_IER);
 268         ier &= ~(flag & PCH_UART_IER_MASK);
 269         iowrite8(ier, priv->membase + UART_IER);
 270 }
 271
 272 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
 273                                  unsigned int parity, unsigned int bits,
 274                                  unsigned int stb)
 275 {
 276         unsigned int dll, dlm, lcr;
 277         int div;
 278
 279         div = DIV_ROUND(priv->base_baud / 16, baud);
 280         if (div < 0 || USHRT_MAX <= div) {
 281                 pr_err("Invalid Baud(div=0x%x)\n", div);
 282                 return -EINVAL;
 283         }
 284
 285         dll = (unsigned int)div & 0x00FFU;
 286         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 287
 288         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 289                 pr_err("Invalid parity(0x%x)\n", parity);
 290                 return -EINVAL;
 291         }
 292
 293         if (bits & ~PCH_UART_LCR_WLS) {
 294                 pr_err("Invalid bits(0x%x)\n", bits);
 295                 return -EINVAL;
 296         }
 297
 298         if (stb & ~PCH_UART_LCR_STB) {
 299                 pr_err("Invalid STB(0x%x)\n", stb);
 300                 return -EINVAL;
 301         }
 302
 303         lcr = parity;
 304         lcr |= bits;
 305         lcr |= stb;
 306
 307         pr_debug("%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
 308                  __func__, baud, div, lcr, jiffies);
 309         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 310         iowrite8(dll, priv->membase + PCH_UART_DLL);
 311         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 312         iowrite8(lcr, priv->membase + UART_LCR);
 313
 314         return 0;
 315 }
 316
 317 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 318                                     unsigned int flag)
 319 {
 320         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 321                 pr_err("%s:Invalid flag(0x%x)\n", __func__, flag);
 322                 return -EINVAL;
 323         }
 324
 325         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 326         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 327                  priv->membase + UART_FCR);
 328         iowrite8(priv->fcr, priv->membase + UART_FCR);
 329
 330         return 0;
 331 }
 332
 333 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 334                                  unsigned int dmamode,
 335                                  unsigned int fifo_size, unsigned int trigger)
 336 {
 337         u8 fcr;
 338
 339         if (dmamode & ~PCH_UART_FCR_DMS) {
 340                 pr_err("%s:Invalid DMA Mode(0x%x)\n", __func__, dmamode);
 341                 return -EINVAL;
 342         }
 343
 344         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 345                 pr_err("%s:Invalid FIFO SIZE(0x%x)\n", __func__, fifo_size);
 346                 return -EINVAL;
 347         }
 348
 349         if (trigger & ~PCH_UART_FCR_RFTL) {
 350                 pr_err("%s:Invalid TRIGGER(0x%x)\n", __func__, trigger);
 351                 return -EINVAL;
 352         }
 353
 354         switch (priv->fifo_size) {
 355         case 256:
 356                 priv->trigger_level =
 357                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 358                 break;
 359         case 64:
 360                 priv->trigger_level =
 361                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 362                 break;
 363         case 16:
 364                 priv->trigger_level =
 365                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 366                 break;
 367         default:
 368                 priv->trigger_level =
 369                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 370                 break;
 371         }
 372         fcr =
 373             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 374         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 375         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 376                  priv->membase + UART_FCR);
 377         iowrite8(fcr, priv->membase + UART_FCR);
 378         priv->fcr = fcr;
 379
 380         return 0;
 381 }
 382
 383 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 384 {
 385         priv->dmsr = 0;
 386         return get_msr(priv, priv->membase);
 387 }
 388
 389 static int pch_uart_hal_write(struct eg20t_port *priv,
 390                               const unsigned char *buf, int tx_size)
 391 {
 392         int i;
 393         unsigned int thr;
 394
 395         for (i = 0; i < tx_size;) {
 396                 thr = buf[i++];
 397                 iowrite8(thr, priv->membase + PCH_UART_THR);
 398         }
 399         return i;
 400 }
 401
 402 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 403                              int rx_size)
 404 {
 405         int i;
 406         u8 rbr, lsr;
 407
 408         lsr = ioread8(priv->membase + UART_LSR);
 409         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 410              i < rx_size && lsr & UART_LSR_DR;
 411              lsr = ioread8(priv->membase + UART_LSR)) {
 412                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 413                 buf[i++] = rbr;
 414         }
 415         return i;
 416 }
 417
 418 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
 419 {
 420         unsigned int iir;
 421         int ret;
 422
 423         iir = ioread8(priv->membase + UART_IIR);
 424         ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
 425         return ret;
 426 }
 427
 428 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 429 {
 430         return ioread8(priv->membase + UART_LSR);
 431 }
 432
 433 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 434 {
 435         unsigned int lcr;
 436
 437         lcr = ioread8(priv->membase + UART_LCR);
 438         if (on)
 439                 lcr |= PCH_UART_LCR_SB;
 440         else
 441                 lcr &= ~PCH_UART_LCR_SB;
 442
 443         iowrite8(lcr, priv->membase + UART_LCR);
 444 }
 445
 446 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 447                    int size)
 448 {
 449         struct uart_port *port;
 450         struct tty_struct *tty;
 451
 452         port = &priv->port;
 453         tty = tty_port_tty_get(&port->state->port);
 454         if (!tty) {
 455                 pr_debug("%s:tty is busy now", __func__);
 456                 return -EBUSY;
 457         }
 458
 459         tty_insert_flip_string(tty, buf, size);
 460         tty_flip_buffer_push(tty);
 461         tty_kref_put(tty);
 462
 463         return 0;
 464 }
 465
 466 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 467 {
 468         int ret;
 469         struct uart_port *port = &priv->port;
 470
 471         if (port->x_char) {
 472                 pr_debug("%s:X character send %02x (%lu)\n", __func__,
 473                         port->x_char, jiffies);
 474                 buf[0] = port->x_char;
 475                 port->x_char = 0;
 476                 ret = 1;
 477         } else {
 478                 ret = 0;
 479         }
 480
 481         return ret;
 482 }
 483
 484 static int dma_push_rx(struct eg20t_port *priv, int size)
 485 {
 486         struct tty_struct *tty;
 487         int room;
 488         struct uart_port *port = &priv->port;
 489
 490         port = &priv->port;
 491         tty = tty_port_tty_get(&port->state->port);
 492         if (!tty) {
 493                 pr_debug("%s:tty is busy now", __func__);
 494                 return 0;
 495         }
 496
 497         room = tty_buffer_request_room(tty, size);
 498
 499         if (room < size)
 500                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 501                          size - room);
 502         if (!room)
 503                 return room;
 504
 505         tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
 506
 507         port->icount.rx += room;
 508         tty_kref_put(tty);
 509
 510         return room;
 511 }
 512
 513 static void pch_free_dma(struct uart_port *port)
 514 {
 515         struct eg20t_port *priv;
 516         priv = container_of(port, struct eg20t_port, port);
 517
 518         if (priv->chan_tx) {
 519                 dma_release_channel(priv->chan_tx);
 520                 priv->chan_tx = NULL;
 521         }
 522         if (priv->chan_rx) {
 523                 dma_release_channel(priv->chan_rx);
 524                 priv->chan_rx = NULL;
 525         }
 526         if (sg_dma_address(&priv->sg_rx))
 527                 dma_free_coherent(port->dev, port->fifosize,
 528                                   sg_virt(&priv->sg_rx),
 529                                   sg_dma_address(&priv->sg_rx));
 530
 531         return;
 532 }
 533
 534 static bool filter(struct dma_chan *chan, void *slave)
 535 {
 536         struct pch_dma_slave *param = slave;
 537
 538         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 539                                                   chan->device->dev)) {
 540                 chan->private = param;
 541                 return true;
 542         } else {
 543                 return false;
 544         }
 545 }
 546
 547 static void pch_request_dma(struct uart_port *port)
 548 {
 549         dma_cap_mask_t mask;
 550         struct dma_chan *chan;
 551         struct pci_dev *dma_dev;
 552         struct pch_dma_slave *param;
 553         struct eg20t_port *priv =
 554                                 container_of(port, struct eg20t_port, port);
 555         dma_cap_zero(mask);
 556         dma_cap_set(DMA_SLAVE, mask);
 557
 558         dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev
 559                                                                 information */
 560         /* Set Tx DMA */
 561         param = &priv->param_tx;
 562         param->dma_dev = &dma_dev->dev;
 563         param->chan_id = priv->port.line;
 564         param->tx_reg = port->mapbase + UART_TX;
 565         chan = dma_request_channel(mask, filter, param);
 566         if (!chan) {
 567                 pr_err("%s:dma_request_channel FAILS(Tx)\n", __func__);
 568                 return;
 569         }
 570         priv->chan_tx = chan;
 571
 572         /* Set Rx DMA */
 573         param = &priv->param_rx;
 574         param->dma_dev = &dma_dev->dev;
 575         param->chan_id = priv->port.line + 1; /* Rx = Tx + 1 */
 576         param->rx_reg = port->mapbase + UART_RX;
 577         chan = dma_request_channel(mask, filter, param);
 578         if (!chan) {
 579                 pr_err("%s:dma_request_channel FAILS(Rx)\n", __func__);
 580                 dma_release_channel(priv->chan_tx);
 581                 return;
 582         }
 583
 584         /* Get Consistent memory for DMA */
 585         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 586                                     &priv->rx_buf_dma, GFP_KERNEL);
 587         priv->chan_rx = chan;
 588 }
 589
 590 static void pch_dma_rx_complete(void *arg)
 591 {
 592         struct eg20t_port *priv = arg;
 593         struct uart_port *port = &priv->port;
 594         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
 595
 596         if (!tty) {
 597                 pr_debug("%s:tty is busy now", __func__);
 598                 return;
 599         }
 600
 601         if (dma_push_rx(priv, priv->trigger_level))
 602                 tty_flip_buffer_push(tty);
 603
 604         tty_kref_put(tty);
 605 }
 606
 607 static void pch_dma_tx_complete(void *arg)
 608 {
 609         struct eg20t_port *priv = arg;
 610         struct uart_port *port = &priv->port;
 611         struct circ_buf *xmit = &port->state->xmit;
 612
 613         xmit->tail += sg_dma_len(&priv->sg_tx);
 614         xmit->tail &= UART_XMIT_SIZE - 1;
 615         port->icount.tx += sg_dma_len(&priv->sg_tx);
 616
 617         async_tx_ack(priv->desc_tx);
 618         priv->tx_dma_use = 0;
 619 }
 620
 621 static int pop_tx(struct eg20t_port *priv, unsigned char *buf, int size)
 622 {
 623         int count = 0;
 624         struct uart_port *port = &priv->port;
 625         struct circ_buf *xmit = &port->state->xmit;
 626
 627         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 628                 goto pop_tx_end;
 629
 630         do {
 631                 int cnt_to_end =
 632                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 633                 int sz = min(size - count, cnt_to_end);
 634                 memcpy(&buf[count], &xmit->buf[xmit->tail], sz);
 635                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 636                 count += sz;
 637         } while (!uart_circ_empty(xmit) && count < size);
 638
 639 pop_tx_end:
 640         pr_debug("%d characters. Remained %d characters. (%lu)\n",
 641                  count, size - count, jiffies);
 642
 643         return count;
 644 }
 645
 646 static int handle_rx_to(struct eg20t_port *priv)
 647 {
 648         struct pch_uart_buffer *buf;
 649         int rx_size;
 650         int ret;
 651         if (!priv->start_rx) {
 652                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
 653                 return 0;
 654         }
 655         buf = &priv->rxbuf;
 656         do {
 657                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 658                 ret = push_rx(priv, buf->buf, rx_size);
 659                 if (ret)
 660                         return 0;
 661         } while (rx_size == buf->size);
 662
 663         return PCH_UART_HANDLED_RX_INT;
 664 }
 665
 666 static int handle_rx(struct eg20t_port *priv)
 667 {
 668         return handle_rx_to(priv);
 669 }
 670
 671 static int dma_handle_rx(struct eg20t_port *priv)
 672 {
 673         struct uart_port *port = &priv->port;
 674         struct dma_async_tx_descriptor *desc;
 675         struct scatterlist *sg;
 676
 677         priv = container_of(port, struct eg20t_port, port);
 678         sg = &priv->sg_rx;
 679
 680         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 681
 682         sg_dma_len(sg) = priv->fifo_size;
 683
 684         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 685                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 686                      ~PAGE_MASK);
 687
 688         sg_dma_address(sg) = priv->rx_buf_dma;
 689
 690         desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
 691                         sg, 1, DMA_FROM_DEVICE,
 692                         DMA_PREP_INTERRUPT);
 693         if (!desc)
 694                 return 0;
 695
 696         priv->desc_rx = desc;
 697         desc->callback = pch_dma_rx_complete;
 698         desc->callback_param = priv;
 699         desc->tx_submit(desc);
 700         dma_async_issue_pending(priv->chan_rx);
 701
 702         return PCH_UART_HANDLED_RX_INT;
 703 }
 704
 705 static unsigned int handle_tx(struct eg20t_port *priv)
 706 {
 707         struct uart_port *port = &priv->port;
 708         struct circ_buf *xmit = &port->state->xmit;
 709         int ret;
 710         int fifo_size;
 711         int tx_size;
 712         int size;
 713         int tx_empty;
 714
 715         if (!priv->start_tx) {
 716                 pr_info("%s:Tx isn't started. (%lu)\n", __func__, jiffies);
 717                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 718                 priv->tx_empty = 1;
 719                 return 0;
 720         }
 721
 722         fifo_size = max(priv->fifo_size, 1);
 723         tx_empty = 1;
 724         if (pop_tx_x(priv, xmit->buf)) {
 725                 pch_uart_hal_write(priv, xmit->buf, 1);
 726                 port->icount.tx++;
 727                 tx_empty = 0;
 728                 fifo_size--;
 729         }
 730         size = min(xmit->head - xmit->tail, fifo_size);
 731         tx_size = pop_tx(priv, xmit->buf, size);
 732         if (tx_size > 0) {
 733                 ret = pch_uart_hal_write(priv, xmit->buf, tx_size);
 734                 port->icount.tx += ret;
 735                 tx_empty = 0;
 736         }
 737
 738         priv->tx_empty = tx_empty;
 739
 740         if (tx_empty)
 741                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 742
 743         return PCH_UART_HANDLED_TX_INT;
 744 }
 745
 746 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 747 {
 748         struct uart_port *port = &priv->port;
 749         struct circ_buf *xmit = &port->state->xmit;
 750         struct scatterlist *sg = &priv->sg_tx;
 751         int nent;
 752         int fifo_size;
 753         int tx_empty;
 754         struct dma_async_tx_descriptor *desc;
 755
 756         if (!priv->start_tx) {
 757                 pr_info("%s:Tx isn't started. (%lu)\n", __func__, jiffies);
 758                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 759                 priv->tx_empty = 1;
 760                 return 0;
 761         }
 762
 763         fifo_size = max(priv->fifo_size, 1);
 764         tx_empty = 1;
 765         if (pop_tx_x(priv, xmit->buf)) {
 766                 pch_uart_hal_write(priv, xmit->buf, 1);
 767                 port->icount.tx++;
 768                 tx_empty = 0;
 769                 fifo_size--;
 770         }
 771
 772         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 773
 774         priv->tx_dma_use = 1;
 775
 776         sg_init_table(&priv->sg_tx, 1); /* Initialize SG table */
 777
 778         sg_set_page(&priv->sg_tx, virt_to_page(xmit->buf),
 779                     UART_XMIT_SIZE, (int)xmit->buf & ~PAGE_MASK);
 780
 781         nent = dma_map_sg(port->dev, &priv->sg_tx, 1, DMA_TO_DEVICE);
 782         if (!nent) {
 783                 pr_err("%s:dma_map_sg Failed\n", __func__);
 784                 return 0;
 785         }
 786
 787         sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
 788         sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
 789                               sg->offset;
 790         sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail,
 791                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 792                              xmit->tail, UART_XMIT_SIZE));
 793
 794         desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
 795                 sg, nent, DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 796         if (!desc) {
 797                 pr_err("%s:device_prep_slave_sg Failed\n", __func__);
 798                 return 0;
 799         }
 800
 801         dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
 802
 803         priv->desc_tx = desc;
 804         desc->callback = pch_dma_tx_complete;
 805         desc->callback_param = priv;
 806
 807         desc->tx_submit(desc);
 808
 809         dma_async_issue_pending(priv->chan_tx);
 810
 811         return PCH_UART_HANDLED_TX_INT;
 812 }
 813
 814 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
 815 {
 816         u8 fcr = ioread8(priv->membase + UART_FCR);
 817
 818         /* Reset FIFO */
 819         fcr |= UART_FCR_CLEAR_RCVR;
 820         iowrite8(fcr, priv->membase + UART_FCR);
 821
 822         if (lsr & PCH_UART_LSR_ERR)
 823                 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
 824
 825         if (lsr & UART_LSR_FE)
 826                 dev_err(&priv->pdev->dev, "Framing Error\n");
 827
 828         if (lsr & UART_LSR_PE)
 829                 dev_err(&priv->pdev->dev, "Parity Error\n");
 830
 831         if (lsr & UART_LSR_OE)
 832                 dev_err(&priv->pdev->dev, "Overrun Error\n");
 833 }
 834
 835 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
 836 {
 837         struct eg20t_port *priv = dev_id;
 838         unsigned int handled;
 839         u8 lsr;
 840         int ret = 0;
 841         unsigned int iid;
 842         unsigned long flags;
 843
 844         spin_lock_irqsave(&priv->port.lock, flags);
 845         handled = 0;
 846         while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
 847                 switch (iid) {
 848                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
 849                         lsr = pch_uart_hal_get_line_status(priv);
 850                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
 851                                                 UART_LSR_PE | UART_LSR_OE)) {
 852                                 pch_uart_err_ir(priv, lsr);
 853                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
 854                         }
 855                         break;
 856                 case PCH_UART_IID_RDR:  /* Received Data Ready */
 857                         if (priv->use_dma)
 858                                 ret = dma_handle_rx(priv);
 859                         else
 860                                 ret = handle_rx(priv);
 861                         break;
 862                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
 863                                                    (FIFO Timeout) */
 864                         ret = handle_rx_to(priv);
 865                         break;
 866                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
 867                                                    Empty */
 868                         if (priv->use_dma)
 869                                 ret = dma_handle_tx(priv);
 870                         else
 871                                 ret = handle_tx(priv);
 872                         break;
 873                 case PCH_UART_IID_MS:   /* Modem Status */
 874                         ret = PCH_UART_HANDLED_MS_INT;
 875                         break;
 876                 default:        /* Never junp to this label */
 877                         pr_err("%s:iid=%d (%lu)\n", __func__, iid, jiffies);
 878                         ret = -1;
 879                         break;
 880                 }
 881                 handled |= (unsigned int)ret;
 882         }
 883         if (handled == 0 && iid <= 1) {
 884                 if (priv->int_dis_flag)
 885                         priv->int_dis_flag = 0;
 886         }
 887
 888         spin_unlock_irqrestore(&priv->port.lock, flags);
 889         return IRQ_RETVAL(handled);
 890 }
 891
 892 /* This function tests whether the transmitter fifo and shifter for the port
 893                                                 described by 'port' is empty. */
 894 static unsigned int pch_uart_tx_empty(struct uart_port *port)
 895 {
 896         struct eg20t_port *priv;
 897         int ret;
 898         priv = container_of(port, struct eg20t_port, port);
 899         if (priv->tx_empty)
 900                 ret = TIOCSER_TEMT;
 901         else
 902                 ret = 0;
 903
 904         return ret;
 905 }
 906
 907 /* Returns the current state of modem control inputs. */
 908 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
 909 {
 910         struct eg20t_port *priv;
 911         u8 modem;
 912         unsigned int ret = 0;
 913
 914         priv = container_of(port, struct eg20t_port, port);
 915         modem = pch_uart_hal_get_modem(priv);
 916
 917         if (modem & UART_MSR_DCD)
 918                 ret |= TIOCM_CAR;
 919
 920         if (modem & UART_MSR_RI)
 921                 ret |= TIOCM_RNG;
 922
 923         if (modem & UART_MSR_DSR)
 924                 ret |= TIOCM_DSR;
 925
 926         if (modem & UART_MSR_CTS)
 927                 ret |= TIOCM_CTS;
 928
 929         return ret;
 930 }
 931
 932 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 933 {
 934         u32 mcr = 0;
 935         unsigned int dat;
 936         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
 937
 938         if (mctrl & TIOCM_DTR)
 939                 mcr |= UART_MCR_DTR;
 940         if (mctrl & TIOCM_RTS)
 941                 mcr |= UART_MCR_RTS;
 942         if (mctrl & TIOCM_LOOP)
 943                 mcr |= UART_MCR_LOOP;
 944
 945         if (mctrl) {
 946                 dat = pch_uart_get_mctrl(port);
 947                 dat |= mcr;
 948                 iowrite8(dat, priv->membase + UART_MCR);
 949         }
 950 }
 951
 952 static void pch_uart_stop_tx(struct uart_port *port)
 953 {
 954         struct eg20t_port *priv;
 955         priv = container_of(port, struct eg20t_port, port);
 956         priv->start_tx = 0;
 957         priv->tx_dma_use = 0;
 958 }
 959
 960 static void pch_uart_start_tx(struct uart_port *port)
 961 {
 962         struct eg20t_port *priv;
 963
 964         priv = container_of(port, struct eg20t_port, port);
 965
 966         if (priv->use_dma)
 967                 if (priv->tx_dma_use)
 968                         return;
 969
 970         priv->start_tx = 1;
 971         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 972 }
 973
 974 static void pch_uart_stop_rx(struct uart_port *port)
 975 {
 976         struct eg20t_port *priv;
 977         priv = container_of(port, struct eg20t_port, port);
 978         priv->start_rx = 0;
 979         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
 980         priv->int_dis_flag = 1;
 981 }
 982
 983 /* Enable the modem status interrupts. */
 984 static void pch_uart_enable_ms(struct uart_port *port)
 985 {
 986         struct eg20t_port *priv;
 987         priv = container_of(port, struct eg20t_port, port);
 988         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
 989 }
 990
 991 /* Control the transmission of a break signal. */
 992 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
 993 {
 994         struct eg20t_port *priv;
 995         unsigned long flags;
 996
 997         priv = container_of(port, struct eg20t_port, port);
 998         spin_lock_irqsave(&port->lock, flags);
 999         pch_uart_hal_set_break(priv, ctl);
1000         spin_unlock_irqrestore(&port->lock, flags);
1001 }
1002
1003 /* Grab any interrupt resources and initialise any low level driver state. */
1004 static int pch_uart_startup(struct uart_port *port)
1005 {
1006         struct eg20t_port *priv;
1007         int ret;
1008         int fifo_size;
1009         int trigger_level;
1010
1011         priv = container_of(port, struct eg20t_port, port);
1012         priv->tx_empty = 1;
1013         port->uartclk = priv->base_baud;
1014         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1015         ret = pch_uart_hal_set_line(priv, default_baud,
1016                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1017                               PCH_UART_HAL_STB1);
1018         if (ret)
1019                 return ret;
1020
1021         switch (priv->fifo_size) {
1022         case 256:
1023                 fifo_size = PCH_UART_HAL_FIFO256;
1024                 break;
1025         case 64:
1026                 fifo_size = PCH_UART_HAL_FIFO64;
1027                 break;
1028         case 16:
1029                 fifo_size = PCH_UART_HAL_FIFO16;
1030         case 1:
1031         default:
1032                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1033                 break;
1034         }
1035
1036         switch (priv->trigger) {
1037         case PCH_UART_HAL_TRIGGER1:
1038                 trigger_level = 1;
1039                 break;
1040         case PCH_UART_HAL_TRIGGER_L:
1041                 trigger_level = priv->fifo_size / 4;
1042                 break;
1043         case PCH_UART_HAL_TRIGGER_M:
1044                 trigger_level = priv->fifo_size / 2;
1045                 break;
1046         case PCH_UART_HAL_TRIGGER_H:
1047         default:
1048                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1049                 break;
1050         }
1051
1052         priv->trigger_level = trigger_level;
1053         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1054                                     fifo_size, priv->trigger);
1055         if (ret < 0)
1056                 return ret;
1057
1058         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1059                         KBUILD_MODNAME, priv);
1060         if (ret < 0)
1061                 return ret;
1062
1063         if (priv->use_dma)
1064                 pch_request_dma(port);
1065
1066         priv->start_rx = 1;
1067         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1068         uart_update_timeout(port, CS8, default_baud);
1069
1070         return 0;
1071 }
1072
1073 static void pch_uart_shutdown(struct uart_port *port)
1074 {
1075         struct eg20t_port *priv;
1076         int ret;
1077
1078         priv = container_of(port, struct eg20t_port, port);
1079         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1080         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1081         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1082                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1083         if (ret)
1084                 pr_err("pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1085
1086         if (priv->use_dma_flag)
1087                 pch_free_dma(port);
1088
1089         free_irq(priv->port.irq, priv);
1090 }
1091
1092 /* Change the port parameters, including word length, parity, stop
1093  *bits.  Update read_status_mask and ignore_status_mask to indicate
1094  *the types of events we are interested in receiving.  */
1095 static void pch_uart_set_termios(struct uart_port *port,
1096                                  struct ktermios *termios, struct ktermios *old)
1097 {
1098         int baud;
1099         int rtn;
1100         unsigned int parity, bits, stb;
1101         struct eg20t_port *priv;
1102         unsigned long flags;
1103
1104         priv = container_of(port, struct eg20t_port, port);
1105         switch (termios->c_cflag & CSIZE) {
1106         case CS5:
1107                 bits = PCH_UART_HAL_5BIT;
1108                 break;
1109         case CS6:
1110                 bits = PCH_UART_HAL_6BIT;
1111                 break;
1112         case CS7:
1113                 bits = PCH_UART_HAL_7BIT;
1114                 break;
1115         default:                /* CS8 */
1116                 bits = PCH_UART_HAL_8BIT;
1117                 break;
1118         }
1119         if (termios->c_cflag & CSTOPB)
1120                 stb = PCH_UART_HAL_STB2;
1121         else
1122                 stb = PCH_UART_HAL_STB1;
1123
1124         if (termios->c_cflag & PARENB) {
1125                 if (!(termios->c_cflag & PARODD))
1126                         parity = PCH_UART_HAL_PARITY_ODD;
1127                 else
1128                         parity = PCH_UART_HAL_PARITY_EVEN;
1129
1130         } else {
1131                 parity = PCH_UART_HAL_PARITY_NONE;
1132         }
1133         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1134
1135         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1136
1137         spin_lock_irqsave(&port->lock, flags);
1138
1139         uart_update_timeout(port, termios->c_cflag, baud);
1140         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1141         if (rtn)
1142                 goto out;
1143
1144         /* Don't rewrite B0 */
1145         if (tty_termios_baud_rate(termios))
1146                 tty_termios_encode_baud_rate(termios, baud, baud);
1147
1148 out:
1149         spin_unlock_irqrestore(&port->lock, flags);
1150 }
1151
1152 static const char *pch_uart_type(struct uart_port *port)
1153 {
1154         return KBUILD_MODNAME;
1155 }
1156
1157 static void pch_uart_release_port(struct uart_port *port)
1158 {
1159         struct eg20t_port *priv;
1160
1161         priv = container_of(port, struct eg20t_port, port);
1162         pci_iounmap(priv->pdev, priv->membase);
1163         pci_release_regions(priv->pdev);
1164 }
1165
1166 static int pch_uart_request_port(struct uart_port *port)
1167 {
1168         struct eg20t_port *priv;
1169         int ret;
1170         void __iomem *membase;
1171
1172         priv = container_of(port, struct eg20t_port, port);
1173         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1174         if (ret < 0)
1175                 return -EBUSY;
1176
1177         membase = pci_iomap(priv->pdev, 1, 0);
1178         if (!membase) {
1179                 pci_release_regions(priv->pdev);
1180                 return -EBUSY;
1181         }
1182         priv->membase = port->membase = membase;
1183
1184         return 0;
1185 }
1186
1187 static void pch_uart_config_port(struct uart_port *port, int type)
1188 {
1189         struct eg20t_port *priv;
1190
1191         priv = container_of(port, struct eg20t_port, port);
1192         if (type & UART_CONFIG_TYPE) {
1193                 port->type = priv->port_type;
1194                 pch_uart_request_port(port);
1195         }
1196 }
1197
1198 static int pch_uart_verify_port(struct uart_port *port,
1199                                 struct serial_struct *serinfo)
1200 {
1201         struct eg20t_port *priv;
1202
1203         priv = container_of(port, struct eg20t_port, port);
1204         if (serinfo->flags & UPF_LOW_LATENCY) {
1205                 pr_info("PCH UART : Use PIO Mode (without DMA)\n");
1206                 priv->use_dma = 0;
1207                 serinfo->flags &= ~UPF_LOW_LATENCY;
1208         } else {
1209 #ifndef CONFIG_PCH_DMA
1210                 pr_err("%s : PCH DMA is not Loaded.\n", __func__);
1211                 return -EOPNOTSUPP;
1212 #endif
1213                 priv->use_dma = 1;
1214                 priv->use_dma_flag = 1;
1215                 pr_info("PCH UART : Use DMA Mode\n");
1216         }
1217
1218         return 0;
1219 }
1220
1221 static struct uart_ops pch_uart_ops = {
1222         .tx_empty = pch_uart_tx_empty,
1223         .set_mctrl = pch_uart_set_mctrl,
1224         .get_mctrl = pch_uart_get_mctrl,
1225         .stop_tx = pch_uart_stop_tx,
1226         .start_tx = pch_uart_start_tx,
1227         .stop_rx = pch_uart_stop_rx,
1228         .enable_ms = pch_uart_enable_ms,
1229         .break_ctl = pch_uart_break_ctl,
1230         .startup = pch_uart_startup,
1231         .shutdown = pch_uart_shutdown,
1232         .set_termios = pch_uart_set_termios,
1233 /*      .pm             = pch_uart_pm,          Not supported yet */
1234 /*      .set_wake       = pch_uart_set_wake,    Not supported yet */
1235         .type = pch_uart_type,
1236         .release_port = pch_uart_release_port,
1237         .request_port = pch_uart_request_port,
1238         .config_port = pch_uart_config_port,
1239         .verify_port = pch_uart_verify_port
1240 };
1241
1242 static struct uart_driver pch_uart_driver = {
1243         .owner = THIS_MODULE,
1244         .driver_name = KBUILD_MODNAME,
1245         .dev_name = PCH_UART_DRIVER_DEVICE,
1246         .major = 0,
1247         .minor = 0,
1248         .nr = PCH_UART_NR,
1249 };
1250
1251 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1252                                                 int port_type)
1253 {
1254         struct eg20t_port *priv;
1255         int ret;
1256         unsigned int iobase;
1257         unsigned int mapbase;
1258         unsigned char *rxbuf;
1259         int fifosize, base_baud;
1260         static int num;
1261
1262         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1263         if (priv == NULL)
1264                 goto init_port_alloc_err;
1265
1266         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1267         if (!rxbuf)
1268                 goto init_port_free_txbuf;
1269
1270         switch (port_type) {
1271         case PORT_UNKNOWN:
1272                 fifosize = 256; /* UART0 */
1273                 base_baud = 1843200; /* 1.8432MHz */
1274                 break;
1275         case PORT_8250:
1276                 fifosize = 64; /* UART1~3 */
1277                 base_baud = 1843200; /* 1.8432MHz */
1278                 break;
1279         default:
1280                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1281                 goto init_port_hal_free;
1282         }
1283
1284         iobase = pci_resource_start(pdev, 0);
1285         mapbase = pci_resource_start(pdev, 1);
1286         priv->mapbase = mapbase;
1287         priv->iobase = iobase;
1288         priv->pdev = pdev;
1289         priv->tx_empty = 1;
1290         priv->rxbuf.buf = rxbuf;
1291         priv->rxbuf.size = PAGE_SIZE;
1292
1293         priv->fifo_size = fifosize;
1294         priv->base_baud = base_baud;
1295         priv->port_type = PORT_MAX_8250 + port_type + 1;
1296         priv->port.dev = &pdev->dev;
1297         priv->port.iobase = iobase;
1298         priv->port.membase = NULL;
1299         priv->port.mapbase = mapbase;
1300         priv->port.irq = pdev->irq;
1301         priv->port.iotype = UPIO_PORT;
1302         priv->port.ops = &pch_uart_ops;
1303         priv->port.flags = UPF_BOOT_AUTOCONF;
1304         priv->port.fifosize = fifosize;
1305         priv->port.line = num++;
1306         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1307
1308         pci_set_drvdata(pdev, priv);
1309         pch_uart_hal_request(pdev, fifosize, base_baud);
1310         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1311         if (ret < 0)
1312                 goto init_port_hal_free;
1313
1314         return priv;
1315
1316 init_port_hal_free:
1317         free_page((unsigned long)rxbuf);
1318 init_port_free_txbuf:
1319         kfree(priv);
1320 init_port_alloc_err:
1321
1322         return NULL;
1323 }
1324
1325 static void pch_uart_exit_port(struct eg20t_port *priv)
1326 {
1327         uart_remove_one_port(&pch_uart_driver, &priv->port);
1328         pci_set_drvdata(priv->pdev, NULL);
1329         free_page((unsigned long)priv->rxbuf.buf);
1330 }
1331
1332 static void pch_uart_pci_remove(struct pci_dev *pdev)
1333 {
1334         struct eg20t_port *priv;
1335
1336         priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1337         pch_uart_exit_port(priv);
1338         pci_disable_device(pdev);
1339         kfree(priv);
1340         return;
1341 }
1342 #ifdef CONFIG_PM
1343 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1344 {
1345         struct eg20t_port *priv = pci_get_drvdata(pdev);
1346
1347         uart_suspend_port(&pch_uart_driver, &priv->port);
1348
1349         pci_save_state(pdev);
1350         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1351         return 0;
1352 }
1353
1354 static int pch_uart_pci_resume(struct pci_dev *pdev)
1355 {
1356         struct eg20t_port *priv = pci_get_drvdata(pdev);
1357         int ret;
1358
1359         pci_set_power_state(pdev, PCI_D0);
1360         pci_restore_state(pdev);
1361
1362         ret = pci_enable_device(pdev);
1363         if (ret) {
1364                 dev_err(&pdev->dev,
1365                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1366                 return ret;
1367         }
1368
1369         uart_resume_port(&pch_uart_driver, &priv->port);
1370
1371         return 0;
1372 }
1373 #else
1374 #define pch_uart_pci_suspend NULL
1375 #define pch_uart_pci_resume NULL
1376 #endif
1377
1378 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1379         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1380          .driver_data = PCH_UART_8LINE},
1381         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1382          .driver_data = PCH_UART_2LINE},
1383         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1384          .driver_data = PCH_UART_2LINE},
1385         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1386          .driver_data = PCH_UART_2LINE},
1387         {0,},
1388 };
1389
1390 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1391                                         const struct pci_device_id *id)
1392 {
1393         int ret;
1394         struct eg20t_port *priv;
1395
1396         ret = pci_enable_device(pdev);
1397         if (ret < 0)
1398                 goto probe_error;
1399
1400         priv = pch_uart_init_port(pdev, id->driver_data);
1401         if (!priv) {
1402                 ret = -EBUSY;
1403                 goto probe_disable_device;
1404         }
1405         pci_set_drvdata(pdev, priv);
1406
1407         return ret;
1408
1409 probe_disable_device:
1410         pci_disable_device(pdev);
1411 probe_error:
1412         return ret;
1413 }
1414
1415 static struct pci_driver pch_uart_pci_driver = {
1416         .name = "pch_uart",
1417         .id_table = pch_uart_pci_id,
1418         .probe = pch_uart_pci_probe,
1419         .remove = __devexit_p(pch_uart_pci_remove),
1420         .suspend = pch_uart_pci_suspend,
1421         .resume = pch_uart_pci_resume,
1422 };
1423
1424 static int __init pch_uart_module_init(void)
1425 {
1426         int ret;
1427
1428         /* register as UART driver */
1429         ret = uart_register_driver(&pch_uart_driver);
1430         if (ret < 0)
1431                 return ret;
1432
1433         /* register as PCI driver */
1434         ret = pci_register_driver(&pch_uart_pci_driver);
1435         if (ret < 0)
1436                 uart_unregister_driver(&pch_uart_driver);
1437
1438         return ret;
1439 }
1440 module_init(pch_uart_module_init);
1441
1442 static void __exit pch_uart_module_exit(void)
1443 {
1444         pci_unregister_driver(&pch_uart_pci_driver);
1445         uart_unregister_driver(&pch_uart_driver);
1446 }
1447 module_exit(pch_uart_module_exit);
1448
1449 MODULE_LICENSE("GPL v2");
1450 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1451 module_param(default_baud, uint, S_IRUGO);