2 * linux/drivers/char/8250.c
4 * Driver for 8250/16550-type serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * A note about mapbase / membase
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
21 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/ioport.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/sysrq.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/serial_reg.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial.h>
38 #include <linux/serial_8250.h>
39 #include <linux/nmi.h>
40 #include <linux/mutex.h>
41 #include <linux/slab.h>
54 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
55 * is unsafe when used on edge-triggered interrupts.
57 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
59 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
61 static struct uart_driver serial8250_reg;
63 static int serial_index(struct uart_port *port)
65 return (serial8250_reg.minor - 64) + port->line;
68 static unsigned int skip_txen_test; /* force skip of txen test at init time */
74 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
76 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
80 #define DEBUG_INTR(fmt...) printk(fmt)
82 #define DEBUG_INTR(fmt...) do { } while (0)
85 #define PASS_LIMIT 256
87 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
91 * We default to IRQ0 for the "no irq" hack. Some
92 * machine types want others as well - they're free
93 * to redefine this in their header file.
95 #define is_real_interrupt(irq) ((irq) != 0)
97 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
98 #define CONFIG_SERIAL_DETECT_IRQ 1
100 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
101 #define CONFIG_SERIAL_MANY_PORTS 1
105 * HUB6 is always on. This will be removed once the header
106 * files have been cleaned.
108 #define CONFIG_HUB6 1
110 #include <asm/serial.h>
112 * SERIAL_PORT_DFNS tells us about built-in ports that have no
113 * standard enumeration mechanism. Platforms that can find all
114 * serial ports via mechanisms like ACPI or PCI need not supply it.
116 #ifndef SERIAL_PORT_DFNS
117 #define SERIAL_PORT_DFNS
120 static const struct old_serial_port old_serial_port[] = {
121 SERIAL_PORT_DFNS /* defined in asm/serial.h */
124 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
126 #ifdef CONFIG_SERIAL_8250_RSA
128 #define PORT_RSA_MAX 4
129 static unsigned long probe_rsa[PORT_RSA_MAX];
130 static unsigned int probe_rsa_count;
131 #endif /* CONFIG_SERIAL_8250_RSA */
133 struct uart_8250_port {
134 struct uart_port port;
135 struct timer_list timer; /* "no irq" timer */
136 struct list_head list; /* ports on this IRQ */
137 unsigned short capabilities; /* port capabilities */
138 unsigned short bugs; /* port bugs */
139 unsigned int tx_loadsz; /* transmit fifo load size */
144 unsigned char mcr_mask; /* mask of user bits */
145 unsigned char mcr_force; /* mask of forced bits */
146 unsigned char cur_iotype; /* Running I/O type */
149 * Some bits in registers are cleared on a read, so they must
150 * be saved whenever the register is read but the bits will not
151 * be immediately processed.
153 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
154 unsigned char lsr_saved_flags;
155 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
156 unsigned char msr_saved_flags;
160 struct hlist_node node;
162 spinlock_t lock; /* Protects list not the hash */
163 struct list_head *head;
166 #define NR_IRQ_HASH 32 /* Can be adjusted later */
167 static struct hlist_head irq_lists[NR_IRQ_HASH];
168 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
171 * Here we define the default xmit fifo size used for each type of UART.
173 static const struct serial8250_config uart_config[] = {
198 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
199 .flags = UART_CAP_FIFO,
210 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
216 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
218 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
224 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
226 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
234 .name = "16C950/954",
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
238 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
281 .flags = UART_CAP_FIFO,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
288 .flags = UART_CAP_FIFO,
294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
306 #if defined(CONFIG_MIPS_ALCHEMY)
308 /* Au1x00 UART hardware has a weird register layout */
309 static const u8 au_io_in_map[] = {
319 static const u8 au_io_out_map[] = {
327 /* sane hardware needs no mapping */
328 static inline int map_8250_in_reg(struct uart_port *p, int offset)
330 if (p->iotype != UPIO_AU)
332 return au_io_in_map[offset];
335 static inline int map_8250_out_reg(struct uart_port *p, int offset)
337 if (p->iotype != UPIO_AU)
339 return au_io_out_map[offset];
342 #elif defined(CONFIG_SERIAL_8250_RM9K)
366 static inline int map_8250_in_reg(struct uart_port *p, int offset)
368 if (p->iotype != UPIO_RM9000)
370 return regmap_in[offset];
373 static inline int map_8250_out_reg(struct uart_port *p, int offset)
375 if (p->iotype != UPIO_RM9000)
377 return regmap_out[offset];
382 /* sane hardware needs no mapping */
383 #define map_8250_in_reg(up, offset) (offset)
384 #define map_8250_out_reg(up, offset) (offset)
388 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
390 offset = map_8250_in_reg(p, offset) << p->regshift;
391 outb(p->hub6 - 1 + offset, p->iobase);
392 return inb(p->iobase + 1);
395 static void hub6_serial_out(struct uart_port *p, int offset, int value)
397 offset = map_8250_out_reg(p, offset) << p->regshift;
398 outb(p->hub6 - 1 + offset, p->iobase);
399 outb(value, p->iobase + 1);
402 static unsigned int mem_serial_in(struct uart_port *p, int offset)
404 offset = map_8250_in_reg(p, offset) << p->regshift;
405 return readb(p->membase + offset);
408 static void mem_serial_out(struct uart_port *p, int offset, int value)
410 offset = map_8250_out_reg(p, offset) << p->regshift;
411 writeb(value, p->membase + offset);
414 static void mem32_serial_out(struct uart_port *p, int offset, int value)
416 offset = map_8250_out_reg(p, offset) << p->regshift;
417 writel(value, p->membase + offset);
420 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
422 offset = map_8250_in_reg(p, offset) << p->regshift;
423 return readl(p->membase + offset);
426 static unsigned int au_serial_in(struct uart_port *p, int offset)
428 offset = map_8250_in_reg(p, offset) << p->regshift;
429 return __raw_readl(p->membase + offset);
432 static void au_serial_out(struct uart_port *p, int offset, int value)
434 offset = map_8250_out_reg(p, offset) << p->regshift;
435 __raw_writel(value, p->membase + offset);
438 static unsigned int tsi_serial_in(struct uart_port *p, int offset)
441 offset = map_8250_in_reg(p, offset) << p->regshift;
442 if (offset == UART_IIR) {
443 tmp = readl(p->membase + (UART_IIR & ~3));
444 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
446 return readb(p->membase + offset);
449 static void tsi_serial_out(struct uart_port *p, int offset, int value)
451 offset = map_8250_out_reg(p, offset) << p->regshift;
452 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
453 writeb(value, p->membase + offset);
456 static void dwapb_serial_out(struct uart_port *p, int offset, int value)
458 int save_offset = offset;
459 offset = map_8250_out_reg(p, offset) << p->regshift;
460 /* Save the LCR value so it can be re-written when a
461 * Busy Detect interrupt occurs. */
462 if (save_offset == UART_LCR) {
463 struct uart_8250_port *up = (struct uart_8250_port *)p;
466 writeb(value, p->membase + offset);
467 /* Read the IER to ensure any interrupt is cleared before
468 * returning from ISR. */
469 if (save_offset == UART_TX || save_offset == UART_IER)
470 value = p->serial_in(p, UART_IER);
473 static unsigned int io_serial_in(struct uart_port *p, int offset)
475 offset = map_8250_in_reg(p, offset) << p->regshift;
476 return inb(p->iobase + offset);
479 static void io_serial_out(struct uart_port *p, int offset, int value)
481 offset = map_8250_out_reg(p, offset) << p->regshift;
482 outb(value, p->iobase + offset);
485 static void set_io_from_upio(struct uart_port *p)
487 struct uart_8250_port *up = (struct uart_8250_port *)p;
490 p->serial_in = hub6_serial_in;
491 p->serial_out = hub6_serial_out;
495 p->serial_in = mem_serial_in;
496 p->serial_out = mem_serial_out;
501 p->serial_in = mem32_serial_in;
502 p->serial_out = mem32_serial_out;
506 p->serial_in = au_serial_in;
507 p->serial_out = au_serial_out;
511 p->serial_in = tsi_serial_in;
512 p->serial_out = tsi_serial_out;
516 p->serial_in = mem_serial_in;
517 p->serial_out = dwapb_serial_out;
521 p->serial_in = io_serial_in;
522 p->serial_out = io_serial_out;
525 /* Remember loaded iotype */
526 up->cur_iotype = p->iotype;
530 serial_out_sync(struct uart_8250_port *up, int offset, int value)
532 struct uart_port *p = &up->port;
538 p->serial_out(p, offset, value);
539 p->serial_in(p, UART_LCR); /* safe, no side-effects */
542 p->serial_out(p, offset, value);
546 #define serial_in(up, offset) \
547 (up->port.serial_in(&(up)->port, (offset)))
548 #define serial_out(up, offset, value) \
549 (up->port.serial_out(&(up)->port, (offset), (value)))
551 * We used to support using pause I/O for certain machines. We
552 * haven't supported this for a while, but just in case it's badly
553 * needed for certain old 386 machines, I've left these #define's
556 #define serial_inp(up, offset) serial_in(up, offset)
557 #define serial_outp(up, offset, value) serial_out(up, offset, value)
559 /* Uart divisor latch read */
560 static inline int _serial_dl_read(struct uart_8250_port *up)
562 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
565 /* Uart divisor latch write */
566 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
568 serial_outp(up, UART_DLL, value & 0xff);
569 serial_outp(up, UART_DLM, value >> 8 & 0xff);
572 #if defined(CONFIG_MIPS_ALCHEMY)
573 /* Au1x00 haven't got a standard divisor latch */
574 static int serial_dl_read(struct uart_8250_port *up)
576 if (up->port.iotype == UPIO_AU)
577 return __raw_readl(up->port.membase + 0x28);
579 return _serial_dl_read(up);
582 static void serial_dl_write(struct uart_8250_port *up, int value)
584 if (up->port.iotype == UPIO_AU)
585 __raw_writel(value, up->port.membase + 0x28);
587 _serial_dl_write(up, value);
589 #elif defined(CONFIG_SERIAL_8250_RM9K)
590 static int serial_dl_read(struct uart_8250_port *up)
592 return (up->port.iotype == UPIO_RM9000) ?
593 (((__raw_readl(up->port.membase + 0x10) << 8) |
594 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
598 static void serial_dl_write(struct uart_8250_port *up, int value)
600 if (up->port.iotype == UPIO_RM9000) {
601 __raw_writel(value, up->port.membase + 0x08);
602 __raw_writel(value >> 8, up->port.membase + 0x10);
604 _serial_dl_write(up, value);
608 #define serial_dl_read(up) _serial_dl_read(up)
609 #define serial_dl_write(up, value) _serial_dl_write(up, value)
615 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
617 serial_out(up, UART_SCR, offset);
618 serial_out(up, UART_ICR, value);
621 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
625 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
626 serial_out(up, UART_SCR, offset);
627 value = serial_in(up, UART_ICR);
628 serial_icr_write(up, UART_ACR, up->acr);
636 static void serial8250_clear_fifos(struct uart_8250_port *p)
638 if (p->capabilities & UART_CAP_FIFO) {
639 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
640 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
641 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
642 serial_outp(p, UART_FCR, 0);
647 * IER sleep support. UARTs which have EFRs need the "extended
648 * capability" bit enabled. Note that on XR16C850s, we need to
649 * reset LCR to write to IER.
651 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
653 if (p->capabilities & UART_CAP_SLEEP) {
654 if (p->capabilities & UART_CAP_EFR) {
655 serial_outp(p, UART_LCR, 0xBF);
656 serial_outp(p, UART_EFR, UART_EFR_ECB);
657 serial_outp(p, UART_LCR, 0);
659 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
660 if (p->capabilities & UART_CAP_EFR) {
661 serial_outp(p, UART_LCR, 0xBF);
662 serial_outp(p, UART_EFR, 0);
663 serial_outp(p, UART_LCR, 0);
668 #ifdef CONFIG_SERIAL_8250_RSA
670 * Attempts to turn on the RSA FIFO. Returns zero on failure.
671 * We set the port uart clock rate if we succeed.
673 static int __enable_rsa(struct uart_8250_port *up)
678 mode = serial_inp(up, UART_RSA_MSR);
679 result = mode & UART_RSA_MSR_FIFO;
682 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
683 mode = serial_inp(up, UART_RSA_MSR);
684 result = mode & UART_RSA_MSR_FIFO;
688 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
693 static void enable_rsa(struct uart_8250_port *up)
695 if (up->port.type == PORT_RSA) {
696 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
697 spin_lock_irq(&up->port.lock);
699 spin_unlock_irq(&up->port.lock);
701 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
702 serial_outp(up, UART_RSA_FRR, 0);
707 * Attempts to turn off the RSA FIFO. Returns zero on failure.
708 * It is unknown why interrupts were disabled in here. However,
709 * the caller is expected to preserve this behaviour by grabbing
710 * the spinlock before calling this function.
712 static void disable_rsa(struct uart_8250_port *up)
717 if (up->port.type == PORT_RSA &&
718 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
719 spin_lock_irq(&up->port.lock);
721 mode = serial_inp(up, UART_RSA_MSR);
722 result = !(mode & UART_RSA_MSR_FIFO);
725 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
726 mode = serial_inp(up, UART_RSA_MSR);
727 result = !(mode & UART_RSA_MSR_FIFO);
731 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
732 spin_unlock_irq(&up->port.lock);
735 #endif /* CONFIG_SERIAL_8250_RSA */
738 * This is a quickie test to see how big the FIFO is.
739 * It doesn't work at all the time, more's the pity.
741 static int size_fifo(struct uart_8250_port *up)
743 unsigned char old_fcr, old_mcr, old_lcr;
744 unsigned short old_dl;
747 old_lcr = serial_inp(up, UART_LCR);
748 serial_outp(up, UART_LCR, 0);
749 old_fcr = serial_inp(up, UART_FCR);
750 old_mcr = serial_inp(up, UART_MCR);
751 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
752 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
753 serial_outp(up, UART_MCR, UART_MCR_LOOP);
754 serial_outp(up, UART_LCR, UART_LCR_DLAB);
755 old_dl = serial_dl_read(up);
756 serial_dl_write(up, 0x0001);
757 serial_outp(up, UART_LCR, 0x03);
758 for (count = 0; count < 256; count++)
759 serial_outp(up, UART_TX, count);
760 mdelay(20);/* FIXME - schedule_timeout */
761 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
762 (count < 256); count++)
763 serial_inp(up, UART_RX);
764 serial_outp(up, UART_FCR, old_fcr);
765 serial_outp(up, UART_MCR, old_mcr);
766 serial_outp(up, UART_LCR, UART_LCR_DLAB);
767 serial_dl_write(up, old_dl);
768 serial_outp(up, UART_LCR, old_lcr);
774 * Read UART ID using the divisor method - set DLL and DLM to zero
775 * and the revision will be in DLL and device type in DLM. We
776 * preserve the device state across this.
778 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
780 unsigned char old_dll, old_dlm, old_lcr;
783 old_lcr = serial_inp(p, UART_LCR);
784 serial_outp(p, UART_LCR, UART_LCR_DLAB);
786 old_dll = serial_inp(p, UART_DLL);
787 old_dlm = serial_inp(p, UART_DLM);
789 serial_outp(p, UART_DLL, 0);
790 serial_outp(p, UART_DLM, 0);
792 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
794 serial_outp(p, UART_DLL, old_dll);
795 serial_outp(p, UART_DLM, old_dlm);
796 serial_outp(p, UART_LCR, old_lcr);
802 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
803 * When this function is called we know it is at least a StarTech
804 * 16650 V2, but it might be one of several StarTech UARTs, or one of
805 * its clones. (We treat the broken original StarTech 16650 V1 as a
806 * 16550, and why not? Startech doesn't seem to even acknowledge its
809 * What evil have men's minds wrought...
811 static void autoconfig_has_efr(struct uart_8250_port *up)
813 unsigned int id1, id2, id3, rev;
816 * Everything with an EFR has SLEEP
818 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
821 * First we check to see if it's an Oxford Semiconductor UART.
823 * If we have to do this here because some non-National
824 * Semiconductor clone chips lock up if you try writing to the
825 * LSR register (which serial_icr_read does)
829 * Check for Oxford Semiconductor 16C950.
831 * EFR [4] must be set else this test fails.
833 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
834 * claims that it's needed for 952 dual UART's (which are not
835 * recommended for new designs).
838 serial_out(up, UART_LCR, 0xBF);
839 serial_out(up, UART_EFR, UART_EFR_ECB);
840 serial_out(up, UART_LCR, 0x00);
841 id1 = serial_icr_read(up, UART_ID1);
842 id2 = serial_icr_read(up, UART_ID2);
843 id3 = serial_icr_read(up, UART_ID3);
844 rev = serial_icr_read(up, UART_REV);
846 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
848 if (id1 == 0x16 && id2 == 0xC9 &&
849 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
850 up->port.type = PORT_16C950;
853 * Enable work around for the Oxford Semiconductor 952 rev B
854 * chip which causes it to seriously miscalculate baud rates
857 if (id3 == 0x52 && rev == 0x01)
858 up->bugs |= UART_BUG_QUOT;
863 * We check for a XR16C850 by setting DLL and DLM to 0, and then
864 * reading back DLL and DLM. The chip type depends on the DLM
866 * 0x10 - XR16C850 and the DLL contains the chip revision.
870 id1 = autoconfig_read_divisor_id(up);
871 DEBUG_AUTOCONF("850id=%04x ", id1);
874 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
875 up->port.type = PORT_16850;
880 * It wasn't an XR16C850.
882 * We distinguish between the '654 and the '650 by counting
883 * how many bytes are in the FIFO. I'm using this for now,
884 * since that's the technique that was sent to me in the
885 * serial driver update, but I'm not convinced this works.
886 * I've had problems doing this in the past. -TYT
888 if (size_fifo(up) == 64)
889 up->port.type = PORT_16654;
891 up->port.type = PORT_16650V2;
895 * We detected a chip without a FIFO. Only two fall into
896 * this category - the original 8250 and the 16450. The
897 * 16450 has a scratch register (accessible with LCR=0)
899 static void autoconfig_8250(struct uart_8250_port *up)
901 unsigned char scratch, status1, status2;
903 up->port.type = PORT_8250;
905 scratch = serial_in(up, UART_SCR);
906 serial_outp(up, UART_SCR, 0xa5);
907 status1 = serial_in(up, UART_SCR);
908 serial_outp(up, UART_SCR, 0x5a);
909 status2 = serial_in(up, UART_SCR);
910 serial_outp(up, UART_SCR, scratch);
912 if (status1 == 0xa5 && status2 == 0x5a)
913 up->port.type = PORT_16450;
916 static int broken_efr(struct uart_8250_port *up)
919 * Exar ST16C2550 "A2" devices incorrectly detect as
920 * having an EFR, and report an ID of 0x0201. See
921 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
923 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
930 * We know that the chip has FIFOs. Does it have an EFR? The
931 * EFR is located in the same register position as the IIR and
932 * we know the top two bits of the IIR are currently set. The
933 * EFR should contain zero. Try to read the EFR.
935 static void autoconfig_16550a(struct uart_8250_port *up)
937 unsigned char status1, status2;
938 unsigned int iersave;
940 up->port.type = PORT_16550A;
941 up->capabilities |= UART_CAP_FIFO;
944 * Check for presence of the EFR when DLAB is set.
945 * Only ST16C650V1 UARTs pass this test.
947 serial_outp(up, UART_LCR, UART_LCR_DLAB);
948 if (serial_in(up, UART_EFR) == 0) {
949 serial_outp(up, UART_EFR, 0xA8);
950 if (serial_in(up, UART_EFR) != 0) {
951 DEBUG_AUTOCONF("EFRv1 ");
952 up->port.type = PORT_16650;
953 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
955 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
957 serial_outp(up, UART_EFR, 0);
962 * Maybe it requires 0xbf to be written to the LCR.
963 * (other ST16C650V2 UARTs, TI16C752A, etc)
965 serial_outp(up, UART_LCR, 0xBF);
966 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
967 DEBUG_AUTOCONF("EFRv2 ");
968 autoconfig_has_efr(up);
973 * Check for a National Semiconductor SuperIO chip.
974 * Attempt to switch to bank 2, read the value of the LOOP bit
975 * from EXCR1. Switch back to bank 0, change it in MCR. Then
976 * switch back to bank 2, read it from EXCR1 again and check
977 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
979 serial_outp(up, UART_LCR, 0);
980 status1 = serial_in(up, UART_MCR);
981 serial_outp(up, UART_LCR, 0xE0);
982 status2 = serial_in(up, 0x02); /* EXCR1 */
984 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
985 serial_outp(up, UART_LCR, 0);
986 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
987 serial_outp(up, UART_LCR, 0xE0);
988 status2 = serial_in(up, 0x02); /* EXCR1 */
989 serial_outp(up, UART_LCR, 0);
990 serial_outp(up, UART_MCR, status1);
992 if ((status2 ^ status1) & UART_MCR_LOOP) {
995 serial_outp(up, UART_LCR, 0xE0);
997 quot = serial_dl_read(up);
1000 status1 = serial_in(up, 0x04); /* EXCR2 */
1001 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1002 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1003 serial_outp(up, 0x04, status1);
1005 serial_dl_write(up, quot);
1007 serial_outp(up, UART_LCR, 0);
1009 up->port.uartclk = 921600*16;
1010 up->port.type = PORT_NS16550A;
1011 up->capabilities |= UART_NATSEMI;
1017 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1018 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1019 * Try setting it with and without DLAB set. Cheap clones
1020 * set bit 5 without DLAB set.
1022 serial_outp(up, UART_LCR, 0);
1023 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1024 status1 = serial_in(up, UART_IIR) >> 5;
1025 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1026 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1027 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1028 status2 = serial_in(up, UART_IIR) >> 5;
1029 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1030 serial_outp(up, UART_LCR, 0);
1032 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1034 if (status1 == 6 && status2 == 7) {
1035 up->port.type = PORT_16750;
1036 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1041 * Try writing and reading the UART_IER_UUE bit (b6).
1042 * If it works, this is probably one of the Xscale platform's
1044 * We're going to explicitly set the UUE bit to 0 before
1045 * trying to write and read a 1 just to make sure it's not
1046 * already a 1 and maybe locked there before we even start start.
1048 iersave = serial_in(up, UART_IER);
1049 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1050 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1052 * OK it's in a known zero state, try writing and reading
1053 * without disturbing the current state of the other bits.
1055 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1056 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1059 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1061 DEBUG_AUTOCONF("Xscale ");
1062 up->port.type = PORT_XSCALE;
1063 up->capabilities |= UART_CAP_UUE;
1068 * If we got here we couldn't force the IER_UUE bit to 0.
1069 * Log it and continue.
1071 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1073 serial_outp(up, UART_IER, iersave);
1076 * We distinguish between 16550A and U6 16550A by counting
1077 * how many bytes are in the FIFO.
1079 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1080 up->port.type = PORT_U6_16550A;
1081 up->capabilities |= UART_CAP_AFE;
1086 * This routine is called by rs_init() to initialize a specific serial
1087 * port. It determines what type of UART chip this serial port is
1088 * using: 8250, 16450, 16550, 16550A. The important question is
1089 * whether or not this UART is a 16550A or not, since this will
1090 * determine whether or not we can use its FIFO features or not.
1092 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1094 unsigned char status1, scratch, scratch2, scratch3;
1095 unsigned char save_lcr, save_mcr;
1096 unsigned long flags;
1098 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1101 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1102 serial_index(&up->port), up->port.iobase, up->port.membase);
1105 * We really do need global IRQs disabled here - we're going to
1106 * be frobbing the chips IRQ enable register to see if it exists.
1108 spin_lock_irqsave(&up->port.lock, flags);
1110 up->capabilities = 0;
1113 if (!(up->port.flags & UPF_BUGGY_UART)) {
1115 * Do a simple existence test first; if we fail this,
1116 * there's no point trying anything else.
1118 * 0x80 is used as a nonsense port to prevent against
1119 * false positives due to ISA bus float. The
1120 * assumption is that 0x80 is a non-existent port;
1121 * which should be safe since include/asm/io.h also
1122 * makes this assumption.
1124 * Note: this is safe as long as MCR bit 4 is clear
1125 * and the device is in "PC" mode.
1127 scratch = serial_inp(up, UART_IER);
1128 serial_outp(up, UART_IER, 0);
1133 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1134 * 16C754B) allow only to modify them if an EFR bit is set.
1136 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1137 serial_outp(up, UART_IER, 0x0F);
1141 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1142 serial_outp(up, UART_IER, scratch);
1143 if (scratch2 != 0 || scratch3 != 0x0F) {
1145 * We failed; there's nothing here
1147 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1148 scratch2, scratch3);
1153 save_mcr = serial_in(up, UART_MCR);
1154 save_lcr = serial_in(up, UART_LCR);
1157 * Check to see if a UART is really there. Certain broken
1158 * internal modems based on the Rockwell chipset fail this
1159 * test, because they apparently don't implement the loopback
1160 * test mode. So this test is skipped on the COM 1 through
1161 * COM 4 ports. This *should* be safe, since no board
1162 * manufacturer would be stupid enough to design a board
1163 * that conflicts with COM 1-4 --- we hope!
1165 if (!(up->port.flags & UPF_SKIP_TEST)) {
1166 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1167 status1 = serial_inp(up, UART_MSR) & 0xF0;
1168 serial_outp(up, UART_MCR, save_mcr);
1169 if (status1 != 0x90) {
1170 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1177 * We're pretty sure there's a port here. Lets find out what
1178 * type of port it is. The IIR top two bits allows us to find
1179 * out if it's 8250 or 16450, 16550, 16550A or later. This
1180 * determines what we test for next.
1182 * We also initialise the EFR (if any) to zero for later. The
1183 * EFR occupies the same register location as the FCR and IIR.
1185 serial_outp(up, UART_LCR, 0xBF);
1186 serial_outp(up, UART_EFR, 0);
1187 serial_outp(up, UART_LCR, 0);
1189 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1190 scratch = serial_in(up, UART_IIR) >> 6;
1192 DEBUG_AUTOCONF("iir=%d ", scratch);
1196 autoconfig_8250(up);
1199 up->port.type = PORT_UNKNOWN;
1202 up->port.type = PORT_16550;
1205 autoconfig_16550a(up);
1209 #ifdef CONFIG_SERIAL_8250_RSA
1211 * Only probe for RSA ports if we got the region.
1213 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1216 for (i = 0 ; i < probe_rsa_count; ++i) {
1217 if (probe_rsa[i] == up->port.iobase &&
1219 up->port.type = PORT_RSA;
1226 serial_outp(up, UART_LCR, save_lcr);
1228 if (up->capabilities != uart_config[up->port.type].flags) {
1230 "ttyS%d: detected caps %08x should be %08x\n",
1231 serial_index(&up->port), up->capabilities,
1232 uart_config[up->port.type].flags);
1235 up->port.fifosize = uart_config[up->port.type].fifo_size;
1236 up->capabilities = uart_config[up->port.type].flags;
1237 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1239 if (up->port.type == PORT_UNKNOWN)
1245 #ifdef CONFIG_SERIAL_8250_RSA
1246 if (up->port.type == PORT_RSA)
1247 serial_outp(up, UART_RSA_FRR, 0);
1249 serial_outp(up, UART_MCR, save_mcr);
1250 serial8250_clear_fifos(up);
1251 serial_in(up, UART_RX);
1252 if (up->capabilities & UART_CAP_UUE)
1253 serial_outp(up, UART_IER, UART_IER_UUE);
1255 serial_outp(up, UART_IER, 0);
1258 spin_unlock_irqrestore(&up->port.lock, flags);
1259 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1262 static void autoconfig_irq(struct uart_8250_port *up)
1264 unsigned char save_mcr, save_ier;
1265 unsigned char save_ICP = 0;
1266 unsigned int ICP = 0;
1270 if (up->port.flags & UPF_FOURPORT) {
1271 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1272 save_ICP = inb_p(ICP);
1277 /* forget possible initially masked and pending IRQ */
1278 probe_irq_off(probe_irq_on());
1279 save_mcr = serial_inp(up, UART_MCR);
1280 save_ier = serial_inp(up, UART_IER);
1281 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1283 irqs = probe_irq_on();
1284 serial_outp(up, UART_MCR, 0);
1286 if (up->port.flags & UPF_FOURPORT) {
1287 serial_outp(up, UART_MCR,
1288 UART_MCR_DTR | UART_MCR_RTS);
1290 serial_outp(up, UART_MCR,
1291 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1293 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1294 (void)serial_inp(up, UART_LSR);
1295 (void)serial_inp(up, UART_RX);
1296 (void)serial_inp(up, UART_IIR);
1297 (void)serial_inp(up, UART_MSR);
1298 serial_outp(up, UART_TX, 0xFF);
1300 irq = probe_irq_off(irqs);
1302 serial_outp(up, UART_MCR, save_mcr);
1303 serial_outp(up, UART_IER, save_ier);
1305 if (up->port.flags & UPF_FOURPORT)
1306 outb_p(save_ICP, ICP);
1308 up->port.irq = (irq > 0) ? irq : 0;
1311 static inline void __stop_tx(struct uart_8250_port *p)
1313 if (p->ier & UART_IER_THRI) {
1314 p->ier &= ~UART_IER_THRI;
1315 serial_out(p, UART_IER, p->ier);
1319 static void serial8250_stop_tx(struct uart_port *port)
1321 struct uart_8250_port *up = (struct uart_8250_port *)port;
1326 * We really want to stop the transmitter from sending.
1328 if (up->port.type == PORT_16C950) {
1329 up->acr |= UART_ACR_TXDIS;
1330 serial_icr_write(up, UART_ACR, up->acr);
1334 static void transmit_chars(struct uart_8250_port *up);
1336 static void serial8250_start_tx(struct uart_port *port)
1338 struct uart_8250_port *up = (struct uart_8250_port *)port;
1340 if (!(up->ier & UART_IER_THRI)) {
1341 up->ier |= UART_IER_THRI;
1342 serial_out(up, UART_IER, up->ier);
1344 if (up->bugs & UART_BUG_TXEN) {
1346 lsr = serial_in(up, UART_LSR);
1347 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1348 if ((up->port.type == PORT_RM9000) ?
1349 (lsr & UART_LSR_THRE) :
1350 (lsr & UART_LSR_TEMT))
1356 * Re-enable the transmitter if we disabled it.
1358 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1359 up->acr &= ~UART_ACR_TXDIS;
1360 serial_icr_write(up, UART_ACR, up->acr);
1364 static void serial8250_stop_rx(struct uart_port *port)
1366 struct uart_8250_port *up = (struct uart_8250_port *)port;
1368 up->ier &= ~UART_IER_RLSI;
1369 up->port.read_status_mask &= ~UART_LSR_DR;
1370 serial_out(up, UART_IER, up->ier);
1373 static void serial8250_enable_ms(struct uart_port *port)
1375 struct uart_8250_port *up = (struct uart_8250_port *)port;
1377 /* no MSR capabilities */
1378 if (up->bugs & UART_BUG_NOMSR)
1381 up->ier |= UART_IER_MSI;
1382 serial_out(up, UART_IER, up->ier);
1386 receive_chars(struct uart_8250_port *up, unsigned int *status)
1388 struct tty_struct *tty = up->port.state->port.tty;
1389 unsigned char ch, lsr = *status;
1390 int max_count = 256;
1394 if (likely(lsr & UART_LSR_DR))
1395 ch = serial_inp(up, UART_RX);
1398 * Intel 82571 has a Serial Over Lan device that will
1399 * set UART_LSR_BI without setting UART_LSR_DR when
1400 * it receives a break. To avoid reading from the
1401 * receive buffer without UART_LSR_DR bit set, we
1402 * just force the read character to be 0
1407 up->port.icount.rx++;
1409 lsr |= up->lsr_saved_flags;
1410 up->lsr_saved_flags = 0;
1412 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1414 * For statistics only
1416 if (lsr & UART_LSR_BI) {
1417 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1418 up->port.icount.brk++;
1420 * We do the SysRQ and SAK checking
1421 * here because otherwise the break
1422 * may get masked by ignore_status_mask
1423 * or read_status_mask.
1425 if (uart_handle_break(&up->port))
1427 } else if (lsr & UART_LSR_PE)
1428 up->port.icount.parity++;
1429 else if (lsr & UART_LSR_FE)
1430 up->port.icount.frame++;
1431 if (lsr & UART_LSR_OE)
1432 up->port.icount.overrun++;
1435 * Mask off conditions which should be ignored.
1437 lsr &= up->port.read_status_mask;
1439 if (lsr & UART_LSR_BI) {
1440 DEBUG_INTR("handling break....");
1442 } else if (lsr & UART_LSR_PE)
1444 else if (lsr & UART_LSR_FE)
1447 if (uart_handle_sysrq_char(&up->port, ch))
1450 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1453 lsr = serial_inp(up, UART_LSR);
1454 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1455 spin_unlock(&up->port.lock);
1456 tty_flip_buffer_push(tty);
1457 spin_lock(&up->port.lock);
1461 static void transmit_chars(struct uart_8250_port *up)
1463 struct circ_buf *xmit = &up->port.state->xmit;
1466 if (up->port.x_char) {
1467 serial_outp(up, UART_TX, up->port.x_char);
1468 up->port.icount.tx++;
1469 up->port.x_char = 0;
1472 if (uart_tx_stopped(&up->port)) {
1473 serial8250_stop_tx(&up->port);
1476 if (uart_circ_empty(xmit)) {
1481 count = up->tx_loadsz;
1483 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1484 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1485 up->port.icount.tx++;
1486 if (uart_circ_empty(xmit))
1488 } while (--count > 0);
1490 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1491 uart_write_wakeup(&up->port);
1493 DEBUG_INTR("THRE...");
1495 if (uart_circ_empty(xmit))
1499 static unsigned int check_modem_status(struct uart_8250_port *up)
1501 unsigned int status = serial_in(up, UART_MSR);
1503 status |= up->msr_saved_flags;
1504 up->msr_saved_flags = 0;
1505 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1506 up->port.state != NULL) {
1507 if (status & UART_MSR_TERI)
1508 up->port.icount.rng++;
1509 if (status & UART_MSR_DDSR)
1510 up->port.icount.dsr++;
1511 if (status & UART_MSR_DDCD)
1512 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1513 if (status & UART_MSR_DCTS)
1514 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1516 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1523 * This handles the interrupt from one port.
1525 static void serial8250_handle_port(struct uart_8250_port *up)
1527 unsigned int status;
1528 unsigned long flags;
1530 spin_lock_irqsave(&up->port.lock, flags);
1532 status = serial_inp(up, UART_LSR);
1534 DEBUG_INTR("status = %x...", status);
1536 if (status & (UART_LSR_DR | UART_LSR_BI))
1537 receive_chars(up, &status);
1538 check_modem_status(up);
1539 if (status & UART_LSR_THRE)
1542 spin_unlock_irqrestore(&up->port.lock, flags);
1546 * This is the serial driver's interrupt routine.
1548 * Arjan thinks the old way was overly complex, so it got simplified.
1549 * Alan disagrees, saying that need the complexity to handle the weird
1550 * nature of ISA shared interrupts. (This is a special exception.)
1552 * In order to handle ISA shared interrupts properly, we need to check
1553 * that all ports have been serviced, and therefore the ISA interrupt
1554 * line has been de-asserted.
1556 * This means we need to loop through all ports. checking that they
1557 * don't have an interrupt pending.
1559 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1561 struct irq_info *i = dev_id;
1562 struct list_head *l, *end = NULL;
1563 int pass_counter = 0, handled = 0;
1565 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1567 spin_lock(&i->lock);
1571 struct uart_8250_port *up;
1574 up = list_entry(l, struct uart_8250_port, list);
1576 iir = serial_in(up, UART_IIR);
1577 if (!(iir & UART_IIR_NO_INT)) {
1578 serial8250_handle_port(up);
1583 } else if (up->port.iotype == UPIO_DWAPB &&
1584 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1585 /* The DesignWare APB UART has an Busy Detect (0x07)
1586 * interrupt meaning an LCR write attempt occured while the
1587 * UART was busy. The interrupt must be cleared by reading
1588 * the UART status register (USR) and the LCR re-written. */
1589 unsigned int status;
1590 status = *(volatile u32 *)up->port.private_data;
1591 serial_out(up, UART_LCR, up->lcr);
1596 } else if (end == NULL)
1601 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1602 /* If we hit this, we're dead. */
1603 printk(KERN_ERR "serial8250: too much work for "
1609 spin_unlock(&i->lock);
1611 DEBUG_INTR("end.\n");
1613 return IRQ_RETVAL(handled);
1617 * To support ISA shared interrupts, we need to have one interrupt
1618 * handler that ensures that the IRQ line has been deasserted
1619 * before returning. Failing to do this will result in the IRQ
1620 * line being stuck active, and, since ISA irqs are edge triggered,
1621 * no more IRQs will be seen.
1623 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1625 spin_lock_irq(&i->lock);
1627 if (!list_empty(i->head)) {
1628 if (i->head == &up->list)
1629 i->head = i->head->next;
1630 list_del(&up->list);
1632 BUG_ON(i->head != &up->list);
1635 spin_unlock_irq(&i->lock);
1636 /* List empty so throw away the hash node */
1637 if (i->head == NULL) {
1638 hlist_del(&i->node);
1643 static int serial_link_irq_chain(struct uart_8250_port *up)
1645 struct hlist_head *h;
1646 struct hlist_node *n;
1648 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1650 mutex_lock(&hash_mutex);
1652 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1654 hlist_for_each(n, h) {
1655 i = hlist_entry(n, struct irq_info, node);
1656 if (i->irq == up->port.irq)
1661 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1663 mutex_unlock(&hash_mutex);
1666 spin_lock_init(&i->lock);
1667 i->irq = up->port.irq;
1668 hlist_add_head(&i->node, h);
1670 mutex_unlock(&hash_mutex);
1672 spin_lock_irq(&i->lock);
1675 list_add(&up->list, i->head);
1676 spin_unlock_irq(&i->lock);
1680 INIT_LIST_HEAD(&up->list);
1681 i->head = &up->list;
1682 spin_unlock_irq(&i->lock);
1683 irq_flags |= up->port.irqflags;
1684 ret = request_irq(up->port.irq, serial8250_interrupt,
1685 irq_flags, "serial", i);
1687 serial_do_unlink(i, up);
1693 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1696 struct hlist_node *n;
1697 struct hlist_head *h;
1699 mutex_lock(&hash_mutex);
1701 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1703 hlist_for_each(n, h) {
1704 i = hlist_entry(n, struct irq_info, node);
1705 if (i->irq == up->port.irq)
1710 BUG_ON(i->head == NULL);
1712 if (list_empty(i->head))
1713 free_irq(up->port.irq, i);
1715 serial_do_unlink(i, up);
1716 mutex_unlock(&hash_mutex);
1720 * This function is used to handle ports that do not have an
1721 * interrupt. This doesn't work very well for 16450's, but gives
1722 * barely passable results for a 16550A. (Although at the expense
1723 * of much CPU overhead).
1725 static void serial8250_timeout(unsigned long data)
1727 struct uart_8250_port *up = (struct uart_8250_port *)data;
1730 iir = serial_in(up, UART_IIR);
1731 if (!(iir & UART_IIR_NO_INT))
1732 serial8250_handle_port(up);
1733 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1736 static void serial8250_backup_timeout(unsigned long data)
1738 struct uart_8250_port *up = (struct uart_8250_port *)data;
1739 unsigned int iir, ier = 0, lsr;
1740 unsigned long flags;
1743 * Must disable interrupts or else we risk racing with the interrupt
1746 if (is_real_interrupt(up->port.irq)) {
1747 ier = serial_in(up, UART_IER);
1748 serial_out(up, UART_IER, 0);
1751 iir = serial_in(up, UART_IIR);
1754 * This should be a safe test for anyone who doesn't trust the
1755 * IIR bits on their UART, but it's specifically designed for
1756 * the "Diva" UART used on the management processor on many HP
1757 * ia64 and parisc boxes.
1759 spin_lock_irqsave(&up->port.lock, flags);
1760 lsr = serial_in(up, UART_LSR);
1761 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1762 spin_unlock_irqrestore(&up->port.lock, flags);
1763 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1764 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1765 (lsr & UART_LSR_THRE)) {
1766 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1767 iir |= UART_IIR_THRI;
1770 if (!(iir & UART_IIR_NO_INT))
1771 serial8250_handle_port(up);
1773 if (is_real_interrupt(up->port.irq))
1774 serial_out(up, UART_IER, ier);
1776 /* Standard timer interval plus 0.2s to keep the port running */
1777 mod_timer(&up->timer,
1778 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1781 static unsigned int serial8250_tx_empty(struct uart_port *port)
1783 struct uart_8250_port *up = (struct uart_8250_port *)port;
1784 unsigned long flags;
1787 spin_lock_irqsave(&up->port.lock, flags);
1788 lsr = serial_in(up, UART_LSR);
1789 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1790 spin_unlock_irqrestore(&up->port.lock, flags);
1792 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1795 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1797 struct uart_8250_port *up = (struct uart_8250_port *)port;
1798 unsigned int status;
1801 status = check_modem_status(up);
1804 if (status & UART_MSR_DCD)
1806 if (status & UART_MSR_RI)
1808 if (status & UART_MSR_DSR)
1810 if (status & UART_MSR_CTS)
1815 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1817 struct uart_8250_port *up = (struct uart_8250_port *)port;
1818 unsigned char mcr = 0;
1820 if (mctrl & TIOCM_RTS)
1821 mcr |= UART_MCR_RTS;
1822 if (mctrl & TIOCM_DTR)
1823 mcr |= UART_MCR_DTR;
1824 if (mctrl & TIOCM_OUT1)
1825 mcr |= UART_MCR_OUT1;
1826 if (mctrl & TIOCM_OUT2)
1827 mcr |= UART_MCR_OUT2;
1828 if (mctrl & TIOCM_LOOP)
1829 mcr |= UART_MCR_LOOP;
1831 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1833 serial_out(up, UART_MCR, mcr);
1836 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1838 struct uart_8250_port *up = (struct uart_8250_port *)port;
1839 unsigned long flags;
1841 spin_lock_irqsave(&up->port.lock, flags);
1842 if (break_state == -1)
1843 up->lcr |= UART_LCR_SBC;
1845 up->lcr &= ~UART_LCR_SBC;
1846 serial_out(up, UART_LCR, up->lcr);
1847 spin_unlock_irqrestore(&up->port.lock, flags);
1851 * Wait for transmitter & holding register to empty
1853 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1855 unsigned int status, tmout = 10000;
1857 /* Wait up to 10ms for the character(s) to be sent. */
1859 status = serial_in(up, UART_LSR);
1861 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1863 if ((status & bits) == bits)
1870 /* Wait up to 1s for flow control if necessary */
1871 if (up->port.flags & UPF_CONS_FLOW) {
1873 for (tmout = 1000000; tmout; tmout--) {
1874 unsigned int msr = serial_in(up, UART_MSR);
1875 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1876 if (msr & UART_MSR_CTS)
1879 touch_nmi_watchdog();
1884 #ifdef CONFIG_CONSOLE_POLL
1886 * Console polling routines for writing and reading from the uart while
1887 * in an interrupt or debug context.
1890 static int serial8250_get_poll_char(struct uart_port *port)
1892 struct uart_8250_port *up = (struct uart_8250_port *)port;
1893 unsigned char lsr = serial_inp(up, UART_LSR);
1895 if (!(lsr & UART_LSR_DR))
1896 return NO_POLL_CHAR;
1898 return serial_inp(up, UART_RX);
1902 static void serial8250_put_poll_char(struct uart_port *port,
1906 struct uart_8250_port *up = (struct uart_8250_port *)port;
1909 * First save the IER then disable the interrupts
1911 ier = serial_in(up, UART_IER);
1912 if (up->capabilities & UART_CAP_UUE)
1913 serial_out(up, UART_IER, UART_IER_UUE);
1915 serial_out(up, UART_IER, 0);
1917 wait_for_xmitr(up, BOTH_EMPTY);
1919 * Send the character out.
1920 * If a LF, also do CR...
1922 serial_out(up, UART_TX, c);
1924 wait_for_xmitr(up, BOTH_EMPTY);
1925 serial_out(up, UART_TX, 13);
1929 * Finally, wait for transmitter to become empty
1930 * and restore the IER
1932 wait_for_xmitr(up, BOTH_EMPTY);
1933 serial_out(up, UART_IER, ier);
1936 #endif /* CONFIG_CONSOLE_POLL */
1938 static int serial8250_startup(struct uart_port *port)
1940 struct uart_8250_port *up = (struct uart_8250_port *)port;
1941 unsigned long flags;
1942 unsigned char lsr, iir;
1945 up->capabilities = uart_config[up->port.type].flags;
1948 if (up->port.iotype != up->cur_iotype)
1949 set_io_from_upio(port);
1951 if (up->port.type == PORT_16C950) {
1952 /* Wake up and initialize UART */
1954 serial_outp(up, UART_LCR, 0xBF);
1955 serial_outp(up, UART_EFR, UART_EFR_ECB);
1956 serial_outp(up, UART_IER, 0);
1957 serial_outp(up, UART_LCR, 0);
1958 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1959 serial_outp(up, UART_LCR, 0xBF);
1960 serial_outp(up, UART_EFR, UART_EFR_ECB);
1961 serial_outp(up, UART_LCR, 0);
1964 #ifdef CONFIG_SERIAL_8250_RSA
1966 * If this is an RSA port, see if we can kick it up to the
1967 * higher speed clock.
1973 * Clear the FIFO buffers and disable them.
1974 * (they will be reenabled in set_termios())
1976 serial8250_clear_fifos(up);
1979 * Clear the interrupt registers.
1981 (void) serial_inp(up, UART_LSR);
1982 (void) serial_inp(up, UART_RX);
1983 (void) serial_inp(up, UART_IIR);
1984 (void) serial_inp(up, UART_MSR);
1987 * At this point, there's no way the LSR could still be 0xff;
1988 * if it is, then bail out, because there's likely no UART
1991 if (!(up->port.flags & UPF_BUGGY_UART) &&
1992 (serial_inp(up, UART_LSR) == 0xff)) {
1993 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1994 serial_index(&up->port));
1999 * For a XR16C850, we need to set the trigger levels
2001 if (up->port.type == PORT_16850) {
2004 serial_outp(up, UART_LCR, 0xbf);
2006 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2007 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2008 serial_outp(up, UART_TRG, UART_TRG_96);
2009 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2010 serial_outp(up, UART_TRG, UART_TRG_96);
2012 serial_outp(up, UART_LCR, 0);
2015 if (is_real_interrupt(up->port.irq)) {
2018 * Test for UARTs that do not reassert THRE when the
2019 * transmitter is idle and the interrupt has already
2020 * been cleared. Real 16550s should always reassert
2021 * this interrupt whenever the transmitter is idle and
2022 * the interrupt is enabled. Delays are necessary to
2023 * allow register changes to become visible.
2025 spin_lock_irqsave(&up->port.lock, flags);
2026 if (up->port.irqflags & IRQF_SHARED)
2027 disable_irq_nosync(up->port.irq);
2029 wait_for_xmitr(up, UART_LSR_THRE);
2030 serial_out_sync(up, UART_IER, UART_IER_THRI);
2031 udelay(1); /* allow THRE to set */
2032 iir1 = serial_in(up, UART_IIR);
2033 serial_out(up, UART_IER, 0);
2034 serial_out_sync(up, UART_IER, UART_IER_THRI);
2035 udelay(1); /* allow a working UART time to re-assert THRE */
2036 iir = serial_in(up, UART_IIR);
2037 serial_out(up, UART_IER, 0);
2039 if (up->port.irqflags & IRQF_SHARED)
2040 enable_irq(up->port.irq);
2041 spin_unlock_irqrestore(&up->port.lock, flags);
2044 * If the interrupt is not reasserted, setup a timer to
2045 * kick the UART on a regular basis.
2047 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2048 up->bugs |= UART_BUG_THRE;
2049 pr_debug("ttyS%d - using backup timer\n",
2050 serial_index(port));
2055 * The above check will only give an accurate result the first time
2056 * the port is opened so this value needs to be preserved.
2058 if (up->bugs & UART_BUG_THRE) {
2059 up->timer.function = serial8250_backup_timeout;
2060 up->timer.data = (unsigned long)up;
2061 mod_timer(&up->timer, jiffies +
2062 uart_poll_timeout(port) + HZ / 5);
2066 * If the "interrupt" for this port doesn't correspond with any
2067 * hardware interrupt, we use a timer-based system. The original
2068 * driver used to do this with IRQ0.
2070 if (!is_real_interrupt(up->port.irq)) {
2071 up->timer.data = (unsigned long)up;
2072 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2074 retval = serial_link_irq_chain(up);
2080 * Now, initialize the UART
2082 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2084 spin_lock_irqsave(&up->port.lock, flags);
2085 if (up->port.flags & UPF_FOURPORT) {
2086 if (!is_real_interrupt(up->port.irq))
2087 up->port.mctrl |= TIOCM_OUT1;
2090 * Most PC uarts need OUT2 raised to enable interrupts.
2092 if (is_real_interrupt(up->port.irq))
2093 up->port.mctrl |= TIOCM_OUT2;
2095 serial8250_set_mctrl(&up->port, up->port.mctrl);
2097 /* Serial over Lan (SoL) hack:
2098 Intel 8257x Gigabit ethernet chips have a
2099 16550 emulation, to be used for Serial Over Lan.
2100 Those chips take a longer time than a normal
2101 serial device to signalize that a transmission
2102 data was queued. Due to that, the above test generally
2103 fails. One solution would be to delay the reading of
2104 iir. However, this is not reliable, since the timeout
2105 is variable. So, let's just don't test if we receive
2106 TX irq. This way, we'll never enable UART_BUG_TXEN.
2108 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2109 goto dont_test_tx_en;
2112 * Do a quick test to see if we receive an
2113 * interrupt when we enable the TX irq.
2115 serial_outp(up, UART_IER, UART_IER_THRI);
2116 lsr = serial_in(up, UART_LSR);
2117 iir = serial_in(up, UART_IIR);
2118 serial_outp(up, UART_IER, 0);
2120 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2121 if (!(up->bugs & UART_BUG_TXEN)) {
2122 up->bugs |= UART_BUG_TXEN;
2123 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2124 serial_index(port));
2127 up->bugs &= ~UART_BUG_TXEN;
2131 spin_unlock_irqrestore(&up->port.lock, flags);
2134 * Clear the interrupt registers again for luck, and clear the
2135 * saved flags to avoid getting false values from polling
2136 * routines or the previous session.
2138 serial_inp(up, UART_LSR);
2139 serial_inp(up, UART_RX);
2140 serial_inp(up, UART_IIR);
2141 serial_inp(up, UART_MSR);
2142 up->lsr_saved_flags = 0;
2143 up->msr_saved_flags = 0;
2146 * Finally, enable interrupts. Note: Modem status interrupts
2147 * are set via set_termios(), which will be occurring imminently
2148 * anyway, so we don't enable them here.
2150 up->ier = UART_IER_RLSI | UART_IER_RDI;
2151 serial_outp(up, UART_IER, up->ier);
2153 if (up->port.flags & UPF_FOURPORT) {
2156 * Enable interrupts on the AST Fourport board
2158 icp = (up->port.iobase & 0xfe0) | 0x01f;
2166 static void serial8250_shutdown(struct uart_port *port)
2168 struct uart_8250_port *up = (struct uart_8250_port *)port;
2169 unsigned long flags;
2172 * Disable interrupts from this port
2175 serial_outp(up, UART_IER, 0);
2177 spin_lock_irqsave(&up->port.lock, flags);
2178 if (up->port.flags & UPF_FOURPORT) {
2179 /* reset interrupts on the AST Fourport board */
2180 inb((up->port.iobase & 0xfe0) | 0x1f);
2181 up->port.mctrl |= TIOCM_OUT1;
2183 up->port.mctrl &= ~TIOCM_OUT2;
2185 serial8250_set_mctrl(&up->port, up->port.mctrl);
2186 spin_unlock_irqrestore(&up->port.lock, flags);
2189 * Disable break condition and FIFOs
2191 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2192 serial8250_clear_fifos(up);
2194 #ifdef CONFIG_SERIAL_8250_RSA
2196 * Reset the RSA board back to 115kbps compat mode.
2202 * Read data port to reset things, and then unlink from
2205 (void) serial_in(up, UART_RX);
2207 del_timer_sync(&up->timer);
2208 up->timer.function = serial8250_timeout;
2209 if (is_real_interrupt(up->port.irq))
2210 serial_unlink_irq_chain(up);
2213 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2218 * Handle magic divisors for baud rates above baud_base on
2219 * SMSC SuperIO chips.
2221 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2222 baud == (port->uartclk/4))
2224 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2225 baud == (port->uartclk/8))
2228 quot = uart_get_divisor(port, baud);
2234 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2235 struct ktermios *old)
2237 struct uart_8250_port *up = (struct uart_8250_port *)port;
2238 unsigned char cval, fcr = 0;
2239 unsigned long flags;
2240 unsigned int baud, quot;
2242 switch (termios->c_cflag & CSIZE) {
2244 cval = UART_LCR_WLEN5;
2247 cval = UART_LCR_WLEN6;
2250 cval = UART_LCR_WLEN7;
2254 cval = UART_LCR_WLEN8;
2258 if (termios->c_cflag & CSTOPB)
2259 cval |= UART_LCR_STOP;
2260 if (termios->c_cflag & PARENB)
2261 cval |= UART_LCR_PARITY;
2262 if (!(termios->c_cflag & PARODD))
2263 cval |= UART_LCR_EPAR;
2265 if (termios->c_cflag & CMSPAR)
2266 cval |= UART_LCR_SPAR;
2270 * Ask the core to calculate the divisor for us.
2272 baud = uart_get_baud_rate(port, termios, old,
2273 port->uartclk / 16 / 0xffff,
2274 port->uartclk / 16);
2275 quot = serial8250_get_divisor(port, baud);
2278 * Oxford Semi 952 rev B workaround
2280 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2283 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2285 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2287 fcr = uart_config[up->port.type].fcr;
2291 * MCR-based auto flow control. When AFE is enabled, RTS will be
2292 * deasserted when the receive FIFO contains more characters than
2293 * the trigger, or the MCR RTS bit is cleared. In the case where
2294 * the remote UART is not using CTS auto flow control, we must
2295 * have sufficient FIFO entries for the latency of the remote
2296 * UART to respond. IOW, at least 32 bytes of FIFO.
2298 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2299 up->mcr &= ~UART_MCR_AFE;
2300 if (termios->c_cflag & CRTSCTS)
2301 up->mcr |= UART_MCR_AFE;
2305 * Ok, we're now changing the port state. Do it with
2306 * interrupts disabled.
2308 spin_lock_irqsave(&up->port.lock, flags);
2311 * Update the per-port timeout.
2313 uart_update_timeout(port, termios->c_cflag, baud);
2315 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2316 if (termios->c_iflag & INPCK)
2317 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2318 if (termios->c_iflag & (BRKINT | PARMRK))
2319 up->port.read_status_mask |= UART_LSR_BI;
2322 * Characteres to ignore
2324 up->port.ignore_status_mask = 0;
2325 if (termios->c_iflag & IGNPAR)
2326 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2327 if (termios->c_iflag & IGNBRK) {
2328 up->port.ignore_status_mask |= UART_LSR_BI;
2330 * If we're ignoring parity and break indicators,
2331 * ignore overruns too (for real raw support).
2333 if (termios->c_iflag & IGNPAR)
2334 up->port.ignore_status_mask |= UART_LSR_OE;
2338 * ignore all characters if CREAD is not set
2340 if ((termios->c_cflag & CREAD) == 0)
2341 up->port.ignore_status_mask |= UART_LSR_DR;
2344 * CTS flow control flag and modem status interrupts
2346 up->ier &= ~UART_IER_MSI;
2347 if (!(up->bugs & UART_BUG_NOMSR) &&
2348 UART_ENABLE_MS(&up->port, termios->c_cflag))
2349 up->ier |= UART_IER_MSI;
2350 if (up->capabilities & UART_CAP_UUE)
2351 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2353 serial_out(up, UART_IER, up->ier);
2355 if (up->capabilities & UART_CAP_EFR) {
2356 unsigned char efr = 0;
2358 * TI16C752/Startech hardware flow control. FIXME:
2359 * - TI16C752 requires control thresholds to be set.
2360 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2362 if (termios->c_cflag & CRTSCTS)
2363 efr |= UART_EFR_CTS;
2365 serial_outp(up, UART_LCR, 0xBF);
2366 serial_outp(up, UART_EFR, efr);
2369 #ifdef CONFIG_ARCH_OMAP
2370 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2371 if (cpu_is_omap1510() && is_omap_port(up)) {
2372 if (baud == 115200) {
2374 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2376 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2380 if (up->capabilities & UART_NATSEMI) {
2381 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2382 serial_outp(up, UART_LCR, 0xe0);
2384 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2387 serial_dl_write(up, quot);
2390 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2391 * is written without DLAB set, this mode will be disabled.
2393 if (up->port.type == PORT_16750)
2394 serial_outp(up, UART_FCR, fcr);
2396 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2397 up->lcr = cval; /* Save LCR */
2398 if (up->port.type != PORT_16750) {
2399 if (fcr & UART_FCR_ENABLE_FIFO) {
2400 /* emulated UARTs (Lucent Venus 167x) need two steps */
2401 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2403 serial_outp(up, UART_FCR, fcr); /* set fcr */
2405 serial8250_set_mctrl(&up->port, up->port.mctrl);
2406 spin_unlock_irqrestore(&up->port.lock, flags);
2407 /* Don't rewrite B0 */
2408 if (tty_termios_baud_rate(termios))
2409 tty_termios_encode_baud_rate(termios, baud, baud);
2411 EXPORT_SYMBOL(serial8250_do_set_termios);
2414 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2415 struct ktermios *old)
2417 if (port->set_termios)
2418 port->set_termios(port, termios, old);
2420 serial8250_do_set_termios(port, termios, old);
2424 serial8250_set_ldisc(struct uart_port *port, int new)
2427 port->flags |= UPF_HARDPPS_CD;
2428 serial8250_enable_ms(port);
2430 port->flags &= ~UPF_HARDPPS_CD;
2434 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2435 unsigned int oldstate)
2437 struct uart_8250_port *p = (struct uart_8250_port *)port;
2439 serial8250_set_sleep(p, state != 0);
2441 EXPORT_SYMBOL(serial8250_do_pm);
2444 serial8250_pm(struct uart_port *port, unsigned int state,
2445 unsigned int oldstate)
2448 port->pm(port, state, oldstate);
2450 serial8250_do_pm(port, state, oldstate);
2453 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2455 if (pt->port.iotype == UPIO_AU)
2457 #ifdef CONFIG_ARCH_OMAP
2458 if (is_omap_port(pt))
2459 return 0x16 << pt->port.regshift;
2461 return 8 << pt->port.regshift;
2465 * Resource handling.
2467 static int serial8250_request_std_resource(struct uart_8250_port *up)
2469 unsigned int size = serial8250_port_size(up);
2472 switch (up->port.iotype) {
2478 if (!up->port.mapbase)
2481 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2486 if (up->port.flags & UPF_IOREMAP) {
2487 up->port.membase = ioremap_nocache(up->port.mapbase,
2489 if (!up->port.membase) {
2490 release_mem_region(up->port.mapbase, size);
2498 if (!request_region(up->port.iobase, size, "serial"))
2505 static void serial8250_release_std_resource(struct uart_8250_port *up)
2507 unsigned int size = serial8250_port_size(up);
2509 switch (up->port.iotype) {
2515 if (!up->port.mapbase)
2518 if (up->port.flags & UPF_IOREMAP) {
2519 iounmap(up->port.membase);
2520 up->port.membase = NULL;
2523 release_mem_region(up->port.mapbase, size);
2528 release_region(up->port.iobase, size);
2533 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2535 unsigned long start = UART_RSA_BASE << up->port.regshift;
2536 unsigned int size = 8 << up->port.regshift;
2539 switch (up->port.iotype) {
2542 start += up->port.iobase;
2543 if (request_region(start, size, "serial-rsa"))
2553 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2555 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2556 unsigned int size = 8 << up->port.regshift;
2558 switch (up->port.iotype) {
2561 release_region(up->port.iobase + offset, size);
2566 static void serial8250_release_port(struct uart_port *port)
2568 struct uart_8250_port *up = (struct uart_8250_port *)port;
2570 serial8250_release_std_resource(up);
2571 if (up->port.type == PORT_RSA)
2572 serial8250_release_rsa_resource(up);
2575 static int serial8250_request_port(struct uart_port *port)
2577 struct uart_8250_port *up = (struct uart_8250_port *)port;
2580 ret = serial8250_request_std_resource(up);
2581 if (ret == 0 && up->port.type == PORT_RSA) {
2582 ret = serial8250_request_rsa_resource(up);
2584 serial8250_release_std_resource(up);
2590 static void serial8250_config_port(struct uart_port *port, int flags)
2592 struct uart_8250_port *up = (struct uart_8250_port *)port;
2593 int probeflags = PROBE_ANY;
2597 * Find the region that we can probe for. This in turn
2598 * tells us whether we can probe for the type of port.
2600 ret = serial8250_request_std_resource(up);
2604 ret = serial8250_request_rsa_resource(up);
2606 probeflags &= ~PROBE_RSA;
2608 if (up->port.iotype != up->cur_iotype)
2609 set_io_from_upio(port);
2611 if (flags & UART_CONFIG_TYPE)
2612 autoconfig(up, probeflags);
2614 /* if access method is AU, it is a 16550 with a quirk */
2615 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2616 up->bugs |= UART_BUG_NOMSR;
2618 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2621 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2622 serial8250_release_rsa_resource(up);
2623 if (up->port.type == PORT_UNKNOWN)
2624 serial8250_release_std_resource(up);
2628 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2630 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2631 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2632 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2633 ser->type == PORT_STARTECH)
2639 serial8250_type(struct uart_port *port)
2641 int type = port->type;
2643 if (type >= ARRAY_SIZE(uart_config))
2645 return uart_config[type].name;
2648 static struct uart_ops serial8250_pops = {
2649 .tx_empty = serial8250_tx_empty,
2650 .set_mctrl = serial8250_set_mctrl,
2651 .get_mctrl = serial8250_get_mctrl,
2652 .stop_tx = serial8250_stop_tx,
2653 .start_tx = serial8250_start_tx,
2654 .stop_rx = serial8250_stop_rx,
2655 .enable_ms = serial8250_enable_ms,
2656 .break_ctl = serial8250_break_ctl,
2657 .startup = serial8250_startup,
2658 .shutdown = serial8250_shutdown,
2659 .set_termios = serial8250_set_termios,
2660 .set_ldisc = serial8250_set_ldisc,
2661 .pm = serial8250_pm,
2662 .type = serial8250_type,
2663 .release_port = serial8250_release_port,
2664 .request_port = serial8250_request_port,
2665 .config_port = serial8250_config_port,
2666 .verify_port = serial8250_verify_port,
2667 #ifdef CONFIG_CONSOLE_POLL
2668 .poll_get_char = serial8250_get_poll_char,
2669 .poll_put_char = serial8250_put_poll_char,
2673 static struct uart_8250_port serial8250_ports[UART_NR];
2675 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2676 unsigned short *capabilities);
2678 void serial8250_set_isa_configurator(
2679 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2681 serial8250_isa_config = v;
2683 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2685 static void __init serial8250_isa_init_ports(void)
2687 struct uart_8250_port *up;
2688 static int first = 1;
2695 for (i = 0; i < nr_uarts; i++) {
2696 struct uart_8250_port *up = &serial8250_ports[i];
2699 spin_lock_init(&up->port.lock);
2701 init_timer(&up->timer);
2702 up->timer.function = serial8250_timeout;
2705 * ALPHA_KLUDGE_MCR needs to be killed.
2707 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2708 up->mcr_force = ALPHA_KLUDGE_MCR;
2710 up->port.ops = &serial8250_pops;
2714 irqflag = IRQF_SHARED;
2716 for (i = 0, up = serial8250_ports;
2717 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2719 up->port.iobase = old_serial_port[i].port;
2720 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2721 up->port.irqflags = old_serial_port[i].irqflags;
2722 up->port.uartclk = old_serial_port[i].baud_base * 16;
2723 up->port.flags = old_serial_port[i].flags;
2724 up->port.hub6 = old_serial_port[i].hub6;
2725 up->port.membase = old_serial_port[i].iomem_base;
2726 up->port.iotype = old_serial_port[i].io_type;
2727 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2728 set_io_from_upio(&up->port);
2729 up->port.irqflags |= irqflag;
2730 if (serial8250_isa_config != NULL)
2731 serial8250_isa_config(i, &up->port, &up->capabilities);
2737 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2739 up->port.type = type;
2740 up->port.fifosize = uart_config[type].fifo_size;
2741 up->capabilities = uart_config[type].flags;
2742 up->tx_loadsz = uart_config[type].tx_loadsz;
2746 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2750 for (i = 0; i < nr_uarts; i++) {
2751 struct uart_8250_port *up = &serial8250_ports[i];
2752 up->cur_iotype = 0xFF;
2755 serial8250_isa_init_ports();
2757 for (i = 0; i < nr_uarts; i++) {
2758 struct uart_8250_port *up = &serial8250_ports[i];
2762 if (up->port.flags & UPF_FIXED_TYPE)
2763 serial8250_init_fixed_type_port(up, up->port.type);
2765 uart_add_one_port(drv, &up->port);
2769 #ifdef CONFIG_SERIAL_8250_CONSOLE
2771 static void serial8250_console_putchar(struct uart_port *port, int ch)
2773 struct uart_8250_port *up = (struct uart_8250_port *)port;
2775 wait_for_xmitr(up, UART_LSR_THRE);
2776 serial_out(up, UART_TX, ch);
2780 * Print a string to the serial port trying not to disturb
2781 * any possible real use of the port...
2783 * The console_lock must be held when we get here.
2786 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2788 struct uart_8250_port *up = &serial8250_ports[co->index];
2789 unsigned long flags;
2793 touch_nmi_watchdog();
2795 local_irq_save(flags);
2796 if (up->port.sysrq) {
2797 /* serial8250_handle_port() already took the lock */
2799 } else if (oops_in_progress) {
2800 locked = spin_trylock(&up->port.lock);
2802 spin_lock(&up->port.lock);
2805 * First save the IER then disable the interrupts
2807 ier = serial_in(up, UART_IER);
2809 if (up->capabilities & UART_CAP_UUE)
2810 serial_out(up, UART_IER, UART_IER_UUE);
2812 serial_out(up, UART_IER, 0);
2814 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2817 * Finally, wait for transmitter to become empty
2818 * and restore the IER
2820 wait_for_xmitr(up, BOTH_EMPTY);
2821 serial_out(up, UART_IER, ier);
2824 * The receive handling will happen properly because the
2825 * receive ready bit will still be set; it is not cleared
2826 * on read. However, modem control will not, we must
2827 * call it if we have saved something in the saved flags
2828 * while processing with interrupts off.
2830 if (up->msr_saved_flags)
2831 check_modem_status(up);
2834 spin_unlock(&up->port.lock);
2835 local_irq_restore(flags);
2838 static int __init serial8250_console_setup(struct console *co, char *options)
2840 struct uart_port *port;
2847 * Check whether an invalid uart number has been specified, and
2848 * if so, search for the first available port that does have
2851 if (co->index >= nr_uarts)
2853 port = &serial8250_ports[co->index].port;
2854 if (!port->iobase && !port->membase)
2858 uart_parse_options(options, &baud, &parity, &bits, &flow);
2860 return uart_set_options(port, co, baud, parity, bits, flow);
2863 static int serial8250_console_early_setup(void)
2865 return serial8250_find_port_for_earlycon();
2868 static struct console serial8250_console = {
2870 .write = serial8250_console_write,
2871 .device = uart_console_device,
2872 .setup = serial8250_console_setup,
2873 .early_setup = serial8250_console_early_setup,
2874 .flags = CON_PRINTBUFFER,
2876 .data = &serial8250_reg,
2879 static int __init serial8250_console_init(void)
2881 if (nr_uarts > UART_NR)
2884 serial8250_isa_init_ports();
2885 register_console(&serial8250_console);
2888 console_initcall(serial8250_console_init);
2890 int serial8250_find_port(struct uart_port *p)
2893 struct uart_port *port;
2895 for (line = 0; line < nr_uarts; line++) {
2896 port = &serial8250_ports[line].port;
2897 if (uart_match_port(p, port))
2903 #define SERIAL8250_CONSOLE &serial8250_console
2905 #define SERIAL8250_CONSOLE NULL
2908 static struct uart_driver serial8250_reg = {
2909 .owner = THIS_MODULE,
2910 .driver_name = "serial",
2914 .cons = SERIAL8250_CONSOLE,
2918 * early_serial_setup - early registration for 8250 ports
2920 * Setup an 8250 port structure prior to console initialisation. Use
2921 * after console initialisation will cause undefined behaviour.
2923 int __init early_serial_setup(struct uart_port *port)
2925 struct uart_port *p;
2927 if (port->line >= ARRAY_SIZE(serial8250_ports))
2930 serial8250_isa_init_ports();
2931 p = &serial8250_ports[port->line].port;
2932 p->iobase = port->iobase;
2933 p->membase = port->membase;
2935 p->irqflags = port->irqflags;
2936 p->uartclk = port->uartclk;
2937 p->fifosize = port->fifosize;
2938 p->regshift = port->regshift;
2939 p->iotype = port->iotype;
2940 p->flags = port->flags;
2941 p->mapbase = port->mapbase;
2942 p->private_data = port->private_data;
2943 p->type = port->type;
2944 p->line = port->line;
2946 set_io_from_upio(p);
2947 if (port->serial_in)
2948 p->serial_in = port->serial_in;
2949 if (port->serial_out)
2950 p->serial_out = port->serial_out;
2956 * serial8250_suspend_port - suspend one serial port
2957 * @line: serial line number
2959 * Suspend one serial port.
2961 void serial8250_suspend_port(int line)
2963 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2967 * serial8250_resume_port - resume one serial port
2968 * @line: serial line number
2970 * Resume one serial port.
2972 void serial8250_resume_port(int line)
2974 struct uart_8250_port *up = &serial8250_ports[line];
2976 if (up->capabilities & UART_NATSEMI) {
2979 /* Ensure it's still in high speed mode */
2980 serial_outp(up, UART_LCR, 0xE0);
2982 tmp = serial_in(up, 0x04); /* EXCR2 */
2983 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2984 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2985 serial_outp(up, 0x04, tmp);
2987 serial_outp(up, UART_LCR, 0);
2989 uart_resume_port(&serial8250_reg, &up->port);
2993 * Register a set of serial devices attached to a platform device. The
2994 * list is terminated with a zero flags entry, which means we expect
2995 * all entries to have at least UPF_BOOT_AUTOCONF set.
2997 static int __devinit serial8250_probe(struct platform_device *dev)
2999 struct plat_serial8250_port *p = dev->dev.platform_data;
3000 struct uart_port port;
3001 int ret, i, irqflag = 0;
3003 memset(&port, 0, sizeof(struct uart_port));
3006 irqflag = IRQF_SHARED;
3008 for (i = 0; p && p->flags != 0; p++, i++) {
3009 port.iobase = p->iobase;
3010 port.membase = p->membase;
3012 port.irqflags = p->irqflags;
3013 port.uartclk = p->uartclk;
3014 port.regshift = p->regshift;
3015 port.iotype = p->iotype;
3016 port.flags = p->flags;
3017 port.mapbase = p->mapbase;
3018 port.hub6 = p->hub6;
3019 port.private_data = p->private_data;
3020 port.type = p->type;
3021 port.serial_in = p->serial_in;
3022 port.serial_out = p->serial_out;
3023 port.set_termios = p->set_termios;
3025 port.dev = &dev->dev;
3026 port.irqflags |= irqflag;
3027 ret = serial8250_register_port(&port);
3029 dev_err(&dev->dev, "unable to register port at index %d "
3030 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3031 p->iobase, (unsigned long long)p->mapbase,
3039 * Remove serial ports registered against a platform device.
3041 static int __devexit serial8250_remove(struct platform_device *dev)
3045 for (i = 0; i < nr_uarts; i++) {
3046 struct uart_8250_port *up = &serial8250_ports[i];
3048 if (up->port.dev == &dev->dev)
3049 serial8250_unregister_port(i);
3054 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3058 for (i = 0; i < UART_NR; i++) {
3059 struct uart_8250_port *up = &serial8250_ports[i];
3061 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3062 uart_suspend_port(&serial8250_reg, &up->port);
3068 static int serial8250_resume(struct platform_device *dev)
3072 for (i = 0; i < UART_NR; i++) {
3073 struct uart_8250_port *up = &serial8250_ports[i];
3075 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3076 serial8250_resume_port(i);
3082 static struct platform_driver serial8250_isa_driver = {
3083 .probe = serial8250_probe,
3084 .remove = __devexit_p(serial8250_remove),
3085 .suspend = serial8250_suspend,
3086 .resume = serial8250_resume,
3088 .name = "serial8250",
3089 .owner = THIS_MODULE,
3094 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3095 * in the table in include/asm/serial.h
3097 static struct platform_device *serial8250_isa_devs;
3100 * serial8250_register_port and serial8250_unregister_port allows for
3101 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3102 * modems and PCI multiport cards.
3104 static DEFINE_MUTEX(serial_mutex);
3106 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3111 * First, find a port entry which matches.
3113 for (i = 0; i < nr_uarts; i++)
3114 if (uart_match_port(&serial8250_ports[i].port, port))
3115 return &serial8250_ports[i];
3118 * We didn't find a matching entry, so look for the first
3119 * free entry. We look for one which hasn't been previously
3120 * used (indicated by zero iobase).
3122 for (i = 0; i < nr_uarts; i++)
3123 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3124 serial8250_ports[i].port.iobase == 0)
3125 return &serial8250_ports[i];
3128 * That also failed. Last resort is to find any entry which
3129 * doesn't have a real port associated with it.
3131 for (i = 0; i < nr_uarts; i++)
3132 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3133 return &serial8250_ports[i];
3139 * serial8250_register_port - register a serial port
3140 * @port: serial port template
3142 * Configure the serial port specified by the request. If the
3143 * port exists and is in use, it is hung up and unregistered
3146 * The port is then probed and if necessary the IRQ is autodetected
3147 * If this fails an error is returned.
3149 * On success the port is ready to use and the line number is returned.
3151 int serial8250_register_port(struct uart_port *port)
3153 struct uart_8250_port *uart;
3156 if (port->uartclk == 0)
3159 mutex_lock(&serial_mutex);
3161 uart = serial8250_find_match_or_unused(port);
3163 uart_remove_one_port(&serial8250_reg, &uart->port);
3165 uart->port.iobase = port->iobase;
3166 uart->port.membase = port->membase;
3167 uart->port.irq = port->irq;
3168 uart->port.irqflags = port->irqflags;
3169 uart->port.uartclk = port->uartclk;
3170 uart->port.fifosize = port->fifosize;
3171 uart->port.regshift = port->regshift;
3172 uart->port.iotype = port->iotype;
3173 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3174 uart->port.mapbase = port->mapbase;
3175 uart->port.private_data = port->private_data;
3177 uart->port.dev = port->dev;
3179 if (port->flags & UPF_FIXED_TYPE)
3180 serial8250_init_fixed_type_port(uart, port->type);
3182 set_io_from_upio(&uart->port);
3183 /* Possibly override default I/O functions. */
3184 if (port->serial_in)
3185 uart->port.serial_in = port->serial_in;
3186 if (port->serial_out)
3187 uart->port.serial_out = port->serial_out;
3188 /* Possibly override set_termios call */
3189 if (port->set_termios)
3190 uart->port.set_termios = port->set_termios;
3192 uart->port.pm = port->pm;
3194 if (serial8250_isa_config != NULL)
3195 serial8250_isa_config(0, &uart->port,
3196 &uart->capabilities);
3198 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3200 ret = uart->port.line;
3202 mutex_unlock(&serial_mutex);
3206 EXPORT_SYMBOL(serial8250_register_port);
3209 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3210 * @line: serial line number
3212 * Remove one serial port. This may not be called from interrupt
3213 * context. We hand the port back to the our control.
3215 void serial8250_unregister_port(int line)
3217 struct uart_8250_port *uart = &serial8250_ports[line];
3219 mutex_lock(&serial_mutex);
3220 uart_remove_one_port(&serial8250_reg, &uart->port);
3221 if (serial8250_isa_devs) {
3222 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3223 uart->port.type = PORT_UNKNOWN;
3224 uart->port.dev = &serial8250_isa_devs->dev;
3225 uart_add_one_port(&serial8250_reg, &uart->port);
3227 uart->port.dev = NULL;
3229 mutex_unlock(&serial_mutex);
3231 EXPORT_SYMBOL(serial8250_unregister_port);
3233 static int __init serial8250_init(void)
3237 if (nr_uarts > UART_NR)
3240 printk(KERN_INFO "Serial: 8250/16550 driver, "
3241 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3242 share_irqs ? "en" : "dis");
3245 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3247 serial8250_reg.nr = UART_NR;
3248 ret = uart_register_driver(&serial8250_reg);
3253 serial8250_isa_devs = platform_device_alloc("serial8250",
3254 PLAT8250_DEV_LEGACY);
3255 if (!serial8250_isa_devs) {
3257 goto unreg_uart_drv;
3260 ret = platform_device_add(serial8250_isa_devs);
3264 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3266 ret = platform_driver_register(&serial8250_isa_driver);
3270 platform_device_del(serial8250_isa_devs);
3272 platform_device_put(serial8250_isa_devs);
3275 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3277 uart_unregister_driver(&serial8250_reg);
3283 static void __exit serial8250_exit(void)
3285 struct platform_device *isa_dev = serial8250_isa_devs;
3288 * This tells serial8250_unregister_port() not to re-register
3289 * the ports (thereby making serial8250_isa_driver permanently
3292 serial8250_isa_devs = NULL;
3294 platform_driver_unregister(&serial8250_isa_driver);
3295 platform_device_unregister(isa_dev);
3298 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3300 uart_unregister_driver(&serial8250_reg);
3304 module_init(serial8250_init);
3305 module_exit(serial8250_exit);
3307 EXPORT_SYMBOL(serial8250_suspend_port);
3308 EXPORT_SYMBOL(serial8250_resume_port);
3310 MODULE_LICENSE("GPL");
3311 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3313 module_param(share_irqs, uint, 0644);
3314 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3317 module_param(nr_uarts, uint, 0644);
3318 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3320 module_param(skip_txen_test, uint, 0644);
3321 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3323 #ifdef CONFIG_SERIAL_8250_RSA
3324 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3325 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3327 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);