drivers/scsi/qla2xxx/qla_sup.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2011 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/delay.h>
  10 #include <linux/slab.h>
  11 #include <linux/vmalloc.h>
  12 #include <asm/uaccess.h>
  13
  14 /*
  15  * NVRAM support routines
  16  */
  17
  18 /**
  19  * qla2x00_lock_nvram_access() -
  20  * @ha: HA context
  21  */
  22 static void
  23 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
  24 {
  25         uint16_t data;
  26         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  27
  28         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  29                 data = RD_REG_WORD(&reg->nvram);
  30                 while (data & NVR_BUSY) {
  31                         udelay(100);
  32                         data = RD_REG_WORD(&reg->nvram);
  33                 }
  34
  35                 /* Lock resource */
  36                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  37                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  38                 udelay(5);
  39                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  40                 while ((data & BIT_0) == 0) {
  41                         /* Lock failed */
  42                         udelay(100);
  43                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  44                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  45                         udelay(5);
  46                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  47                 }
  48         }
  49 }
  50
  51 /**
  52  * qla2x00_unlock_nvram_access() -
  53  * @ha: HA context
  54  */
  55 static void
  56 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
  57 {
  58         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  59
  60         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  61                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  62                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  63         }
  64 }
  65
  66 /**
  67  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
  68  * @ha: HA context
  69  * @data: Serial interface selector
  70  */
  71 static void
  72 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
  73 {
  74         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  75
  76         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  77         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  78         NVRAM_DELAY();
  79         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
  80             NVR_WRT_ENABLE);
  81         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  82         NVRAM_DELAY();
  83         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  84         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
  85         NVRAM_DELAY();
  86 }
  87
  88 /**
  89  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
  90  *      NVRAM.
  91  * @ha: HA context
  92  * @nv_cmd: NVRAM command
  93  *
  94  * Bit definitions for NVRAM command:
  95  *
  96  *      Bit 26     = start bit
  97  *      Bit 25, 24 = opcode
  98  *      Bit 23-16  = address
  99  *      Bit 15-0   = write data
 100  *
 101  * Returns the word read from nvram @addr.
 102  */
 103 static uint16_t
 104 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
 105 {
 106         uint8_t         cnt;
 107         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 108         uint16_t        data = 0;
 109         uint16_t        reg_data;
 110
 111         /* Send command to NVRAM. */
 112         nv_cmd <<= 5;
 113         for (cnt = 0; cnt < 11; cnt++) {
 114                 if (nv_cmd & BIT_31)
 115                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 116                 else
 117                         qla2x00_nv_write(ha, 0);
 118                 nv_cmd <<= 1;
 119         }
 120
 121         /* Read data from NVRAM. */
 122         for (cnt = 0; cnt < 16; cnt++) {
 123                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 124                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 125                 NVRAM_DELAY();
 126                 data <<= 1;
 127                 reg_data = RD_REG_WORD(&reg->nvram);
 128                 if (reg_data & NVR_DATA_IN)
 129                         data |= BIT_0;
 130                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 131                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 132                 NVRAM_DELAY();
 133         }
 134
 135         /* Deselect chip. */
 136         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 137         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 138         NVRAM_DELAY();
 139
 140         return data;
 141 }
 142
 143
 144 /**
 145  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
 146  *      request routine to get the word from NVRAM.
 147  * @ha: HA context
 148  * @addr: Address in NVRAM to read
 149  *
 150  * Returns the word read from nvram @addr.
 151  */
 152 static uint16_t
 153 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
 154 {
 155         uint16_t        data;
 156         uint32_t        nv_cmd;
 157
 158         nv_cmd = addr << 16;
 159         nv_cmd |= NV_READ_OP;
 160         data = qla2x00_nvram_request(ha, nv_cmd);
 161
 162         return (data);
 163 }
 164
 165 /**
 166  * qla2x00_nv_deselect() - Deselect NVRAM operations.
 167  * @ha: HA context
 168  */
 169 static void
 170 qla2x00_nv_deselect(struct qla_hw_data *ha)
 171 {
 172         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 173
 174         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 175         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 176         NVRAM_DELAY();
 177 }
 178
 179 /**
 180  * qla2x00_write_nvram_word() - Write NVRAM data.
 181  * @ha: HA context
 182  * @addr: Address in NVRAM to write
 183  * @data: word to program
 184  */
 185 static void
 186 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
 187 {
 188         int count;
 189         uint16_t word;
 190         uint32_t nv_cmd, wait_cnt;
 191         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 192         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 193
 194         qla2x00_nv_write(ha, NVR_DATA_OUT);
 195         qla2x00_nv_write(ha, 0);
 196         qla2x00_nv_write(ha, 0);
 197
 198         for (word = 0; word < 8; word++)
 199                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 200
 201         qla2x00_nv_deselect(ha);
 202
 203         /* Write data */
 204         nv_cmd = (addr << 16) | NV_WRITE_OP;
 205         nv_cmd |= data;
 206         nv_cmd <<= 5;
 207         for (count = 0; count < 27; count++) {
 208                 if (nv_cmd & BIT_31)
 209                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 210                 else
 211                         qla2x00_nv_write(ha, 0);
 212
 213                 nv_cmd <<= 1;
 214         }
 215
 216         qla2x00_nv_deselect(ha);
 217
 218         /* Wait for NVRAM to become ready */
 219         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 220         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 221         wait_cnt = NVR_WAIT_CNT;
 222         do {
 223                 if (!--wait_cnt) {
 224                         ql_dbg(ql_dbg_user, vha, 0x708d,
 225                             "NVRAM didn't go ready...\n");
 226                         break;
 227                 }
 228                 NVRAM_DELAY();
 229                 word = RD_REG_WORD(&reg->nvram);
 230         } while ((word & NVR_DATA_IN) == 0);
 231
 232         qla2x00_nv_deselect(ha);
 233
 234         /* Disable writes */
 235         qla2x00_nv_write(ha, NVR_DATA_OUT);
 236         for (count = 0; count < 10; count++)
 237                 qla2x00_nv_write(ha, 0);
 238
 239         qla2x00_nv_deselect(ha);
 240 }
 241
 242 static int
 243 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
 244         uint16_t data, uint32_t tmo)
 245 {
 246         int ret, count;
 247         uint16_t word;
 248         uint32_t nv_cmd;
 249         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 250
 251         ret = QLA_SUCCESS;
 252
 253         qla2x00_nv_write(ha, NVR_DATA_OUT);
 254         qla2x00_nv_write(ha, 0);
 255         qla2x00_nv_write(ha, 0);
 256
 257         for (word = 0; word < 8; word++)
 258                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 259
 260         qla2x00_nv_deselect(ha);
 261
 262         /* Write data */
 263         nv_cmd = (addr << 16) | NV_WRITE_OP;
 264         nv_cmd |= data;
 265         nv_cmd <<= 5;
 266         for (count = 0; count < 27; count++) {
 267                 if (nv_cmd & BIT_31)
 268                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 269                 else
 270                         qla2x00_nv_write(ha, 0);
 271
 272                 nv_cmd <<= 1;
 273         }
 274
 275         qla2x00_nv_deselect(ha);
 276
 277         /* Wait for NVRAM to become ready */
 278         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 279         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 280         do {
 281                 NVRAM_DELAY();
 282                 word = RD_REG_WORD(&reg->nvram);
 283                 if (!--tmo) {
 284                         ret = QLA_FUNCTION_FAILED;
 285                         break;
 286                 }
 287         } while ((word & NVR_DATA_IN) == 0);
 288
 289         qla2x00_nv_deselect(ha);
 290
 291         /* Disable writes */
 292         qla2x00_nv_write(ha, NVR_DATA_OUT);
 293         for (count = 0; count < 10; count++)
 294                 qla2x00_nv_write(ha, 0);
 295
 296         qla2x00_nv_deselect(ha);
 297
 298         return ret;
 299 }
 300
 301 /**
 302  * qla2x00_clear_nvram_protection() -
 303  * @ha: HA context
 304  */
 305 static int
 306 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
 307 {
 308         int ret, stat;
 309         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 310         uint32_t word, wait_cnt;
 311         uint16_t wprot, wprot_old;
 312         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 313
 314         /* Clear NVRAM write protection. */
 315         ret = QLA_FUNCTION_FAILED;
 316
 317         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 318         stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
 319             __constant_cpu_to_le16(0x1234), 100000);
 320         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 321         if (stat != QLA_SUCCESS || wprot != 0x1234) {
 322                 /* Write enable. */
 323                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 324                 qla2x00_nv_write(ha, 0);
 325                 qla2x00_nv_write(ha, 0);
 326                 for (word = 0; word < 8; word++)
 327                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 328
 329                 qla2x00_nv_deselect(ha);
 330
 331                 /* Enable protection register. */
 332                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 333                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 334                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 335                 for (word = 0; word < 8; word++)
 336                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 337
 338                 qla2x00_nv_deselect(ha);
 339
 340                 /* Clear protection register (ffff is cleared). */
 341                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 342                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 343                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 344                 for (word = 0; word < 8; word++)
 345                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 346
 347                 qla2x00_nv_deselect(ha);
 348
 349                 /* Wait for NVRAM to become ready. */
 350                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 351                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 352                 wait_cnt = NVR_WAIT_CNT;
 353                 do {
 354                         if (!--wait_cnt) {
 355                                 ql_dbg(ql_dbg_user, vha, 0x708e,
 356                                     "NVRAM didn't go ready...\n");
 357                                 break;
 358                         }
 359                         NVRAM_DELAY();
 360                         word = RD_REG_WORD(&reg->nvram);
 361                 } while ((word & NVR_DATA_IN) == 0);
 362
 363                 if (wait_cnt)
 364                         ret = QLA_SUCCESS;
 365         } else
 366                 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
 367
 368         return ret;
 369 }
 370
 371 static void
 372 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
 373 {
 374         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 375         uint32_t word, wait_cnt;
 376         scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
 377
 378         if (stat != QLA_SUCCESS)
 379                 return;
 380
 381         /* Set NVRAM write protection. */
 382         /* Write enable. */
 383         qla2x00_nv_write(ha, NVR_DATA_OUT);
 384         qla2x00_nv_write(ha, 0);
 385         qla2x00_nv_write(ha, 0);
 386         for (word = 0; word < 8; word++)
 387                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 388
 389         qla2x00_nv_deselect(ha);
 390
 391         /* Enable protection register. */
 392         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 393         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 394         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 395         for (word = 0; word < 8; word++)
 396                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 397
 398         qla2x00_nv_deselect(ha);
 399
 400         /* Enable protection register. */
 401         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 402         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 403         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 404         for (word = 0; word < 8; word++)
 405                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 406
 407         qla2x00_nv_deselect(ha);
 408
 409         /* Wait for NVRAM to become ready. */
 410         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 411         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 412         wait_cnt = NVR_WAIT_CNT;
 413         do {
 414                 if (!--wait_cnt) {
 415                         ql_dbg(ql_dbg_user, vha, 0x708f,
 416                             "NVRAM didn't go ready...\n");
 417                         break;
 418                 }
 419                 NVRAM_DELAY();
 420                 word = RD_REG_WORD(&reg->nvram);
 421         } while ((word & NVR_DATA_IN) == 0);
 422 }
 423
 424
 425 /*****************************************************************************/
 426 /* Flash Manipulation Routines                                               */
 427 /*****************************************************************************/
 428
 429 static inline uint32_t
 430 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
 431 {
 432         return ha->flash_conf_off | faddr;
 433 }
 434
 435 static inline uint32_t
 436 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
 437 {
 438         return ha->flash_data_off | faddr;
 439 }
 440
 441 static inline uint32_t
 442 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
 443 {
 444         return ha->nvram_conf_off | naddr;
 445 }
 446
 447 static inline uint32_t
 448 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
 449 {
 450         return ha->nvram_data_off | naddr;
 451 }
 452
 453 static uint32_t
 454 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
 455 {
 456         int rval;
 457         uint32_t cnt, data;
 458         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 459
 460         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 461         /* Wait for READ cycle to complete. */
 462         rval = QLA_SUCCESS;
 463         for (cnt = 3000;
 464             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 465             rval == QLA_SUCCESS; cnt--) {
 466                 if (cnt)
 467                         udelay(10);
 468                 else
 469                         rval = QLA_FUNCTION_TIMEOUT;
 470                 cond_resched();
 471         }
 472
 473         /* TODO: What happens if we time out? */
 474         data = 0xDEADDEAD;
 475         if (rval == QLA_SUCCESS)
 476                 data = RD_REG_DWORD(&reg->flash_data);
 477
 478         return data;
 479 }
 480
 481 uint32_t *
 482 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
 483     uint32_t dwords)
 484 {
 485         uint32_t i;
 486         struct qla_hw_data *ha = vha->hw;
 487
 488         /* Dword reads to flash. */
 489         for (i = 0; i < dwords; i++, faddr++)
 490                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 491                     flash_data_addr(ha, faddr)));
 492
 493         return dwptr;
 494 }
 495
 496 static int
 497 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
 498 {
 499         int rval;
 500         uint32_t cnt;
 501         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 502
 503         WRT_REG_DWORD(&reg->flash_data, data);
 504         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 505         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 506         /* Wait for Write cycle to complete. */
 507         rval = QLA_SUCCESS;
 508         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 509             rval == QLA_SUCCESS; cnt--) {
 510                 if (cnt)
 511                         udelay(10);
 512                 else
 513                         rval = QLA_FUNCTION_TIMEOUT;
 514                 cond_resched();
 515         }
 516         return rval;
 517 }
 518
 519 static void
 520 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
 521     uint8_t *flash_id)
 522 {
 523         uint32_t ids;
 524
 525         ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
 526         *man_id = LSB(ids);
 527         *flash_id = MSB(ids);
 528
 529         /* Check if man_id and flash_id are valid. */
 530         if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
 531                 /* Read information using 0x9f opcode
 532                  * Device ID, Mfg ID would be read in the format:
 533                  *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
 534                  * Example: ATMEL 0x00 01 45 1F
 535                  * Extract MFG and Dev ID from last two bytes.
 536                  */
 537                 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
 538                 *man_id = LSB(ids);
 539                 *flash_id = MSB(ids);
 540         }
 541 }
 542
 543 static int
 544 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
 545 {
 546         const char *loc, *locations[] = { "DEF", "PCI" };
 547         uint32_t pcihdr, pcids;
 548         uint32_t *dcode;
 549         uint8_t *buf, *bcode, last_image;
 550         uint16_t cnt, chksum, *wptr;
 551         struct qla_flt_location *fltl;
 552         struct qla_hw_data *ha = vha->hw;
 553         struct req_que *req = ha->req_q_map[0];
 554
 555         /*
 556          * FLT-location structure resides after the last PCI region.
 557          */
 558
 559         /* Begin with sane defaults. */
 560         loc = locations[0];
 561         *start = 0;
 562         if (IS_QLA24XX_TYPE(ha))
 563                 *start = FA_FLASH_LAYOUT_ADDR_24;
 564         else if (IS_QLA25XX(ha))
 565                 *start = FA_FLASH_LAYOUT_ADDR;
 566         else if (IS_QLA81XX(ha))
 567                 *start = FA_FLASH_LAYOUT_ADDR_81;
 568         else if (IS_QLA82XX(ha)) {
 569                 *start = FA_FLASH_LAYOUT_ADDR_82;
 570                 goto end;
 571         }
 572         /* Begin with first PCI expansion ROM header. */
 573         buf = (uint8_t *)req->ring;
 574         dcode = (uint32_t *)req->ring;
 575         pcihdr = 0;
 576         last_image = 1;
 577         do {
 578                 /* Verify PCI expansion ROM header. */
 579                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
 580                 bcode = buf + (pcihdr % 4);
 581                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
 582                         goto end;
 583
 584                 /* Locate PCI data structure. */
 585                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
 586                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
 587                 bcode = buf + (pcihdr % 4);
 588
 589                 /* Validate signature of PCI data structure. */
 590                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
 591                     bcode[0x2] != 'I' || bcode[0x3] != 'R')
 592                         goto end;
 593
 594                 last_image = bcode[0x15] & BIT_7;
 595
 596                 /* Locate next PCI expansion ROM. */
 597                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
 598         } while (!last_image);
 599
 600         /* Now verify FLT-location structure. */
 601         fltl = (struct qla_flt_location *)req->ring;
 602         qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
 603             sizeof(struct qla_flt_location) >> 2);
 604         if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
 605             fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
 606                 goto end;
 607
 608         wptr = (uint16_t *)req->ring;
 609         cnt = sizeof(struct qla_flt_location) >> 1;
 610         for (chksum = 0; cnt; cnt--)
 611                 chksum += le16_to_cpu(*wptr++);
 612         if (chksum) {
 613                 ql_log(ql_log_fatal, vha, 0x0045,
 614                     "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
 615                 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
 616                     buf, sizeof(struct qla_flt_location));
 617                 return QLA_FUNCTION_FAILED;
 618         }
 619
 620         /* Good data.  Use specified location. */
 621         loc = locations[1];
 622         *start = (le16_to_cpu(fltl->start_hi) << 16 |
 623             le16_to_cpu(fltl->start_lo)) >> 2;
 624 end:
 625         ql_dbg(ql_dbg_init, vha, 0x0046,
 626             "FLTL[%s] = 0x%x.\n",
 627             loc, *start);
 628         return QLA_SUCCESS;
 629 }
 630
 631 static void
 632 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
 633 {
 634         const char *loc, *locations[] = { "DEF", "FLT" };
 635         const uint32_t def_fw[] =
 636                 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
 637         const uint32_t def_boot[] =
 638                 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
 639         const uint32_t def_vpd_nvram[] =
 640                 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
 641         const uint32_t def_vpd0[] =
 642                 { 0, 0, FA_VPD0_ADDR_81 };
 643         const uint32_t def_vpd1[] =
 644                 { 0, 0, FA_VPD1_ADDR_81 };
 645         const uint32_t def_nvram0[] =
 646                 { 0, 0, FA_NVRAM0_ADDR_81 };
 647         const uint32_t def_nvram1[] =
 648                 { 0, 0, FA_NVRAM1_ADDR_81 };
 649         const uint32_t def_fdt[] =
 650                 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
 651                         FA_FLASH_DESCR_ADDR_81 };
 652         const uint32_t def_npiv_conf0[] =
 653                 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
 654                         FA_NPIV_CONF0_ADDR_81 };
 655         const uint32_t def_npiv_conf1[] =
 656                 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
 657                         FA_NPIV_CONF1_ADDR_81 };
 658         const uint32_t fcp_prio_cfg0[] =
 659                 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25,
 660                         0 };
 661         const uint32_t fcp_prio_cfg1[] =
 662                 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
 663                         0 };
 664         uint32_t def;
 665         uint16_t *wptr;
 666         uint16_t cnt, chksum;
 667         uint32_t start;
 668         struct qla_flt_header *flt;
 669         struct qla_flt_region *region;
 670         struct qla_hw_data *ha = vha->hw;
 671         struct req_que *req = ha->req_q_map[0];
 672
 673         def = 0;
 674         if (IS_QLA25XX(ha))
 675                 def = 1;
 676         else if (IS_QLA81XX(ha))
 677                 def = 2;
 678
 679         /* Assign FCP prio region since older adapters may not have FLT, or
 680            FCP prio region in it's FLT.
 681          */
 682         ha->flt_region_fcp_prio = ha->flags.port0 ?
 683             fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
 684
 685         ha->flt_region_flt = flt_addr;
 686         wptr = (uint16_t *)req->ring;
 687         flt = (struct qla_flt_header *)req->ring;
 688         region = (struct qla_flt_region *)&flt[1];
 689         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 690             flt_addr << 2, OPTROM_BURST_SIZE);
 691         if (*wptr == __constant_cpu_to_le16(0xffff))
 692                 goto no_flash_data;
 693         if (flt->version != __constant_cpu_to_le16(1)) {
 694                 ql_log(ql_log_warn, vha, 0x0047,
 695                     "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
 696                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 697                     le16_to_cpu(flt->checksum));
 698                 goto no_flash_data;
 699         }
 700
 701         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
 702         for (chksum = 0; cnt; cnt--)
 703                 chksum += le16_to_cpu(*wptr++);
 704         if (chksum) {
 705                 ql_log(ql_log_fatal, vha, 0x0048,
 706                     "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
 707                     le16_to_cpu(flt->version), le16_to_cpu(flt->length),
 708                     le16_to_cpu(flt->checksum));
 709                 goto no_flash_data;
 710         }
 711
 712         loc = locations[1];
 713         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
 714         for ( ; cnt; cnt--, region++) {
 715                 /* Store addresses as DWORD offsets. */
 716                 start = le32_to_cpu(region->start) >> 2;
 717                 ql_dbg(ql_dbg_init, vha, 0x0049,
 718                     "FLT[%02x]: start=0x%x "
 719                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code),
 720                     start, le32_to_cpu(region->end) >> 2,
 721                     le32_to_cpu(region->size));
 722
 723                 switch (le32_to_cpu(region->code) & 0xff) {
 724                 case FLT_REG_FW:
 725                         ha->flt_region_fw = start;
 726                         break;
 727                 case FLT_REG_BOOT_CODE:
 728                         ha->flt_region_boot = start;
 729                         break;
 730                 case FLT_REG_VPD_0:
 731                         ha->flt_region_vpd_nvram = start;
 732                         if (IS_QLA82XX(ha))
 733                                 break;
 734                         if (ha->flags.port0)
 735                                 ha->flt_region_vpd = start;
 736                         break;
 737                 case FLT_REG_VPD_1:
 738                         if (IS_QLA82XX(ha))
 739                                 break;
 740                         if (!ha->flags.port0)
 741                                 ha->flt_region_vpd = start;
 742                         break;
 743                 case FLT_REG_NVRAM_0:
 744                         if (ha->flags.port0)
 745                                 ha->flt_region_nvram = start;
 746                         break;
 747                 case FLT_REG_NVRAM_1:
 748                         if (!ha->flags.port0)
 749                                 ha->flt_region_nvram = start;
 750                         break;
 751                 case FLT_REG_FDT:
 752                         ha->flt_region_fdt = start;
 753                         break;
 754                 case FLT_REG_NPIV_CONF_0:
 755                         if (ha->flags.port0)
 756                                 ha->flt_region_npiv_conf = start;
 757                         break;
 758                 case FLT_REG_NPIV_CONF_1:
 759                         if (!ha->flags.port0)
 760                                 ha->flt_region_npiv_conf = start;
 761                         break;
 762                 case FLT_REG_GOLD_FW:
 763                         ha->flt_region_gold_fw = start;
 764                         break;
 765                 case FLT_REG_FCP_PRIO_0:
 766                         if (ha->flags.port0)
 767                                 ha->flt_region_fcp_prio = start;
 768                         break;
 769                 case FLT_REG_FCP_PRIO_1:
 770                         if (!ha->flags.port0)
 771                                 ha->flt_region_fcp_prio = start;
 772                         break;
 773                 case FLT_REG_BOOT_CODE_82XX:
 774                         ha->flt_region_boot = start;
 775                         break;
 776                 case FLT_REG_FW_82XX:
 777                         ha->flt_region_fw = start;
 778                         break;
 779                 case FLT_REG_GOLD_FW_82XX:
 780                         ha->flt_region_gold_fw = start;
 781                         break;
 782                 case FLT_REG_BOOTLOAD_82XX:
 783                         ha->flt_region_bootload = start;
 784                         break;
 785                 case FLT_REG_VPD_82XX:
 786                         ha->flt_region_vpd = start;
 787                         break;
 788                 }
 789         }
 790         goto done;
 791
 792 no_flash_data:
 793         /* Use hardcoded defaults. */
 794         loc = locations[0];
 795         ha->flt_region_fw = def_fw[def];
 796         ha->flt_region_boot = def_boot[def];
 797         ha->flt_region_vpd_nvram = def_vpd_nvram[def];
 798         ha->flt_region_vpd = ha->flags.port0 ?
 799             def_vpd0[def] : def_vpd1[def];
 800         ha->flt_region_nvram = ha->flags.port0 ?
 801             def_nvram0[def] : def_nvram1[def];
 802         ha->flt_region_fdt = def_fdt[def];
 803         ha->flt_region_npiv_conf = ha->flags.port0 ?
 804             def_npiv_conf0[def] : def_npiv_conf1[def];
 805 done:
 806         ql_dbg(ql_dbg_init, vha, 0x004a,
 807             "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x.\n",
 808             loc, ha->flt_region_boot,
 809             ha->flt_region_fw, ha->flt_region_vpd_nvram,
 810             ha->flt_region_vpd);
 811         ql_dbg(ql_dbg_init, vha, 0x004b,
 812             "nvram=0x%x fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n",
 813             ha->flt_region_nvram,
 814             ha->flt_region_fdt, ha->flt_region_flt,
 815             ha->flt_region_npiv_conf, ha->flt_region_fcp_prio);
 816 }
 817
 818 static void
 819 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
 820 {
 821 #define FLASH_BLK_SIZE_4K       0x1000
 822 #define FLASH_BLK_SIZE_32K      0x8000
 823 #define FLASH_BLK_SIZE_64K      0x10000
 824         const char *loc, *locations[] = { "MID", "FDT" };
 825         uint16_t cnt, chksum;
 826         uint16_t *wptr;
 827         struct qla_fdt_layout *fdt;
 828         uint8_t man_id, flash_id;
 829         uint16_t mid = 0, fid = 0;
 830         struct qla_hw_data *ha = vha->hw;
 831         struct req_que *req = ha->req_q_map[0];
 832
 833         wptr = (uint16_t *)req->ring;
 834         fdt = (struct qla_fdt_layout *)req->ring;
 835         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 836             ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
 837         if (*wptr == __constant_cpu_to_le16(0xffff))
 838                 goto no_flash_data;
 839         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
 840             fdt->sig[3] != 'D')
 841                 goto no_flash_data;
 842
 843         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
 844             cnt++)
 845                 chksum += le16_to_cpu(*wptr++);
 846         if (chksum) {
 847                 ql_dbg(ql_dbg_init, vha, 0x004c,
 848                     "Inconsistent FDT detected:"
 849                     " checksum=0x%x id=%c version0x%x.\n", chksum,
 850                     fdt->sig[0], le16_to_cpu(fdt->version));
 851                 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
 852                     (uint8_t *)fdt, sizeof(*fdt));
 853                 goto no_flash_data;
 854         }
 855
 856         loc = locations[1];
 857         mid = le16_to_cpu(fdt->man_id);
 858         fid = le16_to_cpu(fdt->id);
 859         ha->fdt_wrt_disable = fdt->wrt_disable_bits;
 860         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
 861         ha->fdt_block_size = le32_to_cpu(fdt->block_size);
 862         if (fdt->unprotect_sec_cmd) {
 863                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
 864                     fdt->unprotect_sec_cmd);
 865                 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
 866                     flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
 867                     flash_conf_addr(ha, 0x0336);
 868         }
 869         goto done;
 870 no_flash_data:
 871         loc = locations[0];
 872         if (IS_QLA82XX(ha)) {
 873                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 874                 goto done;
 875         }
 876         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 877         mid = man_id;
 878         fid = flash_id;
 879         ha->fdt_wrt_disable = 0x9c;
 880         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
 881         switch (man_id) {
 882         case 0xbf: /* STT flash. */
 883                 if (flash_id == 0x8e)
 884                         ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 885                 else
 886                         ha->fdt_block_size = FLASH_BLK_SIZE_32K;
 887
 888                 if (flash_id == 0x80)
 889                         ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
 890                 break;
 891         case 0x13: /* ST M25P80. */
 892                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 893                 break;
 894         case 0x1f: /* Atmel 26DF081A. */
 895                 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
 896                 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
 897                 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
 898                 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
 899                 break;
 900         default:
 901                 /* Default to 64 kb sector size. */
 902                 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
 903                 break;
 904         }
 905 done:
 906         ql_dbg(ql_dbg_init, vha, 0x004d,
 907             "FDT[%x]: (0x%x/0x%x) erase=0x%x "
 908             "pr=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
 909             ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
 910             ha->fdt_wrt_disable, ha->fdt_block_size);
 911
 912 }
 913
 914 static void
 915 qla2xxx_get_idc_param(scsi_qla_host_t *vha)
 916 {
 917 #define QLA82XX_IDC_PARAM_ADDR       0x003e885c
 918         uint32_t *wptr;
 919         struct qla_hw_data *ha = vha->hw;
 920         struct req_que *req = ha->req_q_map[0];
 921
 922         if (!IS_QLA82XX(ha))
 923                 return;
 924
 925         wptr = (uint32_t *)req->ring;
 926         ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
 927                 QLA82XX_IDC_PARAM_ADDR , 8);
 928
 929         if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
 930                 ha->nx_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
 931                 ha->nx_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT;
 932         } else {
 933                 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
 934                 ha->nx_reset_timeout = le32_to_cpu(*wptr);
 935         }
 936         ql_dbg(ql_dbg_init, vha, 0x004e,
 937             "nx_dev_init_timeout=%d "
 938             "nx_reset_timeout=%d.\n", ha->nx_dev_init_timeout,
 939             ha->nx_reset_timeout);
 940         return;
 941 }
 942
 943 int
 944 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
 945 {
 946         int ret;
 947         uint32_t flt_addr;
 948         struct qla_hw_data *ha = vha->hw;
 949
 950         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA8XXX_TYPE(ha))
 951                 return QLA_SUCCESS;
 952
 953         ret = qla2xxx_find_flt_start(vha, &flt_addr);
 954         if (ret != QLA_SUCCESS)
 955                 return ret;
 956
 957         qla2xxx_get_flt_info(vha, flt_addr);
 958         qla2xxx_get_fdt_info(vha);
 959         qla2xxx_get_idc_param(vha);
 960
 961         return QLA_SUCCESS;
 962 }
 963
 964 void
 965 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
 966 {
 967 #define NPIV_CONFIG_SIZE        (16*1024)
 968         void *data;
 969         uint16_t *wptr;
 970         uint16_t cnt, chksum;
 971         int i;
 972         struct qla_npiv_header hdr;
 973         struct qla_npiv_entry *entry;
 974         struct qla_hw_data *ha = vha->hw;
 975
 976         if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA8XXX_TYPE(ha))
 977                 return;
 978
 979         ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
 980             ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
 981         if (hdr.version == __constant_cpu_to_le16(0xffff))
 982                 return;
 983         if (hdr.version != __constant_cpu_to_le16(1)) {
 984                 ql_dbg(ql_dbg_user, vha, 0x7090,
 985                     "Unsupported NPIV-Config "
 986                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
 987                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
 988                     le16_to_cpu(hdr.checksum));
 989                 return;
 990         }
 991
 992         data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
 993         if (!data) {
 994                 ql_log(ql_log_warn, vha, 0x7091,
 995                     "Unable to allocate memory for data.\n");
 996                 return;
 997         }
 998
 999         ha->isp_ops->read_optrom(vha, (uint8_t *)data,
1000             ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
1001
1002         cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
1003             sizeof(struct qla_npiv_entry)) >> 1;
1004         for (wptr = data, chksum = 0; cnt; cnt--)
1005                 chksum += le16_to_cpu(*wptr++);
1006         if (chksum) {
1007                 ql_dbg(ql_dbg_user, vha, 0x7092,
1008                     "Inconsistent NPIV-Config "
1009                     "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1010                     le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1011                     le16_to_cpu(hdr.checksum));
1012                 goto done;
1013         }
1014
1015         entry = data + sizeof(struct qla_npiv_header);
1016         cnt = le16_to_cpu(hdr.entries);
1017         for (i = 0; cnt; cnt--, entry++, i++) {
1018                 uint16_t flags;
1019                 struct fc_vport_identifiers vid;
1020                 struct fc_vport *vport;
1021
1022                 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
1023
1024                 flags = le16_to_cpu(entry->flags);
1025                 if (flags == 0xffff)
1026                         continue;
1027                 if ((flags & BIT_0) == 0)
1028                         continue;
1029
1030                 memset(&vid, 0, sizeof(vid));
1031                 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
1032                 vid.vport_type = FC_PORTTYPE_NPIV;
1033                 vid.disable = false;
1034                 vid.port_name = wwn_to_u64(entry->port_name);
1035                 vid.node_name = wwn_to_u64(entry->node_name);
1036
1037                 ql_dbg(ql_dbg_user, vha, 0x7093,
1038                     "NPIV[%02x]: wwpn=%llx "
1039                     "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
1040                     (unsigned long long)vid.port_name,
1041                     (unsigned long long)vid.node_name,
1042                     le16_to_cpu(entry->vf_id),
1043                     entry->q_qos, entry->f_qos);
1044
1045                 if (i < QLA_PRECONFIG_VPORTS) {
1046                         vport = fc_vport_create(vha->host, 0, &vid);
1047                         if (!vport)
1048                                 ql_log(ql_log_warn, vha, 0x7094,
1049                                     "NPIV-Config Failed to create vport [%02x]: "
1050                                     "wwpn=%llx wwnn=%llx.\n", cnt,
1051                                     (unsigned long long)vid.port_name,
1052                                     (unsigned long long)vid.node_name);
1053                 }
1054         }
1055 done:
1056         kfree(data);
1057 }
1058
1059 static int
1060 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
1061 {
1062         struct qla_hw_data *ha = vha->hw;
1063         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1064
1065         if (ha->flags.fac_supported)
1066                 return qla81xx_fac_do_write_enable(vha, 1);
1067
1068         /* Enable flash write. */
1069         WRT_REG_DWORD(&reg->ctrl_status,
1070             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1071         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1072
1073         if (!ha->fdt_wrt_disable)
1074                 goto done;
1075
1076         /* Disable flash write-protection, first clear SR protection bit */
1077         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1078         /* Then write zero again to clear remaining SR bits.*/
1079         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1080 done:
1081         return QLA_SUCCESS;
1082 }
1083
1084 static int
1085 qla24xx_protect_flash(scsi_qla_host_t *vha)
1086 {
1087         uint32_t cnt;
1088         struct qla_hw_data *ha = vha->hw;
1089         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1090
1091         if (ha->flags.fac_supported)
1092                 return qla81xx_fac_do_write_enable(vha, 0);
1093
1094         if (!ha->fdt_wrt_disable)
1095                 goto skip_wrt_protect;
1096
1097         /* Enable flash write-protection and wait for completion. */
1098         qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1099             ha->fdt_wrt_disable);
1100         for (cnt = 300; cnt &&
1101             qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1102             cnt--) {
1103                 udelay(10);
1104         }
1105
1106 skip_wrt_protect:
1107         /* Disable flash write. */
1108         WRT_REG_DWORD(&reg->ctrl_status,
1109             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1110         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1111
1112         return QLA_SUCCESS;
1113 }
1114
1115 static int
1116 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1117 {
1118         struct qla_hw_data *ha = vha->hw;
1119         uint32_t start, finish;
1120
1121         if (ha->flags.fac_supported) {
1122                 start = fdata >> 2;
1123                 finish = start + (ha->fdt_block_size >> 2) - 1;
1124                 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1125                     start), flash_data_addr(ha, finish));
1126         }
1127
1128         return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1129             (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1130             ((fdata >> 16) & 0xff));
1131 }
1132
1133 static int
1134 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1135     uint32_t dwords)
1136 {
1137         int ret;
1138         uint32_t liter;
1139         uint32_t sec_mask, rest_addr;
1140         uint32_t fdata;
1141         dma_addr_t optrom_dma;
1142         void *optrom = NULL;
1143         struct qla_hw_data *ha = vha->hw;
1144
1145         /* Prepare burst-capable write on supported ISPs. */
1146         if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
1147             dwords > OPTROM_BURST_DWORDS) {
1148                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1149                     &optrom_dma, GFP_KERNEL);
1150                 if (!optrom) {
1151                         ql_log(ql_log_warn, vha, 0x7095,
1152                             "Unable to allocate "
1153                             "memory for optrom burst write (%x KB).\n",
1154                             OPTROM_BURST_SIZE / 1024);
1155                 }
1156         }
1157
1158         rest_addr = (ha->fdt_block_size >> 2) - 1;
1159         sec_mask = ~rest_addr;
1160
1161         ret = qla24xx_unprotect_flash(vha);
1162         if (ret != QLA_SUCCESS) {
1163                 ql_log(ql_log_warn, vha, 0x7096,
1164                     "Unable to unprotect flash for update.\n");
1165                 goto done;
1166         }
1167
1168         for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1169                 fdata = (faddr & sec_mask) << 2;
1170
1171                 /* Are we at the beginning of a sector? */
1172                 if ((faddr & rest_addr) == 0) {
1173                         /* Do sector unprotect. */
1174                         if (ha->fdt_unprotect_sec_cmd)
1175                                 qla24xx_write_flash_dword(ha,
1176                                     ha->fdt_unprotect_sec_cmd,
1177                                     (fdata & 0xff00) | ((fdata << 16) &
1178                                     0xff0000) | ((fdata >> 16) & 0xff));
1179                         ret = qla24xx_erase_sector(vha, fdata);
1180                         if (ret != QLA_SUCCESS) {
1181                                 ql_dbg(ql_dbg_user, vha, 0x7007,
1182                                     "Unable to erase erase sector: address=%x.\n",
1183                                     faddr);
1184                                 break;
1185                         }
1186                 }
1187
1188                 /* Go with burst-write. */
1189                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1190                         /* Copy data to DMA'ble buffer. */
1191                         memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1192
1193                         ret = qla2x00_load_ram(vha, optrom_dma,
1194                             flash_data_addr(ha, faddr),
1195                             OPTROM_BURST_DWORDS);
1196                         if (ret != QLA_SUCCESS) {
1197                                 ql_log(ql_log_warn, vha, 0x7097,
1198                                     "Unable to burst-write optrom segment "
1199                                     "(%x/%x/%llx).\n", ret,
1200                                     flash_data_addr(ha, faddr),
1201                                     (unsigned long long)optrom_dma);
1202                                 ql_log(ql_log_warn, vha, 0x7098,
1203                                     "Reverting to slow-write.\n");
1204
1205                                 dma_free_coherent(&ha->pdev->dev,
1206                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1207                                 optrom = NULL;
1208                         } else {
1209                                 liter += OPTROM_BURST_DWORDS - 1;
1210                                 faddr += OPTROM_BURST_DWORDS - 1;
1211                                 dwptr += OPTROM_BURST_DWORDS - 1;
1212                                 continue;
1213                         }
1214                 }
1215
1216                 ret = qla24xx_write_flash_dword(ha,
1217                     flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1218                 if (ret != QLA_SUCCESS) {
1219                         ql_dbg(ql_dbg_user, vha, 0x7006,
1220                             "Unable to program flash address=%x data=%x.\n",
1221                             faddr, *dwptr);
1222                         break;
1223                 }
1224
1225                 /* Do sector protect. */
1226                 if (ha->fdt_unprotect_sec_cmd &&
1227                     ((faddr & rest_addr) == rest_addr))
1228                         qla24xx_write_flash_dword(ha,
1229                             ha->fdt_protect_sec_cmd,
1230                             (fdata & 0xff00) | ((fdata << 16) &
1231                             0xff0000) | ((fdata >> 16) & 0xff));
1232         }
1233
1234         ret = qla24xx_protect_flash(vha);
1235         if (ret != QLA_SUCCESS)
1236                 ql_log(ql_log_warn, vha, 0x7099,
1237                     "Unable to protect flash after update.\n");
1238 done:
1239         if (optrom)
1240                 dma_free_coherent(&ha->pdev->dev,
1241                     OPTROM_BURST_SIZE, optrom, optrom_dma);
1242
1243         return ret;
1244 }
1245
1246 uint8_t *
1247 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1248     uint32_t bytes)
1249 {
1250         uint32_t i;
1251         uint16_t *wptr;
1252         struct qla_hw_data *ha = vha->hw;
1253
1254         /* Word reads to NVRAM via registers. */
1255         wptr = (uint16_t *)buf;
1256         qla2x00_lock_nvram_access(ha);
1257         for (i = 0; i < bytes >> 1; i++, naddr++)
1258                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1259                     naddr));
1260         qla2x00_unlock_nvram_access(ha);
1261
1262         return buf;
1263 }
1264
1265 uint8_t *
1266 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1267     uint32_t bytes)
1268 {
1269         uint32_t i;
1270         uint32_t *dwptr;
1271         struct qla_hw_data *ha = vha->hw;
1272
1273         if (IS_QLA82XX(ha))
1274                 return  buf;
1275
1276         /* Dword reads to flash. */
1277         dwptr = (uint32_t *)buf;
1278         for (i = 0; i < bytes >> 2; i++, naddr++)
1279                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1280                     nvram_data_addr(ha, naddr)));
1281
1282         return buf;
1283 }
1284
1285 int
1286 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1287     uint32_t bytes)
1288 {
1289         int ret, stat;
1290         uint32_t i;
1291         uint16_t *wptr;
1292         unsigned long flags;
1293         struct qla_hw_data *ha = vha->hw;
1294
1295         ret = QLA_SUCCESS;
1296
1297         spin_lock_irqsave(&ha->hardware_lock, flags);
1298         qla2x00_lock_nvram_access(ha);
1299
1300         /* Disable NVRAM write-protection. */
1301         stat = qla2x00_clear_nvram_protection(ha);
1302
1303         wptr = (uint16_t *)buf;
1304         for (i = 0; i < bytes >> 1; i++, naddr++) {
1305                 qla2x00_write_nvram_word(ha, naddr,
1306                     cpu_to_le16(*wptr));
1307                 wptr++;
1308         }
1309
1310         /* Enable NVRAM write-protection. */
1311         qla2x00_set_nvram_protection(ha, stat);
1312
1313         qla2x00_unlock_nvram_access(ha);
1314         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1315
1316         return ret;
1317 }
1318
1319 int
1320 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1321     uint32_t bytes)
1322 {
1323         int ret;
1324         uint32_t i;
1325         uint32_t *dwptr;
1326         struct qla_hw_data *ha = vha->hw;
1327         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1328
1329         ret = QLA_SUCCESS;
1330
1331         if (IS_QLA82XX(ha))
1332                 return ret;
1333
1334         /* Enable flash write. */
1335         WRT_REG_DWORD(&reg->ctrl_status,
1336             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1337         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1338
1339         /* Disable NVRAM write-protection. */
1340         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1341         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1342
1343         /* Dword writes to flash. */
1344         dwptr = (uint32_t *)buf;
1345         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1346                 ret = qla24xx_write_flash_dword(ha,
1347                     nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1348                 if (ret != QLA_SUCCESS) {
1349                         ql_dbg(ql_dbg_user, vha, 0x709a,
1350                             "Unable to program nvram address=%x data=%x.\n",
1351                             naddr, *dwptr);
1352                         break;
1353                 }
1354         }
1355
1356         /* Enable NVRAM write-protection. */
1357         qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1358
1359         /* Disable flash write. */
1360         WRT_REG_DWORD(&reg->ctrl_status,
1361             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1362         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
1363
1364         return ret;
1365 }
1366
1367 uint8_t *
1368 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1369     uint32_t bytes)
1370 {
1371         uint32_t i;
1372         uint32_t *dwptr;
1373         struct qla_hw_data *ha = vha->hw;
1374
1375         /* Dword reads to flash. */
1376         dwptr = (uint32_t *)buf;
1377         for (i = 0; i < bytes >> 2; i++, naddr++)
1378                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1379                     flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1380
1381         return buf;
1382 }
1383
1384 int
1385 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1386     uint32_t bytes)
1387 {
1388         struct qla_hw_data *ha = vha->hw;
1389 #define RMW_BUFFER_SIZE (64 * 1024)
1390         uint8_t *dbuf;
1391
1392         dbuf = vmalloc(RMW_BUFFER_SIZE);
1393         if (!dbuf)
1394                 return QLA_MEMORY_ALLOC_FAILED;
1395         ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1396             RMW_BUFFER_SIZE);
1397         memcpy(dbuf + (naddr << 2), buf, bytes);
1398         ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1399             RMW_BUFFER_SIZE);
1400         vfree(dbuf);
1401
1402         return QLA_SUCCESS;
1403 }
1404
1405 static inline void
1406 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1407 {
1408         if (IS_QLA2322(ha)) {
1409                 /* Flip all colors. */
1410                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1411                         /* Turn off. */
1412                         ha->beacon_color_state = 0;
1413                         *pflags = GPIO_LED_ALL_OFF;
1414                 } else {
1415                         /* Turn on. */
1416                         ha->beacon_color_state = QLA_LED_ALL_ON;
1417                         *pflags = GPIO_LED_RGA_ON;
1418                 }
1419         } else {
1420                 /* Flip green led only. */
1421                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1422                         /* Turn off. */
1423                         ha->beacon_color_state = 0;
1424                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1425                 } else {
1426                         /* Turn on. */
1427                         ha->beacon_color_state = QLA_LED_GRN_ON;
1428                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1429                 }
1430         }
1431 }
1432
1433 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1434
1435 void
1436 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1437 {
1438         uint16_t gpio_enable;
1439         uint16_t gpio_data;
1440         uint16_t led_color = 0;
1441         unsigned long flags;
1442         struct qla_hw_data *ha = vha->hw;
1443         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1444
1445         if (IS_QLA82XX(ha))
1446                 return;
1447
1448         spin_lock_irqsave(&ha->hardware_lock, flags);
1449
1450         /* Save the Original GPIOE. */
1451         if (ha->pio_address) {
1452                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1453                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1454         } else {
1455                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1456                 gpio_data = RD_REG_WORD(&reg->gpiod);
1457         }
1458
1459         /* Set the modified gpio_enable values */
1460         gpio_enable |= GPIO_LED_MASK;
1461
1462         if (ha->pio_address) {
1463                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1464         } else {
1465                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1466                 RD_REG_WORD(&reg->gpioe);
1467         }
1468
1469         qla2x00_flip_colors(ha, &led_color);
1470
1471         /* Clear out any previously set LED color. */
1472         gpio_data &= ~GPIO_LED_MASK;
1473
1474         /* Set the new input LED color to GPIOD. */
1475         gpio_data |= led_color;
1476
1477         /* Set the modified gpio_data values */
1478         if (ha->pio_address) {
1479                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1480         } else {
1481                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1482                 RD_REG_WORD(&reg->gpiod);
1483         }
1484
1485         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1486 }
1487
1488 int
1489 qla2x00_beacon_on(struct scsi_qla_host *vha)
1490 {
1491         uint16_t gpio_enable;
1492         uint16_t gpio_data;
1493         unsigned long flags;
1494         struct qla_hw_data *ha = vha->hw;
1495         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1496
1497         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1498         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1499
1500         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1501                 ql_log(ql_log_warn, vha, 0x709b,
1502                     "Unable to update fw options (beacon on).\n");
1503                 return QLA_FUNCTION_FAILED;
1504         }
1505
1506         /* Turn off LEDs. */
1507         spin_lock_irqsave(&ha->hardware_lock, flags);
1508         if (ha->pio_address) {
1509                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1510                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1511         } else {
1512                 gpio_enable = RD_REG_WORD(&reg->gpioe);
1513                 gpio_data = RD_REG_WORD(&reg->gpiod);
1514         }
1515         gpio_enable |= GPIO_LED_MASK;
1516
1517         /* Set the modified gpio_enable values. */
1518         if (ha->pio_address) {
1519                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1520         } else {
1521                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1522                 RD_REG_WORD(&reg->gpioe);
1523         }
1524
1525         /* Clear out previously set LED colour. */
1526         gpio_data &= ~GPIO_LED_MASK;
1527         if (ha->pio_address) {
1528                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1529         } else {
1530                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1531                 RD_REG_WORD(&reg->gpiod);
1532         }
1533         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1534
1535         /*
1536          * Let the per HBA timer kick off the blinking process based on
1537          * the following flags. No need to do anything else now.
1538          */
1539         ha->beacon_blink_led = 1;
1540         ha->beacon_color_state = 0;
1541
1542         return QLA_SUCCESS;
1543 }
1544
1545 int
1546 qla2x00_beacon_off(struct scsi_qla_host *vha)
1547 {
1548         int rval = QLA_SUCCESS;
1549         struct qla_hw_data *ha = vha->hw;
1550
1551         ha->beacon_blink_led = 0;
1552
1553         /* Set the on flag so when it gets flipped it will be off. */
1554         if (IS_QLA2322(ha))
1555                 ha->beacon_color_state = QLA_LED_ALL_ON;
1556         else
1557                 ha->beacon_color_state = QLA_LED_GRN_ON;
1558
1559         ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1560
1561         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1562         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1563
1564         rval = qla2x00_set_fw_options(vha, ha->fw_options);
1565         if (rval != QLA_SUCCESS)
1566                 ql_log(ql_log_warn, vha, 0x709c,
1567                     "Unable to update fw options (beacon off).\n");
1568         return rval;
1569 }
1570
1571
1572 static inline void
1573 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1574 {
1575         /* Flip all colors. */
1576         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1577                 /* Turn off. */
1578                 ha->beacon_color_state = 0;
1579                 *pflags = 0;
1580         } else {
1581                 /* Turn on. */
1582                 ha->beacon_color_state = QLA_LED_ALL_ON;
1583                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1584         }
1585 }
1586
1587 void
1588 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1589 {
1590         uint16_t led_color = 0;
1591         uint32_t gpio_data;
1592         unsigned long flags;
1593         struct qla_hw_data *ha = vha->hw;
1594         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1595
1596         /* Save the Original GPIOD. */
1597         spin_lock_irqsave(&ha->hardware_lock, flags);
1598         gpio_data = RD_REG_DWORD(&reg->gpiod);
1599
1600         /* Enable the gpio_data reg for update. */
1601         gpio_data |= GPDX_LED_UPDATE_MASK;
1602
1603         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1604         gpio_data = RD_REG_DWORD(&reg->gpiod);
1605
1606         /* Set the color bits. */
1607         qla24xx_flip_colors(ha, &led_color);
1608
1609         /* Clear out any previously set LED color. */
1610         gpio_data &= ~GPDX_LED_COLOR_MASK;
1611
1612         /* Set the new input LED color to GPIOD. */
1613         gpio_data |= led_color;
1614
1615         /* Set the modified gpio_data values. */
1616         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1617         gpio_data = RD_REG_DWORD(&reg->gpiod);
1618         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1619 }
1620
1621 int
1622 qla24xx_beacon_on(struct scsi_qla_host *vha)
1623 {
1624         uint32_t gpio_data;
1625         unsigned long flags;
1626         struct qla_hw_data *ha = vha->hw;
1627         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1628
1629         if (IS_QLA82XX(ha))
1630                 return QLA_SUCCESS;
1631
1632         if (ha->beacon_blink_led == 0) {
1633                 /* Enable firmware for update */
1634                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1635
1636                 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1637                         return QLA_FUNCTION_FAILED;
1638
1639                 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1640                     QLA_SUCCESS) {
1641                         ql_log(ql_log_warn, vha, 0x7009,
1642                             "Unable to update fw options (beacon on).\n");
1643                         return QLA_FUNCTION_FAILED;
1644                 }
1645
1646                 spin_lock_irqsave(&ha->hardware_lock, flags);
1647                 gpio_data = RD_REG_DWORD(&reg->gpiod);
1648
1649                 /* Enable the gpio_data reg for update. */
1650                 gpio_data |= GPDX_LED_UPDATE_MASK;
1651                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1652                 RD_REG_DWORD(&reg->gpiod);
1653
1654                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1655         }
1656
1657         /* So all colors blink together. */
1658         ha->beacon_color_state = 0;
1659
1660         /* Let the per HBA timer kick off the blinking process. */
1661         ha->beacon_blink_led = 1;
1662
1663         return QLA_SUCCESS;
1664 }
1665
1666 int
1667 qla24xx_beacon_off(struct scsi_qla_host *vha)
1668 {
1669         uint32_t gpio_data;
1670         unsigned long flags;
1671         struct qla_hw_data *ha = vha->hw;
1672         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1673
1674         if (IS_QLA82XX(ha))
1675                 return QLA_SUCCESS;
1676
1677         ha->beacon_blink_led = 0;
1678         ha->beacon_color_state = QLA_LED_ALL_ON;
1679
1680         ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1681
1682         /* Give control back to firmware. */
1683         spin_lock_irqsave(&ha->hardware_lock, flags);
1684         gpio_data = RD_REG_DWORD(&reg->gpiod);
1685
1686         /* Disable the gpio_data reg for update. */
1687         gpio_data &= ~GPDX_LED_UPDATE_MASK;
1688         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1689         RD_REG_DWORD(&reg->gpiod);
1690         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1691
1692         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1693
1694         if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1695                 ql_log(ql_log_warn, vha, 0x704d,
1696                     "Unable to update fw options (beacon on).\n");
1697                 return QLA_FUNCTION_FAILED;
1698         }
1699
1700         if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1701                 ql_log(ql_log_warn, vha, 0x704e,
1702                     "Unable to update fw options (beacon on).\n");
1703                 return QLA_FUNCTION_FAILED;
1704         }
1705
1706         return QLA_SUCCESS;
1707 }
1708
1709
1710 /*
1711  * Flash support routines
1712  */
1713
1714 /**
1715  * qla2x00_flash_enable() - Setup flash for reading and writing.
1716  * @ha: HA context
1717  */
1718 static void
1719 qla2x00_flash_enable(struct qla_hw_data *ha)
1720 {
1721         uint16_t data;
1722         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1723
1724         data = RD_REG_WORD(&reg->ctrl_status);
1725         data |= CSR_FLASH_ENABLE;
1726         WRT_REG_WORD(&reg->ctrl_status, data);
1727         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1728 }
1729
1730 /**
1731  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1732  * @ha: HA context
1733  */
1734 static void
1735 qla2x00_flash_disable(struct qla_hw_data *ha)
1736 {
1737         uint16_t data;
1738         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1739
1740         data = RD_REG_WORD(&reg->ctrl_status);
1741         data &= ~(CSR_FLASH_ENABLE);
1742         WRT_REG_WORD(&reg->ctrl_status, data);
1743         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1744 }
1745
1746 /**
1747  * qla2x00_read_flash_byte() - Reads a byte from flash
1748  * @ha: HA context
1749  * @addr: Address in flash to read
1750  *
1751  * A word is read from the chip, but, only the lower byte is valid.
1752  *
1753  * Returns the byte read from flash @addr.
1754  */
1755 static uint8_t
1756 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1757 {
1758         uint16_t data;
1759         uint16_t bank_select;
1760         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1761
1762         bank_select = RD_REG_WORD(&reg->ctrl_status);
1763
1764         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1765                 /* Specify 64K address range: */
1766                 /*  clear out Module Select and Flash Address bits [19:16]. */
1767                 bank_select &= ~0xf8;
1768                 bank_select |= addr >> 12 & 0xf0;
1769                 bank_select |= CSR_FLASH_64K_BANK;
1770                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1771                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1772
1773                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1774                 data = RD_REG_WORD(&reg->flash_data);
1775
1776                 return (uint8_t)data;
1777         }
1778
1779         /* Setup bit 16 of flash address. */
1780         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1781                 bank_select |= CSR_FLASH_64K_BANK;
1782                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1783                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1784         } else if (((addr & BIT_16) == 0) &&
1785             (bank_select & CSR_FLASH_64K_BANK)) {
1786                 bank_select &= ~(CSR_FLASH_64K_BANK);
1787                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1788                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1789         }
1790
1791         /* Always perform IO mapped accesses to the FLASH registers. */
1792         if (ha->pio_address) {
1793                 uint16_t data2;
1794
1795                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1796                 do {
1797                         data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1798                         barrier();
1799                         cpu_relax();
1800                         data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1801                 } while (data != data2);
1802         } else {
1803                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1804                 data = qla2x00_debounce_register(&reg->flash_data);
1805         }
1806
1807         return (uint8_t)data;
1808 }
1809
1810 /**
1811  * qla2x00_write_flash_byte() - Write a byte to flash
1812  * @ha: HA context
1813  * @addr: Address in flash to write
1814  * @data: Data to write
1815  */
1816 static void
1817 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1818 {
1819         uint16_t bank_select;
1820         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1821
1822         bank_select = RD_REG_WORD(&reg->ctrl_status);
1823         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1824                 /* Specify 64K address range: */
1825                 /*  clear out Module Select and Flash Address bits [19:16]. */
1826                 bank_select &= ~0xf8;
1827                 bank_select |= addr >> 12 & 0xf0;
1828                 bank_select |= CSR_FLASH_64K_BANK;
1829                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1830                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1831
1832                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1833                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1834                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1835                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1836
1837                 return;
1838         }
1839
1840         /* Setup bit 16 of flash address. */
1841         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1842                 bank_select |= CSR_FLASH_64K_BANK;
1843                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1844                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1845         } else if (((addr & BIT_16) == 0) &&
1846             (bank_select & CSR_FLASH_64K_BANK)) {
1847                 bank_select &= ~(CSR_FLASH_64K_BANK);
1848                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1849                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1850         }
1851
1852         /* Always perform IO mapped accesses to the FLASH registers. */
1853         if (ha->pio_address) {
1854                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1855                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1856         } else {
1857                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1858                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1859                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1860                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1861         }
1862 }
1863
1864 /**
1865  * qla2x00_poll_flash() - Polls flash for completion.
1866  * @ha: HA context
1867  * @addr: Address in flash to poll
1868  * @poll_data: Data to be polled
1869  * @man_id: Flash manufacturer ID
1870  * @flash_id: Flash ID
1871  *
1872  * This function polls the device until bit 7 of what is read matches data
1873  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
1874  * out (a fatal error).  The flash book recommeds reading bit 7 again after
1875  * reading bit 5 as a 1.
1876  *
1877  * Returns 0 on success, else non-zero.
1878  */
1879 static int
1880 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
1881     uint8_t man_id, uint8_t flash_id)
1882 {
1883         int status;
1884         uint8_t flash_data;
1885         uint32_t cnt;
1886
1887         status = 1;
1888
1889         /* Wait for 30 seconds for command to finish. */
1890         poll_data &= BIT_7;
1891         for (cnt = 3000000; cnt; cnt--) {
1892                 flash_data = qla2x00_read_flash_byte(ha, addr);
1893                 if ((flash_data & BIT_7) == poll_data) {
1894                         status = 0;
1895                         break;
1896                 }
1897
1898                 if (man_id != 0x40 && man_id != 0xda) {
1899                         if ((flash_data & BIT_5) && cnt > 2)
1900                                 cnt = 2;
1901                 }
1902                 udelay(10);
1903                 barrier();
1904                 cond_resched();
1905         }
1906         return status;
1907 }
1908
1909 /**
1910  * qla2x00_program_flash_address() - Programs a flash address
1911  * @ha: HA context
1912  * @addr: Address in flash to program
1913  * @data: Data to be written in flash
1914  * @man_id: Flash manufacturer ID
1915  * @flash_id: Flash ID
1916  *
1917  * Returns 0 on success, else non-zero.
1918  */
1919 static int
1920 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1921     uint8_t data, uint8_t man_id, uint8_t flash_id)
1922 {
1923         /* Write Program Command Sequence. */
1924         if (IS_OEM_001(ha)) {
1925                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1926                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1927                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1928                 qla2x00_write_flash_byte(ha, addr, data);
1929         } else {
1930                 if (man_id == 0xda && flash_id == 0xc1) {
1931                         qla2x00_write_flash_byte(ha, addr, data);
1932                         if (addr & 0x7e)
1933                                 return 0;
1934                 } else {
1935                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1936                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1937                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1938                         qla2x00_write_flash_byte(ha, addr, data);
1939                 }
1940         }
1941
1942         udelay(150);
1943
1944         /* Wait for write to complete. */
1945         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1946 }
1947
1948 /**
1949  * qla2x00_erase_flash() - Erase the flash.
1950  * @ha: HA context
1951  * @man_id: Flash manufacturer ID
1952  * @flash_id: Flash ID
1953  *
1954  * Returns 0 on success, else non-zero.
1955  */
1956 static int
1957 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
1958 {
1959         /* Individual Sector Erase Command Sequence */
1960         if (IS_OEM_001(ha)) {
1961                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1962                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1963                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1964                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1965                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1966                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1967         } else {
1968                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1969                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1970                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1971                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1972                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1973                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1974         }
1975
1976         udelay(150);
1977
1978         /* Wait for erase to complete. */
1979         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1980 }
1981
1982 /**
1983  * qla2x00_erase_flash_sector() - Erase a flash sector.
1984  * @ha: HA context
1985  * @addr: Flash sector to erase
1986  * @sec_mask: Sector address mask
1987  * @man_id: Flash manufacturer ID
1988  * @flash_id: Flash ID
1989  *
1990  * Returns 0 on success, else non-zero.
1991  */
1992 static int
1993 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
1994     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1995 {
1996         /* Individual Sector Erase Command Sequence */
1997         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1998         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1999         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2000         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2001         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2002         if (man_id == 0x1f && flash_id == 0x13)
2003                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
2004         else
2005                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
2006
2007         udelay(150);
2008
2009         /* Wait for erase to complete. */
2010         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
2011 }
2012
2013 /**
2014  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
2015  * @man_id: Flash manufacturer ID
2016  * @flash_id: Flash ID
2017  */
2018 static void
2019 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
2020     uint8_t *flash_id)
2021 {
2022         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2023         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2024         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
2025         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
2026         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
2027         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2028         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2029         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
2030 }
2031
2032 static void
2033 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
2034         uint32_t saddr, uint32_t length)
2035 {
2036         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2037         uint32_t midpoint, ilength;
2038         uint8_t data;
2039
2040         midpoint = length / 2;
2041
2042         WRT_REG_WORD(&reg->nvram, 0);
2043         RD_REG_WORD(&reg->nvram);
2044         for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
2045                 if (ilength == midpoint) {
2046                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2047                         RD_REG_WORD(&reg->nvram);
2048                 }
2049                 data = qla2x00_read_flash_byte(ha, saddr);
2050                 if (saddr % 100)
2051                         udelay(10);
2052                 *tmp_buf = data;
2053                 cond_resched();
2054         }
2055 }
2056
2057 static inline void
2058 qla2x00_suspend_hba(struct scsi_qla_host *vha)
2059 {
2060         int cnt;
2061         unsigned long flags;
2062         struct qla_hw_data *ha = vha->hw;
2063         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2064
2065         /* Suspend HBA. */
2066         scsi_block_requests(vha->host);
2067         ha->isp_ops->disable_intrs(ha);
2068         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2069
2070         /* Pause RISC. */
2071         spin_lock_irqsave(&ha->hardware_lock, flags);
2072         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2073         RD_REG_WORD(&reg->hccr);
2074         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2075                 for (cnt = 0; cnt < 30000; cnt++) {
2076                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
2077                                 break;
2078                         udelay(100);
2079                 }
2080         } else {
2081                 udelay(10);
2082         }
2083         spin_unlock_irqrestore(&ha->hardware_lock, flags);
2084 }
2085
2086 static inline void
2087 qla2x00_resume_hba(struct scsi_qla_host *vha)
2088 {
2089         struct qla_hw_data *ha = vha->hw;
2090
2091         /* Resume HBA. */
2092         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2093         set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2094         qla2xxx_wake_dpc(vha);
2095         qla2x00_wait_for_chip_reset(vha);
2096         scsi_unblock_requests(vha->host);
2097 }
2098
2099 uint8_t *
2100 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2101     uint32_t offset, uint32_t length)
2102 {
2103         uint32_t addr, midpoint;
2104         uint8_t *data;
2105         struct qla_hw_data *ha = vha->hw;
2106         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2107
2108         /* Suspend HBA. */
2109         qla2x00_suspend_hba(vha);
2110
2111         /* Go with read. */
2112         midpoint = ha->optrom_size / 2;
2113
2114         qla2x00_flash_enable(ha);
2115         WRT_REG_WORD(&reg->nvram, 0);
2116         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
2117         for (addr = offset, data = buf; addr < length; addr++, data++) {
2118                 if (addr == midpoint) {
2119                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2120                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
2121                 }
2122
2123                 *data = qla2x00_read_flash_byte(ha, addr);
2124         }
2125         qla2x00_flash_disable(ha);
2126
2127         /* Resume HBA. */
2128         qla2x00_resume_hba(vha);
2129
2130         return buf;
2131 }
2132
2133 int
2134 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2135     uint32_t offset, uint32_t length)
2136 {
2137
2138         int rval;
2139         uint8_t man_id, flash_id, sec_number, data;
2140         uint16_t wd;
2141         uint32_t addr, liter, sec_mask, rest_addr;
2142         struct qla_hw_data *ha = vha->hw;
2143         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2144
2145         /* Suspend HBA. */
2146         qla2x00_suspend_hba(vha);
2147
2148         rval = QLA_SUCCESS;
2149         sec_number = 0;
2150
2151         /* Reset ISP chip. */
2152         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2153         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2154
2155         /* Go with write. */
2156         qla2x00_flash_enable(ha);
2157         do {    /* Loop once to provide quick error exit */
2158                 /* Structure of flash memory based on manufacturer */
2159                 if (IS_OEM_001(ha)) {
2160                         /* OEM variant with special flash part. */
2161                         man_id = flash_id = 0;
2162                         rest_addr = 0xffff;
2163                         sec_mask   = 0x10000;
2164                         goto update_flash;
2165                 }
2166                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2167                 switch (man_id) {
2168                 case 0x20: /* ST flash. */
2169                         if (flash_id == 0xd2 || flash_id == 0xe3) {
2170                                 /*
2171                                  * ST m29w008at part - 64kb sector size with
2172                                  * 32kb,8kb,8kb,16kb sectors at memory address
2173                                  * 0xf0000.
2174                                  */
2175                                 rest_addr = 0xffff;
2176                                 sec_mask = 0x10000;
2177                                 break;
2178                         }
2179                         /*
2180                          * ST m29w010b part - 16kb sector size
2181                          * Default to 16kb sectors
2182                          */
2183                         rest_addr = 0x3fff;
2184                         sec_mask = 0x1c000;
2185                         break;
2186                 case 0x40: /* Mostel flash. */
2187                         /* Mostel v29c51001 part - 512 byte sector size. */
2188                         rest_addr = 0x1ff;
2189                         sec_mask = 0x1fe00;
2190                         break;
2191                 case 0xbf: /* SST flash. */
2192                         /* SST39sf10 part - 4kb sector size. */
2193                         rest_addr = 0xfff;
2194                         sec_mask = 0x1f000;
2195                         break;
2196                 case 0xda: /* Winbond flash. */
2197                         /* Winbond W29EE011 part - 256 byte sector size. */
2198                         rest_addr = 0x7f;
2199                         sec_mask = 0x1ff80;
2200                         break;
2201                 case 0xc2: /* Macronix flash. */
2202                         /* 64k sector size. */
2203                         if (flash_id == 0x38 || flash_id == 0x4f) {
2204                                 rest_addr = 0xffff;
2205                                 sec_mask = 0x10000;
2206                                 break;
2207                         }
2208                         /* Fall through... */
2209
2210                 case 0x1f: /* Atmel flash. */
2211                         /* 512k sector size. */
2212                         if (flash_id == 0x13) {
2213                                 rest_addr = 0x7fffffff;
2214                                 sec_mask =   0x80000000;
2215                                 break;
2216                         }
2217                         /* Fall through... */
2218
2219                 case 0x01: /* AMD flash. */
2220                         if (flash_id == 0x38 || flash_id == 0x40 ||
2221                             flash_id == 0x4f) {
2222                                 /* Am29LV081 part - 64kb sector size. */
2223                                 /* Am29LV002BT part - 64kb sector size. */
2224                                 rest_addr = 0xffff;
2225                                 sec_mask = 0x10000;
2226                                 break;
2227                         } else if (flash_id == 0x3e) {
2228                                 /*
2229                                  * Am29LV008b part - 64kb sector size with
2230                                  * 32kb,8kb,8kb,16kb sector at memory address
2231                                  * h0xf0000.
2232                                  */
2233                                 rest_addr = 0xffff;
2234                                 sec_mask = 0x10000;
2235                                 break;
2236                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
2237                                 /*
2238                                  * Am29LV010 part or AM29f010 - 16kb sector
2239                                  * size.
2240                                  */
2241                                 rest_addr = 0x3fff;
2242                                 sec_mask = 0x1c000;
2243                                 break;
2244                         } else if (flash_id == 0x6d) {
2245                                 /* Am29LV001 part - 8kb sector size. */
2246                                 rest_addr = 0x1fff;
2247                                 sec_mask = 0x1e000;
2248                                 break;
2249                         }
2250                 default:
2251                         /* Default to 16 kb sector size. */
2252                         rest_addr = 0x3fff;
2253                         sec_mask = 0x1c000;
2254                         break;
2255                 }
2256
2257 update_flash:
2258                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2259                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2260                                 rval = QLA_FUNCTION_FAILED;
2261                                 break;
2262                         }
2263                 }
2264
2265                 for (addr = offset, liter = 0; liter < length; liter++,
2266                     addr++) {
2267                         data = buf[liter];
2268                         /* Are we at the beginning of a sector? */
2269                         if ((addr & rest_addr) == 0) {
2270                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2271                                         if (addr >= 0x10000UL) {
2272                                                 if (((addr >> 12) & 0xf0) &&
2273                                                     ((man_id == 0x01 &&
2274                                                         flash_id == 0x3e) ||
2275                                                      (man_id == 0x20 &&
2276                                                          flash_id == 0xd2))) {
2277                                                         sec_number++;
2278                                                         if (sec_number == 1) {
2279                                                                 rest_addr =
2280                                                                     0x7fff;
2281                                                                 sec_mask =
2282                                                                     0x18000;
2283                                                         } else if (
2284                                                             sec_number == 2 ||
2285                                                             sec_number == 3) {
2286                                                                 rest_addr =
2287                                                                     0x1fff;
2288                                                                 sec_mask =
2289                                                                     0x1e000;
2290                                                         } else if (
2291                                                             sec_number == 4) {
2292                                                                 rest_addr =
2293                                                                     0x3fff;
2294                                                                 sec_mask =
2295                                                                     0x1c000;
2296                                                         }
2297                                                 }
2298                                         }
2299                                 } else if (addr == ha->optrom_size / 2) {
2300                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2301                                         RD_REG_WORD(&reg->nvram);
2302                                 }
2303
2304                                 if (flash_id == 0xda && man_id == 0xc1) {
2305                                         qla2x00_write_flash_byte(ha, 0x5555,
2306                                             0xaa);
2307                                         qla2x00_write_flash_byte(ha, 0x2aaa,
2308                                             0x55);
2309                                         qla2x00_write_flash_byte(ha, 0x5555,
2310                                             0xa0);
2311                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2312                                         /* Then erase it */
2313                                         if (qla2x00_erase_flash_sector(ha,
2314                                             addr, sec_mask, man_id,
2315                                             flash_id)) {
2316                                                 rval = QLA_FUNCTION_FAILED;
2317                                                 break;
2318                                         }
2319                                         if (man_id == 0x01 && flash_id == 0x6d)
2320                                                 sec_number++;
2321                                 }
2322                         }
2323
2324                         if (man_id == 0x01 && flash_id == 0x6d) {
2325                                 if (sec_number == 1 &&
2326                                     addr == (rest_addr - 1)) {
2327                                         rest_addr = 0x0fff;
2328                                         sec_mask   = 0x1f000;
2329                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2330                                         rest_addr = 0x3fff;
2331                                         sec_mask   = 0x1c000;
2332                                 }
2333                         }
2334
2335                         if (qla2x00_program_flash_address(ha, addr, data,
2336                             man_id, flash_id)) {
2337                                 rval = QLA_FUNCTION_FAILED;
2338                                 break;
2339                         }
2340                         cond_resched();
2341                 }
2342         } while (0);
2343         qla2x00_flash_disable(ha);
2344
2345         /* Resume HBA. */
2346         qla2x00_resume_hba(vha);
2347
2348         return rval;
2349 }
2350
2351 uint8_t *
2352 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2353     uint32_t offset, uint32_t length)
2354 {
2355         struct qla_hw_data *ha = vha->hw;
2356
2357         /* Suspend HBA. */
2358         scsi_block_requests(vha->host);
2359         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2360
2361         /* Go with read. */
2362         qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2363
2364         /* Resume HBA. */
2365         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2366         scsi_unblock_requests(vha->host);
2367
2368         return buf;
2369 }
2370
2371 int
2372 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2373     uint32_t offset, uint32_t length)
2374 {
2375         int rval;
2376         struct qla_hw_data *ha = vha->hw;
2377
2378         /* Suspend HBA. */
2379         scsi_block_requests(vha->host);
2380         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2381
2382         /* Go with write. */
2383         rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2384             length >> 2);
2385
2386         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2387         scsi_unblock_requests(vha->host);
2388
2389         return rval;
2390 }
2391
2392 uint8_t *
2393 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2394     uint32_t offset, uint32_t length)
2395 {
2396         int rval;
2397         dma_addr_t optrom_dma;
2398         void *optrom;
2399         uint8_t *pbuf;
2400         uint32_t faddr, left, burst;
2401         struct qla_hw_data *ha = vha->hw;
2402
2403         if (IS_QLA25XX(ha) || IS_QLA81XX(ha))
2404                 goto try_fast;
2405         if (offset & 0xfff)
2406                 goto slow_read;
2407         if (length < OPTROM_BURST_SIZE)
2408                 goto slow_read;
2409
2410 try_fast:
2411         optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2412             &optrom_dma, GFP_KERNEL);
2413         if (!optrom) {
2414                 ql_log(ql_log_warn, vha, 0x00cc,
2415                     "Unable to allocate memory for optrom burst read (%x KB).\n",
2416                     OPTROM_BURST_SIZE / 1024);
2417                 goto slow_read;
2418         }
2419
2420         pbuf = buf;
2421         faddr = offset >> 2;
2422         left = length >> 2;
2423         burst = OPTROM_BURST_DWORDS;
2424         while (left != 0) {
2425                 if (burst > left)
2426                         burst = left;
2427
2428                 rval = qla2x00_dump_ram(vha, optrom_dma,
2429                     flash_data_addr(ha, faddr), burst);
2430                 if (rval) {
2431                         ql_log(ql_log_warn, vha, 0x00f5,
2432                             "Unable to burst-read optrom segment (%x/%x/%llx).\n",
2433                             rval, flash_data_addr(ha, faddr),
2434                             (unsigned long long)optrom_dma);
2435                         ql_log(ql_log_warn, vha, 0x00f6,
2436                             "Reverting to slow-read.\n");
2437
2438                         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2439                             optrom, optrom_dma);
2440                         goto slow_read;
2441                 }
2442
2443                 memcpy(pbuf, optrom, burst * 4);
2444
2445                 left -= burst;
2446                 faddr += burst;
2447                 pbuf += burst * 4;
2448         }
2449
2450         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2451             optrom_dma);
2452
2453         return buf;
2454
2455 slow_read:
2456     return qla24xx_read_optrom_data(vha, buf, offset, length);
2457 }
2458
2459 /**
2460  * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2461  * @ha: HA context
2462  * @pcids: Pointer to the FCODE PCI data structure
2463  *
2464  * The process of retrieving the FCODE version information is at best
2465  * described as interesting.
2466  *
2467  * Within the first 100h bytes of the image an ASCII string is present
2468  * which contains several pieces of information including the FCODE
2469  * version.  Unfortunately it seems the only reliable way to retrieve
2470  * the version is by scanning for another sentinel within the string,
2471  * the FCODE build date:
2472  *
2473  *      ... 2.00.02 10/17/02 ...
2474  *
2475  * Returns QLA_SUCCESS on successful retrieval of version.
2476  */
2477 static void
2478 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2479 {
2480         int ret = QLA_FUNCTION_FAILED;
2481         uint32_t istart, iend, iter, vend;
2482         uint8_t do_next, rbyte, *vbyte;
2483
2484         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2485
2486         /* Skip the PCI data structure. */
2487         istart = pcids +
2488             ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2489                 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2490         iend = istart + 0x100;
2491         do {
2492                 /* Scan for the sentinel date string...eeewww. */
2493                 do_next = 0;
2494                 iter = istart;
2495                 while ((iter < iend) && !do_next) {
2496                         iter++;
2497                         if (qla2x00_read_flash_byte(ha, iter) == '/') {
2498                                 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2499                                     '/')
2500                                         do_next++;
2501                                 else if (qla2x00_read_flash_byte(ha,
2502                                     iter + 3) == '/')
2503                                         do_next++;
2504                         }
2505                 }
2506                 if (!do_next)
2507                         break;
2508
2509                 /* Backtrack to previous ' ' (space). */
2510                 do_next = 0;
2511                 while ((iter > istart) && !do_next) {
2512                         iter--;
2513                         if (qla2x00_read_flash_byte(ha, iter) == ' ')
2514                                 do_next++;
2515                 }
2516                 if (!do_next)
2517                         break;
2518
2519                 /*
2520                  * Mark end of version tag, and find previous ' ' (space) or
2521                  * string length (recent FCODE images -- major hack ahead!!!).
2522                  */
2523                 vend = iter - 1;
2524                 do_next = 0;
2525                 while ((iter > istart) && !do_next) {
2526                         iter--;
2527                         rbyte = qla2x00_read_flash_byte(ha, iter);
2528                         if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2529                                 do_next++;
2530                 }
2531                 if (!do_next)
2532                         break;
2533
2534                 /* Mark beginning of version tag, and copy data. */
2535                 iter++;
2536                 if ((vend - iter) &&
2537                     ((vend - iter) < sizeof(ha->fcode_revision))) {
2538                         vbyte = ha->fcode_revision;
2539                         while (iter <= vend) {
2540                                 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2541                                 iter++;
2542                         }
2543                         ret = QLA_SUCCESS;
2544                 }
2545         } while (0);
2546
2547         if (ret != QLA_SUCCESS)
2548                 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2549 }
2550
2551 int
2552 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2553 {
2554         int ret = QLA_SUCCESS;
2555         uint8_t code_type, last_image;
2556         uint32_t pcihdr, pcids;
2557         uint8_t *dbyte;
2558         uint16_t *dcode;
2559         struct qla_hw_data *ha = vha->hw;
2560
2561         if (!ha->pio_address || !mbuf)
2562                 return QLA_FUNCTION_FAILED;
2563
2564         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2565         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2566         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2567         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2568
2569         qla2x00_flash_enable(ha);
2570
2571         /* Begin with first PCI expansion ROM header. */
2572         pcihdr = 0;
2573         last_image = 1;
2574         do {
2575                 /* Verify PCI expansion ROM header. */
2576                 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2577                     qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2578                         /* No signature */
2579                         ql_log(ql_log_fatal, vha, 0x0050,
2580                             "No matching ROM signature.\n");
2581                         ret = QLA_FUNCTION_FAILED;
2582                         break;
2583                 }
2584
2585                 /* Locate PCI data structure. */
2586                 pcids = pcihdr +
2587                     ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2588                         qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2589
2590                 /* Validate signature of PCI data structure. */
2591                 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2592                     qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2593                     qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2594                     qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2595                         /* Incorrect header. */
2596                         ql_log(ql_log_fatal, vha, 0x0051,
2597                             "PCI data struct not found pcir_adr=%x.\n", pcids);
2598                         ret = QLA_FUNCTION_FAILED;
2599                         break;
2600                 }
2601
2602                 /* Read version */
2603                 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2604                 switch (code_type) {
2605                 case ROM_CODE_TYPE_BIOS:
2606                         /* Intel x86, PC-AT compatible. */
2607                         ha->bios_revision[0] =
2608                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2609                         ha->bios_revision[1] =
2610                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2611                         ql_dbg(ql_dbg_init, vha, 0x0052,
2612                             "Read BIOS %d.%d.\n",
2613                             ha->bios_revision[1], ha->bios_revision[0]);
2614                         break;
2615                 case ROM_CODE_TYPE_FCODE:
2616                         /* Open Firmware standard for PCI (FCode). */
2617                         /* Eeeewww... */
2618                         qla2x00_get_fcode_version(ha, pcids);
2619                         break;
2620                 case ROM_CODE_TYPE_EFI:
2621                         /* Extensible Firmware Interface (EFI). */
2622                         ha->efi_revision[0] =
2623                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2624                         ha->efi_revision[1] =
2625                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2626                         ql_dbg(ql_dbg_init, vha, 0x0053,
2627                             "Read EFI %d.%d.\n",
2628                             ha->efi_revision[1], ha->efi_revision[0]);
2629                         break;
2630                 default:
2631                         ql_log(ql_log_warn, vha, 0x0054,
2632                             "Unrecognized code type %x at pcids %x.\n",
2633                             code_type, pcids);
2634                         break;
2635                 }
2636
2637                 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2638
2639                 /* Locate next PCI expansion ROM. */
2640                 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2641                     qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2642         } while (!last_image);
2643
2644         if (IS_QLA2322(ha)) {
2645                 /* Read firmware image information. */
2646                 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2647                 dbyte = mbuf;
2648                 memset(dbyte, 0, 8);
2649                 dcode = (uint16_t *)dbyte;
2650
2651                 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2652                     8);
2653                 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a,
2654                     "Dumping fw "
2655                     "ver from flash:.\n");
2656                 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
2657                     (uint8_t *)dbyte, 8);
2658
2659                 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2660                     dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2661                     (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2662                     dcode[3] == 0)) {
2663                         ql_log(ql_log_warn, vha, 0x0057,
2664                             "Unrecognized fw revision at %x.\n",
2665                             ha->flt_region_fw * 4);
2666                 } else {
2667                         /* values are in big endian */
2668                         ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2669                         ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2670                         ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2671                         ql_dbg(ql_dbg_init, vha, 0x0058,
2672                             "FW Version: "
2673                             "%d.%d.%d.\n", ha->fw_revision[0],
2674                             ha->fw_revision[1], ha->fw_revision[2]);
2675                 }
2676         }
2677
2678         qla2x00_flash_disable(ha);
2679
2680         return ret;
2681 }
2682
2683 int
2684 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2685 {
2686         int ret = QLA_SUCCESS;
2687         uint32_t pcihdr, pcids;
2688         uint32_t *dcode;
2689         uint8_t *bcode;
2690         uint8_t code_type, last_image;
2691         int i;
2692         struct qla_hw_data *ha = vha->hw;
2693
2694         if (IS_QLA82XX(ha))
2695                 return ret;
2696
2697         if (!mbuf)
2698                 return QLA_FUNCTION_FAILED;
2699
2700         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2701         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2702         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2703         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2704
2705         dcode = mbuf;
2706
2707         /* Begin with first PCI expansion ROM header. */
2708         pcihdr = ha->flt_region_boot << 2;
2709         last_image = 1;
2710         do {
2711                 /* Verify PCI expansion ROM header. */
2712                 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2713                 bcode = mbuf + (pcihdr % 4);
2714                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2715                         /* No signature */
2716                         ql_log(ql_log_fatal, vha, 0x0059,
2717                             "No matching ROM signature.\n");
2718                         ret = QLA_FUNCTION_FAILED;
2719                         break;
2720                 }
2721
2722                 /* Locate PCI data structure. */
2723                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2724
2725                 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2726                 bcode = mbuf + (pcihdr % 4);
2727
2728                 /* Validate signature of PCI data structure. */
2729                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2730                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2731                         /* Incorrect header. */
2732                         ql_log(ql_log_fatal, vha, 0x005a,
2733                             "PCI data struct not found pcir_adr=%x.\n", pcids);
2734                         ret = QLA_FUNCTION_FAILED;
2735                         break;
2736                 }
2737
2738                 /* Read version */
2739                 code_type = bcode[0x14];
2740                 switch (code_type) {
2741                 case ROM_CODE_TYPE_BIOS:
2742                         /* Intel x86, PC-AT compatible. */
2743                         ha->bios_revision[0] = bcode[0x12];
2744                         ha->bios_revision[1] = bcode[0x13];
2745                         ql_dbg(ql_dbg_init, vha, 0x005b,
2746                             "Read BIOS %d.%d.\n",
2747                             ha->bios_revision[1], ha->bios_revision[0]);
2748                         break;
2749                 case ROM_CODE_TYPE_FCODE:
2750                         /* Open Firmware standard for PCI (FCode). */
2751                         ha->fcode_revision[0] = bcode[0x12];
2752                         ha->fcode_revision[1] = bcode[0x13];
2753                         ql_dbg(ql_dbg_init, vha, 0x005c,
2754                             "Read FCODE %d.%d.\n",
2755                             ha->fcode_revision[1], ha->fcode_revision[0]);
2756                         break;
2757                 case ROM_CODE_TYPE_EFI:
2758                         /* Extensible Firmware Interface (EFI). */
2759                         ha->efi_revision[0] = bcode[0x12];
2760                         ha->efi_revision[1] = bcode[0x13];
2761                         ql_dbg(ql_dbg_init, vha, 0x005d,
2762                             "Read EFI %d.%d.\n",
2763                             ha->efi_revision[1], ha->efi_revision[0]);
2764                         break;
2765                 default:
2766                         ql_log(ql_log_warn, vha, 0x005e,
2767                             "Unrecognized code type %x at pcids %x.\n",
2768                             code_type, pcids);
2769                         break;
2770                 }
2771
2772                 last_image = bcode[0x15] & BIT_7;
2773
2774                 /* Locate next PCI expansion ROM. */
2775                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2776         } while (!last_image);
2777
2778         /* Read firmware image information. */
2779         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2780         dcode = mbuf;
2781
2782         qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2783         for (i = 0; i < 4; i++)
2784                 dcode[i] = be32_to_cpu(dcode[i]);
2785
2786         if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2787             dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2788             (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2789             dcode[3] == 0)) {
2790                 ql_log(ql_log_warn, vha, 0x005f,
2791                     "Unrecognized fw revision at %x.\n",
2792                     ha->flt_region_fw * 4);
2793         } else {
2794                 ha->fw_revision[0] = dcode[0];
2795                 ha->fw_revision[1] = dcode[1];
2796                 ha->fw_revision[2] = dcode[2];
2797                 ha->fw_revision[3] = dcode[3];
2798                 ql_dbg(ql_dbg_init, vha, 0x0060,
2799                     "Firmware revision %d.%d.%d.%d.\n",
2800                     ha->fw_revision[0], ha->fw_revision[1],
2801                     ha->fw_revision[2], ha->fw_revision[3]);
2802         }
2803
2804         /* Check for golden firmware and get version if available */
2805         if (!IS_QLA81XX(ha)) {
2806                 /* Golden firmware is not present in non 81XX adapters */
2807                 return ret;
2808         }
2809
2810         memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
2811         dcode = mbuf;
2812         ha->isp_ops->read_optrom(vha, (uint8_t *)dcode,
2813             ha->flt_region_gold_fw << 2, 32);
2814
2815         if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF &&
2816             dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) {
2817                 ql_log(ql_log_warn, vha, 0x0056,
2818                     "Unrecognized golden fw at 0x%x.\n",
2819                     ha->flt_region_gold_fw * 4);
2820                 return ret;
2821         }
2822
2823         for (i = 4; i < 8; i++)
2824                 ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]);
2825
2826         return ret;
2827 }
2828
2829 static int
2830 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2831 {
2832         if (pos >= end || *pos != 0x82)
2833                 return 0;
2834
2835         pos += 3 + pos[1];
2836         if (pos >= end || *pos != 0x90)
2837                 return 0;
2838
2839         pos += 3 + pos[1];
2840         if (pos >= end || *pos != 0x78)
2841                 return 0;
2842
2843         return 1;
2844 }
2845
2846 int
2847 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2848 {
2849         struct qla_hw_data *ha = vha->hw;
2850         uint8_t *pos = ha->vpd;
2851         uint8_t *end = pos + ha->vpd_size;
2852         int len = 0;
2853
2854         if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2855                 return 0;
2856
2857         while (pos < end && *pos != 0x78) {
2858                 len = (*pos == 0x82) ? pos[1] : pos[2];
2859
2860                 if (!strncmp(pos, key, strlen(key)))
2861                         break;
2862
2863                 if (*pos != 0x90 && *pos != 0x91)
2864                         pos += len;
2865
2866                 pos += 3;
2867         }
2868
2869         if (pos < end - len && *pos != 0x78)
2870                 return snprintf(str, size, "%.*s", len, pos + 3);
2871
2872         return 0;
2873 }
2874
2875 int
2876 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
2877 {
2878         int len, max_len;
2879         uint32_t fcp_prio_addr;
2880         struct qla_hw_data *ha = vha->hw;
2881
2882         if (!ha->fcp_prio_cfg) {
2883                 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE);
2884                 if (!ha->fcp_prio_cfg) {
2885                         ql_log(ql_log_warn, vha, 0x00d5,
2886                             "Unable to allocate memory for fcp priorty data (%x).\n",
2887                             FCP_PRIO_CFG_SIZE);
2888                         return QLA_FUNCTION_FAILED;
2889                 }
2890         }
2891         memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE);
2892
2893         fcp_prio_addr = ha->flt_region_fcp_prio;
2894
2895         /* first read the fcp priority data header from flash */
2896         ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg,
2897                         fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
2898
2899         if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0))
2900                 goto fail;
2901
2902         /* read remaining FCP CMD config data from flash */
2903         fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
2904         len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE;
2905         max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
2906
2907         ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0],
2908                         fcp_prio_addr << 2, (len < max_len ? len : max_len));
2909
2910         /* revalidate the entire FCP priority config data, including entries */
2911         if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1))
2912                 goto fail;
2913
2914         ha->flags.fcp_prio_enabled = 1;
2915         return QLA_SUCCESS;
2916 fail:
2917         vfree(ha->fcp_prio_cfg);
2918         ha->fcp_prio_cfg = NULL;
2919         return QLA_FUNCTION_FAILED;
2920 }