3 * Linux MegaRAID driver for SAS based RAID controllers
5 * Copyright (c) 2003-2005 LSI Corporation.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
12 * FILE : megaraid_sas.h
15 #ifndef LSI_MEGARAID_SAS_H
16 #define LSI_MEGARAID_SAS_H
19 * MegaRAID SAS Driver meta data
21 #define MEGASAS_VERSION "00.00.04.31-rc1"
22 #define MEGASAS_RELDATE "May 3, 2010"
23 #define MEGASAS_EXT_VERSION "Mon. May 3, 11:41:51 PST 2010"
28 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
29 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
30 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
31 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
32 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
33 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
34 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
37 * =====================================
38 * MegaRAID SAS MFI firmware definitions
39 * =====================================
43 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
44 * protocol between the software and firmware. Commands are issued using
49 * FW posts its state in upper 4 bits of outbound_msg_0 register
51 #define MFI_STATE_MASK 0xF0000000
52 #define MFI_STATE_UNDEFINED 0x00000000
53 #define MFI_STATE_BB_INIT 0x10000000
54 #define MFI_STATE_FW_INIT 0x40000000
55 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
56 #define MFI_STATE_FW_INIT_2 0x70000000
57 #define MFI_STATE_DEVICE_SCAN 0x80000000
58 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
59 #define MFI_STATE_FLUSH_CACHE 0xA0000000
60 #define MFI_STATE_READY 0xB0000000
61 #define MFI_STATE_OPERATIONAL 0xC0000000
62 #define MFI_STATE_FAULT 0xF0000000
63 #define MFI_RESET_REQUIRED 0x00000001
65 #define MEGAMFI_FRAME_SIZE 64
68 * During FW init, clear pending cmds & reset state using inbound_msg_0
70 * ABORT : Abort all pending cmds
71 * READY : Move from OPERATIONAL to READY state; discard queue info
72 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
73 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
74 * HOTPLUG : Resume from Hotplug
75 * MFI_STOP_ADP : Send signal to FW to stop processing
77 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
78 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
79 #define DIAG_WRITE_ENABLE (0x00000080)
80 #define DIAG_RESET_ADAPTER (0x00000004)
82 #define MFI_ADP_RESET 0x00000040
83 #define MFI_INIT_ABORT 0x00000001
84 #define MFI_INIT_READY 0x00000002
85 #define MFI_INIT_MFIMODE 0x00000004
86 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
87 #define MFI_INIT_HOTPLUG 0x00000010
88 #define MFI_STOP_ADP 0x00000020
89 #define MFI_RESET_FLAGS MFI_INIT_READY| \
96 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
97 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
98 #define MFI_FRAME_SGL32 0x0000
99 #define MFI_FRAME_SGL64 0x0002
100 #define MFI_FRAME_SENSE32 0x0000
101 #define MFI_FRAME_SENSE64 0x0004
102 #define MFI_FRAME_DIR_NONE 0x0000
103 #define MFI_FRAME_DIR_WRITE 0x0008
104 #define MFI_FRAME_DIR_READ 0x0010
105 #define MFI_FRAME_DIR_BOTH 0x0018
106 #define MFI_FRAME_IEEE 0x0020
109 * Definition for cmd_status
111 #define MFI_CMD_STATUS_POLL_MODE 0xFF
114 * MFI command opcodes
116 #define MFI_CMD_INIT 0x00
117 #define MFI_CMD_LD_READ 0x01
118 #define MFI_CMD_LD_WRITE 0x02
119 #define MFI_CMD_LD_SCSI_IO 0x03
120 #define MFI_CMD_PD_SCSI_IO 0x04
121 #define MFI_CMD_DCMD 0x05
122 #define MFI_CMD_ABORT 0x06
123 #define MFI_CMD_SMP 0x07
124 #define MFI_CMD_STP 0x08
126 #define MR_DCMD_CTRL_GET_INFO 0x01010000
127 #define MR_DCMD_LD_GET_LIST 0x03010000
129 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
130 #define MR_FLUSH_CTRL_CACHE 0x01
131 #define MR_FLUSH_DISK_CACHE 0x02
133 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
134 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
135 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
137 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
138 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
139 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
140 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
142 #define MR_DCMD_CLUSTER 0x08000000
143 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
144 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
145 #define MR_DCMD_PD_LIST_QUERY 0x02010100
148 * MFI command completion codes
152 MFI_STAT_INVALID_CMD = 0x01,
153 MFI_STAT_INVALID_DCMD = 0x02,
154 MFI_STAT_INVALID_PARAMETER = 0x03,
155 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
156 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
157 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
158 MFI_STAT_APP_IN_USE = 0x07,
159 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
160 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
161 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
162 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
163 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
164 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
165 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
166 MFI_STAT_FLASH_BUSY = 0x0f,
167 MFI_STAT_FLASH_ERROR = 0x10,
168 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
169 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
170 MFI_STAT_FLASH_NOT_OPEN = 0x13,
171 MFI_STAT_FLASH_NOT_STARTED = 0x14,
172 MFI_STAT_FLUSH_FAILED = 0x15,
173 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
174 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
175 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
176 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
177 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
178 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
179 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
180 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
181 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
182 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
183 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
184 MFI_STAT_MFC_HW_ERROR = 0x21,
185 MFI_STAT_NO_HW_PRESENT = 0x22,
186 MFI_STAT_NOT_FOUND = 0x23,
187 MFI_STAT_NOT_IN_ENCL = 0x24,
188 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
189 MFI_STAT_PD_TYPE_WRONG = 0x26,
190 MFI_STAT_PR_DISABLED = 0x27,
191 MFI_STAT_ROW_INDEX_INVALID = 0x28,
192 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
193 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
194 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
195 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
196 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
197 MFI_STAT_SCSI_IO_FAILED = 0x2e,
198 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
199 MFI_STAT_SHUTDOWN_FAILED = 0x30,
200 MFI_STAT_TIME_NOT_SET = 0x31,
201 MFI_STAT_WRONG_STATE = 0x32,
202 MFI_STAT_LD_OFFLINE = 0x33,
203 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
204 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
205 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
206 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
207 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
209 MFI_STAT_INVALID_STATUS = 0xFF
213 * Number of mailbox bytes in DCMD message frame
215 #define MFI_MBOX_SIZE 12
219 MR_EVT_CLASS_DEBUG = -2,
220 MR_EVT_CLASS_PROGRESS = -1,
221 MR_EVT_CLASS_INFO = 0,
222 MR_EVT_CLASS_WARNING = 1,
223 MR_EVT_CLASS_CRITICAL = 2,
224 MR_EVT_CLASS_FATAL = 3,
225 MR_EVT_CLASS_DEAD = 4,
231 MR_EVT_LOCALE_LD = 0x0001,
232 MR_EVT_LOCALE_PD = 0x0002,
233 MR_EVT_LOCALE_ENCL = 0x0004,
234 MR_EVT_LOCALE_BBU = 0x0008,
235 MR_EVT_LOCALE_SAS = 0x0010,
236 MR_EVT_LOCALE_CTRL = 0x0020,
237 MR_EVT_LOCALE_CONFIG = 0x0040,
238 MR_EVT_LOCALE_CLUSTER = 0x0080,
239 MR_EVT_LOCALE_ALL = 0xffff,
246 MR_EVT_ARGS_CDB_SENSE,
248 MR_EVT_ARGS_LD_COUNT,
250 MR_EVT_ARGS_LD_OWNER,
251 MR_EVT_ARGS_LD_LBA_PD_LBA,
253 MR_EVT_ARGS_LD_STATE,
254 MR_EVT_ARGS_LD_STRIP,
258 MR_EVT_ARGS_PD_LBA_LD,
260 MR_EVT_ARGS_PD_STATE,
267 MR_EVT_ARGS_PD_SPARE,
268 MR_EVT_ARGS_PD_INDEX,
269 MR_EVT_ARGS_DIAG_PASS,
270 MR_EVT_ARGS_DIAG_FAIL,
271 MR_EVT_ARGS_PD_LBA_LBA,
272 MR_EVT_ARGS_PORT_PHY,
273 MR_EVT_ARGS_PD_MISSING,
274 MR_EVT_ARGS_PD_ADDRESS,
276 MR_EVT_ARGS_CONNECTOR,
279 MR_EVT_ARGS_PD_PATHINFO,
280 MR_EVT_ARGS_PD_POWER_STATE,
285 * define constants for device list query options
287 enum MR_PD_QUERY_TYPE {
288 MR_PD_QUERY_TYPE_ALL = 0,
289 MR_PD_QUERY_TYPE_STATE = 1,
290 MR_PD_QUERY_TYPE_POWER_STATE = 2,
291 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
292 MR_PD_QUERY_TYPE_SPEED = 4,
293 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
296 #define MR_EVT_CFG_CLEARED 0x0004
297 #define MR_EVT_LD_STATE_CHANGE 0x0051
298 #define MR_EVT_PD_INSERTED 0x005b
299 #define MR_EVT_PD_REMOVED 0x0070
300 #define MR_EVT_LD_CREATED 0x008a
301 #define MR_EVT_LD_DELETED 0x008b
302 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
303 #define MR_EVT_LD_OFFLINE 0x00fc
304 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
305 #define MAX_LOGICAL_DRIVES 64
308 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
309 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
310 MR_PD_STATE_HOT_SPARE = 0x02,
311 MR_PD_STATE_OFFLINE = 0x10,
312 MR_PD_STATE_FAILED = 0x11,
313 MR_PD_STATE_REBUILD = 0x14,
314 MR_PD_STATE_ONLINE = 0x18,
315 MR_PD_STATE_COPYBACK = 0x20,
316 MR_PD_STATE_SYSTEM = 0x40,
321 * defines the physical drive address structure
323 struct MR_PD_ADDRESS {
334 u8 enclConnectorIndex;
339 u8 connectedPortBitmap;
340 u8 connectedPortNumbers;
346 * defines the physical drive list structure
351 struct MR_PD_ADDRESS addr[1];
354 struct megasas_pd_list {
361 * defines the logical drive reference structure
373 * defines the logical drive list structure
383 } ldList[MAX_LOGICAL_DRIVES];
387 * SAS controller properties
389 struct megasas_ctrl_prop {
392 u16 pred_fail_poll_interval;
393 u16 intr_throttle_count;
394 u16 intr_throttle_timeouts;
400 u8 cache_flush_interval;
406 u8 disable_auto_rebuild;
407 u8 disable_battery_warn;
409 u16 ecc_bucket_leak_rate;
410 u8 restore_hotspare_on_insertion;
411 u8 expose_encl_devices;
412 u8 maintainPdFailHistory;
413 u8 disallowHostRequestReordering;
416 u8 disableAutoDetectBackplane;
421 * Add properties that can be controlled by
422 * a bit in the following structure.
426 u32 copyBackDisabled : 1;
427 u32 SMARTerEnabled : 1;
428 u32 prCorrectUnconfiguredAreas : 1;
431 u32 SSDSMARTerEnabled : 1;
432 u32 SSDPatrolReadEnabled : 1;
433 u32 enableSpinDownUnconfigured : 1;
434 u32 autoEnhancedImport : 1;
435 u32 enableSecretKeyControl : 1;
436 u32 disableOnlineCtrlReset : 1;
437 u32 allowBootWithPinnedCache : 1;
438 u32 disableSpinDownHS : 1;
449 * SAS controller information
451 struct megasas_ctrl_info {
454 * PCI device information
464 } __attribute__ ((packed)) pci;
467 * Host interface information
480 } __attribute__ ((packed)) host_interface;
483 * Device (backend) interface information
496 } __attribute__ ((packed)) device_interface;
499 * List of components residing in flash. All str are null terminated
501 u32 image_check_word;
502 u32 image_component_count;
511 } __attribute__ ((packed)) image_component[8];
514 * List of flash components that have been flashed on the card, but
515 * are not in use, pending reset of the adapter. This list will be
516 * empty if a flash operation has not occurred. All stings are null
519 u32 pending_image_component_count;
528 } __attribute__ ((packed)) pending_image_component[8];
535 char product_name[80];
539 * Other physical/controller/operation information. Indicates the
540 * presence of the hardware
550 } __attribute__ ((packed)) hw_present;
555 * Maximum data transfer sizes
557 u16 max_concurrent_cmds;
559 u32 max_request_size;
562 * Logical and physical device counts
564 u16 ld_present_count;
565 u16 ld_degraded_count;
566 u16 ld_offline_count;
568 u16 pd_present_count;
569 u16 pd_disk_present_count;
570 u16 pd_disk_pred_failure_count;
571 u16 pd_disk_failed_count;
574 * Memory size information
583 u16 mem_correctable_error_count;
584 u16 mem_uncorrectable_error_count;
587 * Cluster information
589 u8 cluster_permitted;
593 * Additional max data transfer sizes
595 u16 max_strips_per_io;
598 * Controller capabilities structures
609 } __attribute__ ((packed)) raid_levels;
619 u32 cluster_supported:1;
621 u32 spanning_allowed:1;
622 u32 dedicated_hotspares:1;
623 u32 revertible_hotspares:1;
624 u32 foreign_config_import:1;
625 u32 self_diagnostic:1;
626 u32 mixed_redundancy_arr:1;
627 u32 global_hot_spares:1;
630 } __attribute__ ((packed)) adapter_operations;
638 u32 disk_cache_policy:1;
641 } __attribute__ ((packed)) ld_operations;
649 } __attribute__ ((packed)) stripe_sz_ops;
658 } __attribute__ ((packed)) pd_operations;
662 u32 ctrl_supports_sas:1;
663 u32 ctrl_supports_sata:1;
664 u32 allow_mix_in_encl:1;
665 u32 allow_mix_in_ld:1;
666 u32 allow_sata_in_cluster:1;
669 } __attribute__ ((packed)) pd_mix_support;
672 * Define ECC single-bit-error bucket information
678 * Include the controller properties (changeable items)
680 struct megasas_ctrl_prop properties;
683 * Define FW pkg version (set in envt v'bles on OEM basis)
685 char package_version[0x60];
687 u8 pad[0x800 - 0x6a0];
692 * ===============================
693 * MegaRAID SAS driver definitions
694 * ===============================
696 #define MEGASAS_MAX_PD_CHANNELS 2
697 #define MEGASAS_MAX_LD_CHANNELS 2
698 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
699 MEGASAS_MAX_LD_CHANNELS)
700 #define MEGASAS_MAX_DEV_PER_CHANNEL 128
701 #define MEGASAS_DEFAULT_INIT_ID -1
702 #define MEGASAS_MAX_LUN 8
703 #define MEGASAS_MAX_LD 64
704 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
705 MEGASAS_MAX_DEV_PER_CHANNEL)
706 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
707 MEGASAS_MAX_DEV_PER_CHANNEL)
709 #define MEGASAS_MAX_SECTORS (2*1024)
710 #define MEGASAS_DBG_LVL 1
712 #define MEGASAS_FW_BUSY 1
716 #define PTHRU_FRAME 1
719 * When SCSI mid-layer calls driver's reset routine, driver waits for
720 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
721 * that the driver cannot _actually_ abort or reset pending commands. While
722 * it is waiting for the commands to complete, it prints a diagnostic message
723 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
725 #define MEGASAS_RESET_WAIT_TIME 180
726 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
727 #define MEGASAS_RESET_NOTICE_INTERVAL 5
728 #define MEGASAS_IOCTL_CMD 0
729 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90
732 * FW reports the maximum of number of commands that it can accept (maximum
733 * commands that can be outstanding) at any time. The driver must report a
734 * lower number to the mid layer because it can issue a few internal commands
735 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
738 #define MEGASAS_INT_CMDS 32
739 #define MEGASAS_SKINNY_INT_CMDS 5
742 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
743 * SGLs based on the size of dma_addr_t
745 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
747 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
749 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
750 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
751 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
753 #define MFI_OB_INTR_STATUS_MASK 0x00000002
754 #define MFI_POLL_TIMEOUT_SECS 60
755 #define MEGASAS_COMPLETION_TIMER_INTERVAL (HZ/10)
757 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
758 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
759 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
760 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
761 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
763 #define MFI_1068_PCSR_OFFSET 0x84
764 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
765 #define MFI_1068_FW_READY 0xDDDD0000
767 * register set for both 1068 and 1078 controllers
768 * structure extended for 1078 registers
771 struct megasas_register_set {
772 u32 reserved_0[4]; /*0000h*/
774 u32 inbound_msg_0; /*0010h*/
775 u32 inbound_msg_1; /*0014h*/
776 u32 outbound_msg_0; /*0018h*/
777 u32 outbound_msg_1; /*001Ch*/
779 u32 inbound_doorbell; /*0020h*/
780 u32 inbound_intr_status; /*0024h*/
781 u32 inbound_intr_mask; /*0028h*/
783 u32 outbound_doorbell; /*002Ch*/
784 u32 outbound_intr_status; /*0030h*/
785 u32 outbound_intr_mask; /*0034h*/
787 u32 reserved_1[2]; /*0038h*/
789 u32 inbound_queue_port; /*0040h*/
790 u32 outbound_queue_port; /*0044h*/
792 u32 reserved_2[22]; /*0048h*/
794 u32 outbound_doorbell_clear; /*00A0h*/
796 u32 reserved_3[3]; /*00A4h*/
798 u32 outbound_scratch_pad ; /*00B0h*/
800 u32 reserved_4[3]; /*00B4h*/
802 u32 inbound_low_queue_port ; /*00C0h*/
804 u32 inbound_high_queue_port ; /*00C4h*/
806 u32 reserved_5; /*00C8h*/
807 u32 res_6[11]; /*CCh*/
810 u32 index_registers[807]; /*00CCh*/
811 } __attribute__ ((packed));
813 struct megasas_sge32 {
818 } __attribute__ ((packed));
820 struct megasas_sge64 {
825 } __attribute__ ((packed));
827 struct megasas_sge_skinny {
835 struct megasas_sge32 sge32[1];
836 struct megasas_sge64 sge64[1];
837 struct megasas_sge_skinny sge_skinny[1];
839 } __attribute__ ((packed));
841 struct megasas_header {
844 u8 sense_len; /*01h */
845 u8 cmd_status; /*02h */
846 u8 scsi_status; /*03h */
848 u8 target_id; /*04h */
851 u8 sge_count; /*07h */
853 u32 context; /*08h */
857 u16 timeout; /*12h */
858 u32 data_xferlen; /*14h */
860 } __attribute__ ((packed));
862 union megasas_sgl_frame {
864 struct megasas_sge32 sge32[8];
865 struct megasas_sge64 sge64[5];
867 } __attribute__ ((packed));
869 struct megasas_init_frame {
872 u8 reserved_0; /*01h */
873 u8 cmd_status; /*02h */
875 u8 reserved_1; /*03h */
876 u32 reserved_2; /*04h */
878 u32 context; /*08h */
882 u16 reserved_3; /*12h */
883 u32 data_xfer_len; /*14h */
885 u32 queue_info_new_phys_addr_lo; /*18h */
886 u32 queue_info_new_phys_addr_hi; /*1Ch */
887 u32 queue_info_old_phys_addr_lo; /*20h */
888 u32 queue_info_old_phys_addr_hi; /*24h */
890 u32 reserved_4[6]; /*28h */
892 } __attribute__ ((packed));
894 struct megasas_init_queue_info {
896 u32 init_flags; /*00h */
897 u32 reply_queue_entries; /*04h */
899 u32 reply_queue_start_phys_addr_lo; /*08h */
900 u32 reply_queue_start_phys_addr_hi; /*0Ch */
901 u32 producer_index_phys_addr_lo; /*10h */
902 u32 producer_index_phys_addr_hi; /*14h */
903 u32 consumer_index_phys_addr_lo; /*18h */
904 u32 consumer_index_phys_addr_hi; /*1Ch */
906 } __attribute__ ((packed));
908 struct megasas_io_frame {
911 u8 sense_len; /*01h */
912 u8 cmd_status; /*02h */
913 u8 scsi_status; /*03h */
915 u8 target_id; /*04h */
916 u8 access_byte; /*05h */
917 u8 reserved_0; /*06h */
918 u8 sge_count; /*07h */
920 u32 context; /*08h */
924 u16 timeout; /*12h */
925 u32 lba_count; /*14h */
927 u32 sense_buf_phys_addr_lo; /*18h */
928 u32 sense_buf_phys_addr_hi; /*1Ch */
930 u32 start_lba_lo; /*20h */
931 u32 start_lba_hi; /*24h */
933 union megasas_sgl sgl; /*28h */
935 } __attribute__ ((packed));
937 struct megasas_pthru_frame {
940 u8 sense_len; /*01h */
941 u8 cmd_status; /*02h */
942 u8 scsi_status; /*03h */
944 u8 target_id; /*04h */
947 u8 sge_count; /*07h */
949 u32 context; /*08h */
953 u16 timeout; /*12h */
954 u32 data_xfer_len; /*14h */
956 u32 sense_buf_phys_addr_lo; /*18h */
957 u32 sense_buf_phys_addr_hi; /*1Ch */
960 union megasas_sgl sgl; /*30h */
962 } __attribute__ ((packed));
964 struct megasas_dcmd_frame {
967 u8 reserved_0; /*01h */
968 u8 cmd_status; /*02h */
969 u8 reserved_1[4]; /*03h */
970 u8 sge_count; /*07h */
972 u32 context; /*08h */
976 u16 timeout; /*12h */
978 u32 data_xfer_len; /*14h */
987 union megasas_sgl sgl; /*28h */
989 } __attribute__ ((packed));
991 struct megasas_abort_frame {
994 u8 reserved_0; /*01h */
995 u8 cmd_status; /*02h */
997 u8 reserved_1; /*03h */
998 u32 reserved_2; /*04h */
1000 u32 context; /*08h */
1004 u16 reserved_3; /*12h */
1005 u32 reserved_4; /*14h */
1007 u32 abort_context; /*18h */
1010 u32 abort_mfi_phys_addr_lo; /*20h */
1011 u32 abort_mfi_phys_addr_hi; /*24h */
1013 u32 reserved_5[6]; /*28h */
1015 } __attribute__ ((packed));
1017 struct megasas_smp_frame {
1020 u8 reserved_1; /*01h */
1021 u8 cmd_status; /*02h */
1022 u8 connection_status; /*03h */
1024 u8 reserved_2[3]; /*04h */
1025 u8 sge_count; /*07h */
1027 u32 context; /*08h */
1031 u16 timeout; /*12h */
1033 u32 data_xfer_len; /*14h */
1034 u64 sas_addr; /*18h */
1037 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1038 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1041 } __attribute__ ((packed));
1043 struct megasas_stp_frame {
1046 u8 reserved_1; /*01h */
1047 u8 cmd_status; /*02h */
1048 u8 reserved_2; /*03h */
1050 u8 target_id; /*04h */
1051 u8 reserved_3[2]; /*05h */
1052 u8 sge_count; /*07h */
1054 u32 context; /*08h */
1058 u16 timeout; /*12h */
1060 u32 data_xfer_len; /*14h */
1062 u16 fis[10]; /*18h */
1066 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1067 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1070 } __attribute__ ((packed));
1072 union megasas_frame {
1074 struct megasas_header hdr;
1075 struct megasas_init_frame init;
1076 struct megasas_io_frame io;
1077 struct megasas_pthru_frame pthru;
1078 struct megasas_dcmd_frame dcmd;
1079 struct megasas_abort_frame abort;
1080 struct megasas_smp_frame smp;
1081 struct megasas_stp_frame stp;
1088 union megasas_evt_class_locale {
1094 } __attribute__ ((packed)) members;
1098 } __attribute__ ((packed));
1100 struct megasas_evt_log_info {
1104 u32 shutdown_seq_num;
1107 } __attribute__ ((packed));
1109 struct megasas_progress {
1112 u16 elapsed_seconds;
1114 } __attribute__ ((packed));
1116 struct megasas_evtarg_ld {
1122 } __attribute__ ((packed));
1124 struct megasas_evtarg_pd {
1129 } __attribute__ ((packed));
1131 struct megasas_evt_detail {
1136 union megasas_evt_class_locale cl;
1142 struct megasas_evtarg_pd pd;
1148 } __attribute__ ((packed)) cdbSense;
1150 struct megasas_evtarg_ld ld;
1153 struct megasas_evtarg_ld ld;
1155 } __attribute__ ((packed)) ld_count;
1159 struct megasas_evtarg_ld ld;
1160 } __attribute__ ((packed)) ld_lba;
1163 struct megasas_evtarg_ld ld;
1166 } __attribute__ ((packed)) ld_owner;
1171 struct megasas_evtarg_ld ld;
1172 struct megasas_evtarg_pd pd;
1173 } __attribute__ ((packed)) ld_lba_pd_lba;
1176 struct megasas_evtarg_ld ld;
1177 struct megasas_progress prog;
1178 } __attribute__ ((packed)) ld_prog;
1181 struct megasas_evtarg_ld ld;
1184 } __attribute__ ((packed)) ld_state;
1188 struct megasas_evtarg_ld ld;
1189 } __attribute__ ((packed)) ld_strip;
1191 struct megasas_evtarg_pd pd;
1194 struct megasas_evtarg_pd pd;
1196 } __attribute__ ((packed)) pd_err;
1200 struct megasas_evtarg_pd pd;
1201 } __attribute__ ((packed)) pd_lba;
1205 struct megasas_evtarg_pd pd;
1206 struct megasas_evtarg_ld ld;
1207 } __attribute__ ((packed)) pd_lba_ld;
1210 struct megasas_evtarg_pd pd;
1211 struct megasas_progress prog;
1212 } __attribute__ ((packed)) pd_prog;
1215 struct megasas_evtarg_pd pd;
1218 } __attribute__ ((packed)) pd_state;
1225 } __attribute__ ((packed)) pci;
1233 } __attribute__ ((packed)) time;
1239 } __attribute__ ((packed)) ecc;
1247 char description[128];
1249 } __attribute__ ((packed));
1251 struct megasas_aen_event {
1252 struct work_struct hotplug_work;
1253 struct megasas_instance *instance;
1256 struct megasas_instance {
1259 dma_addr_t producer_h;
1261 dma_addr_t consumer_h;
1264 dma_addr_t reply_queue_h;
1266 unsigned long base_addr;
1267 struct megasas_register_set __iomem *reg_set;
1269 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
1270 u8 ld_ids[MEGASAS_MAX_LD_IDS];
1275 u32 max_sectors_per_req;
1276 struct megasas_aen_event *ev;
1278 struct megasas_cmd **cmd_list;
1279 struct list_head cmd_pool;
1280 /* used to sync fire the cmd to fw */
1281 spinlock_t cmd_pool_lock;
1282 /* used to sync fire the cmd to fw */
1283 spinlock_t hba_lock;
1284 /* used to synch producer, consumer ptrs in dpc */
1285 spinlock_t completion_lock;
1286 struct dma_pool *frame_dma_pool;
1287 struct dma_pool *sense_dma_pool;
1289 struct megasas_evt_detail *evt_detail;
1290 dma_addr_t evt_detail_h;
1291 struct megasas_cmd *aen_cmd;
1292 struct mutex aen_mutex;
1293 struct semaphore ioctl_sem;
1295 struct Scsi_Host *host;
1297 wait_queue_head_t int_cmd_wait_q;
1298 wait_queue_head_t abort_cmd_wait_q;
1300 struct pci_dev *pdev;
1302 u32 fw_support_ieee;
1304 atomic_t fw_outstanding;
1305 atomic_t fw_reset_no_pci_access;
1307 struct megasas_instance_template *instancet;
1308 struct tasklet_struct isr_tasklet;
1309 struct work_struct work_init;
1315 u8 disableOnlineCtrlReset;
1317 unsigned long last_time;
1321 struct timer_list io_completion_timer;
1322 struct list_head internal_reset_pending_q;
1326 MEGASAS_HBA_OPERATIONAL = 0,
1327 MEGASAS_ADPRESET_SM_INFAULT = 1,
1328 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1329 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
1330 MEGASAS_HW_CRITICAL_ERROR = 4,
1331 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
1334 struct megasas_instance_template {
1335 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1336 u32, struct megasas_register_set __iomem *);
1338 void (*enable_intr)(struct megasas_register_set __iomem *) ;
1339 void (*disable_intr)(struct megasas_register_set __iomem *);
1341 int (*clear_intr)(struct megasas_register_set __iomem *);
1343 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1344 int (*adp_reset)(struct megasas_instance *, \
1345 struct megasas_register_set __iomem *);
1346 int (*check_reset)(struct megasas_instance *, \
1347 struct megasas_register_set __iomem *);
1350 #define MEGASAS_IS_LOGICAL(scp) \
1351 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1353 #define MEGASAS_DEV_INDEX(inst, scp) \
1354 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1357 struct megasas_cmd {
1359 union megasas_frame *frame;
1360 dma_addr_t frame_phys_addr;
1362 dma_addr_t sense_phys_addr;
1368 u8 retry_for_fw_reset;
1371 struct list_head list;
1372 struct scsi_cmnd *scmd;
1373 struct megasas_instance *instance;
1377 #define MAX_MGMT_ADAPTERS 1024
1378 #define MAX_IOCTL_SGE 16
1380 struct megasas_iocpacket {
1390 struct megasas_header hdr;
1393 struct iovec sgl[MAX_IOCTL_SGE];
1395 } __attribute__ ((packed));
1397 struct megasas_aen {
1401 u32 class_locale_word;
1402 } __attribute__ ((packed));
1404 #ifdef CONFIG_COMPAT
1405 struct compat_megasas_iocpacket {
1414 struct megasas_header hdr;
1416 struct compat_iovec sgl[MAX_IOCTL_SGE];
1417 } __attribute__ ((packed));
1419 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
1422 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
1423 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1425 struct megasas_mgmt_info {
1428 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1432 #endif /*LSI_MEGARAID_SAS_H */