2 * Linux MegaRAID driver for SAS based RAID controllers
4 * Copyright (c) 2009-2011 LSI Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 * FILE: megaraid_sas.h
22 * Authors: LSI Corporation
24 * Send feedback to: <megaraidlinux@lsi.com>
26 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
30 #ifndef LSI_MEGARAID_SAS_H
31 #define LSI_MEGARAID_SAS_H
34 * MegaRAID SAS Driver meta data
36 #define MEGASAS_VERSION "00.00.06.12-rc1"
37 #define MEGASAS_RELDATE "Oct. 5, 2011"
38 #define MEGASAS_EXT_VERSION "Wed. Oct. 5 17:00:00 PDT 2011"
43 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
44 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
45 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
46 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
47 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
48 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
49 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
50 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
51 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
54 * =====================================
55 * MegaRAID SAS MFI firmware definitions
56 * =====================================
60 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
61 * protocol between the software and firmware. Commands are issued using
66 * FW posts its state in upper 4 bits of outbound_msg_0 register
68 #define MFI_STATE_MASK 0xF0000000
69 #define MFI_STATE_UNDEFINED 0x00000000
70 #define MFI_STATE_BB_INIT 0x10000000
71 #define MFI_STATE_FW_INIT 0x40000000
72 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
73 #define MFI_STATE_FW_INIT_2 0x70000000
74 #define MFI_STATE_DEVICE_SCAN 0x80000000
75 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
76 #define MFI_STATE_FLUSH_CACHE 0xA0000000
77 #define MFI_STATE_READY 0xB0000000
78 #define MFI_STATE_OPERATIONAL 0xC0000000
79 #define MFI_STATE_FAULT 0xF0000000
80 #define MFI_RESET_REQUIRED 0x00000001
81 #define MFI_RESET_ADAPTER 0x00000002
82 #define MEGAMFI_FRAME_SIZE 64
85 * During FW init, clear pending cmds & reset state using inbound_msg_0
87 * ABORT : Abort all pending cmds
88 * READY : Move from OPERATIONAL to READY state; discard queue info
89 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
90 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
91 * HOTPLUG : Resume from Hotplug
92 * MFI_STOP_ADP : Send signal to FW to stop processing
94 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
95 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
96 #define DIAG_WRITE_ENABLE (0x00000080)
97 #define DIAG_RESET_ADAPTER (0x00000004)
99 #define MFI_ADP_RESET 0x00000040
100 #define MFI_INIT_ABORT 0x00000001
101 #define MFI_INIT_READY 0x00000002
102 #define MFI_INIT_MFIMODE 0x00000004
103 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
104 #define MFI_INIT_HOTPLUG 0x00000010
105 #define MFI_STOP_ADP 0x00000020
106 #define MFI_RESET_FLAGS MFI_INIT_READY| \
113 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
114 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
115 #define MFI_FRAME_SGL32 0x0000
116 #define MFI_FRAME_SGL64 0x0002
117 #define MFI_FRAME_SENSE32 0x0000
118 #define MFI_FRAME_SENSE64 0x0004
119 #define MFI_FRAME_DIR_NONE 0x0000
120 #define MFI_FRAME_DIR_WRITE 0x0008
121 #define MFI_FRAME_DIR_READ 0x0010
122 #define MFI_FRAME_DIR_BOTH 0x0018
123 #define MFI_FRAME_IEEE 0x0020
126 * Definition for cmd_status
128 #define MFI_CMD_STATUS_POLL_MODE 0xFF
131 * MFI command opcodes
133 #define MFI_CMD_INIT 0x00
134 #define MFI_CMD_LD_READ 0x01
135 #define MFI_CMD_LD_WRITE 0x02
136 #define MFI_CMD_LD_SCSI_IO 0x03
137 #define MFI_CMD_PD_SCSI_IO 0x04
138 #define MFI_CMD_DCMD 0x05
139 #define MFI_CMD_ABORT 0x06
140 #define MFI_CMD_SMP 0x07
141 #define MFI_CMD_STP 0x08
142 #define MFI_CMD_INVALID 0xff
144 #define MR_DCMD_CTRL_GET_INFO 0x01010000
145 #define MR_DCMD_LD_GET_LIST 0x03010000
147 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
148 #define MR_FLUSH_CTRL_CACHE 0x01
149 #define MR_FLUSH_DISK_CACHE 0x02
151 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
152 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
153 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
155 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
156 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
157 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
158 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
160 #define MR_DCMD_CLUSTER 0x08000000
161 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
162 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
163 #define MR_DCMD_PD_LIST_QUERY 0x02010100
166 * MFI command completion codes
170 MFI_STAT_INVALID_CMD = 0x01,
171 MFI_STAT_INVALID_DCMD = 0x02,
172 MFI_STAT_INVALID_PARAMETER = 0x03,
173 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
174 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
175 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
176 MFI_STAT_APP_IN_USE = 0x07,
177 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
178 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
179 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
180 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
181 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
182 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
183 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
184 MFI_STAT_FLASH_BUSY = 0x0f,
185 MFI_STAT_FLASH_ERROR = 0x10,
186 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
187 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
188 MFI_STAT_FLASH_NOT_OPEN = 0x13,
189 MFI_STAT_FLASH_NOT_STARTED = 0x14,
190 MFI_STAT_FLUSH_FAILED = 0x15,
191 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
192 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
193 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
194 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
195 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
196 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
197 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
198 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
199 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
200 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
201 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
202 MFI_STAT_MFC_HW_ERROR = 0x21,
203 MFI_STAT_NO_HW_PRESENT = 0x22,
204 MFI_STAT_NOT_FOUND = 0x23,
205 MFI_STAT_NOT_IN_ENCL = 0x24,
206 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
207 MFI_STAT_PD_TYPE_WRONG = 0x26,
208 MFI_STAT_PR_DISABLED = 0x27,
209 MFI_STAT_ROW_INDEX_INVALID = 0x28,
210 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
211 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
212 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
213 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
214 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
215 MFI_STAT_SCSI_IO_FAILED = 0x2e,
216 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
217 MFI_STAT_SHUTDOWN_FAILED = 0x30,
218 MFI_STAT_TIME_NOT_SET = 0x31,
219 MFI_STAT_WRONG_STATE = 0x32,
220 MFI_STAT_LD_OFFLINE = 0x33,
221 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
222 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
223 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
224 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
225 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
226 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
228 MFI_STAT_INVALID_STATUS = 0xFF
232 * Number of mailbox bytes in DCMD message frame
234 #define MFI_MBOX_SIZE 12
238 MR_EVT_CLASS_DEBUG = -2,
239 MR_EVT_CLASS_PROGRESS = -1,
240 MR_EVT_CLASS_INFO = 0,
241 MR_EVT_CLASS_WARNING = 1,
242 MR_EVT_CLASS_CRITICAL = 2,
243 MR_EVT_CLASS_FATAL = 3,
244 MR_EVT_CLASS_DEAD = 4,
250 MR_EVT_LOCALE_LD = 0x0001,
251 MR_EVT_LOCALE_PD = 0x0002,
252 MR_EVT_LOCALE_ENCL = 0x0004,
253 MR_EVT_LOCALE_BBU = 0x0008,
254 MR_EVT_LOCALE_SAS = 0x0010,
255 MR_EVT_LOCALE_CTRL = 0x0020,
256 MR_EVT_LOCALE_CONFIG = 0x0040,
257 MR_EVT_LOCALE_CLUSTER = 0x0080,
258 MR_EVT_LOCALE_ALL = 0xffff,
265 MR_EVT_ARGS_CDB_SENSE,
267 MR_EVT_ARGS_LD_COUNT,
269 MR_EVT_ARGS_LD_OWNER,
270 MR_EVT_ARGS_LD_LBA_PD_LBA,
272 MR_EVT_ARGS_LD_STATE,
273 MR_EVT_ARGS_LD_STRIP,
277 MR_EVT_ARGS_PD_LBA_LD,
279 MR_EVT_ARGS_PD_STATE,
286 MR_EVT_ARGS_PD_SPARE,
287 MR_EVT_ARGS_PD_INDEX,
288 MR_EVT_ARGS_DIAG_PASS,
289 MR_EVT_ARGS_DIAG_FAIL,
290 MR_EVT_ARGS_PD_LBA_LBA,
291 MR_EVT_ARGS_PORT_PHY,
292 MR_EVT_ARGS_PD_MISSING,
293 MR_EVT_ARGS_PD_ADDRESS,
295 MR_EVT_ARGS_CONNECTOR,
298 MR_EVT_ARGS_PD_PATHINFO,
299 MR_EVT_ARGS_PD_POWER_STATE,
304 #define SGE_BUFFER_SIZE 4096
306 * define constants for device list query options
308 enum MR_PD_QUERY_TYPE {
309 MR_PD_QUERY_TYPE_ALL = 0,
310 MR_PD_QUERY_TYPE_STATE = 1,
311 MR_PD_QUERY_TYPE_POWER_STATE = 2,
312 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
313 MR_PD_QUERY_TYPE_SPEED = 4,
314 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
317 #define MR_EVT_CFG_CLEARED 0x0004
318 #define MR_EVT_LD_STATE_CHANGE 0x0051
319 #define MR_EVT_PD_INSERTED 0x005b
320 #define MR_EVT_PD_REMOVED 0x0070
321 #define MR_EVT_LD_CREATED 0x008a
322 #define MR_EVT_LD_DELETED 0x008b
323 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
324 #define MR_EVT_LD_OFFLINE 0x00fc
325 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
326 #define MAX_LOGICAL_DRIVES 64
329 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
330 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
331 MR_PD_STATE_HOT_SPARE = 0x02,
332 MR_PD_STATE_OFFLINE = 0x10,
333 MR_PD_STATE_FAILED = 0x11,
334 MR_PD_STATE_REBUILD = 0x14,
335 MR_PD_STATE_ONLINE = 0x18,
336 MR_PD_STATE_COPYBACK = 0x20,
337 MR_PD_STATE_SYSTEM = 0x40,
342 * defines the physical drive address structure
344 struct MR_PD_ADDRESS {
355 u8 enclConnectorIndex;
360 u8 connectedPortBitmap;
361 u8 connectedPortNumbers;
367 * defines the physical drive list structure
372 struct MR_PD_ADDRESS addr[1];
375 struct megasas_pd_list {
382 * defines the logical drive reference structure
394 * defines the logical drive list structure
404 } ldList[MAX_LOGICAL_DRIVES];
408 * SAS controller properties
410 struct megasas_ctrl_prop {
413 u16 pred_fail_poll_interval;
414 u16 intr_throttle_count;
415 u16 intr_throttle_timeouts;
421 u8 cache_flush_interval;
427 u8 disable_auto_rebuild;
428 u8 disable_battery_warn;
430 u16 ecc_bucket_leak_rate;
431 u8 restore_hotspare_on_insertion;
432 u8 expose_encl_devices;
433 u8 maintainPdFailHistory;
434 u8 disallowHostRequestReordering;
437 u8 disableAutoDetectBackplane;
442 * Add properties that can be controlled by
443 * a bit in the following structure.
446 u32 copyBackDisabled : 1;
447 u32 SMARTerEnabled : 1;
448 u32 prCorrectUnconfiguredAreas : 1;
451 u32 SSDSMARTerEnabled : 1;
452 u32 SSDPatrolReadEnabled : 1;
453 u32 enableSpinDownUnconfigured : 1;
454 u32 autoEnhancedImport : 1;
455 u32 enableSecretKeyControl : 1;
456 u32 disableOnlineCtrlReset : 1;
457 u32 allowBootWithPinnedCache : 1;
458 u32 disableSpinDownHS : 1;
469 * SAS controller information
471 struct megasas_ctrl_info {
474 * PCI device information
484 } __attribute__ ((packed)) pci;
487 * Host interface information
500 } __attribute__ ((packed)) host_interface;
503 * Device (backend) interface information
516 } __attribute__ ((packed)) device_interface;
519 * List of components residing in flash. All str are null terminated
521 u32 image_check_word;
522 u32 image_component_count;
531 } __attribute__ ((packed)) image_component[8];
534 * List of flash components that have been flashed on the card, but
535 * are not in use, pending reset of the adapter. This list will be
536 * empty if a flash operation has not occurred. All stings are null
539 u32 pending_image_component_count;
548 } __attribute__ ((packed)) pending_image_component[8];
555 char product_name[80];
559 * Other physical/controller/operation information. Indicates the
560 * presence of the hardware
570 } __attribute__ ((packed)) hw_present;
575 * Maximum data transfer sizes
577 u16 max_concurrent_cmds;
579 u32 max_request_size;
582 * Logical and physical device counts
584 u16 ld_present_count;
585 u16 ld_degraded_count;
586 u16 ld_offline_count;
588 u16 pd_present_count;
589 u16 pd_disk_present_count;
590 u16 pd_disk_pred_failure_count;
591 u16 pd_disk_failed_count;
594 * Memory size information
603 u16 mem_correctable_error_count;
604 u16 mem_uncorrectable_error_count;
607 * Cluster information
609 u8 cluster_permitted;
613 * Additional max data transfer sizes
615 u16 max_strips_per_io;
618 * Controller capabilities structures
629 } __attribute__ ((packed)) raid_levels;
639 u32 cluster_supported:1;
641 u32 spanning_allowed:1;
642 u32 dedicated_hotspares:1;
643 u32 revertible_hotspares:1;
644 u32 foreign_config_import:1;
645 u32 self_diagnostic:1;
646 u32 mixed_redundancy_arr:1;
647 u32 global_hot_spares:1;
650 } __attribute__ ((packed)) adapter_operations;
658 u32 disk_cache_policy:1;
661 } __attribute__ ((packed)) ld_operations;
669 } __attribute__ ((packed)) stripe_sz_ops;
678 } __attribute__ ((packed)) pd_operations;
682 u32 ctrl_supports_sas:1;
683 u32 ctrl_supports_sata:1;
684 u32 allow_mix_in_encl:1;
685 u32 allow_mix_in_ld:1;
686 u32 allow_sata_in_cluster:1;
689 } __attribute__ ((packed)) pd_mix_support;
692 * Define ECC single-bit-error bucket information
698 * Include the controller properties (changeable items)
700 struct megasas_ctrl_prop properties;
703 * Define FW pkg version (set in envt v'bles on OEM basis)
705 char package_version[0x60];
707 u8 pad[0x800 - 0x6a0];
712 * ===============================
713 * MegaRAID SAS driver definitions
714 * ===============================
716 #define MEGASAS_MAX_PD_CHANNELS 2
717 #define MEGASAS_MAX_LD_CHANNELS 2
718 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
719 MEGASAS_MAX_LD_CHANNELS)
720 #define MEGASAS_MAX_DEV_PER_CHANNEL 128
721 #define MEGASAS_DEFAULT_INIT_ID -1
722 #define MEGASAS_MAX_LUN 8
723 #define MEGASAS_MAX_LD 64
724 #define MEGASAS_DEFAULT_CMD_PER_LUN 256
725 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
726 MEGASAS_MAX_DEV_PER_CHANNEL)
727 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
728 MEGASAS_MAX_DEV_PER_CHANNEL)
730 #define MEGASAS_MAX_SECTORS (2*1024)
731 #define MEGASAS_MAX_SECTORS_IEEE (2*128)
732 #define MEGASAS_DBG_LVL 1
734 #define MEGASAS_FW_BUSY 1
738 #define PTHRU_FRAME 1
741 * When SCSI mid-layer calls driver's reset routine, driver waits for
742 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
743 * that the driver cannot _actually_ abort or reset pending commands. While
744 * it is waiting for the commands to complete, it prints a diagnostic message
745 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
747 #define MEGASAS_RESET_WAIT_TIME 180
748 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
749 #define MEGASAS_RESET_NOTICE_INTERVAL 5
750 #define MEGASAS_IOCTL_CMD 0
751 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90
754 * FW reports the maximum of number of commands that it can accept (maximum
755 * commands that can be outstanding) at any time. The driver must report a
756 * lower number to the mid layer because it can issue a few internal commands
757 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
760 #define MEGASAS_INT_CMDS 32
761 #define MEGASAS_SKINNY_INT_CMDS 5
763 #define MEGASAS_MAX_MSIX_QUEUES 16
765 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
766 * SGLs based on the size of dma_addr_t
768 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
770 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
772 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
773 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
774 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
776 #define MFI_OB_INTR_STATUS_MASK 0x00000002
777 #define MFI_POLL_TIMEOUT_SECS 60
778 #define MEGASAS_COMPLETION_TIMER_INTERVAL (HZ/10)
780 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
781 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
782 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
783 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
784 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
786 #define MFI_1068_PCSR_OFFSET 0x84
787 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
788 #define MFI_1068_FW_READY 0xDDDD0000
790 * register set for both 1068 and 1078 controllers
791 * structure extended for 1078 registers
794 struct megasas_register_set {
795 u32 doorbell; /*0000h*/
796 u32 fusion_seq_offset; /*0004h*/
797 u32 fusion_host_diag; /*0008h*/
798 u32 reserved_01; /*000Ch*/
800 u32 inbound_msg_0; /*0010h*/
801 u32 inbound_msg_1; /*0014h*/
802 u32 outbound_msg_0; /*0018h*/
803 u32 outbound_msg_1; /*001Ch*/
805 u32 inbound_doorbell; /*0020h*/
806 u32 inbound_intr_status; /*0024h*/
807 u32 inbound_intr_mask; /*0028h*/
809 u32 outbound_doorbell; /*002Ch*/
810 u32 outbound_intr_status; /*0030h*/
811 u32 outbound_intr_mask; /*0034h*/
813 u32 reserved_1[2]; /*0038h*/
815 u32 inbound_queue_port; /*0040h*/
816 u32 outbound_queue_port; /*0044h*/
818 u32 reserved_2[9]; /*0048h*/
819 u32 reply_post_host_index; /*006Ch*/
820 u32 reserved_2_2[12]; /*0070h*/
822 u32 outbound_doorbell_clear; /*00A0h*/
824 u32 reserved_3[3]; /*00A4h*/
826 u32 outbound_scratch_pad ; /*00B0h*/
827 u32 outbound_scratch_pad_2; /*00B4h*/
829 u32 reserved_4[2]; /*00B8h*/
831 u32 inbound_low_queue_port ; /*00C0h*/
833 u32 inbound_high_queue_port ; /*00C4h*/
835 u32 reserved_5; /*00C8h*/
836 u32 res_6[11]; /*CCh*/
839 u32 index_registers[807]; /*00CCh*/
840 } __attribute__ ((packed));
842 struct megasas_sge32 {
847 } __attribute__ ((packed));
849 struct megasas_sge64 {
854 } __attribute__ ((packed));
856 struct megasas_sge_skinny {
864 struct megasas_sge32 sge32[1];
865 struct megasas_sge64 sge64[1];
866 struct megasas_sge_skinny sge_skinny[1];
868 } __attribute__ ((packed));
870 struct megasas_header {
873 u8 sense_len; /*01h */
874 u8 cmd_status; /*02h */
875 u8 scsi_status; /*03h */
877 u8 target_id; /*04h */
880 u8 sge_count; /*07h */
882 u32 context; /*08h */
886 u16 timeout; /*12h */
887 u32 data_xferlen; /*14h */
889 } __attribute__ ((packed));
891 union megasas_sgl_frame {
893 struct megasas_sge32 sge32[8];
894 struct megasas_sge64 sge64[5];
896 } __attribute__ ((packed));
898 struct megasas_init_frame {
901 u8 reserved_0; /*01h */
902 u8 cmd_status; /*02h */
904 u8 reserved_1; /*03h */
905 u32 reserved_2; /*04h */
907 u32 context; /*08h */
911 u16 reserved_3; /*12h */
912 u32 data_xfer_len; /*14h */
914 u32 queue_info_new_phys_addr_lo; /*18h */
915 u32 queue_info_new_phys_addr_hi; /*1Ch */
916 u32 queue_info_old_phys_addr_lo; /*20h */
917 u32 queue_info_old_phys_addr_hi; /*24h */
919 u32 reserved_4[6]; /*28h */
921 } __attribute__ ((packed));
923 struct megasas_init_queue_info {
925 u32 init_flags; /*00h */
926 u32 reply_queue_entries; /*04h */
928 u32 reply_queue_start_phys_addr_lo; /*08h */
929 u32 reply_queue_start_phys_addr_hi; /*0Ch */
930 u32 producer_index_phys_addr_lo; /*10h */
931 u32 producer_index_phys_addr_hi; /*14h */
932 u32 consumer_index_phys_addr_lo; /*18h */
933 u32 consumer_index_phys_addr_hi; /*1Ch */
935 } __attribute__ ((packed));
937 struct megasas_io_frame {
940 u8 sense_len; /*01h */
941 u8 cmd_status; /*02h */
942 u8 scsi_status; /*03h */
944 u8 target_id; /*04h */
945 u8 access_byte; /*05h */
946 u8 reserved_0; /*06h */
947 u8 sge_count; /*07h */
949 u32 context; /*08h */
953 u16 timeout; /*12h */
954 u32 lba_count; /*14h */
956 u32 sense_buf_phys_addr_lo; /*18h */
957 u32 sense_buf_phys_addr_hi; /*1Ch */
959 u32 start_lba_lo; /*20h */
960 u32 start_lba_hi; /*24h */
962 union megasas_sgl sgl; /*28h */
964 } __attribute__ ((packed));
966 struct megasas_pthru_frame {
969 u8 sense_len; /*01h */
970 u8 cmd_status; /*02h */
971 u8 scsi_status; /*03h */
973 u8 target_id; /*04h */
976 u8 sge_count; /*07h */
978 u32 context; /*08h */
982 u16 timeout; /*12h */
983 u32 data_xfer_len; /*14h */
985 u32 sense_buf_phys_addr_lo; /*18h */
986 u32 sense_buf_phys_addr_hi; /*1Ch */
989 union megasas_sgl sgl; /*30h */
991 } __attribute__ ((packed));
993 struct megasas_dcmd_frame {
996 u8 reserved_0; /*01h */
997 u8 cmd_status; /*02h */
998 u8 reserved_1[4]; /*03h */
999 u8 sge_count; /*07h */
1001 u32 context; /*08h */
1005 u16 timeout; /*12h */
1007 u32 data_xfer_len; /*14h */
1008 u32 opcode; /*18h */
1016 union megasas_sgl sgl; /*28h */
1018 } __attribute__ ((packed));
1020 struct megasas_abort_frame {
1023 u8 reserved_0; /*01h */
1024 u8 cmd_status; /*02h */
1026 u8 reserved_1; /*03h */
1027 u32 reserved_2; /*04h */
1029 u32 context; /*08h */
1033 u16 reserved_3; /*12h */
1034 u32 reserved_4; /*14h */
1036 u32 abort_context; /*18h */
1039 u32 abort_mfi_phys_addr_lo; /*20h */
1040 u32 abort_mfi_phys_addr_hi; /*24h */
1042 u32 reserved_5[6]; /*28h */
1044 } __attribute__ ((packed));
1046 struct megasas_smp_frame {
1049 u8 reserved_1; /*01h */
1050 u8 cmd_status; /*02h */
1051 u8 connection_status; /*03h */
1053 u8 reserved_2[3]; /*04h */
1054 u8 sge_count; /*07h */
1056 u32 context; /*08h */
1060 u16 timeout; /*12h */
1062 u32 data_xfer_len; /*14h */
1063 u64 sas_addr; /*18h */
1066 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1067 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1070 } __attribute__ ((packed));
1072 struct megasas_stp_frame {
1075 u8 reserved_1; /*01h */
1076 u8 cmd_status; /*02h */
1077 u8 reserved_2; /*03h */
1079 u8 target_id; /*04h */
1080 u8 reserved_3[2]; /*05h */
1081 u8 sge_count; /*07h */
1083 u32 context; /*08h */
1087 u16 timeout; /*12h */
1089 u32 data_xfer_len; /*14h */
1091 u16 fis[10]; /*18h */
1095 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1096 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1099 } __attribute__ ((packed));
1101 union megasas_frame {
1103 struct megasas_header hdr;
1104 struct megasas_init_frame init;
1105 struct megasas_io_frame io;
1106 struct megasas_pthru_frame pthru;
1107 struct megasas_dcmd_frame dcmd;
1108 struct megasas_abort_frame abort;
1109 struct megasas_smp_frame smp;
1110 struct megasas_stp_frame stp;
1117 union megasas_evt_class_locale {
1123 } __attribute__ ((packed)) members;
1127 } __attribute__ ((packed));
1129 struct megasas_evt_log_info {
1133 u32 shutdown_seq_num;
1136 } __attribute__ ((packed));
1138 struct megasas_progress {
1141 u16 elapsed_seconds;
1143 } __attribute__ ((packed));
1145 struct megasas_evtarg_ld {
1151 } __attribute__ ((packed));
1153 struct megasas_evtarg_pd {
1158 } __attribute__ ((packed));
1160 struct megasas_evt_detail {
1165 union megasas_evt_class_locale cl;
1171 struct megasas_evtarg_pd pd;
1177 } __attribute__ ((packed)) cdbSense;
1179 struct megasas_evtarg_ld ld;
1182 struct megasas_evtarg_ld ld;
1184 } __attribute__ ((packed)) ld_count;
1188 struct megasas_evtarg_ld ld;
1189 } __attribute__ ((packed)) ld_lba;
1192 struct megasas_evtarg_ld ld;
1195 } __attribute__ ((packed)) ld_owner;
1200 struct megasas_evtarg_ld ld;
1201 struct megasas_evtarg_pd pd;
1202 } __attribute__ ((packed)) ld_lba_pd_lba;
1205 struct megasas_evtarg_ld ld;
1206 struct megasas_progress prog;
1207 } __attribute__ ((packed)) ld_prog;
1210 struct megasas_evtarg_ld ld;
1213 } __attribute__ ((packed)) ld_state;
1217 struct megasas_evtarg_ld ld;
1218 } __attribute__ ((packed)) ld_strip;
1220 struct megasas_evtarg_pd pd;
1223 struct megasas_evtarg_pd pd;
1225 } __attribute__ ((packed)) pd_err;
1229 struct megasas_evtarg_pd pd;
1230 } __attribute__ ((packed)) pd_lba;
1234 struct megasas_evtarg_pd pd;
1235 struct megasas_evtarg_ld ld;
1236 } __attribute__ ((packed)) pd_lba_ld;
1239 struct megasas_evtarg_pd pd;
1240 struct megasas_progress prog;
1241 } __attribute__ ((packed)) pd_prog;
1244 struct megasas_evtarg_pd pd;
1247 } __attribute__ ((packed)) pd_state;
1254 } __attribute__ ((packed)) pci;
1262 } __attribute__ ((packed)) time;
1268 } __attribute__ ((packed)) ecc;
1276 char description[128];
1278 } __attribute__ ((packed));
1280 struct megasas_aen_event {
1281 struct work_struct hotplug_work;
1282 struct megasas_instance *instance;
1285 struct megasas_irq_context {
1286 struct megasas_instance *instance;
1290 struct megasas_instance {
1293 dma_addr_t producer_h;
1295 dma_addr_t consumer_h;
1298 dma_addr_t reply_queue_h;
1300 struct megasas_register_set __iomem *reg_set;
1302 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
1303 u8 ld_ids[MEGASAS_MAX_LD_IDS];
1308 /* For Fusion its num IOCTL cmds, for others MFI based its
1311 u32 max_sectors_per_req;
1312 struct megasas_aen_event *ev;
1314 struct megasas_cmd **cmd_list;
1315 struct list_head cmd_pool;
1316 /* used to sync fire the cmd to fw */
1317 spinlock_t cmd_pool_lock;
1318 /* used to sync fire the cmd to fw */
1319 spinlock_t hba_lock;
1320 /* used to synch producer, consumer ptrs in dpc */
1321 spinlock_t completion_lock;
1322 struct dma_pool *frame_dma_pool;
1323 struct dma_pool *sense_dma_pool;
1325 struct megasas_evt_detail *evt_detail;
1326 dma_addr_t evt_detail_h;
1327 struct megasas_cmd *aen_cmd;
1328 struct mutex aen_mutex;
1329 struct semaphore ioctl_sem;
1331 struct Scsi_Host *host;
1333 wait_queue_head_t int_cmd_wait_q;
1334 wait_queue_head_t abort_cmd_wait_q;
1336 struct pci_dev *pdev;
1338 u32 fw_support_ieee;
1340 atomic_t fw_outstanding;
1341 atomic_t fw_reset_no_pci_access;
1343 struct megasas_instance_template *instancet;
1344 struct tasklet_struct isr_tasklet;
1345 struct work_struct work_init;
1351 u8 disableOnlineCtrlReset;
1353 unsigned long last_time;
1357 struct timer_list io_completion_timer;
1358 struct list_head internal_reset_pending_q;
1360 /* Ptr to hba specific information */
1362 unsigned int msix_vectors;
1363 struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
1364 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
1366 struct megasas_cmd *map_update_cmd;
1369 struct mutex reset_mutex;
1373 MEGASAS_HBA_OPERATIONAL = 0,
1374 MEGASAS_ADPRESET_SM_INFAULT = 1,
1375 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1376 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
1377 MEGASAS_HW_CRITICAL_ERROR = 4,
1378 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
1381 struct megasas_instance_template {
1382 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1383 u32, struct megasas_register_set __iomem *);
1385 void (*enable_intr)(struct megasas_register_set __iomem *) ;
1386 void (*disable_intr)(struct megasas_register_set __iomem *);
1388 int (*clear_intr)(struct megasas_register_set __iomem *);
1390 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1391 int (*adp_reset)(struct megasas_instance *, \
1392 struct megasas_register_set __iomem *);
1393 int (*check_reset)(struct megasas_instance *, \
1394 struct megasas_register_set __iomem *);
1395 irqreturn_t (*service_isr)(int irq, void *devp);
1396 void (*tasklet)(unsigned long);
1397 u32 (*init_adapter)(struct megasas_instance *);
1398 u32 (*build_and_issue_cmd) (struct megasas_instance *,
1399 struct scsi_cmnd *);
1400 void (*issue_dcmd) (struct megasas_instance *instance,
1401 struct megasas_cmd *cmd);
1404 #define MEGASAS_IS_LOGICAL(scp) \
1405 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1407 #define MEGASAS_DEV_INDEX(inst, scp) \
1408 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1411 struct megasas_cmd {
1413 union megasas_frame *frame;
1414 dma_addr_t frame_phys_addr;
1416 dma_addr_t sense_phys_addr;
1422 u8 retry_for_fw_reset;
1425 struct list_head list;
1426 struct scsi_cmnd *scmd;
1427 struct megasas_instance *instance;
1437 #define MAX_MGMT_ADAPTERS 1024
1438 #define MAX_IOCTL_SGE 16
1440 struct megasas_iocpacket {
1450 struct megasas_header hdr;
1453 struct iovec sgl[MAX_IOCTL_SGE];
1455 } __attribute__ ((packed));
1457 struct megasas_aen {
1461 u32 class_locale_word;
1462 } __attribute__ ((packed));
1464 #ifdef CONFIG_COMPAT
1465 struct compat_megasas_iocpacket {
1474 struct megasas_header hdr;
1476 struct compat_iovec sgl[MAX_IOCTL_SGE];
1477 } __attribute__ ((packed));
1479 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
1482 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
1483 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1485 struct megasas_mgmt_info {
1488 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1492 #define msi_control_reg(base) (base + PCI_MSI_FLAGS)
1493 #define PCI_MSIX_FLAGS_ENABLE (1 << 15)
1495 #endif /*LSI_MEGARAID_SAS_H */