drivers/scsi/lpfc/lpfc_hw4.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2009 Emulex.  All rights reserved.                *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *******************************************************************/
  20
  21 /* Macros to deal with bit fields. Each bit field must have 3 #defines
  22  * associated with it (_SHIFT, _MASK, and _WORD).
  23  * EG. For a bit field that is in the 7th bit of the "field4" field of a
  24  * structure and is 2 bits in size the following #defines must exist:
  25  *      struct temp {
  26  *              uint32_t        field1;
  27  *              uint32_t        field2;
  28  *              uint32_t        field3;
  29  *              uint32_t        field4;
  30  *      #define example_bit_field_SHIFT         7
  31  *      #define example_bit_field_MASK          0x03
  32  *      #define example_bit_field_WORD          field4
  33  *              uint32_t        field5;
  34  *      };
  35  * Then the macros below may be used to get or set the value of that field.
  36  * EG. To get the value of the bit field from the above example:
  37  *      struct temp t1;
  38  *      value = bf_get(example_bit_field, &t1);
  39  * And then to set that bit field:
  40  *      bf_set(example_bit_field, &t1, 2);
  41  * Or clear that bit field:
  42  *      bf_set(example_bit_field, &t1, 0);
  43  */
  44 #define bf_get_le32(name, ptr) \
  45         ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
  46 #define bf_get(name, ptr) \
  47         (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
  48 #define bf_set_le32(name, ptr, value) \
  49         ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
  50         name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
  51         ~(name##_MASK << name##_SHIFT)))))
  52 #define bf_set(name, ptr, value) \
  53         ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
  54                  ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
  55
  56 struct dma_address {
  57         uint32_t addr_lo;
  58         uint32_t addr_hi;
  59 };
  60
  61 struct lpfc_sli_intf {
  62         uint32_t word0;
  63 #define lpfc_sli_intf_valid_SHIFT               29
  64 #define lpfc_sli_intf_valid_MASK                0x00000007
  65 #define lpfc_sli_intf_valid_WORD                word0
  66 #define LPFC_SLI_INTF_VALID             6
  67 #define lpfc_sli_intf_sli_hint2_SHIFT           24
  68 #define lpfc_sli_intf_sli_hint2_MASK            0x0000001F
  69 #define lpfc_sli_intf_sli_hint2_WORD            word0
  70 #define LPFC_SLI_INTF_SLI_HINT2_NONE    0
  71 #define lpfc_sli_intf_sli_hint1_SHIFT           16
  72 #define lpfc_sli_intf_sli_hint1_MASK            0x000000FF
  73 #define lpfc_sli_intf_sli_hint1_WORD            word0
  74 #define LPFC_SLI_INTF_SLI_HINT1_NONE    0
  75 #define LPFC_SLI_INTF_SLI_HINT1_1       1
  76 #define LPFC_SLI_INTF_SLI_HINT1_2       2
  77 #define lpfc_sli_intf_if_type_SHIFT             12
  78 #define lpfc_sli_intf_if_type_MASK              0x0000000F
  79 #define lpfc_sli_intf_if_type_WORD              word0
  80 #define LPFC_SLI_INTF_IF_TYPE_0         0
  81 #define LPFC_SLI_INTF_IF_TYPE_1         1
  82 #define LPFC_SLI_INTF_IF_TYPE_2         2
  83 #define lpfc_sli_intf_sli_family_SHIFT          8
  84 #define lpfc_sli_intf_sli_family_MASK           0x0000000F
  85 #define lpfc_sli_intf_sli_family_WORD           word0
  86 #define LPFC_SLI_INTF_FAMILY_BE2        0x0
  87 #define LPFC_SLI_INTF_FAMILY_BE3        0x1
  88 #define LPFC_SLI_INTF_FAMILY_LNCR_A0    0xa
  89 #define LPFC_SLI_INTF_FAMILY_LNCR_B0    0xb
  90 #define lpfc_sli_intf_slirev_SHIFT              4
  91 #define lpfc_sli_intf_slirev_MASK               0x0000000F
  92 #define lpfc_sli_intf_slirev_WORD               word0
  93 #define LPFC_SLI_INTF_REV_SLI3          3
  94 #define LPFC_SLI_INTF_REV_SLI4          4
  95 #define lpfc_sli_intf_func_type_SHIFT           0
  96 #define lpfc_sli_intf_func_type_MASK            0x00000001
  97 #define lpfc_sli_intf_func_type_WORD            word0
  98 #define LPFC_SLI_INTF_IF_TYPE_PHYS      0
  99 #define LPFC_SLI_INTF_IF_TYPE_VIRT      1
 100 };
 101
 102 #define LPFC_SLI4_MBX_EMBED     true
 103 #define LPFC_SLI4_MBX_NEMBED    false
 104
 105 #define LPFC_SLI4_MB_WORD_COUNT         64
 106 #define LPFC_MAX_MQ_PAGE                8
 107 #define LPFC_MAX_WQ_PAGE                8
 108 #define LPFC_MAX_CQ_PAGE                4
 109 #define LPFC_MAX_EQ_PAGE                8
 110
 111 #define LPFC_VIR_FUNC_MAX       32 /* Maximum number of virtual functions */
 112 #define LPFC_PCI_FUNC_MAX        5 /* Maximum number of PCI functions */
 113 #define LPFC_VFR_PAGE_SIZE      0x1000 /* 4KB BAR2 per-VF register page size */
 114
 115 /* Define SLI4 Alignment requirements. */
 116 #define LPFC_ALIGN_16_BYTE      16
 117 #define LPFC_ALIGN_64_BYTE      64
 118
 119 /* Define SLI4 specific definitions. */
 120 #define LPFC_MQ_CQE_BYTE_OFFSET 256
 121 #define LPFC_MBX_CMD_HDR_LENGTH 16
 122 #define LPFC_MBX_ERROR_RANGE    0x4000
 123 #define LPFC_BMBX_BIT1_ADDR_HI  0x2
 124 #define LPFC_BMBX_BIT1_ADDR_LO  0
 125 #define LPFC_RPI_HDR_COUNT      64
 126 #define LPFC_HDR_TEMPLATE_SIZE  4096
 127 #define LPFC_RPI_ALLOC_ERROR    0xFFFF
 128 #define LPFC_FCF_RECORD_WD_CNT  132
 129 #define LPFC_ENTIRE_FCF_DATABASE 0
 130 #define LPFC_DFLT_FCF_INDEX      0
 131
 132 /* Virtual function numbers */
 133 #define LPFC_VF0                0
 134 #define LPFC_VF1                1
 135 #define LPFC_VF2                2
 136 #define LPFC_VF3                3
 137 #define LPFC_VF4                4
 138 #define LPFC_VF5                5
 139 #define LPFC_VF6                6
 140 #define LPFC_VF7                7
 141 #define LPFC_VF8                8
 142 #define LPFC_VF9                9
 143 #define LPFC_VF10               10
 144 #define LPFC_VF11               11
 145 #define LPFC_VF12               12
 146 #define LPFC_VF13               13
 147 #define LPFC_VF14               14
 148 #define LPFC_VF15               15
 149 #define LPFC_VF16               16
 150 #define LPFC_VF17               17
 151 #define LPFC_VF18               18
 152 #define LPFC_VF19               19
 153 #define LPFC_VF20               20
 154 #define LPFC_VF21               21
 155 #define LPFC_VF22               22
 156 #define LPFC_VF23               23
 157 #define LPFC_VF24               24
 158 #define LPFC_VF25               25
 159 #define LPFC_VF26               26
 160 #define LPFC_VF27               27
 161 #define LPFC_VF28               28
 162 #define LPFC_VF29               29
 163 #define LPFC_VF30               30
 164 #define LPFC_VF31               31
 165
 166 /* PCI function numbers */
 167 #define LPFC_PCI_FUNC0          0
 168 #define LPFC_PCI_FUNC1          1
 169 #define LPFC_PCI_FUNC2          2
 170 #define LPFC_PCI_FUNC3          3
 171 #define LPFC_PCI_FUNC4          4
 172
 173 /* Active interrupt test count */
 174 #define LPFC_ACT_INTR_CNT       4
 175
 176 /* Delay Multiplier constant */
 177 #define LPFC_DMULT_CONST       651042
 178 #define LPFC_MIM_IMAX          636
 179 #define LPFC_FP_DEF_IMAX       10000
 180 #define LPFC_SP_DEF_IMAX       10000
 181
 182 /* PORT_CAPABILITIES constants. */
 183 #define LPFC_MAX_SUPPORTED_PAGES        8
 184
 185 struct ulp_bde64 {
 186         union ULP_BDE_TUS {
 187                 uint32_t w;
 188                 struct {
 189 #ifdef __BIG_ENDIAN_BITFIELD
 190                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 191                                                    VALUE !! */
 192                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 193 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 194                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 195                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 196                                                    VALUE !! */
 197 #endif
 198 #define BUFF_TYPE_BDE_64    0x00        /* BDE (Host_resident) */
 199 #define BUFF_TYPE_BDE_IMMED 0x01        /* Immediate Data BDE */
 200 #define BUFF_TYPE_BDE_64P   0x02        /* BDE (Port-resident) */
 201 #define BUFF_TYPE_BDE_64I   0x08        /* Input BDE (Host-resident) */
 202 #define BUFF_TYPE_BDE_64IP  0x0A        /* Input BDE (Port-resident) */
 203 #define BUFF_TYPE_BLP_64    0x40        /* BLP (Host-resident) */
 204 #define BUFF_TYPE_BLP_64P   0x42        /* BLP (Port-resident) */
 205                 } f;
 206         } tus;
 207         uint32_t addrLow;
 208         uint32_t addrHigh;
 209 };
 210
 211 struct lpfc_sli4_flags {
 212         uint32_t word0;
 213 #define lpfc_fip_flag_SHIFT 0
 214 #define lpfc_fip_flag_MASK 0x00000001
 215 #define lpfc_fip_flag_WORD word0
 216 };
 217
 218 struct sli4_bls_acc {
 219         uint32_t word0_rsvd;      /* Word0 must be reserved */
 220         uint32_t word1;
 221 #define lpfc_abts_orig_SHIFT      0
 222 #define lpfc_abts_orig_MASK       0x00000001
 223 #define lpfc_abts_orig_WORD       word1
 224 #define LPFC_ABTS_UNSOL_RSP       1
 225 #define LPFC_ABTS_UNSOL_INT       0
 226         uint32_t word2;
 227 #define lpfc_abts_rxid_SHIFT      0
 228 #define lpfc_abts_rxid_MASK       0x0000FFFF
 229 #define lpfc_abts_rxid_WORD       word2
 230 #define lpfc_abts_oxid_SHIFT      16
 231 #define lpfc_abts_oxid_MASK       0x0000FFFF
 232 #define lpfc_abts_oxid_WORD       word2
 233         uint32_t word3;
 234         uint32_t word4;
 235         uint32_t word5_rsvd;    /* Word5 must be reserved */
 236 };
 237
 238 /* event queue entry structure */
 239 struct lpfc_eqe {
 240         uint32_t word0;
 241 #define lpfc_eqe_resource_id_SHIFT      16
 242 #define lpfc_eqe_resource_id_MASK       0x000000FF
 243 #define lpfc_eqe_resource_id_WORD       word0
 244 #define lpfc_eqe_minor_code_SHIFT       4
 245 #define lpfc_eqe_minor_code_MASK        0x00000FFF
 246 #define lpfc_eqe_minor_code_WORD        word0
 247 #define lpfc_eqe_major_code_SHIFT       1
 248 #define lpfc_eqe_major_code_MASK        0x00000007
 249 #define lpfc_eqe_major_code_WORD        word0
 250 #define lpfc_eqe_valid_SHIFT            0
 251 #define lpfc_eqe_valid_MASK             0x00000001
 252 #define lpfc_eqe_valid_WORD             word0
 253 };
 254
 255 /* completion queue entry structure (common fields for all cqe types) */
 256 struct lpfc_cqe {
 257         uint32_t reserved0;
 258         uint32_t reserved1;
 259         uint32_t reserved2;
 260         uint32_t word3;
 261 #define lpfc_cqe_valid_SHIFT            31
 262 #define lpfc_cqe_valid_MASK             0x00000001
 263 #define lpfc_cqe_valid_WORD             word3
 264 #define lpfc_cqe_code_SHIFT             16
 265 #define lpfc_cqe_code_MASK              0x000000FF
 266 #define lpfc_cqe_code_WORD              word3
 267 };
 268
 269 /* Completion Queue Entry Status Codes */
 270 #define CQE_STATUS_SUCCESS              0x0
 271 #define CQE_STATUS_FCP_RSP_FAILURE      0x1
 272 #define CQE_STATUS_REMOTE_STOP          0x2
 273 #define CQE_STATUS_LOCAL_REJECT         0x3
 274 #define CQE_STATUS_NPORT_RJT            0x4
 275 #define CQE_STATUS_FABRIC_RJT           0x5
 276 #define CQE_STATUS_NPORT_BSY            0x6
 277 #define CQE_STATUS_FABRIC_BSY           0x7
 278 #define CQE_STATUS_INTERMED_RSP         0x8
 279 #define CQE_STATUS_LS_RJT               0x9
 280 #define CQE_STATUS_CMD_REJECT           0xb
 281 #define CQE_STATUS_FCP_TGT_LENCHECK     0xc
 282 #define CQE_STATUS_NEED_BUFF_ENTRY      0xf
 283
 284 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
 285 #define CQE_HW_STATUS_NO_ERR            0x0
 286 #define CQE_HW_STATUS_UNDERRUN          0x1
 287 #define CQE_HW_STATUS_OVERRUN           0x2
 288
 289 /* Completion Queue Entry Codes */
 290 #define CQE_CODE_COMPL_WQE              0x1
 291 #define CQE_CODE_RELEASE_WQE            0x2
 292 #define CQE_CODE_RECEIVE                0x4
 293 #define CQE_CODE_XRI_ABORTED            0x5
 294
 295 /* completion queue entry for wqe completions */
 296 struct lpfc_wcqe_complete {
 297         uint32_t word0;
 298 #define lpfc_wcqe_c_request_tag_SHIFT   16
 299 #define lpfc_wcqe_c_request_tag_MASK    0x0000FFFF
 300 #define lpfc_wcqe_c_request_tag_WORD    word0
 301 #define lpfc_wcqe_c_status_SHIFT        8
 302 #define lpfc_wcqe_c_status_MASK         0x000000FF
 303 #define lpfc_wcqe_c_status_WORD         word0
 304 #define lpfc_wcqe_c_hw_status_SHIFT     0
 305 #define lpfc_wcqe_c_hw_status_MASK      0x000000FF
 306 #define lpfc_wcqe_c_hw_status_WORD      word0
 307         uint32_t total_data_placed;
 308         uint32_t parameter;
 309         uint32_t word3;
 310 #define lpfc_wcqe_c_valid_SHIFT         lpfc_cqe_valid_SHIFT
 311 #define lpfc_wcqe_c_valid_MASK          lpfc_cqe_valid_MASK
 312 #define lpfc_wcqe_c_valid_WORD          lpfc_cqe_valid_WORD
 313 #define lpfc_wcqe_c_xb_SHIFT            28
 314 #define lpfc_wcqe_c_xb_MASK             0x00000001
 315 #define lpfc_wcqe_c_xb_WORD             word3
 316 #define lpfc_wcqe_c_pv_SHIFT            27
 317 #define lpfc_wcqe_c_pv_MASK             0x00000001
 318 #define lpfc_wcqe_c_pv_WORD             word3
 319 #define lpfc_wcqe_c_priority_SHIFT      24
 320 #define lpfc_wcqe_c_priority_MASK               0x00000007
 321 #define lpfc_wcqe_c_priority_WORD               word3
 322 #define lpfc_wcqe_c_code_SHIFT          lpfc_cqe_code_SHIFT
 323 #define lpfc_wcqe_c_code_MASK           lpfc_cqe_code_MASK
 324 #define lpfc_wcqe_c_code_WORD           lpfc_cqe_code_WORD
 325 };
 326
 327 /* completion queue entry for wqe release */
 328 struct lpfc_wcqe_release {
 329         uint32_t reserved0;
 330         uint32_t reserved1;
 331         uint32_t word2;
 332 #define lpfc_wcqe_r_wq_id_SHIFT         16
 333 #define lpfc_wcqe_r_wq_id_MASK          0x0000FFFF
 334 #define lpfc_wcqe_r_wq_id_WORD          word2
 335 #define lpfc_wcqe_r_wqe_index_SHIFT     0
 336 #define lpfc_wcqe_r_wqe_index_MASK      0x0000FFFF
 337 #define lpfc_wcqe_r_wqe_index_WORD      word2
 338         uint32_t word3;
 339 #define lpfc_wcqe_r_valid_SHIFT         lpfc_cqe_valid_SHIFT
 340 #define lpfc_wcqe_r_valid_MASK          lpfc_cqe_valid_MASK
 341 #define lpfc_wcqe_r_valid_WORD          lpfc_cqe_valid_WORD
 342 #define lpfc_wcqe_r_code_SHIFT          lpfc_cqe_code_SHIFT
 343 #define lpfc_wcqe_r_code_MASK           lpfc_cqe_code_MASK
 344 #define lpfc_wcqe_r_code_WORD           lpfc_cqe_code_WORD
 345 };
 346
 347 struct sli4_wcqe_xri_aborted {
 348         uint32_t word0;
 349 #define lpfc_wcqe_xa_status_SHIFT               8
 350 #define lpfc_wcqe_xa_status_MASK                0x000000FF
 351 #define lpfc_wcqe_xa_status_WORD                word0
 352         uint32_t parameter;
 353         uint32_t word2;
 354 #define lpfc_wcqe_xa_remote_xid_SHIFT   16
 355 #define lpfc_wcqe_xa_remote_xid_MASK    0x0000FFFF
 356 #define lpfc_wcqe_xa_remote_xid_WORD    word2
 357 #define lpfc_wcqe_xa_xri_SHIFT          0
 358 #define lpfc_wcqe_xa_xri_MASK           0x0000FFFF
 359 #define lpfc_wcqe_xa_xri_WORD           word2
 360         uint32_t word3;
 361 #define lpfc_wcqe_xa_valid_SHIFT        lpfc_cqe_valid_SHIFT
 362 #define lpfc_wcqe_xa_valid_MASK         lpfc_cqe_valid_MASK
 363 #define lpfc_wcqe_xa_valid_WORD         lpfc_cqe_valid_WORD
 364 #define lpfc_wcqe_xa_ia_SHIFT           30
 365 #define lpfc_wcqe_xa_ia_MASK            0x00000001
 366 #define lpfc_wcqe_xa_ia_WORD            word3
 367 #define CQE_XRI_ABORTED_IA_REMOTE       0
 368 #define CQE_XRI_ABORTED_IA_LOCAL        1
 369 #define lpfc_wcqe_xa_br_SHIFT           29
 370 #define lpfc_wcqe_xa_br_MASK            0x00000001
 371 #define lpfc_wcqe_xa_br_WORD            word3
 372 #define CQE_XRI_ABORTED_BR_BA_ACC       0
 373 #define CQE_XRI_ABORTED_BR_BA_RJT       1
 374 #define lpfc_wcqe_xa_eo_SHIFT           28
 375 #define lpfc_wcqe_xa_eo_MASK            0x00000001
 376 #define lpfc_wcqe_xa_eo_WORD            word3
 377 #define CQE_XRI_ABORTED_EO_REMOTE       0
 378 #define CQE_XRI_ABORTED_EO_LOCAL        1
 379 #define lpfc_wcqe_xa_code_SHIFT         lpfc_cqe_code_SHIFT
 380 #define lpfc_wcqe_xa_code_MASK          lpfc_cqe_code_MASK
 381 #define lpfc_wcqe_xa_code_WORD          lpfc_cqe_code_WORD
 382 };
 383
 384 /* completion queue entry structure for rqe completion */
 385 struct lpfc_rcqe {
 386         uint32_t word0;
 387 #define lpfc_rcqe_bindex_SHIFT          16
 388 #define lpfc_rcqe_bindex_MASK           0x0000FFF
 389 #define lpfc_rcqe_bindex_WORD           word0
 390 #define lpfc_rcqe_status_SHIFT          8
 391 #define lpfc_rcqe_status_MASK           0x000000FF
 392 #define lpfc_rcqe_status_WORD           word0
 393 #define FC_STATUS_RQ_SUCCESS            0x10 /* Async receive successful */
 394 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED   0x11 /* payload truncated */
 395 #define FC_STATUS_INSUFF_BUF_NEED_BUF   0x12 /* Insufficient buffers */
 396 #define FC_STATUS_INSUFF_BUF_FRM_DISC   0x13 /* Frame Discard */
 397         uint32_t reserved1;
 398         uint32_t word2;
 399 #define lpfc_rcqe_length_SHIFT          16
 400 #define lpfc_rcqe_length_MASK           0x0000FFFF
 401 #define lpfc_rcqe_length_WORD           word2
 402 #define lpfc_rcqe_rq_id_SHIFT           6
 403 #define lpfc_rcqe_rq_id_MASK            0x000003FF
 404 #define lpfc_rcqe_rq_id_WORD            word2
 405 #define lpfc_rcqe_fcf_id_SHIFT          0
 406 #define lpfc_rcqe_fcf_id_MASK           0x0000003F
 407 #define lpfc_rcqe_fcf_id_WORD           word2
 408         uint32_t word3;
 409 #define lpfc_rcqe_valid_SHIFT           lpfc_cqe_valid_SHIFT
 410 #define lpfc_rcqe_valid_MASK            lpfc_cqe_valid_MASK
 411 #define lpfc_rcqe_valid_WORD            lpfc_cqe_valid_WORD
 412 #define lpfc_rcqe_port_SHIFT            30
 413 #define lpfc_rcqe_port_MASK             0x00000001
 414 #define lpfc_rcqe_port_WORD             word3
 415 #define lpfc_rcqe_hdr_length_SHIFT      24
 416 #define lpfc_rcqe_hdr_length_MASK       0x0000001F
 417 #define lpfc_rcqe_hdr_length_WORD       word3
 418 #define lpfc_rcqe_code_SHIFT            lpfc_cqe_code_SHIFT
 419 #define lpfc_rcqe_code_MASK             lpfc_cqe_code_MASK
 420 #define lpfc_rcqe_code_WORD             lpfc_cqe_code_WORD
 421 #define lpfc_rcqe_eof_SHIFT             8
 422 #define lpfc_rcqe_eof_MASK              0x000000FF
 423 #define lpfc_rcqe_eof_WORD              word3
 424 #define FCOE_EOFn       0x41
 425 #define FCOE_EOFt       0x42
 426 #define FCOE_EOFni      0x49
 427 #define FCOE_EOFa       0x50
 428 #define lpfc_rcqe_sof_SHIFT             0
 429 #define lpfc_rcqe_sof_MASK              0x000000FF
 430 #define lpfc_rcqe_sof_WORD              word3
 431 #define FCOE_SOFi2      0x2d
 432 #define FCOE_SOFi3      0x2e
 433 #define FCOE_SOFn2      0x35
 434 #define FCOE_SOFn3      0x36
 435 };
 436
 437 struct lpfc_rqe {
 438         uint32_t address_hi;
 439         uint32_t address_lo;
 440 };
 441
 442 /* buffer descriptors */
 443 struct lpfc_bde4 {
 444         uint32_t addr_hi;
 445         uint32_t addr_lo;
 446         uint32_t word2;
 447 #define lpfc_bde4_last_SHIFT            31
 448 #define lpfc_bde4_last_MASK             0x00000001
 449 #define lpfc_bde4_last_WORD             word2
 450 #define lpfc_bde4_sge_offset_SHIFT      0
 451 #define lpfc_bde4_sge_offset_MASK       0x000003FF
 452 #define lpfc_bde4_sge_offset_WORD       word2
 453         uint32_t word3;
 454 #define lpfc_bde4_length_SHIFT          0
 455 #define lpfc_bde4_length_MASK           0x000000FF
 456 #define lpfc_bde4_length_WORD           word3
 457 };
 458
 459 struct lpfc_register {
 460         uint32_t word0;
 461 };
 462
 463 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
 464 #define LPFC_UERR_STATUS_HI             0x00A4
 465 #define LPFC_UERR_STATUS_LO             0x00A0
 466 #define LPFC_UE_MASK_HI                 0x00AC
 467 #define LPFC_UE_MASK_LO                 0x00A8
 468
 469 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
 470 #define LPFC_SLI_INTF                   0x0058
 471
 472 #define LPFC_SLIPORT_IF2_SMPHR          0x0400
 473 #define lpfc_port_smphr_perr_SHIFT      31
 474 #define lpfc_port_smphr_perr_MASK       0x1
 475 #define lpfc_port_smphr_perr_WORD       word0
 476 #define lpfc_port_smphr_sfi_SHIFT       30
 477 #define lpfc_port_smphr_sfi_MASK        0x1
 478 #define lpfc_port_smphr_sfi_WORD        word0
 479 #define lpfc_port_smphr_nip_SHIFT       29
 480 #define lpfc_port_smphr_nip_MASK        0x1
 481 #define lpfc_port_smphr_nip_WORD        word0
 482 #define lpfc_port_smphr_ipc_SHIFT       28
 483 #define lpfc_port_smphr_ipc_MASK        0x1
 484 #define lpfc_port_smphr_ipc_WORD        word0
 485 #define lpfc_port_smphr_scr1_SHIFT      27
 486 #define lpfc_port_smphr_scr1_MASK       0x1
 487 #define lpfc_port_smphr_scr1_WORD       word0
 488 #define lpfc_port_smphr_scr2_SHIFT      26
 489 #define lpfc_port_smphr_scr2_MASK       0x1
 490 #define lpfc_port_smphr_scr2_WORD       word0
 491 #define lpfc_port_smphr_host_scratch_SHIFT      16
 492 #define lpfc_port_smphr_host_scratch_MASK       0xFF
 493 #define lpfc_port_smphr_host_scratch_WORD       word0
 494 #define lpfc_port_smphr_port_status_SHIFT       0
 495 #define lpfc_port_smphr_port_status_MASK        0xFFFF
 496 #define lpfc_port_smphr_port_status_WORD        word0
 497
 498 #define LPFC_POST_STAGE_POWER_ON_RESET                  0x0000
 499 #define LPFC_POST_STAGE_AWAITING_HOST_RDY               0x0001
 500 #define LPFC_POST_STAGE_HOST_RDY                        0x0002
 501 #define LPFC_POST_STAGE_BE_RESET                        0x0003
 502 #define LPFC_POST_STAGE_SEEPROM_CS_START                0x0100
 503 #define LPFC_POST_STAGE_SEEPROM_CS_DONE                 0x0101
 504 #define LPFC_POST_STAGE_DDR_CONFIG_START                0x0200
 505 #define LPFC_POST_STAGE_DDR_CONFIG_DONE                 0x0201
 506 #define LPFC_POST_STAGE_DDR_CALIBRATE_START             0x0300
 507 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE              0x0301
 508 #define LPFC_POST_STAGE_DDR_TEST_START                  0x0400
 509 #define LPFC_POST_STAGE_DDR_TEST_DONE                   0x0401
 510 #define LPFC_POST_STAGE_REDBOOT_INIT_START              0x0600
 511 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE               0x0601
 512 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START             0x0700
 513 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE              0x0701
 514 #define LPFC_POST_STAGE_ARMFW_START                     0x0800
 515 #define LPFC_POST_STAGE_DHCP_QUERY_START                0x0900
 516 #define LPFC_POST_STAGE_DHCP_QUERY_DONE                 0x0901
 517 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START     0x0A00
 518 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE      0x0A01
 519 #define LPFC_POST_STAGE_RC_OPTION_SET                   0x0B00
 520 #define LPFC_POST_STAGE_SWITCH_LINK                     0x0B01
 521 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE               0x0B02
 522 #define LPFC_POST_STAGE_PERFROM_TFTP                    0x0B03
 523 #define LPFC_POST_STAGE_PARSE_XML                       0x0B04
 524 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE                  0x0B05
 525 #define LPFC_POST_STAGE_FLASH_IMAGE                     0x0B06
 526 #define LPFC_POST_STAGE_RC_DONE                         0x0B07
 527 #define LPFC_POST_STAGE_REBOOT_SYSTEM                   0x0B08
 528 #define LPFC_POST_STAGE_MAC_ADDRESS                     0x0C00
 529 #define LPFC_POST_STAGE_PORT_READY                      0xC000
 530 #define LPFC_POST_STAGE_PORT_UE                         0xF000
 531
 532 #define LPFC_SLIPORT_STATUS             0x0404
 533 #define lpfc_sliport_status_err_SHIFT   31
 534 #define lpfc_sliport_status_err_MASK    0x1
 535 #define lpfc_sliport_status_err_WORD    word0
 536 #define lpfc_sliport_status_end_SHIFT   30
 537 #define lpfc_sliport_status_end_MASK    0x1
 538 #define lpfc_sliport_status_end_WORD    word0
 539 #define lpfc_sliport_status_oti_SHIFT   29
 540 #define lpfc_sliport_status_oti_MASK    0x1
 541 #define lpfc_sliport_status_oti_WORD    word0
 542 #define lpfc_sliport_status_rn_SHIFT    24
 543 #define lpfc_sliport_status_rn_MASK     0x1
 544 #define lpfc_sliport_status_rn_WORD     word0
 545 #define lpfc_sliport_status_rdy_SHIFT   23
 546 #define lpfc_sliport_status_rdy_MASK    0x1
 547 #define lpfc_sliport_status_rdy_WORD    word0
 548 #define MAX_IF_TYPE_2_RESETS    1000
 549
 550 #define LPFC_SLIPORT_CNTRL              0x0408
 551 #define lpfc_sliport_ctrl_end_SHIFT     30
 552 #define lpfc_sliport_ctrl_end_MASK      0x1
 553 #define lpfc_sliport_ctrl_end_WORD      word0
 554 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
 555 #define LPFC_SLIPORT_BIG_ENDIAN    1
 556 #define lpfc_sliport_ctrl_ip_SHIFT      27
 557 #define lpfc_sliport_ctrl_ip_MASK       0x1
 558 #define lpfc_sliport_ctrl_ip_WORD       word0
 559 #define LPFC_SLIPORT_INIT_PORT  1
 560
 561 #define LPFC_SLIPORT_ERR_1              0x040C
 562 #define LPFC_SLIPORT_ERR_2              0x0410
 563
 564 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
 565  * reside in BAR 2.
 566  */
 567 #define LPFC_SLIPORT_IF0_SMPHR  0x00AC
 568
 569 #define LPFC_IMR_MASK_ALL       0xFFFFFFFF
 570 #define LPFC_ISCR_CLEAR_ALL     0xFFFFFFFF
 571
 572 #define LPFC_HST_ISR0           0x0C18
 573 #define LPFC_HST_ISR1           0x0C1C
 574 #define LPFC_HST_ISR2           0x0C20
 575 #define LPFC_HST_ISR3           0x0C24
 576 #define LPFC_HST_ISR4           0x0C28
 577
 578 #define LPFC_HST_IMR0           0x0C48
 579 #define LPFC_HST_IMR1           0x0C4C
 580 #define LPFC_HST_IMR2           0x0C50
 581 #define LPFC_HST_IMR3           0x0C54
 582 #define LPFC_HST_IMR4           0x0C58
 583
 584 #define LPFC_HST_ISCR0          0x0C78
 585 #define LPFC_HST_ISCR1          0x0C7C
 586 #define LPFC_HST_ISCR2          0x0C80
 587 #define LPFC_HST_ISCR3          0x0C84
 588 #define LPFC_HST_ISCR4          0x0C88
 589
 590 #define LPFC_SLI4_INTR0                 BIT0
 591 #define LPFC_SLI4_INTR1                 BIT1
 592 #define LPFC_SLI4_INTR2                 BIT2
 593 #define LPFC_SLI4_INTR3                 BIT3
 594 #define LPFC_SLI4_INTR4                 BIT4
 595 #define LPFC_SLI4_INTR5                 BIT5
 596 #define LPFC_SLI4_INTR6                 BIT6
 597 #define LPFC_SLI4_INTR7                 BIT7
 598 #define LPFC_SLI4_INTR8                 BIT8
 599 #define LPFC_SLI4_INTR9                 BIT9
 600 #define LPFC_SLI4_INTR10                BIT10
 601 #define LPFC_SLI4_INTR11                BIT11
 602 #define LPFC_SLI4_INTR12                BIT12
 603 #define LPFC_SLI4_INTR13                BIT13
 604 #define LPFC_SLI4_INTR14                BIT14
 605 #define LPFC_SLI4_INTR15                BIT15
 606 #define LPFC_SLI4_INTR16                BIT16
 607 #define LPFC_SLI4_INTR17                BIT17
 608 #define LPFC_SLI4_INTR18                BIT18
 609 #define LPFC_SLI4_INTR19                BIT19
 610 #define LPFC_SLI4_INTR20                BIT20
 611 #define LPFC_SLI4_INTR21                BIT21
 612 #define LPFC_SLI4_INTR22                BIT22
 613 #define LPFC_SLI4_INTR23                BIT23
 614 #define LPFC_SLI4_INTR24                BIT24
 615 #define LPFC_SLI4_INTR25                BIT25
 616 #define LPFC_SLI4_INTR26                BIT26
 617 #define LPFC_SLI4_INTR27                BIT27
 618 #define LPFC_SLI4_INTR28                BIT28
 619 #define LPFC_SLI4_INTR29                BIT29
 620 #define LPFC_SLI4_INTR30                BIT30
 621 #define LPFC_SLI4_INTR31                BIT31
 622
 623 /*
 624  * The Doorbell registers defined here exist in different BAR
 625  * register sets depending on the UCNA Port's reported if_type
 626  * value.  For UCNA ports running SLI4 and if_type 0, they reside in
 627  * BAR4.  For UCNA ports running SLI4 and if_type 2, they reside in
 628  * BAR0.  The offsets are the same so the driver must account for
 629  * any base address difference.
 630  */
 631 #define LPFC_RQ_DOORBELL                0x00A0
 632 #define lpfc_rq_doorbell_num_posted_SHIFT       16
 633 #define lpfc_rq_doorbell_num_posted_MASK        0x3FFF
 634 #define lpfc_rq_doorbell_num_posted_WORD        word0
 635 #define LPFC_RQ_POST_BATCH              8       /* RQEs to post at one time */
 636 #define lpfc_rq_doorbell_id_SHIFT               0
 637 #define lpfc_rq_doorbell_id_MASK                0xFFFF
 638 #define lpfc_rq_doorbell_id_WORD                word0
 639
 640 #define LPFC_WQ_DOORBELL                0x0040
 641 #define lpfc_wq_doorbell_num_posted_SHIFT       24
 642 #define lpfc_wq_doorbell_num_posted_MASK        0x00FF
 643 #define lpfc_wq_doorbell_num_posted_WORD        word0
 644 #define lpfc_wq_doorbell_index_SHIFT            16
 645 #define lpfc_wq_doorbell_index_MASK             0x00FF
 646 #define lpfc_wq_doorbell_index_WORD             word0
 647 #define lpfc_wq_doorbell_id_SHIFT               0
 648 #define lpfc_wq_doorbell_id_MASK                0xFFFF
 649 #define lpfc_wq_doorbell_id_WORD                word0
 650
 651 #define LPFC_EQCQ_DOORBELL              0x0120
 652 #define lpfc_eqcq_doorbell_se_SHIFT             31
 653 #define lpfc_eqcq_doorbell_se_MASK              0x0001
 654 #define lpfc_eqcq_doorbell_se_WORD              word0
 655 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF    0
 656 #define LPFC_EQCQ_SOLICIT_ENABLE_ON     1
 657 #define lpfc_eqcq_doorbell_arm_SHIFT            29
 658 #define lpfc_eqcq_doorbell_arm_MASK             0x0001
 659 #define lpfc_eqcq_doorbell_arm_WORD             word0
 660 #define lpfc_eqcq_doorbell_num_released_SHIFT   16
 661 #define lpfc_eqcq_doorbell_num_released_MASK    0x1FFF
 662 #define lpfc_eqcq_doorbell_num_released_WORD    word0
 663 #define lpfc_eqcq_doorbell_qt_SHIFT             10
 664 #define lpfc_eqcq_doorbell_qt_MASK              0x0001
 665 #define lpfc_eqcq_doorbell_qt_WORD              word0
 666 #define LPFC_QUEUE_TYPE_COMPLETION      0
 667 #define LPFC_QUEUE_TYPE_EVENT           1
 668 #define lpfc_eqcq_doorbell_eqci_SHIFT           9
 669 #define lpfc_eqcq_doorbell_eqci_MASK            0x0001
 670 #define lpfc_eqcq_doorbell_eqci_WORD            word0
 671 #define lpfc_eqcq_doorbell_cqid_SHIFT           0
 672 #define lpfc_eqcq_doorbell_cqid_MASK            0x03FF
 673 #define lpfc_eqcq_doorbell_cqid_WORD            word0
 674 #define lpfc_eqcq_doorbell_eqid_SHIFT           0
 675 #define lpfc_eqcq_doorbell_eqid_MASK            0x01FF
 676 #define lpfc_eqcq_doorbell_eqid_WORD            word0
 677
 678 #define LPFC_BMBX                       0x0160
 679 #define lpfc_bmbx_addr_SHIFT            2
 680 #define lpfc_bmbx_addr_MASK             0x3FFFFFFF
 681 #define lpfc_bmbx_addr_WORD             word0
 682 #define lpfc_bmbx_hi_SHIFT              1
 683 #define lpfc_bmbx_hi_MASK               0x0001
 684 #define lpfc_bmbx_hi_WORD               word0
 685 #define lpfc_bmbx_rdy_SHIFT             0
 686 #define lpfc_bmbx_rdy_MASK              0x0001
 687 #define lpfc_bmbx_rdy_WORD              word0
 688
 689 #define LPFC_MQ_DOORBELL                        0x0140
 690 #define lpfc_mq_doorbell_num_posted_SHIFT       16
 691 #define lpfc_mq_doorbell_num_posted_MASK        0x3FFF
 692 #define lpfc_mq_doorbell_num_posted_WORD        word0
 693 #define lpfc_mq_doorbell_id_SHIFT               0
 694 #define lpfc_mq_doorbell_id_MASK                0xFFFF
 695 #define lpfc_mq_doorbell_id_WORD                word0
 696
 697 struct lpfc_sli4_cfg_mhdr {
 698         uint32_t word1;
 699 #define lpfc_mbox_hdr_emb_SHIFT         0
 700 #define lpfc_mbox_hdr_emb_MASK          0x00000001
 701 #define lpfc_mbox_hdr_emb_WORD          word1
 702 #define lpfc_mbox_hdr_sge_cnt_SHIFT     3
 703 #define lpfc_mbox_hdr_sge_cnt_MASK      0x0000001F
 704 #define lpfc_mbox_hdr_sge_cnt_WORD      word1
 705         uint32_t payload_length;
 706         uint32_t tag_lo;
 707         uint32_t tag_hi;
 708         uint32_t reserved5;
 709 };
 710
 711 union lpfc_sli4_cfg_shdr {
 712         struct {
 713                 uint32_t word6;
 714 #define lpfc_mbox_hdr_opcode_SHIFT              0
 715 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
 716 #define lpfc_mbox_hdr_opcode_WORD               word6
 717 #define lpfc_mbox_hdr_subsystem_SHIFT           8
 718 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
 719 #define lpfc_mbox_hdr_subsystem_WORD            word6
 720 #define lpfc_mbox_hdr_port_number_SHIFT         16
 721 #define lpfc_mbox_hdr_port_number_MASK          0x000000FF
 722 #define lpfc_mbox_hdr_port_number_WORD          word6
 723 #define lpfc_mbox_hdr_domain_SHIFT              24
 724 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
 725 #define lpfc_mbox_hdr_domain_WORD               word6
 726                 uint32_t timeout;
 727                 uint32_t request_length;
 728                 uint32_t reserved9;
 729         } request;
 730         struct {
 731                 uint32_t word6;
 732 #define lpfc_mbox_hdr_opcode_SHIFT              0
 733 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
 734 #define lpfc_mbox_hdr_opcode_WORD               word6
 735 #define lpfc_mbox_hdr_subsystem_SHIFT           8
 736 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
 737 #define lpfc_mbox_hdr_subsystem_WORD            word6
 738 #define lpfc_mbox_hdr_domain_SHIFT              24
 739 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
 740 #define lpfc_mbox_hdr_domain_WORD               word6
 741                 uint32_t word7;
 742 #define lpfc_mbox_hdr_status_SHIFT              0
 743 #define lpfc_mbox_hdr_status_MASK               0x000000FF
 744 #define lpfc_mbox_hdr_status_WORD               word7
 745 #define lpfc_mbox_hdr_add_status_SHIFT          8
 746 #define lpfc_mbox_hdr_add_status_MASK           0x000000FF
 747 #define lpfc_mbox_hdr_add_status_WORD           word7
 748                 uint32_t response_length;
 749                 uint32_t actual_response_length;
 750         } response;
 751 };
 752
 753 /* Mailbox structures */
 754 struct mbox_header {
 755         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
 756         union  lpfc_sli4_cfg_shdr cfg_shdr;
 757 };
 758
 759 /* Subsystem Definitions */
 760 #define LPFC_MBOX_SUBSYSTEM_COMMON      0x1
 761 #define LPFC_MBOX_SUBSYSTEM_FCOE        0xC
 762
 763 /* Device Specific Definitions */
 764
 765 /* The HOST ENDIAN defines are in Big Endian format. */
 766 #define HOST_ENDIAN_LOW_WORD0   0xFF3412FF
 767 #define HOST_ENDIAN_HIGH_WORD1  0xFF7856FF
 768
 769 /* Common Opcodes */
 770 #define LPFC_MBOX_OPCODE_CQ_CREATE              0x0C
 771 #define LPFC_MBOX_OPCODE_EQ_CREATE              0x0D
 772 #define LPFC_MBOX_OPCODE_MQ_CREATE              0x15
 773 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES    0x20
 774 #define LPFC_MBOX_OPCODE_NOP                    0x21
 775 #define LPFC_MBOX_OPCODE_MQ_DESTROY             0x35
 776 #define LPFC_MBOX_OPCODE_CQ_DESTROY             0x36
 777 #define LPFC_MBOX_OPCODE_EQ_DESTROY             0x37
 778 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG           0x3A
 779 #define LPFC_MBOX_OPCODE_FUNCTION_RESET         0x3D
 780 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT          0x5A
 781 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS    0xB5
 782
 783 /* FCoE Opcodes */
 784 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE                 0x01
 785 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY                0x02
 786 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES            0x03
 787 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES          0x04
 788 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE                 0x05
 789 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY                0x06
 790 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE            0x08
 791 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF                   0x09
 792 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF                0x0A
 793 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE         0x0B
 794 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF            0x10
 795
 796 /* Mailbox command structures */
 797 struct eq_context {
 798         uint32_t word0;
 799 #define lpfc_eq_context_size_SHIFT      31
 800 #define lpfc_eq_context_size_MASK       0x00000001
 801 #define lpfc_eq_context_size_WORD       word0
 802 #define LPFC_EQE_SIZE_4                 0x0
 803 #define LPFC_EQE_SIZE_16                0x1
 804 #define lpfc_eq_context_valid_SHIFT     29
 805 #define lpfc_eq_context_valid_MASK      0x00000001
 806 #define lpfc_eq_context_valid_WORD      word0
 807         uint32_t word1;
 808 #define lpfc_eq_context_count_SHIFT     26
 809 #define lpfc_eq_context_count_MASK      0x00000003
 810 #define lpfc_eq_context_count_WORD      word1
 811 #define LPFC_EQ_CNT_256         0x0
 812 #define LPFC_EQ_CNT_512         0x1
 813 #define LPFC_EQ_CNT_1024        0x2
 814 #define LPFC_EQ_CNT_2048        0x3
 815 #define LPFC_EQ_CNT_4096        0x4
 816         uint32_t word2;
 817 #define lpfc_eq_context_delay_multi_SHIFT       13
 818 #define lpfc_eq_context_delay_multi_MASK        0x000003FF
 819 #define lpfc_eq_context_delay_multi_WORD        word2
 820         uint32_t reserved3;
 821 };
 822
 823 struct sgl_page_pairs {
 824         uint32_t sgl_pg0_addr_lo;
 825         uint32_t sgl_pg0_addr_hi;
 826         uint32_t sgl_pg1_addr_lo;
 827         uint32_t sgl_pg1_addr_hi;
 828 };
 829
 830 struct lpfc_mbx_post_sgl_pages {
 831         struct mbox_header header;
 832         uint32_t word0;
 833 #define lpfc_post_sgl_pages_xri_SHIFT   0
 834 #define lpfc_post_sgl_pages_xri_MASK    0x0000FFFF
 835 #define lpfc_post_sgl_pages_xri_WORD    word0
 836 #define lpfc_post_sgl_pages_xricnt_SHIFT        16
 837 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
 838 #define lpfc_post_sgl_pages_xricnt_WORD word0
 839         struct sgl_page_pairs  sgl_pg_pairs[1];
 840 };
 841
 842 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
 843 struct lpfc_mbx_post_uembed_sgl_page1 {
 844         union  lpfc_sli4_cfg_shdr cfg_shdr;
 845         uint32_t word0;
 846         struct sgl_page_pairs sgl_pg_pairs;
 847 };
 848
 849 struct lpfc_mbx_sge {
 850         uint32_t pa_lo;
 851         uint32_t pa_hi;
 852         uint32_t length;
 853 };
 854
 855 struct lpfc_mbx_nembed_cmd {
 856         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
 857 #define LPFC_SLI4_MBX_SGE_MAX_PAGES     19
 858         struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
 859 };
 860
 861 struct lpfc_mbx_nembed_sge_virt {
 862         void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
 863 };
 864
 865 struct lpfc_mbx_eq_create {
 866         struct mbox_header header;
 867         union {
 868                 struct {
 869                         uint32_t word0;
 870 #define lpfc_mbx_eq_create_num_pages_SHIFT      0
 871 #define lpfc_mbx_eq_create_num_pages_MASK       0x0000FFFF
 872 #define lpfc_mbx_eq_create_num_pages_WORD       word0
 873                         struct eq_context context;
 874                         struct dma_address page[LPFC_MAX_EQ_PAGE];
 875                 } request;
 876                 struct {
 877                         uint32_t word0;
 878 #define lpfc_mbx_eq_create_q_id_SHIFT   0
 879 #define lpfc_mbx_eq_create_q_id_MASK    0x0000FFFF
 880 #define lpfc_mbx_eq_create_q_id_WORD    word0
 881                 } response;
 882         } u;
 883 };
 884
 885 struct lpfc_mbx_eq_destroy {
 886         struct mbox_header header;
 887         union {
 888                 struct {
 889                         uint32_t word0;
 890 #define lpfc_mbx_eq_destroy_q_id_SHIFT  0
 891 #define lpfc_mbx_eq_destroy_q_id_MASK   0x0000FFFF
 892 #define lpfc_mbx_eq_destroy_q_id_WORD   word0
 893                 } request;
 894                 struct {
 895                         uint32_t word0;
 896                 } response;
 897         } u;
 898 };
 899
 900 struct lpfc_mbx_nop {
 901         struct mbox_header header;
 902         uint32_t context[2];
 903 };
 904
 905 struct cq_context {
 906         uint32_t word0;
 907 #define lpfc_cq_context_event_SHIFT     31
 908 #define lpfc_cq_context_event_MASK      0x00000001
 909 #define lpfc_cq_context_event_WORD      word0
 910 #define lpfc_cq_context_valid_SHIFT     29
 911 #define lpfc_cq_context_valid_MASK      0x00000001
 912 #define lpfc_cq_context_valid_WORD      word0
 913 #define lpfc_cq_context_count_SHIFT     27
 914 #define lpfc_cq_context_count_MASK      0x00000003
 915 #define lpfc_cq_context_count_WORD      word0
 916 #define LPFC_CQ_CNT_256         0x0
 917 #define LPFC_CQ_CNT_512         0x1
 918 #define LPFC_CQ_CNT_1024        0x2
 919         uint32_t word1;
 920 #define lpfc_cq_eq_id_SHIFT             22
 921 #define lpfc_cq_eq_id_MASK              0x000000FF
 922 #define lpfc_cq_eq_id_WORD              word1
 923         uint32_t reserved0;
 924         uint32_t reserved1;
 925 };
 926
 927 struct lpfc_mbx_cq_create {
 928         struct mbox_header header;
 929         union {
 930                 struct {
 931                         uint32_t word0;
 932 #define lpfc_mbx_cq_create_num_pages_SHIFT      0
 933 #define lpfc_mbx_cq_create_num_pages_MASK       0x0000FFFF
 934 #define lpfc_mbx_cq_create_num_pages_WORD       word0
 935                         struct cq_context context;
 936                         struct dma_address page[LPFC_MAX_CQ_PAGE];
 937                 } request;
 938                 struct {
 939                         uint32_t word0;
 940 #define lpfc_mbx_cq_create_q_id_SHIFT   0
 941 #define lpfc_mbx_cq_create_q_id_MASK    0x0000FFFF
 942 #define lpfc_mbx_cq_create_q_id_WORD    word0
 943                 } response;
 944         } u;
 945 };
 946
 947 struct lpfc_mbx_cq_destroy {
 948         struct mbox_header header;
 949         union {
 950                 struct {
 951                         uint32_t word0;
 952 #define lpfc_mbx_cq_destroy_q_id_SHIFT  0
 953 #define lpfc_mbx_cq_destroy_q_id_MASK   0x0000FFFF
 954 #define lpfc_mbx_cq_destroy_q_id_WORD   word0
 955                 } request;
 956                 struct {
 957                         uint32_t word0;
 958                 } response;
 959         } u;
 960 };
 961
 962 struct wq_context {
 963         uint32_t reserved0;
 964         uint32_t reserved1;
 965         uint32_t reserved2;
 966         uint32_t reserved3;
 967 };
 968
 969 struct lpfc_mbx_wq_create {
 970         struct mbox_header header;
 971         union {
 972                 struct {
 973                         uint32_t word0;
 974 #define lpfc_mbx_wq_create_num_pages_SHIFT      0
 975 #define lpfc_mbx_wq_create_num_pages_MASK       0x0000FFFF
 976 #define lpfc_mbx_wq_create_num_pages_WORD       word0
 977 #define lpfc_mbx_wq_create_cq_id_SHIFT          16
 978 #define lpfc_mbx_wq_create_cq_id_MASK           0x0000FFFF
 979 #define lpfc_mbx_wq_create_cq_id_WORD           word0
 980                         struct dma_address page[LPFC_MAX_WQ_PAGE];
 981                 } request;
 982                 struct {
 983                         uint32_t word0;
 984 #define lpfc_mbx_wq_create_q_id_SHIFT   0
 985 #define lpfc_mbx_wq_create_q_id_MASK    0x0000FFFF
 986 #define lpfc_mbx_wq_create_q_id_WORD    word0
 987                 } response;
 988         } u;
 989 };
 990
 991 struct lpfc_mbx_wq_destroy {
 992         struct mbox_header header;
 993         union {
 994                 struct {
 995                         uint32_t word0;
 996 #define lpfc_mbx_wq_destroy_q_id_SHIFT  0
 997 #define lpfc_mbx_wq_destroy_q_id_MASK   0x0000FFFF
 998 #define lpfc_mbx_wq_destroy_q_id_WORD   word0
 999                 } request;
1000                 struct {
1001                         uint32_t word0;
1002                 } response;
1003         } u;
1004 };
1005
1006 #define LPFC_HDR_BUF_SIZE 128
1007 #define LPFC_DATA_BUF_SIZE 2048
1008 struct rq_context {
1009         uint32_t word0;
1010 #define lpfc_rq_context_rq_size_SHIFT   16
1011 #define lpfc_rq_context_rq_size_MASK    0x0000000F
1012 #define lpfc_rq_context_rq_size_WORD    word0
1013 #define LPFC_RQ_RING_SIZE_512           9       /* 512 entries */
1014 #define LPFC_RQ_RING_SIZE_1024          10      /* 1024 entries */
1015 #define LPFC_RQ_RING_SIZE_2048          11      /* 2048 entries */
1016 #define LPFC_RQ_RING_SIZE_4096          12      /* 4096 entries */
1017         uint32_t reserved1;
1018         uint32_t word2;
1019 #define lpfc_rq_context_cq_id_SHIFT     16
1020 #define lpfc_rq_context_cq_id_MASK      0x000003FF
1021 #define lpfc_rq_context_cq_id_WORD      word2
1022 #define lpfc_rq_context_buf_size_SHIFT  0
1023 #define lpfc_rq_context_buf_size_MASK   0x0000FFFF
1024 #define lpfc_rq_context_buf_size_WORD   word2
1025         uint32_t reserved3;
1026 };
1027
1028 struct lpfc_mbx_rq_create {
1029         struct mbox_header header;
1030         union {
1031                 struct {
1032                         uint32_t word0;
1033 #define lpfc_mbx_rq_create_num_pages_SHIFT      0
1034 #define lpfc_mbx_rq_create_num_pages_MASK       0x0000FFFF
1035 #define lpfc_mbx_rq_create_num_pages_WORD       word0
1036                         struct rq_context context;
1037                         struct dma_address page[LPFC_MAX_WQ_PAGE];
1038                 } request;
1039                 struct {
1040                         uint32_t word0;
1041 #define lpfc_mbx_rq_create_q_id_SHIFT   0
1042 #define lpfc_mbx_rq_create_q_id_MASK    0x0000FFFF
1043 #define lpfc_mbx_rq_create_q_id_WORD    word0
1044                 } response;
1045         } u;
1046 };
1047
1048 struct lpfc_mbx_rq_destroy {
1049         struct mbox_header header;
1050         union {
1051                 struct {
1052                         uint32_t word0;
1053 #define lpfc_mbx_rq_destroy_q_id_SHIFT  0
1054 #define lpfc_mbx_rq_destroy_q_id_MASK   0x0000FFFF
1055 #define lpfc_mbx_rq_destroy_q_id_WORD   word0
1056                 } request;
1057                 struct {
1058                         uint32_t word0;
1059                 } response;
1060         } u;
1061 };
1062
1063 struct mq_context {
1064         uint32_t word0;
1065 #define lpfc_mq_context_cq_id_SHIFT     22
1066 #define lpfc_mq_context_cq_id_MASK      0x000003FF
1067 #define lpfc_mq_context_cq_id_WORD      word0
1068 #define lpfc_mq_context_count_SHIFT     16
1069 #define lpfc_mq_context_count_MASK      0x0000000F
1070 #define lpfc_mq_context_count_WORD      word0
1071 #define LPFC_MQ_CNT_16          0x5
1072 #define LPFC_MQ_CNT_32          0x6
1073 #define LPFC_MQ_CNT_64          0x7
1074 #define LPFC_MQ_CNT_128         0x8
1075         uint32_t word1;
1076 #define lpfc_mq_context_valid_SHIFT     31
1077 #define lpfc_mq_context_valid_MASK      0x00000001
1078 #define lpfc_mq_context_valid_WORD      word1
1079         uint32_t reserved2;
1080         uint32_t reserved3;
1081 };
1082
1083 struct lpfc_mbx_mq_create {
1084         struct mbox_header header;
1085         union {
1086                 struct {
1087                         uint32_t word0;
1088 #define lpfc_mbx_mq_create_num_pages_SHIFT      0
1089 #define lpfc_mbx_mq_create_num_pages_MASK       0x0000FFFF
1090 #define lpfc_mbx_mq_create_num_pages_WORD       word0
1091                         struct mq_context context;
1092                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1093                 } request;
1094                 struct {
1095                         uint32_t word0;
1096 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1097 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1098 #define lpfc_mbx_mq_create_q_id_WORD    word0
1099                 } response;
1100         } u;
1101 };
1102
1103 struct lpfc_mbx_mq_create_ext {
1104         struct mbox_header header;
1105         union {
1106                 struct {
1107                         uint32_t word0;
1108 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT          0
1109 #define lpfc_mbx_mq_create_ext_num_pages_MASK           0x0000FFFF
1110 #define lpfc_mbx_mq_create_ext_num_pages_WORD           word0
1111                         uint32_t async_evt_bmap;
1112 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT     LPFC_TRAILER_CODE_LINK
1113 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK      0x00000001
1114 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD      async_evt_bmap
1115 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT      LPFC_TRAILER_CODE_FCOE
1116 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK       0x00000001
1117 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD       async_evt_bmap
1118 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT   LPFC_TRAILER_CODE_GRP5
1119 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK    0x00000001
1120 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD    async_evt_bmap
1121 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT       LPFC_TRAILER_CODE_FC
1122 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK        0x00000001
1123 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD        async_evt_bmap
1124 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT      LPFC_TRAILER_CODE_SLI
1125 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK       0x00000001
1126 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD       async_evt_bmap
1127                         struct mq_context context;
1128                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1129                 } request;
1130                 struct {
1131                         uint32_t word0;
1132 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1133 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1134 #define lpfc_mbx_mq_create_q_id_WORD    word0
1135                 } response;
1136         } u;
1137 #define LPFC_ASYNC_EVENT_LINK_STATE     0x2
1138 #define LPFC_ASYNC_EVENT_FCF_STATE      0x4
1139 #define LPFC_ASYNC_EVENT_GROUP5         0x20
1140 };
1141
1142 struct lpfc_mbx_mq_destroy {
1143         struct mbox_header header;
1144         union {
1145                 struct {
1146                         uint32_t word0;
1147 #define lpfc_mbx_mq_destroy_q_id_SHIFT  0
1148 #define lpfc_mbx_mq_destroy_q_id_MASK   0x0000FFFF
1149 #define lpfc_mbx_mq_destroy_q_id_WORD   word0
1150                 } request;
1151                 struct {
1152                         uint32_t word0;
1153                 } response;
1154         } u;
1155 };
1156
1157 struct lpfc_mbx_post_hdr_tmpl {
1158         struct mbox_header header;
1159         uint32_t word10;
1160 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT  0
1161 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK   0x0000FFFF
1162 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD   word10
1163 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT   16
1164 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK    0x0000FFFF
1165 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD    word10
1166         uint32_t rpi_paddr_lo;
1167         uint32_t rpi_paddr_hi;
1168 };
1169
1170 struct sli4_sge {       /* SLI-4 */
1171         uint32_t addr_hi;
1172         uint32_t addr_lo;
1173
1174         uint32_t word2;
1175 #define lpfc_sli4_sge_offset_SHIFT      0 /* Offset of buffer - Not used*/
1176 #define lpfc_sli4_sge_offset_MASK       0x00FFFFFF
1177 #define lpfc_sli4_sge_offset_WORD       word2
1178 #define lpfc_sli4_sge_last_SHIFT        31 /* Last SEG in the SGL sets
1179                                                 this  flag !! */
1180 #define lpfc_sli4_sge_last_MASK         0x00000001
1181 #define lpfc_sli4_sge_last_WORD         word2
1182         uint32_t sge_len;
1183 };
1184
1185 struct fcf_record {
1186         uint32_t max_rcv_size;
1187         uint32_t fka_adv_period;
1188         uint32_t fip_priority;
1189         uint32_t word3;
1190 #define lpfc_fcf_record_mac_0_SHIFT             0
1191 #define lpfc_fcf_record_mac_0_MASK              0x000000FF
1192 #define lpfc_fcf_record_mac_0_WORD              word3
1193 #define lpfc_fcf_record_mac_1_SHIFT             8
1194 #define lpfc_fcf_record_mac_1_MASK              0x000000FF
1195 #define lpfc_fcf_record_mac_1_WORD              word3
1196 #define lpfc_fcf_record_mac_2_SHIFT             16
1197 #define lpfc_fcf_record_mac_2_MASK              0x000000FF
1198 #define lpfc_fcf_record_mac_2_WORD              word3
1199 #define lpfc_fcf_record_mac_3_SHIFT             24
1200 #define lpfc_fcf_record_mac_3_MASK              0x000000FF
1201 #define lpfc_fcf_record_mac_3_WORD              word3
1202         uint32_t word4;
1203 #define lpfc_fcf_record_mac_4_SHIFT             0
1204 #define lpfc_fcf_record_mac_4_MASK              0x000000FF
1205 #define lpfc_fcf_record_mac_4_WORD              word4
1206 #define lpfc_fcf_record_mac_5_SHIFT             8
1207 #define lpfc_fcf_record_mac_5_MASK              0x000000FF
1208 #define lpfc_fcf_record_mac_5_WORD              word4
1209 #define lpfc_fcf_record_fcf_avail_SHIFT         16
1210 #define lpfc_fcf_record_fcf_avail_MASK          0x000000FF
1211 #define lpfc_fcf_record_fcf_avail_WORD          word4
1212 #define lpfc_fcf_record_mac_addr_prov_SHIFT     24
1213 #define lpfc_fcf_record_mac_addr_prov_MASK      0x000000FF
1214 #define lpfc_fcf_record_mac_addr_prov_WORD      word4
1215 #define LPFC_FCF_FPMA           1       /* Fabric Provided MAC Address */
1216 #define LPFC_FCF_SPMA           2       /* Server Provided MAC Address */
1217         uint32_t word5;
1218 #define lpfc_fcf_record_fab_name_0_SHIFT        0
1219 #define lpfc_fcf_record_fab_name_0_MASK         0x000000FF
1220 #define lpfc_fcf_record_fab_name_0_WORD         word5
1221 #define lpfc_fcf_record_fab_name_1_SHIFT        8
1222 #define lpfc_fcf_record_fab_name_1_MASK         0x000000FF
1223 #define lpfc_fcf_record_fab_name_1_WORD         word5
1224 #define lpfc_fcf_record_fab_name_2_SHIFT        16
1225 #define lpfc_fcf_record_fab_name_2_MASK         0x000000FF
1226 #define lpfc_fcf_record_fab_name_2_WORD         word5
1227 #define lpfc_fcf_record_fab_name_3_SHIFT        24
1228 #define lpfc_fcf_record_fab_name_3_MASK         0x000000FF
1229 #define lpfc_fcf_record_fab_name_3_WORD         word5
1230         uint32_t word6;
1231 #define lpfc_fcf_record_fab_name_4_SHIFT        0
1232 #define lpfc_fcf_record_fab_name_4_MASK         0x000000FF
1233 #define lpfc_fcf_record_fab_name_4_WORD         word6
1234 #define lpfc_fcf_record_fab_name_5_SHIFT        8
1235 #define lpfc_fcf_record_fab_name_5_MASK         0x000000FF
1236 #define lpfc_fcf_record_fab_name_5_WORD         word6
1237 #define lpfc_fcf_record_fab_name_6_SHIFT        16
1238 #define lpfc_fcf_record_fab_name_6_MASK         0x000000FF
1239 #define lpfc_fcf_record_fab_name_6_WORD         word6
1240 #define lpfc_fcf_record_fab_name_7_SHIFT        24
1241 #define lpfc_fcf_record_fab_name_7_MASK         0x000000FF
1242 #define lpfc_fcf_record_fab_name_7_WORD         word6
1243         uint32_t word7;
1244 #define lpfc_fcf_record_fc_map_0_SHIFT          0
1245 #define lpfc_fcf_record_fc_map_0_MASK           0x000000FF
1246 #define lpfc_fcf_record_fc_map_0_WORD           word7
1247 #define lpfc_fcf_record_fc_map_1_SHIFT          8
1248 #define lpfc_fcf_record_fc_map_1_MASK           0x000000FF
1249 #define lpfc_fcf_record_fc_map_1_WORD           word7
1250 #define lpfc_fcf_record_fc_map_2_SHIFT          16
1251 #define lpfc_fcf_record_fc_map_2_MASK           0x000000FF
1252 #define lpfc_fcf_record_fc_map_2_WORD           word7
1253 #define lpfc_fcf_record_fcf_valid_SHIFT         24
1254 #define lpfc_fcf_record_fcf_valid_MASK          0x000000FF
1255 #define lpfc_fcf_record_fcf_valid_WORD          word7
1256         uint32_t word8;
1257 #define lpfc_fcf_record_fcf_index_SHIFT         0
1258 #define lpfc_fcf_record_fcf_index_MASK          0x0000FFFF
1259 #define lpfc_fcf_record_fcf_index_WORD          word8
1260 #define lpfc_fcf_record_fcf_state_SHIFT         16
1261 #define lpfc_fcf_record_fcf_state_MASK          0x0000FFFF
1262 #define lpfc_fcf_record_fcf_state_WORD          word8
1263         uint8_t vlan_bitmap[512];
1264         uint32_t word137;
1265 #define lpfc_fcf_record_switch_name_0_SHIFT     0
1266 #define lpfc_fcf_record_switch_name_0_MASK      0x000000FF
1267 #define lpfc_fcf_record_switch_name_0_WORD      word137
1268 #define lpfc_fcf_record_switch_name_1_SHIFT     8
1269 #define lpfc_fcf_record_switch_name_1_MASK      0x000000FF
1270 #define lpfc_fcf_record_switch_name_1_WORD      word137
1271 #define lpfc_fcf_record_switch_name_2_SHIFT     16
1272 #define lpfc_fcf_record_switch_name_2_MASK      0x000000FF
1273 #define lpfc_fcf_record_switch_name_2_WORD      word137
1274 #define lpfc_fcf_record_switch_name_3_SHIFT     24
1275 #define lpfc_fcf_record_switch_name_3_MASK      0x000000FF
1276 #define lpfc_fcf_record_switch_name_3_WORD      word137
1277         uint32_t word138;
1278 #define lpfc_fcf_record_switch_name_4_SHIFT     0
1279 #define lpfc_fcf_record_switch_name_4_MASK      0x000000FF
1280 #define lpfc_fcf_record_switch_name_4_WORD      word138
1281 #define lpfc_fcf_record_switch_name_5_SHIFT     8
1282 #define lpfc_fcf_record_switch_name_5_MASK      0x000000FF
1283 #define lpfc_fcf_record_switch_name_5_WORD      word138
1284 #define lpfc_fcf_record_switch_name_6_SHIFT     16
1285 #define lpfc_fcf_record_switch_name_6_MASK      0x000000FF
1286 #define lpfc_fcf_record_switch_name_6_WORD      word138
1287 #define lpfc_fcf_record_switch_name_7_SHIFT     24
1288 #define lpfc_fcf_record_switch_name_7_MASK      0x000000FF
1289 #define lpfc_fcf_record_switch_name_7_WORD      word138
1290 };
1291
1292 struct lpfc_mbx_read_fcf_tbl {
1293         union lpfc_sli4_cfg_shdr cfg_shdr;
1294         union {
1295                 struct {
1296                         uint32_t word10;
1297 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT        0
1298 #define lpfc_mbx_read_fcf_tbl_indx_MASK         0x0000FFFF
1299 #define lpfc_mbx_read_fcf_tbl_indx_WORD         word10
1300                 } request;
1301                 struct {
1302                         uint32_t eventag;
1303                 } response;
1304         } u;
1305         uint32_t word11;
1306 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT   0
1307 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK    0x0000FFFF
1308 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD    word11
1309 };
1310
1311 struct lpfc_mbx_add_fcf_tbl_entry {
1312         union lpfc_sli4_cfg_shdr cfg_shdr;
1313         uint32_t word10;
1314 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT        0
1315 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK         0x0000FFFF
1316 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD         word10
1317         struct lpfc_mbx_sge fcf_sge;
1318 };
1319
1320 struct lpfc_mbx_del_fcf_tbl_entry {
1321         struct mbox_header header;
1322         uint32_t word10;
1323 #define lpfc_mbx_del_fcf_tbl_count_SHIFT        0
1324 #define lpfc_mbx_del_fcf_tbl_count_MASK         0x0000FFFF
1325 #define lpfc_mbx_del_fcf_tbl_count_WORD         word10
1326 #define lpfc_mbx_del_fcf_tbl_index_SHIFT        16
1327 #define lpfc_mbx_del_fcf_tbl_index_MASK         0x0000FFFF
1328 #define lpfc_mbx_del_fcf_tbl_index_WORD         word10
1329 };
1330
1331 struct lpfc_mbx_redisc_fcf_tbl {
1332         struct mbox_header header;
1333         uint32_t word10;
1334 #define lpfc_mbx_redisc_fcf_count_SHIFT         0
1335 #define lpfc_mbx_redisc_fcf_count_MASK          0x0000FFFF
1336 #define lpfc_mbx_redisc_fcf_count_WORD          word10
1337         uint32_t resvd;
1338         uint32_t word12;
1339 #define lpfc_mbx_redisc_fcf_index_SHIFT         0
1340 #define lpfc_mbx_redisc_fcf_index_MASK          0x0000FFFF
1341 #define lpfc_mbx_redisc_fcf_index_WORD          word12
1342 };
1343
1344 struct lpfc_mbx_query_fw_cfg {
1345         struct mbox_header header;
1346         uint32_t config_number;
1347         uint32_t asic_rev;
1348         uint32_t phys_port;
1349         uint32_t function_mode;
1350 /* firmware Function Mode */
1351 #define lpfc_function_mode_toe_SHIFT            0
1352 #define lpfc_function_mode_toe_MASK             0x00000001
1353 #define lpfc_function_mode_toe_WORD             function_mode
1354 #define lpfc_function_mode_nic_SHIFT            1
1355 #define lpfc_function_mode_nic_MASK             0x00000001
1356 #define lpfc_function_mode_nic_WORD             function_mode
1357 #define lpfc_function_mode_rdma_SHIFT           2
1358 #define lpfc_function_mode_rdma_MASK            0x00000001
1359 #define lpfc_function_mode_rdma_WORD            function_mode
1360 #define lpfc_function_mode_vm_SHIFT             3
1361 #define lpfc_function_mode_vm_MASK              0x00000001
1362 #define lpfc_function_mode_vm_WORD              function_mode
1363 #define lpfc_function_mode_iscsi_i_SHIFT        4
1364 #define lpfc_function_mode_iscsi_i_MASK         0x00000001
1365 #define lpfc_function_mode_iscsi_i_WORD         function_mode
1366 #define lpfc_function_mode_iscsi_t_SHIFT        5
1367 #define lpfc_function_mode_iscsi_t_MASK         0x00000001
1368 #define lpfc_function_mode_iscsi_t_WORD         function_mode
1369 #define lpfc_function_mode_fcoe_i_SHIFT         6
1370 #define lpfc_function_mode_fcoe_i_MASK          0x00000001
1371 #define lpfc_function_mode_fcoe_i_WORD          function_mode
1372 #define lpfc_function_mode_fcoe_t_SHIFT         7
1373 #define lpfc_function_mode_fcoe_t_MASK          0x00000001
1374 #define lpfc_function_mode_fcoe_t_WORD          function_mode
1375 #define lpfc_function_mode_dal_SHIFT            8
1376 #define lpfc_function_mode_dal_MASK             0x00000001
1377 #define lpfc_function_mode_dal_WORD             function_mode
1378 #define lpfc_function_mode_lro_SHIFT            9
1379 #define lpfc_function_mode_lro_MASK             0x00000001
1380 #define lpfc_function_mode_lro_WORD             function_mode
1381 #define lpfc_function_mode_flex10_SHIFT         10
1382 #define lpfc_function_mode_flex10_MASK          0x00000001
1383 #define lpfc_function_mode_flex10_WORD          function_mode
1384 #define lpfc_function_mode_ncsi_SHIFT           11
1385 #define lpfc_function_mode_ncsi_MASK            0x00000001
1386 #define lpfc_function_mode_ncsi_WORD            function_mode
1387 };
1388
1389 /* Status field for embedded SLI_CONFIG mailbox command */
1390 #define STATUS_SUCCESS                                  0x0
1391 #define STATUS_FAILED                                   0x1
1392 #define STATUS_ILLEGAL_REQUEST                          0x2
1393 #define STATUS_ILLEGAL_FIELD                            0x3
1394 #define STATUS_INSUFFICIENT_BUFFER                      0x4
1395 #define STATUS_UNAUTHORIZED_REQUEST                     0x5
1396 #define STATUS_FLASHROM_SAVE_FAILED                     0x17
1397 #define STATUS_FLASHROM_RESTORE_FAILED                  0x18
1398 #define STATUS_ICCBINDEX_ALLOC_FAILED                   0x1a
1399 #define STATUS_IOCTLHANDLE_ALLOC_FAILED                 0x1b
1400 #define STATUS_INVALID_PHY_ADDR_FROM_OSM                0x1c
1401 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM            0x1d
1402 #define STATUS_ASSERT_FAILED                            0x1e
1403 #define STATUS_INVALID_SESSION                          0x1f
1404 #define STATUS_INVALID_CONNECTION                       0x20
1405 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT               0x21
1406 #define STATUS_BTL_NO_FREE_SLOT_PATH                    0x24
1407 #define STATUS_BTL_NO_FREE_SLOT_TGTID                   0x25
1408 #define STATUS_OSM_DEVSLOT_NOT_FOUND                    0x26
1409 #define STATUS_FLASHROM_READ_FAILED                     0x27
1410 #define STATUS_POLL_IOCTL_TIMEOUT                       0x28
1411 #define STATUS_ERROR_ACITMAIN                           0x2a
1412 #define STATUS_REBOOT_REQUIRED                          0x2c
1413 #define STATUS_FCF_IN_USE                               0x3a
1414 #define STATUS_FCF_TABLE_EMPTY                          0x43
1415
1416 struct lpfc_mbx_sli4_config {
1417         struct mbox_header header;
1418 };
1419
1420 struct lpfc_mbx_init_vfi {
1421         uint32_t word1;
1422 #define lpfc_init_vfi_vr_SHIFT          31
1423 #define lpfc_init_vfi_vr_MASK           0x00000001
1424 #define lpfc_init_vfi_vr_WORD           word1
1425 #define lpfc_init_vfi_vt_SHIFT          30
1426 #define lpfc_init_vfi_vt_MASK           0x00000001
1427 #define lpfc_init_vfi_vt_WORD           word1
1428 #define lpfc_init_vfi_vf_SHIFT          29
1429 #define lpfc_init_vfi_vf_MASK           0x00000001
1430 #define lpfc_init_vfi_vf_WORD           word1
1431 #define lpfc_init_vfi_vp_SHIFT          28
1432 #define lpfc_init_vfi_vp_MASK           0x00000001
1433 #define lpfc_init_vfi_vp_WORD           word1
1434 #define lpfc_init_vfi_vfi_SHIFT         0
1435 #define lpfc_init_vfi_vfi_MASK          0x0000FFFF
1436 #define lpfc_init_vfi_vfi_WORD          word1
1437         uint32_t word2;
1438 #define lpfc_init_vfi_vpi_SHIFT         16
1439 #define lpfc_init_vfi_vpi_MASK          0x0000FFFF
1440 #define lpfc_init_vfi_vpi_WORD          word2
1441 #define lpfc_init_vfi_fcfi_SHIFT        0
1442 #define lpfc_init_vfi_fcfi_MASK         0x0000FFFF
1443 #define lpfc_init_vfi_fcfi_WORD         word2
1444         uint32_t word3;
1445 #define lpfc_init_vfi_pri_SHIFT         13
1446 #define lpfc_init_vfi_pri_MASK          0x00000007
1447 #define lpfc_init_vfi_pri_WORD          word3
1448 #define lpfc_init_vfi_vf_id_SHIFT       1
1449 #define lpfc_init_vfi_vf_id_MASK        0x00000FFF
1450 #define lpfc_init_vfi_vf_id_WORD        word3
1451         uint32_t word4;
1452 #define lpfc_init_vfi_hop_count_SHIFT   24
1453 #define lpfc_init_vfi_hop_count_MASK    0x000000FF
1454 #define lpfc_init_vfi_hop_count_WORD    word4
1455 };
1456
1457 struct lpfc_mbx_reg_vfi {
1458         uint32_t word1;
1459 #define lpfc_reg_vfi_vp_SHIFT           28
1460 #define lpfc_reg_vfi_vp_MASK            0x00000001
1461 #define lpfc_reg_vfi_vp_WORD            word1
1462 #define lpfc_reg_vfi_vfi_SHIFT          0
1463 #define lpfc_reg_vfi_vfi_MASK           0x0000FFFF
1464 #define lpfc_reg_vfi_vfi_WORD           word1
1465         uint32_t word2;
1466 #define lpfc_reg_vfi_vpi_SHIFT          16
1467 #define lpfc_reg_vfi_vpi_MASK           0x0000FFFF
1468 #define lpfc_reg_vfi_vpi_WORD           word2
1469 #define lpfc_reg_vfi_fcfi_SHIFT         0
1470 #define lpfc_reg_vfi_fcfi_MASK          0x0000FFFF
1471 #define lpfc_reg_vfi_fcfi_WORD          word2
1472         uint32_t wwn[2];
1473         struct ulp_bde64 bde;
1474         uint32_t e_d_tov;
1475         uint32_t r_a_tov;
1476         uint32_t word10;
1477 #define lpfc_reg_vfi_nport_id_SHIFT             0
1478 #define lpfc_reg_vfi_nport_id_MASK              0x00FFFFFF
1479 #define lpfc_reg_vfi_nport_id_WORD              word10
1480 };
1481
1482 struct lpfc_mbx_init_vpi {
1483         uint32_t word1;
1484 #define lpfc_init_vpi_vfi_SHIFT         16
1485 #define lpfc_init_vpi_vfi_MASK          0x0000FFFF
1486 #define lpfc_init_vpi_vfi_WORD          word1
1487 #define lpfc_init_vpi_vpi_SHIFT         0
1488 #define lpfc_init_vpi_vpi_MASK          0x0000FFFF
1489 #define lpfc_init_vpi_vpi_WORD          word1
1490 };
1491
1492 struct lpfc_mbx_read_vpi {
1493         uint32_t word1_rsvd;
1494         uint32_t word2;
1495 #define lpfc_mbx_read_vpi_vnportid_SHIFT        0
1496 #define lpfc_mbx_read_vpi_vnportid_MASK         0x00FFFFFF
1497 #define lpfc_mbx_read_vpi_vnportid_WORD         word2
1498         uint32_t word3_rsvd;
1499         uint32_t word4;
1500 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT        0
1501 #define lpfc_mbx_read_vpi_acq_alpa_MASK         0x000000FF
1502 #define lpfc_mbx_read_vpi_acq_alpa_WORD         word4
1503 #define lpfc_mbx_read_vpi_pb_SHIFT              15
1504 #define lpfc_mbx_read_vpi_pb_MASK               0x00000001
1505 #define lpfc_mbx_read_vpi_pb_WORD               word4
1506 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT       16
1507 #define lpfc_mbx_read_vpi_spec_alpa_MASK        0x000000FF
1508 #define lpfc_mbx_read_vpi_spec_alpa_WORD        word4
1509 #define lpfc_mbx_read_vpi_ns_SHIFT              30
1510 #define lpfc_mbx_read_vpi_ns_MASK               0x00000001
1511 #define lpfc_mbx_read_vpi_ns_WORD               word4
1512 #define lpfc_mbx_read_vpi_hl_SHIFT              31
1513 #define lpfc_mbx_read_vpi_hl_MASK               0x00000001
1514 #define lpfc_mbx_read_vpi_hl_WORD               word4
1515         uint32_t word5_rsvd;
1516         uint32_t word6;
1517 #define lpfc_mbx_read_vpi_vpi_SHIFT             0
1518 #define lpfc_mbx_read_vpi_vpi_MASK              0x0000FFFF
1519 #define lpfc_mbx_read_vpi_vpi_WORD              word6
1520         uint32_t word7;
1521 #define lpfc_mbx_read_vpi_mac_0_SHIFT           0
1522 #define lpfc_mbx_read_vpi_mac_0_MASK            0x000000FF
1523 #define lpfc_mbx_read_vpi_mac_0_WORD            word7
1524 #define lpfc_mbx_read_vpi_mac_1_SHIFT           8
1525 #define lpfc_mbx_read_vpi_mac_1_MASK            0x000000FF
1526 #define lpfc_mbx_read_vpi_mac_1_WORD            word7
1527 #define lpfc_mbx_read_vpi_mac_2_SHIFT           16
1528 #define lpfc_mbx_read_vpi_mac_2_MASK            0x000000FF
1529 #define lpfc_mbx_read_vpi_mac_2_WORD            word7
1530 #define lpfc_mbx_read_vpi_mac_3_SHIFT           24
1531 #define lpfc_mbx_read_vpi_mac_3_MASK            0x000000FF
1532 #define lpfc_mbx_read_vpi_mac_3_WORD            word7
1533         uint32_t word8;
1534 #define lpfc_mbx_read_vpi_mac_4_SHIFT           0
1535 #define lpfc_mbx_read_vpi_mac_4_MASK            0x000000FF
1536 #define lpfc_mbx_read_vpi_mac_4_WORD            word8
1537 #define lpfc_mbx_read_vpi_mac_5_SHIFT           8
1538 #define lpfc_mbx_read_vpi_mac_5_MASK            0x000000FF
1539 #define lpfc_mbx_read_vpi_mac_5_WORD            word8
1540 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT        16
1541 #define lpfc_mbx_read_vpi_vlan_tag_MASK         0x00000FFF
1542 #define lpfc_mbx_read_vpi_vlan_tag_WORD         word8
1543 #define lpfc_mbx_read_vpi_vv_SHIFT              28
1544 #define lpfc_mbx_read_vpi_vv_MASK               0x0000001
1545 #define lpfc_mbx_read_vpi_vv_WORD               word8
1546 };
1547
1548 struct lpfc_mbx_unreg_vfi {
1549         uint32_t word1_rsvd;
1550         uint32_t word2;
1551 #define lpfc_unreg_vfi_vfi_SHIFT        0
1552 #define lpfc_unreg_vfi_vfi_MASK         0x0000FFFF
1553 #define lpfc_unreg_vfi_vfi_WORD         word2
1554 };
1555
1556 struct lpfc_mbx_resume_rpi {
1557         uint32_t word1;
1558 #define lpfc_resume_rpi_index_SHIFT     0
1559 #define lpfc_resume_rpi_index_MASK      0x0000FFFF
1560 #define lpfc_resume_rpi_index_WORD      word1
1561 #define lpfc_resume_rpi_ii_SHIFT        30
1562 #define lpfc_resume_rpi_ii_MASK         0x00000003
1563 #define lpfc_resume_rpi_ii_WORD         word1
1564 #define RESUME_INDEX_RPI                0
1565 #define RESUME_INDEX_VPI                1
1566 #define RESUME_INDEX_VFI                2
1567 #define RESUME_INDEX_FCFI               3
1568         uint32_t event_tag;
1569 };
1570
1571 #define REG_FCF_INVALID_QID     0xFFFF
1572 struct lpfc_mbx_reg_fcfi {
1573         uint32_t word1;
1574 #define lpfc_reg_fcfi_info_index_SHIFT  0
1575 #define lpfc_reg_fcfi_info_index_MASK   0x0000FFFF
1576 #define lpfc_reg_fcfi_info_index_WORD   word1
1577 #define lpfc_reg_fcfi_fcfi_SHIFT        16
1578 #define lpfc_reg_fcfi_fcfi_MASK         0x0000FFFF
1579 #define lpfc_reg_fcfi_fcfi_WORD         word1
1580         uint32_t word2;
1581 #define lpfc_reg_fcfi_rq_id1_SHIFT      0
1582 #define lpfc_reg_fcfi_rq_id1_MASK       0x0000FFFF
1583 #define lpfc_reg_fcfi_rq_id1_WORD       word2
1584 #define lpfc_reg_fcfi_rq_id0_SHIFT      16
1585 #define lpfc_reg_fcfi_rq_id0_MASK       0x0000FFFF
1586 #define lpfc_reg_fcfi_rq_id0_WORD       word2
1587         uint32_t word3;
1588 #define lpfc_reg_fcfi_rq_id3_SHIFT      0
1589 #define lpfc_reg_fcfi_rq_id3_MASK       0x0000FFFF
1590 #define lpfc_reg_fcfi_rq_id3_WORD       word3
1591 #define lpfc_reg_fcfi_rq_id2_SHIFT      16
1592 #define lpfc_reg_fcfi_rq_id2_MASK       0x0000FFFF
1593 #define lpfc_reg_fcfi_rq_id2_WORD       word3
1594         uint32_t word4;
1595 #define lpfc_reg_fcfi_type_match0_SHIFT 24
1596 #define lpfc_reg_fcfi_type_match0_MASK  0x000000FF
1597 #define lpfc_reg_fcfi_type_match0_WORD  word4
1598 #define lpfc_reg_fcfi_type_mask0_SHIFT  16
1599 #define lpfc_reg_fcfi_type_mask0_MASK   0x000000FF
1600 #define lpfc_reg_fcfi_type_mask0_WORD   word4
1601 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
1602 #define lpfc_reg_fcfi_rctl_match0_MASK  0x000000FF
1603 #define lpfc_reg_fcfi_rctl_match0_WORD  word4
1604 #define lpfc_reg_fcfi_rctl_mask0_SHIFT  0
1605 #define lpfc_reg_fcfi_rctl_mask0_MASK   0x000000FF
1606 #define lpfc_reg_fcfi_rctl_mask0_WORD   word4
1607         uint32_t word5;
1608 #define lpfc_reg_fcfi_type_match1_SHIFT 24
1609 #define lpfc_reg_fcfi_type_match1_MASK  0x000000FF
1610 #define lpfc_reg_fcfi_type_match1_WORD  word5
1611 #define lpfc_reg_fcfi_type_mask1_SHIFT  16
1612 #define lpfc_reg_fcfi_type_mask1_MASK   0x000000FF
1613 #define lpfc_reg_fcfi_type_mask1_WORD   word5
1614 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
1615 #define lpfc_reg_fcfi_rctl_match1_MASK  0x000000FF
1616 #define lpfc_reg_fcfi_rctl_match1_WORD  word5
1617 #define lpfc_reg_fcfi_rctl_mask1_SHIFT  0
1618 #define lpfc_reg_fcfi_rctl_mask1_MASK   0x000000FF
1619 #define lpfc_reg_fcfi_rctl_mask1_WORD   word5
1620         uint32_t word6;
1621 #define lpfc_reg_fcfi_type_match2_SHIFT 24
1622 #define lpfc_reg_fcfi_type_match2_MASK  0x000000FF
1623 #define lpfc_reg_fcfi_type_match2_WORD  word6
1624 #define lpfc_reg_fcfi_type_mask2_SHIFT  16
1625 #define lpfc_reg_fcfi_type_mask2_MASK   0x000000FF
1626 #define lpfc_reg_fcfi_type_mask2_WORD   word6
1627 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
1628 #define lpfc_reg_fcfi_rctl_match2_MASK  0x000000FF
1629 #define lpfc_reg_fcfi_rctl_match2_WORD  word6
1630 #define lpfc_reg_fcfi_rctl_mask2_SHIFT  0
1631 #define lpfc_reg_fcfi_rctl_mask2_MASK   0x000000FF
1632 #define lpfc_reg_fcfi_rctl_mask2_WORD   word6
1633         uint32_t word7;
1634 #define lpfc_reg_fcfi_type_match3_SHIFT 24
1635 #define lpfc_reg_fcfi_type_match3_MASK  0x000000FF
1636 #define lpfc_reg_fcfi_type_match3_WORD  word7
1637 #define lpfc_reg_fcfi_type_mask3_SHIFT  16
1638 #define lpfc_reg_fcfi_type_mask3_MASK   0x000000FF
1639 #define lpfc_reg_fcfi_type_mask3_WORD   word7
1640 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
1641 #define lpfc_reg_fcfi_rctl_match3_MASK  0x000000FF
1642 #define lpfc_reg_fcfi_rctl_match3_WORD  word7
1643 #define lpfc_reg_fcfi_rctl_mask3_SHIFT  0
1644 #define lpfc_reg_fcfi_rctl_mask3_MASK   0x000000FF
1645 #define lpfc_reg_fcfi_rctl_mask3_WORD   word7
1646         uint32_t word8;
1647 #define lpfc_reg_fcfi_mam_SHIFT         13
1648 #define lpfc_reg_fcfi_mam_MASK          0x00000003
1649 #define lpfc_reg_fcfi_mam_WORD          word8
1650 #define LPFC_MAM_BOTH           0       /* Both SPMA and FPMA */
1651 #define LPFC_MAM_SPMA           1       /* Server Provided MAC Address */
1652 #define LPFC_MAM_FPMA           2       /* Fabric Provided MAC Address */
1653 #define lpfc_reg_fcfi_vv_SHIFT          12
1654 #define lpfc_reg_fcfi_vv_MASK           0x00000001
1655 #define lpfc_reg_fcfi_vv_WORD           word8
1656 #define lpfc_reg_fcfi_vlan_tag_SHIFT    0
1657 #define lpfc_reg_fcfi_vlan_tag_MASK     0x00000FFF
1658 #define lpfc_reg_fcfi_vlan_tag_WORD     word8
1659 };
1660
1661 struct lpfc_mbx_unreg_fcfi {
1662         uint32_t word1_rsv;
1663         uint32_t word2;
1664 #define lpfc_unreg_fcfi_SHIFT           0
1665 #define lpfc_unreg_fcfi_MASK            0x0000FFFF
1666 #define lpfc_unreg_fcfi_WORD            word2
1667 };
1668
1669 struct lpfc_mbx_read_rev {
1670         uint32_t word1;
1671 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT           16
1672 #define lpfc_mbx_rd_rev_sli_lvl_MASK            0x0000000F
1673 #define lpfc_mbx_rd_rev_sli_lvl_WORD            word1
1674 #define lpfc_mbx_rd_rev_fcoe_SHIFT              20
1675 #define lpfc_mbx_rd_rev_fcoe_MASK               0x00000001
1676 #define lpfc_mbx_rd_rev_fcoe_WORD               word1
1677 #define lpfc_mbx_rd_rev_cee_ver_SHIFT           21
1678 #define lpfc_mbx_rd_rev_cee_ver_MASK            0x00000003
1679 #define lpfc_mbx_rd_rev_cee_ver_WORD            word1
1680 #define LPFC_PREDCBX_CEE_MODE   0
1681 #define LPFC_DCBX_CEE_MODE      1
1682 #define lpfc_mbx_rd_rev_vpd_SHIFT               29
1683 #define lpfc_mbx_rd_rev_vpd_MASK                0x00000001
1684 #define lpfc_mbx_rd_rev_vpd_WORD                word1
1685         uint32_t first_hw_rev;
1686         uint32_t second_hw_rev;
1687         uint32_t word4_rsvd;
1688         uint32_t third_hw_rev;
1689         uint32_t word6;
1690 #define lpfc_mbx_rd_rev_fcph_low_SHIFT          0
1691 #define lpfc_mbx_rd_rev_fcph_low_MASK           0x000000FF
1692 #define lpfc_mbx_rd_rev_fcph_low_WORD           word6
1693 #define lpfc_mbx_rd_rev_fcph_high_SHIFT         8
1694 #define lpfc_mbx_rd_rev_fcph_high_MASK          0x000000FF
1695 #define lpfc_mbx_rd_rev_fcph_high_WORD          word6
1696 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT       16
1697 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK        0x000000FF
1698 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD        word6
1699 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT      24
1700 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK       0x000000FF
1701 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD       word6
1702         uint32_t word7_rsvd;
1703         uint32_t fw_id_rev;
1704         uint8_t  fw_name[16];
1705         uint32_t ulp_fw_id_rev;
1706         uint8_t  ulp_fw_name[16];
1707         uint32_t word18_47_rsvd[30];
1708         uint32_t word48;
1709 #define lpfc_mbx_rd_rev_avail_len_SHIFT         0
1710 #define lpfc_mbx_rd_rev_avail_len_MASK          0x00FFFFFF
1711 #define lpfc_mbx_rd_rev_avail_len_WORD          word48
1712         uint32_t vpd_paddr_low;
1713         uint32_t vpd_paddr_high;
1714         uint32_t avail_vpd_len;
1715         uint32_t rsvd_52_63[12];
1716 };
1717
1718 struct lpfc_mbx_read_config {
1719         uint32_t word1;
1720 #define lpfc_mbx_rd_conf_max_bbc_SHIFT          0
1721 #define lpfc_mbx_rd_conf_max_bbc_MASK           0x000000FF
1722 #define lpfc_mbx_rd_conf_max_bbc_WORD           word1
1723 #define lpfc_mbx_rd_conf_init_bbc_SHIFT         8
1724 #define lpfc_mbx_rd_conf_init_bbc_MASK          0x000000FF
1725 #define lpfc_mbx_rd_conf_init_bbc_WORD          word1
1726         uint32_t word2;
1727 #define lpfc_mbx_rd_conf_nport_did_SHIFT        0
1728 #define lpfc_mbx_rd_conf_nport_did_MASK         0x00FFFFFF
1729 #define lpfc_mbx_rd_conf_nport_did_WORD         word2
1730 #define lpfc_mbx_rd_conf_topology_SHIFT         24
1731 #define lpfc_mbx_rd_conf_topology_MASK          0x000000FF
1732 #define lpfc_mbx_rd_conf_topology_WORD          word2
1733         uint32_t word3;
1734 #define lpfc_mbx_rd_conf_ao_SHIFT               0
1735 #define lpfc_mbx_rd_conf_ao_MASK                0x00000001
1736 #define lpfc_mbx_rd_conf_ao_WORD                word3
1737 #define lpfc_mbx_rd_conf_bb_scn_SHIFT           8
1738 #define lpfc_mbx_rd_conf_bb_scn_MASK            0x0000000F
1739 #define lpfc_mbx_rd_conf_bb_scn_WORD            word3
1740 #define lpfc_mbx_rd_conf_cbb_scn_SHIFT          12
1741 #define lpfc_mbx_rd_conf_cbb_scn_MASK           0x0000000F
1742 #define lpfc_mbx_rd_conf_cbb_scn_WORD           word3
1743 #define lpfc_mbx_rd_conf_mc_SHIFT               29
1744 #define lpfc_mbx_rd_conf_mc_MASK                0x00000001
1745 #define lpfc_mbx_rd_conf_mc_WORD                word3
1746         uint32_t word4;
1747 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT          0
1748 #define lpfc_mbx_rd_conf_e_d_tov_MASK           0x0000FFFF
1749 #define lpfc_mbx_rd_conf_e_d_tov_WORD           word4
1750         uint32_t word5;
1751 #define lpfc_mbx_rd_conf_lp_tov_SHIFT           0
1752 #define lpfc_mbx_rd_conf_lp_tov_MASK            0x0000FFFF
1753 #define lpfc_mbx_rd_conf_lp_tov_WORD            word5
1754         uint32_t word6;
1755 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT          0
1756 #define lpfc_mbx_rd_conf_r_a_tov_MASK           0x0000FFFF
1757 #define lpfc_mbx_rd_conf_r_a_tov_WORD           word6
1758         uint32_t word7;
1759 #define lpfc_mbx_rd_conf_r_t_tov_SHIFT          0
1760 #define lpfc_mbx_rd_conf_r_t_tov_MASK           0x000000FF
1761 #define lpfc_mbx_rd_conf_r_t_tov_WORD           word7
1762         uint32_t word8;
1763 #define lpfc_mbx_rd_conf_al_tov_SHIFT           0
1764 #define lpfc_mbx_rd_conf_al_tov_MASK            0x0000000F
1765 #define lpfc_mbx_rd_conf_al_tov_WORD            word8
1766         uint32_t word9;
1767 #define lpfc_mbx_rd_conf_lmt_SHIFT              0
1768 #define lpfc_mbx_rd_conf_lmt_MASK               0x0000FFFF
1769 #define lpfc_mbx_rd_conf_lmt_WORD               word9
1770         uint32_t word10;
1771 #define lpfc_mbx_rd_conf_max_alpa_SHIFT         0
1772 #define lpfc_mbx_rd_conf_max_alpa_MASK          0x000000FF
1773 #define lpfc_mbx_rd_conf_max_alpa_WORD          word10
1774         uint32_t word11_rsvd;
1775         uint32_t word12;
1776 #define lpfc_mbx_rd_conf_xri_base_SHIFT         0
1777 #define lpfc_mbx_rd_conf_xri_base_MASK          0x0000FFFF
1778 #define lpfc_mbx_rd_conf_xri_base_WORD          word12
1779 #define lpfc_mbx_rd_conf_xri_count_SHIFT        16
1780 #define lpfc_mbx_rd_conf_xri_count_MASK         0x0000FFFF
1781 #define lpfc_mbx_rd_conf_xri_count_WORD         word12
1782         uint32_t word13;
1783 #define lpfc_mbx_rd_conf_rpi_base_SHIFT         0
1784 #define lpfc_mbx_rd_conf_rpi_base_MASK          0x0000FFFF
1785 #define lpfc_mbx_rd_conf_rpi_base_WORD          word13
1786 #define lpfc_mbx_rd_conf_rpi_count_SHIFT        16
1787 #define lpfc_mbx_rd_conf_rpi_count_MASK         0x0000FFFF
1788 #define lpfc_mbx_rd_conf_rpi_count_WORD         word13
1789         uint32_t word14;
1790 #define lpfc_mbx_rd_conf_vpi_base_SHIFT         0
1791 #define lpfc_mbx_rd_conf_vpi_base_MASK          0x0000FFFF
1792 #define lpfc_mbx_rd_conf_vpi_base_WORD          word14
1793 #define lpfc_mbx_rd_conf_vpi_count_SHIFT        16
1794 #define lpfc_mbx_rd_conf_vpi_count_MASK         0x0000FFFF
1795 #define lpfc_mbx_rd_conf_vpi_count_WORD         word14
1796         uint32_t word15;
1797 #define lpfc_mbx_rd_conf_vfi_base_SHIFT         0
1798 #define lpfc_mbx_rd_conf_vfi_base_MASK          0x0000FFFF
1799 #define lpfc_mbx_rd_conf_vfi_base_WORD          word15
1800 #define lpfc_mbx_rd_conf_vfi_count_SHIFT        16
1801 #define lpfc_mbx_rd_conf_vfi_count_MASK         0x0000FFFF
1802 #define lpfc_mbx_rd_conf_vfi_count_WORD         word15
1803         uint32_t word16;
1804 #define lpfc_mbx_rd_conf_fcfi_base_SHIFT        0
1805 #define lpfc_mbx_rd_conf_fcfi_base_MASK         0x0000FFFF
1806 #define lpfc_mbx_rd_conf_fcfi_base_WORD         word16
1807 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT       16
1808 #define lpfc_mbx_rd_conf_fcfi_count_MASK        0x0000FFFF
1809 #define lpfc_mbx_rd_conf_fcfi_count_WORD        word16
1810         uint32_t word17;
1811 #define lpfc_mbx_rd_conf_rq_count_SHIFT         0
1812 #define lpfc_mbx_rd_conf_rq_count_MASK          0x0000FFFF
1813 #define lpfc_mbx_rd_conf_rq_count_WORD          word17
1814 #define lpfc_mbx_rd_conf_eq_count_SHIFT         16
1815 #define lpfc_mbx_rd_conf_eq_count_MASK          0x0000FFFF
1816 #define lpfc_mbx_rd_conf_eq_count_WORD          word17
1817         uint32_t word18;
1818 #define lpfc_mbx_rd_conf_wq_count_SHIFT         0
1819 #define lpfc_mbx_rd_conf_wq_count_MASK          0x0000FFFF
1820 #define lpfc_mbx_rd_conf_wq_count_WORD          word18
1821 #define lpfc_mbx_rd_conf_cq_count_SHIFT         16
1822 #define lpfc_mbx_rd_conf_cq_count_MASK          0x0000FFFF
1823 #define lpfc_mbx_rd_conf_cq_count_WORD          word18
1824 };
1825
1826 struct lpfc_mbx_request_features {
1827         uint32_t word1;
1828 #define lpfc_mbx_rq_ftr_qry_SHIFT               0
1829 #define lpfc_mbx_rq_ftr_qry_MASK                0x00000001
1830 #define lpfc_mbx_rq_ftr_qry_WORD                word1
1831         uint32_t word2;
1832 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT           0
1833 #define lpfc_mbx_rq_ftr_rq_iaab_MASK            0x00000001
1834 #define lpfc_mbx_rq_ftr_rq_iaab_WORD            word2
1835 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT           1
1836 #define lpfc_mbx_rq_ftr_rq_npiv_MASK            0x00000001
1837 #define lpfc_mbx_rq_ftr_rq_npiv_WORD            word2
1838 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT            2
1839 #define lpfc_mbx_rq_ftr_rq_dif_MASK             0x00000001
1840 #define lpfc_mbx_rq_ftr_rq_dif_WORD             word2
1841 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT             3
1842 #define lpfc_mbx_rq_ftr_rq_vf_MASK              0x00000001
1843 #define lpfc_mbx_rq_ftr_rq_vf_WORD              word2
1844 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT           4
1845 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK            0x00000001
1846 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD            word2
1847 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT           5
1848 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK            0x00000001
1849 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD            word2
1850 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT           6
1851 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK            0x00000001
1852 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD            word2
1853 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT           7
1854 #define lpfc_mbx_rq_ftr_rq_ifip_MASK            0x00000001
1855 #define lpfc_mbx_rq_ftr_rq_ifip_WORD            word2
1856 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT          11
1857 #define lpfc_mbx_rq_ftr_rq_perfh_MASK           0x00000001
1858 #define lpfc_mbx_rq_ftr_rq_perfh_WORD           word2
1859         uint32_t word3;
1860 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT          0
1861 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK           0x00000001
1862 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD           word3
1863 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT          1
1864 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK           0x00000001
1865 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD           word3
1866 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT           2
1867 #define lpfc_mbx_rq_ftr_rsp_dif_MASK            0x00000001
1868 #define lpfc_mbx_rq_ftr_rsp_dif_WORD            word3
1869 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT            3
1870 #define lpfc_mbx_rq_ftr_rsp_vf__MASK            0x00000001
1871 #define lpfc_mbx_rq_ftr_rsp_vf_WORD             word3
1872 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT          4
1873 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK           0x00000001
1874 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD           word3
1875 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT          5
1876 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK           0x00000001
1877 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD           word3
1878 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT          6
1879 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK           0x00000001
1880 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD           word3
1881 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT          7
1882 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK           0x00000001
1883 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD           word3
1884 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT         11
1885 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK          0x00000001
1886 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD          word3
1887 };
1888
1889 struct lpfc_mbx_supp_pages {
1890         uint32_t word1;
1891 #define qs_SHIFT                                0
1892 #define qs_MASK                                 0x00000001
1893 #define qs_WORD                                 word1
1894 #define wr_SHIFT                                1
1895 #define wr_MASK                                 0x00000001
1896 #define wr_WORD                                 word1
1897 #define pf_SHIFT                                8
1898 #define pf_MASK                                 0x000000ff
1899 #define pf_WORD                                 word1
1900 #define cpn_SHIFT                               16
1901 #define cpn_MASK                                0x000000ff
1902 #define cpn_WORD                                word1
1903         uint32_t word2;
1904 #define list_offset_SHIFT                       0
1905 #define list_offset_MASK                        0x000000ff
1906 #define list_offset_WORD                        word2
1907 #define next_offset_SHIFT                       8
1908 #define next_offset_MASK                        0x000000ff
1909 #define next_offset_WORD                        word2
1910 #define elem_cnt_SHIFT                          16
1911 #define elem_cnt_MASK                           0x000000ff
1912 #define elem_cnt_WORD                           word2
1913         uint32_t word3;
1914 #define pn_0_SHIFT                              24
1915 #define pn_0_MASK                               0x000000ff
1916 #define pn_0_WORD                               word3
1917 #define pn_1_SHIFT                              16
1918 #define pn_1_MASK                               0x000000ff
1919 #define pn_1_WORD                               word3
1920 #define pn_2_SHIFT                              8
1921 #define pn_2_MASK                               0x000000ff
1922 #define pn_2_WORD                               word3
1923 #define pn_3_SHIFT                              0
1924 #define pn_3_MASK                               0x000000ff
1925 #define pn_3_WORD                               word3
1926         uint32_t word4;
1927 #define pn_4_SHIFT                              24
1928 #define pn_4_MASK                               0x000000ff
1929 #define pn_4_WORD                               word4
1930 #define pn_5_SHIFT                              16
1931 #define pn_5_MASK                               0x000000ff
1932 #define pn_5_WORD                               word4
1933 #define pn_6_SHIFT                              8
1934 #define pn_6_MASK                               0x000000ff
1935 #define pn_6_WORD                               word4
1936 #define pn_7_SHIFT                              0
1937 #define pn_7_MASK                               0x000000ff
1938 #define pn_7_WORD                               word4
1939         uint32_t rsvd[27];
1940 #define LPFC_SUPP_PAGES                 0
1941 #define LPFC_BLOCK_GUARD_PROFILES       1
1942 #define LPFC_SLI4_PARAMETERS            2
1943 };
1944
1945 struct lpfc_mbx_pc_sli4_params {
1946         uint32_t word1;
1947 #define qs_SHIFT                                0
1948 #define qs_MASK                                 0x00000001
1949 #define qs_WORD                                 word1
1950 #define wr_SHIFT                                1
1951 #define wr_MASK                                 0x00000001
1952 #define wr_WORD                                 word1
1953 #define pf_SHIFT                                8
1954 #define pf_MASK                                 0x000000ff
1955 #define pf_WORD                                 word1
1956 #define cpn_SHIFT                               16
1957 #define cpn_MASK                                0x000000ff
1958 #define cpn_WORD                                word1
1959         uint32_t word2;
1960 #define if_type_SHIFT                           0
1961 #define if_type_MASK                            0x00000007
1962 #define if_type_WORD                            word2
1963 #define sli_rev_SHIFT                           4
1964 #define sli_rev_MASK                            0x0000000f
1965 #define sli_rev_WORD                            word2
1966 #define sli_family_SHIFT                        8
1967 #define sli_family_MASK                         0x000000ff
1968 #define sli_family_WORD                         word2
1969 #define featurelevel_1_SHIFT                    16
1970 #define featurelevel_1_MASK                     0x000000ff
1971 #define featurelevel_1_WORD                     word2
1972 #define featurelevel_2_SHIFT                    24
1973 #define featurelevel_2_MASK                     0x0000001f
1974 #define featurelevel_2_WORD                     word2
1975         uint32_t word3;
1976 #define fcoe_SHIFT                              0
1977 #define fcoe_MASK                               0x00000001
1978 #define fcoe_WORD                               word3
1979 #define fc_SHIFT                                1
1980 #define fc_MASK                                 0x00000001
1981 #define fc_WORD                                 word3
1982 #define nic_SHIFT                               2
1983 #define nic_MASK                                0x00000001
1984 #define nic_WORD                                word3
1985 #define iscsi_SHIFT                             3
1986 #define iscsi_MASK                              0x00000001
1987 #define iscsi_WORD                              word3
1988 #define rdma_SHIFT                              4
1989 #define rdma_MASK                               0x00000001
1990 #define rdma_WORD                               word3
1991         uint32_t sge_supp_len;
1992 #define SLI4_PAGE_SIZE 4096
1993         uint32_t word5;
1994 #define if_page_sz_SHIFT                        0
1995 #define if_page_sz_MASK                         0x0000ffff
1996 #define if_page_sz_WORD                         word5
1997 #define loopbk_scope_SHIFT                      24
1998 #define loopbk_scope_MASK                       0x0000000f
1999 #define loopbk_scope_WORD                       word5
2000 #define rq_db_window_SHIFT                      28
2001 #define rq_db_window_MASK                       0x0000000f
2002 #define rq_db_window_WORD                       word5
2003         uint32_t word6;
2004 #define eq_pages_SHIFT                          0
2005 #define eq_pages_MASK                           0x0000000f
2006 #define eq_pages_WORD                           word6
2007 #define eqe_size_SHIFT                          8
2008 #define eqe_size_MASK                           0x000000ff
2009 #define eqe_size_WORD                           word6
2010         uint32_t word7;
2011 #define cq_pages_SHIFT                          0
2012 #define cq_pages_MASK                           0x0000000f
2013 #define cq_pages_WORD                           word7
2014 #define cqe_size_SHIFT                          8
2015 #define cqe_size_MASK                           0x000000ff
2016 #define cqe_size_WORD                           word7
2017         uint32_t word8;
2018 #define mq_pages_SHIFT                          0
2019 #define mq_pages_MASK                           0x0000000f
2020 #define mq_pages_WORD                           word8
2021 #define mqe_size_SHIFT                          8
2022 #define mqe_size_MASK                           0x000000ff
2023 #define mqe_size_WORD                           word8
2024 #define mq_elem_cnt_SHIFT                       16
2025 #define mq_elem_cnt_MASK                        0x000000ff
2026 #define mq_elem_cnt_WORD                        word8
2027         uint32_t word9;
2028 #define wq_pages_SHIFT                          0
2029 #define wq_pages_MASK                           0x0000ffff
2030 #define wq_pages_WORD                           word9
2031 #define wqe_size_SHIFT                          8
2032 #define wqe_size_MASK                           0x000000ff
2033 #define wqe_size_WORD                           word9
2034         uint32_t word10;
2035 #define rq_pages_SHIFT                          0
2036 #define rq_pages_MASK                           0x0000ffff
2037 #define rq_pages_WORD                           word10
2038 #define rqe_size_SHIFT                          8
2039 #define rqe_size_MASK                           0x000000ff
2040 #define rqe_size_WORD                           word10
2041         uint32_t word11;
2042 #define hdr_pages_SHIFT                         0
2043 #define hdr_pages_MASK                          0x0000000f
2044 #define hdr_pages_WORD                          word11
2045 #define hdr_size_SHIFT                          8
2046 #define hdr_size_MASK                           0x0000000f
2047 #define hdr_size_WORD                           word11
2048 #define hdr_pp_align_SHIFT                      16
2049 #define hdr_pp_align_MASK                       0x0000ffff
2050 #define hdr_pp_align_WORD                       word11
2051         uint32_t word12;
2052 #define sgl_pages_SHIFT                         0
2053 #define sgl_pages_MASK                          0x0000000f
2054 #define sgl_pages_WORD                          word12
2055 #define sgl_pp_align_SHIFT                      16
2056 #define sgl_pp_align_MASK                       0x0000ffff
2057 #define sgl_pp_align_WORD                       word12
2058         uint32_t rsvd_13_63[51];
2059 };
2060
2061 struct lpfc_sli4_parameters {
2062         uint32_t word0;
2063 #define cfg_prot_type_SHIFT                     0
2064 #define cfg_prot_type_MASK                      0x000000FF
2065 #define cfg_prot_type_WORD                      word0
2066         uint32_t word1;
2067 #define cfg_ft_SHIFT                            0
2068 #define cfg_ft_MASK                             0x00000001
2069 #define cfg_ft_WORD                             word1
2070 #define cfg_sli_rev_SHIFT                       4
2071 #define cfg_sli_rev_MASK                        0x0000000f
2072 #define cfg_sli_rev_WORD                        word1
2073 #define cfg_sli_family_SHIFT                    8
2074 #define cfg_sli_family_MASK                     0x0000000f
2075 #define cfg_sli_family_WORD                     word1
2076 #define cfg_if_type_SHIFT                       12
2077 #define cfg_if_type_MASK                        0x0000000f
2078 #define cfg_if_type_WORD                        word1
2079 #define cfg_sli_hint_1_SHIFT                    16
2080 #define cfg_sli_hint_1_MASK                     0x000000ff
2081 #define cfg_sli_hint_1_WORD                     word1
2082 #define cfg_sli_hint_2_SHIFT                    24
2083 #define cfg_sli_hint_2_MASK                     0x0000001f
2084 #define cfg_sli_hint_2_WORD                     word1
2085         uint32_t word2;
2086         uint32_t word3;
2087         uint32_t word4;
2088 #define cfg_cqv_SHIFT                           14
2089 #define cfg_cqv_MASK                            0x00000003
2090 #define cfg_cqv_WORD                            word4
2091         uint32_t word5;
2092         uint32_t word6;
2093 #define cfg_mqv_SHIFT                           14
2094 #define cfg_mqv_MASK                            0x00000003
2095 #define cfg_mqv_WORD                            word6
2096         uint32_t word7;
2097         uint32_t word8;
2098 #define cfg_wqv_SHIFT                           14
2099 #define cfg_wqv_MASK                            0x00000003
2100 #define cfg_wqv_WORD                            word8
2101         uint32_t word9;
2102         uint32_t word10;
2103 #define cfg_rqv_SHIFT                           14
2104 #define cfg_rqv_MASK                            0x00000003
2105 #define cfg_rqv_WORD                            word10
2106         uint32_t word11;
2107 #define cfg_rq_db_window_SHIFT                  28
2108 #define cfg_rq_db_window_MASK                   0x0000000f
2109 #define cfg_rq_db_window_WORD                   word11
2110         uint32_t word12;
2111 #define cfg_fcoe_SHIFT                          0
2112 #define cfg_fcoe_MASK                           0x00000001
2113 #define cfg_fcoe_WORD                           word12
2114 #define cfg_phwq_SHIFT                          15
2115 #define cfg_phwq_MASK                           0x00000001
2116 #define cfg_phwq_WORD                           word12
2117 #define cfg_loopbk_scope_SHIFT                  28
2118 #define cfg_loopbk_scope_MASK                   0x0000000f
2119 #define cfg_loopbk_scope_WORD                   word12
2120         uint32_t sge_supp_len;
2121         uint32_t word14;
2122 #define cfg_sgl_page_cnt_SHIFT                  0
2123 #define cfg_sgl_page_cnt_MASK                   0x0000000f
2124 #define cfg_sgl_page_cnt_WORD                   word14
2125 #define cfg_sgl_page_size_SHIFT                 8
2126 #define cfg_sgl_page_size_MASK                  0x000000ff
2127 #define cfg_sgl_page_size_WORD                  word14
2128 #define cfg_sgl_pp_align_SHIFT                  16
2129 #define cfg_sgl_pp_align_MASK                   0x000000ff
2130 #define cfg_sgl_pp_align_WORD                   word14
2131         uint32_t word15;
2132         uint32_t word16;
2133         uint32_t word17;
2134         uint32_t word18;
2135         uint32_t word19;
2136 };
2137
2138 struct lpfc_mbx_get_sli4_parameters {
2139         struct mbox_header header;
2140         struct lpfc_sli4_parameters sli4_parameters;
2141 };
2142
2143 /* Mailbox Completion Queue Error Messages */
2144 #define MB_CQE_STATUS_SUCCESS                   0x0
2145 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES   0x1
2146 #define MB_CQE_STATUS_INVALID_PARAMETER         0x2
2147 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES    0x3
2148 #define MB_CEQ_STATUS_QUEUE_FLUSHING            0x4
2149 #define MB_CQE_STATUS_DMA_FAILED                0x5
2150
2151 /* mailbox queue entry structure */
2152 struct lpfc_mqe {
2153         uint32_t word0;
2154 #define lpfc_mqe_status_SHIFT           16
2155 #define lpfc_mqe_status_MASK            0x0000FFFF
2156 #define lpfc_mqe_status_WORD            word0
2157 #define lpfc_mqe_command_SHIFT          8
2158 #define lpfc_mqe_command_MASK           0x000000FF
2159 #define lpfc_mqe_command_WORD           word0
2160         union {
2161                 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
2162                 /* sli4 mailbox commands */
2163                 struct lpfc_mbx_sli4_config sli4_config;
2164                 struct lpfc_mbx_init_vfi init_vfi;
2165                 struct lpfc_mbx_reg_vfi reg_vfi;
2166                 struct lpfc_mbx_reg_vfi unreg_vfi;
2167                 struct lpfc_mbx_init_vpi init_vpi;
2168                 struct lpfc_mbx_resume_rpi resume_rpi;
2169                 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
2170                 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
2171                 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
2172                 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
2173                 struct lpfc_mbx_reg_fcfi reg_fcfi;
2174                 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
2175                 struct lpfc_mbx_mq_create mq_create;
2176                 struct lpfc_mbx_mq_create_ext mq_create_ext;
2177                 struct lpfc_mbx_eq_create eq_create;
2178                 struct lpfc_mbx_cq_create cq_create;
2179                 struct lpfc_mbx_wq_create wq_create;
2180                 struct lpfc_mbx_rq_create rq_create;
2181                 struct lpfc_mbx_mq_destroy mq_destroy;
2182                 struct lpfc_mbx_eq_destroy eq_destroy;
2183                 struct lpfc_mbx_cq_destroy cq_destroy;
2184                 struct lpfc_mbx_wq_destroy wq_destroy;
2185                 struct lpfc_mbx_rq_destroy rq_destroy;
2186                 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
2187                 struct lpfc_mbx_nembed_cmd nembed_cmd;
2188                 struct lpfc_mbx_read_rev read_rev;
2189                 struct lpfc_mbx_read_vpi read_vpi;
2190                 struct lpfc_mbx_read_config rd_config;
2191                 struct lpfc_mbx_request_features req_ftrs;
2192                 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
2193                 struct lpfc_mbx_query_fw_cfg query_fw_cfg;
2194                 struct lpfc_mbx_supp_pages supp_pages;
2195                 struct lpfc_mbx_pc_sli4_params sli4_params;
2196                 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
2197                 struct lpfc_mbx_nop nop;
2198         } un;
2199 };
2200
2201 struct lpfc_mcqe {
2202         uint32_t word0;
2203 #define lpfc_mcqe_status_SHIFT          0
2204 #define lpfc_mcqe_status_MASK           0x0000FFFF
2205 #define lpfc_mcqe_status_WORD           word0
2206 #define lpfc_mcqe_ext_status_SHIFT      16
2207 #define lpfc_mcqe_ext_status_MASK       0x0000FFFF
2208 #define lpfc_mcqe_ext_status_WORD       word0
2209         uint32_t mcqe_tag0;
2210         uint32_t mcqe_tag1;
2211         uint32_t trailer;
2212 #define lpfc_trailer_valid_SHIFT        31
2213 #define lpfc_trailer_valid_MASK         0x00000001
2214 #define lpfc_trailer_valid_WORD         trailer
2215 #define lpfc_trailer_async_SHIFT        30
2216 #define lpfc_trailer_async_MASK         0x00000001
2217 #define lpfc_trailer_async_WORD         trailer
2218 #define lpfc_trailer_hpi_SHIFT          29
2219 #define lpfc_trailer_hpi_MASK           0x00000001
2220 #define lpfc_trailer_hpi_WORD           trailer
2221 #define lpfc_trailer_completed_SHIFT    28
2222 #define lpfc_trailer_completed_MASK     0x00000001
2223 #define lpfc_trailer_completed_WORD     trailer
2224 #define lpfc_trailer_consumed_SHIFT     27
2225 #define lpfc_trailer_consumed_MASK      0x00000001
2226 #define lpfc_trailer_consumed_WORD      trailer
2227 #define lpfc_trailer_type_SHIFT         16
2228 #define lpfc_trailer_type_MASK          0x000000FF
2229 #define lpfc_trailer_type_WORD          trailer
2230 #define lpfc_trailer_code_SHIFT         8
2231 #define lpfc_trailer_code_MASK          0x000000FF
2232 #define lpfc_trailer_code_WORD          trailer
2233 #define LPFC_TRAILER_CODE_LINK  0x1
2234 #define LPFC_TRAILER_CODE_FCOE  0x2
2235 #define LPFC_TRAILER_CODE_DCBX  0x3
2236 #define LPFC_TRAILER_CODE_GRP5  0x5
2237 #define LPFC_TRAILER_CODE_FC    0x10
2238 #define LPFC_TRAILER_CODE_SLI   0x11
2239 };
2240
2241 struct lpfc_acqe_link {
2242         uint32_t word0;
2243 #define lpfc_acqe_link_speed_SHIFT              24
2244 #define lpfc_acqe_link_speed_MASK               0x000000FF
2245 #define lpfc_acqe_link_speed_WORD               word0
2246 #define LPFC_ASYNC_LINK_SPEED_ZERO              0x0
2247 #define LPFC_ASYNC_LINK_SPEED_10MBPS            0x1
2248 #define LPFC_ASYNC_LINK_SPEED_100MBPS           0x2
2249 #define LPFC_ASYNC_LINK_SPEED_1GBPS             0x3
2250 #define LPFC_ASYNC_LINK_SPEED_10GBPS            0x4
2251 #define lpfc_acqe_link_duplex_SHIFT             16
2252 #define lpfc_acqe_link_duplex_MASK              0x000000FF
2253 #define lpfc_acqe_link_duplex_WORD              word0
2254 #define LPFC_ASYNC_LINK_DUPLEX_NONE             0x0
2255 #define LPFC_ASYNC_LINK_DUPLEX_HALF             0x1
2256 #define LPFC_ASYNC_LINK_DUPLEX_FULL             0x2
2257 #define lpfc_acqe_link_status_SHIFT             8
2258 #define lpfc_acqe_link_status_MASK              0x000000FF
2259 #define lpfc_acqe_link_status_WORD              word0
2260 #define LPFC_ASYNC_LINK_STATUS_DOWN             0x0
2261 #define LPFC_ASYNC_LINK_STATUS_UP               0x1
2262 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN     0x2
2263 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP       0x3
2264 #define lpfc_acqe_link_type_SHIFT               6
2265 #define lpfc_acqe_link_type_MASK                0x00000003
2266 #define lpfc_acqe_link_type_WORD                word0
2267 #define lpfc_acqe_link_number_SHIFT             0
2268 #define lpfc_acqe_link_number_MASK              0x0000003F
2269 #define lpfc_acqe_link_number_WORD              word0
2270         uint32_t word1;
2271 #define lpfc_acqe_link_fault_SHIFT      0
2272 #define lpfc_acqe_link_fault_MASK       0x000000FF
2273 #define lpfc_acqe_link_fault_WORD       word1
2274 #define LPFC_ASYNC_LINK_FAULT_NONE      0x0
2275 #define LPFC_ASYNC_LINK_FAULT_LOCAL     0x1
2276 #define LPFC_ASYNC_LINK_FAULT_REMOTE    0x2
2277 #define lpfc_acqe_logical_link_speed_SHIFT      16
2278 #define lpfc_acqe_logical_link_speed_MASK       0x0000FFFF
2279 #define lpfc_acqe_logical_link_speed_WORD       word1
2280         uint32_t event_tag;
2281         uint32_t trailer;
2282 #define LPFC_LINK_EVENT_TYPE_PHYSICAL   0x0
2283 #define LPFC_LINK_EVENT_TYPE_VIRTUAL    0x1
2284 };
2285
2286 struct lpfc_acqe_fip {
2287         uint32_t index;
2288         uint32_t word1;
2289 #define lpfc_acqe_fip_fcf_count_SHIFT           0
2290 #define lpfc_acqe_fip_fcf_count_MASK            0x0000FFFF
2291 #define lpfc_acqe_fip_fcf_count_WORD            word1
2292 #define lpfc_acqe_fip_event_type_SHIFT          16
2293 #define lpfc_acqe_fip_event_type_MASK           0x0000FFFF
2294 #define lpfc_acqe_fip_event_type_WORD           word1
2295         uint32_t event_tag;
2296         uint32_t trailer;
2297 #define LPFC_FIP_EVENT_TYPE_NEW_FCF             0x1
2298 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL      0x2
2299 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD            0x3
2300 #define LPFC_FIP_EVENT_TYPE_CVL                 0x4
2301 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD       0x5
2302 };
2303
2304 struct lpfc_acqe_dcbx {
2305         uint32_t tlv_ttl;
2306         uint32_t reserved;
2307         uint32_t event_tag;
2308         uint32_t trailer;
2309 };
2310
2311 struct lpfc_acqe_grp5 {
2312         uint32_t word0;
2313 #define lpfc_acqe_grp5_type_SHIFT               6
2314 #define lpfc_acqe_grp5_type_MASK                0x00000003
2315 #define lpfc_acqe_grp5_type_WORD                word0
2316 #define lpfc_acqe_grp5_number_SHIFT             0
2317 #define lpfc_acqe_grp5_number_MASK              0x0000003F
2318 #define lpfc_acqe_grp5_number_WORD              word0
2319         uint32_t word1;
2320 #define lpfc_acqe_grp5_llink_spd_SHIFT  16
2321 #define lpfc_acqe_grp5_llink_spd_MASK   0x0000FFFF
2322 #define lpfc_acqe_grp5_llink_spd_WORD   word1
2323         uint32_t event_tag;
2324         uint32_t trailer;
2325 };
2326
2327 struct lpfc_acqe_fc_la {
2328         uint32_t word0;
2329 #define lpfc_acqe_fc_la_speed_SHIFT             24
2330 #define lpfc_acqe_fc_la_speed_MASK              0x000000FF
2331 #define lpfc_acqe_fc_la_speed_WORD              word0
2332 #define LPFC_FC_LA_SPEED_UNKOWN         0x0
2333 #define LPFC_FC_LA_SPEED_1G             0x1
2334 #define LPFC_FC_LA_SPEED_2G             0x2
2335 #define LPFC_FC_LA_SPEED_4G             0x4
2336 #define LPFC_FC_LA_SPEED_8G             0x8
2337 #define LPFC_FC_LA_SPEED_10G            0xA
2338 #define LPFC_FC_LA_SPEED_16G            0x10
2339 #define lpfc_acqe_fc_la_topology_SHIFT          16
2340 #define lpfc_acqe_fc_la_topology_MASK           0x000000FF
2341 #define lpfc_acqe_fc_la_topology_WORD           word0
2342 #define LPFC_FC_LA_TOP_UNKOWN           0x0
2343 #define LPFC_FC_LA_TOP_P2P              0x1
2344 #define LPFC_FC_LA_TOP_FCAL             0x2
2345 #define LPFC_FC_LA_TOP_INTERNAL_LOOP    0x3
2346 #define LPFC_FC_LA_TOP_SERDES_LOOP      0x4
2347 #define lpfc_acqe_fc_la_att_type_SHIFT          8
2348 #define lpfc_acqe_fc_la_att_type_MASK           0x000000FF
2349 #define lpfc_acqe_fc_la_att_type_WORD           word0
2350 #define LPFC_FC_LA_TYPE_LINK_UP         0x1
2351 #define LPFC_FC_LA_TYPE_LINK_DOWN       0x2
2352 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA    0x3
2353 #define lpfc_acqe_fc_la_port_type_SHIFT         6
2354 #define lpfc_acqe_fc_la_port_type_MASK          0x00000003
2355 #define lpfc_acqe_fc_la_port_type_WORD          word0
2356 #define LPFC_LINK_TYPE_ETHERNET         0x0
2357 #define LPFC_LINK_TYPE_FC               0x1
2358 #define lpfc_acqe_fc_la_port_number_SHIFT       0
2359 #define lpfc_acqe_fc_la_port_number_MASK        0x0000003F
2360 #define lpfc_acqe_fc_la_port_number_WORD        word0
2361         uint32_t word1;
2362 #define lpfc_acqe_fc_la_llink_spd_SHIFT         16
2363 #define lpfc_acqe_fc_la_llink_spd_MASK          0x0000FFFF
2364 #define lpfc_acqe_fc_la_llink_spd_WORD          word1
2365 #define lpfc_acqe_fc_la_fault_SHIFT             0
2366 #define lpfc_acqe_fc_la_fault_MASK              0x000000FF
2367 #define lpfc_acqe_fc_la_fault_WORD              word1
2368 #define LPFC_FC_LA_FAULT_NONE           0x0
2369 #define LPFC_FC_LA_FAULT_LOCAL          0x1
2370 #define LPFC_FC_LA_FAULT_REMOTE         0x2
2371         uint32_t event_tag;
2372         uint32_t trailer;
2373 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK           0x1
2374 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK       0x2
2375 };
2376
2377 struct lpfc_acqe_sli {
2378         uint32_t event_data1;
2379         uint32_t event_data2;
2380         uint32_t reserved;
2381         uint32_t trailer;
2382 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR          0x1
2383 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP           0x2
2384 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP           0x3
2385 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST          0x4
2386 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP           0x5
2387 };
2388
2389 /*
2390  * Define the bootstrap mailbox (bmbx) region used to communicate
2391  * mailbox command between the host and port. The mailbox consists
2392  * of a payload area of 256 bytes and a completion queue of length
2393  * 16 bytes.
2394  */
2395 struct lpfc_bmbx_create {
2396         struct lpfc_mqe mqe;
2397         struct lpfc_mcqe mcqe;
2398 };
2399
2400 #define SGL_ALIGN_SZ 64
2401 #define SGL_PAGE_SIZE 4096
2402 /* align SGL addr on a size boundary - adjust address up */
2403 #define NO_XRI  ((uint16_t)-1)
2404
2405 struct wqe_common {
2406         uint32_t word6;
2407 #define wqe_xri_tag_SHIFT     0
2408 #define wqe_xri_tag_MASK      0x0000FFFF
2409 #define wqe_xri_tag_WORD      word6
2410 #define wqe_ctxt_tag_SHIFT    16
2411 #define wqe_ctxt_tag_MASK     0x0000FFFF
2412 #define wqe_ctxt_tag_WORD     word6
2413         uint32_t word7;
2414 #define wqe_ct_SHIFT          2
2415 #define wqe_ct_MASK           0x00000003
2416 #define wqe_ct_WORD           word7
2417 #define wqe_status_SHIFT      4
2418 #define wqe_status_MASK       0x0000000f
2419 #define wqe_status_WORD       word7
2420 #define wqe_cmnd_SHIFT        8
2421 #define wqe_cmnd_MASK         0x000000ff
2422 #define wqe_cmnd_WORD         word7
2423 #define wqe_class_SHIFT       16
2424 #define wqe_class_MASK        0x00000007
2425 #define wqe_class_WORD        word7
2426 #define wqe_pu_SHIFT          20
2427 #define wqe_pu_MASK           0x00000003
2428 #define wqe_pu_WORD           word7
2429 #define wqe_erp_SHIFT         22
2430 #define wqe_erp_MASK          0x00000001
2431 #define wqe_erp_WORD          word7
2432 #define wqe_lnk_SHIFT         23
2433 #define wqe_lnk_MASK          0x00000001
2434 #define wqe_lnk_WORD          word7
2435 #define wqe_tmo_SHIFT         24
2436 #define wqe_tmo_MASK          0x000000ff
2437 #define wqe_tmo_WORD          word7
2438         uint32_t abort_tag; /* word 8 in WQE */
2439         uint32_t word9;
2440 #define wqe_reqtag_SHIFT      0
2441 #define wqe_reqtag_MASK       0x0000FFFF
2442 #define wqe_reqtag_WORD       word9
2443 #define wqe_rcvoxid_SHIFT     16
2444 #define wqe_rcvoxid_MASK      0x0000FFFF
2445 #define wqe_rcvoxid_WORD      word9
2446         uint32_t word10;
2447 #define wqe_ebde_cnt_SHIFT    0
2448 #define wqe_ebde_cnt_MASK     0x0000000f
2449 #define wqe_ebde_cnt_WORD     word10
2450 #define wqe_lenloc_SHIFT      7
2451 #define wqe_lenloc_MASK       0x00000003
2452 #define wqe_lenloc_WORD       word10
2453 #define LPFC_WQE_LENLOC_NONE            0
2454 #define LPFC_WQE_LENLOC_WORD3   1
2455 #define LPFC_WQE_LENLOC_WORD12  2
2456 #define LPFC_WQE_LENLOC_WORD4   3
2457 #define wqe_qosd_SHIFT        9
2458 #define wqe_qosd_MASK         0x00000001
2459 #define wqe_qosd_WORD         word10
2460 #define wqe_xbl_SHIFT         11
2461 #define wqe_xbl_MASK          0x00000001
2462 #define wqe_xbl_WORD          word10
2463 #define wqe_iod_SHIFT         13
2464 #define wqe_iod_MASK          0x00000001
2465 #define wqe_iod_WORD          word10
2466 #define LPFC_WQE_IOD_WRITE      0
2467 #define LPFC_WQE_IOD_READ       1
2468 #define wqe_dbde_SHIFT        14
2469 #define wqe_dbde_MASK         0x00000001
2470 #define wqe_dbde_WORD         word10
2471 #define wqe_wqes_SHIFT        15
2472 #define wqe_wqes_MASK         0x00000001
2473 #define wqe_wqes_WORD         word10
2474 /* Note that this field overlaps above fields */
2475 #define wqe_wqid_SHIFT        1
2476 #define wqe_wqid_MASK         0x0000007f
2477 #define wqe_wqid_WORD         word10
2478 #define wqe_pri_SHIFT         16
2479 #define wqe_pri_MASK          0x00000007
2480 #define wqe_pri_WORD          word10
2481 #define wqe_pv_SHIFT          19
2482 #define wqe_pv_MASK           0x00000001
2483 #define wqe_pv_WORD           word10
2484 #define wqe_xc_SHIFT          21
2485 #define wqe_xc_MASK           0x00000001
2486 #define wqe_xc_WORD           word10
2487 #define wqe_ccpe_SHIFT        23
2488 #define wqe_ccpe_MASK         0x00000001
2489 #define wqe_ccpe_WORD         word10
2490 #define wqe_ccp_SHIFT         24
2491 #define wqe_ccp_MASK          0x000000ff
2492 #define wqe_ccp_WORD          word10
2493         uint32_t word11;
2494 #define wqe_cmd_type_SHIFT    0
2495 #define wqe_cmd_type_MASK     0x0000000f
2496 #define wqe_cmd_type_WORD     word11
2497 #define wqe_els_id_SHIFT      4
2498 #define wqe_els_id_MASK       0x00000003
2499 #define wqe_els_id_WORD       word11
2500 #define LPFC_ELS_ID_FLOGI       3
2501 #define LPFC_ELS_ID_FDISC       2
2502 #define LPFC_ELS_ID_LOGO        1
2503 #define LPFC_ELS_ID_DEFAULT     0
2504 #define wqe_wqec_SHIFT        7
2505 #define wqe_wqec_MASK         0x00000001
2506 #define wqe_wqec_WORD         word11
2507 #define wqe_cqid_SHIFT        16
2508 #define wqe_cqid_MASK         0x0000ffff
2509 #define wqe_cqid_WORD         word11
2510 #define LPFC_WQE_CQ_ID_DEFAULT  0xffff
2511 };
2512
2513 struct wqe_did {
2514         uint32_t word5;
2515 #define wqe_els_did_SHIFT         0
2516 #define wqe_els_did_MASK          0x00FFFFFF
2517 #define wqe_els_did_WORD          word5
2518 #define wqe_xmit_bls_pt_SHIFT         28
2519 #define wqe_xmit_bls_pt_MASK          0x00000003
2520 #define wqe_xmit_bls_pt_WORD          word5
2521 #define wqe_xmit_bls_ar_SHIFT         30
2522 #define wqe_xmit_bls_ar_MASK          0x00000001
2523 #define wqe_xmit_bls_ar_WORD          word5
2524 #define wqe_xmit_bls_xo_SHIFT         31
2525 #define wqe_xmit_bls_xo_MASK          0x00000001
2526 #define wqe_xmit_bls_xo_WORD          word5
2527 };
2528
2529 struct lpfc_wqe_generic{
2530         struct ulp_bde64 bde;
2531         uint32_t word3;
2532         uint32_t word4;
2533         uint32_t word5;
2534         struct wqe_common wqe_com;
2535         uint32_t payload[4];
2536 };
2537
2538 struct els_request64_wqe {
2539         struct ulp_bde64 bde;
2540         uint32_t payload_len;
2541         uint32_t word4;
2542 #define els_req64_sid_SHIFT         0
2543 #define els_req64_sid_MASK          0x00FFFFFF
2544 #define els_req64_sid_WORD          word4
2545 #define els_req64_sp_SHIFT          24
2546 #define els_req64_sp_MASK           0x00000001
2547 #define els_req64_sp_WORD           word4
2548 #define els_req64_vf_SHIFT          25
2549 #define els_req64_vf_MASK           0x00000001
2550 #define els_req64_vf_WORD           word4
2551         struct wqe_did  wqe_dest;
2552         struct wqe_common wqe_com; /* words 6-11 */
2553         uint32_t word12;
2554 #define els_req64_vfid_SHIFT        1
2555 #define els_req64_vfid_MASK         0x00000FFF
2556 #define els_req64_vfid_WORD         word12
2557 #define els_req64_pri_SHIFT         13
2558 #define els_req64_pri_MASK          0x00000007
2559 #define els_req64_pri_WORD          word12
2560         uint32_t word13;
2561 #define els_req64_hopcnt_SHIFT      24
2562 #define els_req64_hopcnt_MASK       0x000000ff
2563 #define els_req64_hopcnt_WORD       word13
2564         uint32_t reserved[2];
2565 };
2566
2567 struct xmit_els_rsp64_wqe {
2568         struct ulp_bde64 bde;
2569         uint32_t response_payload_len;
2570         uint32_t rsvd4;
2571         struct wqe_did wqe_dest;
2572         struct wqe_common wqe_com; /* words 6-11 */
2573         uint32_t rsvd_12_15[4];
2574 };
2575
2576 struct xmit_bls_rsp64_wqe {
2577         uint32_t payload0;
2578 /* Payload0 for BA_ACC */
2579 #define xmit_bls_rsp64_acc_seq_id_SHIFT        16
2580 #define xmit_bls_rsp64_acc_seq_id_MASK         0x000000ff
2581 #define xmit_bls_rsp64_acc_seq_id_WORD         payload0
2582 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT   24
2583 #define xmit_bls_rsp64_acc_seq_id_vald_MASK    0x000000ff
2584 #define xmit_bls_rsp64_acc_seq_id_vald_WORD    payload0
2585 /* Payload0 for BA_RJT */
2586 #define xmit_bls_rsp64_rjt_vspec_SHIFT   0
2587 #define xmit_bls_rsp64_rjt_vspec_MASK    0x000000ff
2588 #define xmit_bls_rsp64_rjt_vspec_WORD    payload0
2589 #define xmit_bls_rsp64_rjt_expc_SHIFT    8
2590 #define xmit_bls_rsp64_rjt_expc_MASK     0x000000ff
2591 #define xmit_bls_rsp64_rjt_expc_WORD     payload0
2592 #define xmit_bls_rsp64_rjt_rsnc_SHIFT    16
2593 #define xmit_bls_rsp64_rjt_rsnc_MASK     0x000000ff
2594 #define xmit_bls_rsp64_rjt_rsnc_WORD     payload0
2595         uint32_t word1;
2596 #define xmit_bls_rsp64_rxid_SHIFT  0
2597 #define xmit_bls_rsp64_rxid_MASK   0x0000ffff
2598 #define xmit_bls_rsp64_rxid_WORD   word1
2599 #define xmit_bls_rsp64_oxid_SHIFT  16
2600 #define xmit_bls_rsp64_oxid_MASK   0x0000ffff
2601 #define xmit_bls_rsp64_oxid_WORD   word1
2602         uint32_t word2;
2603 #define xmit_bls_rsp64_seqcnthi_SHIFT  0
2604 #define xmit_bls_rsp64_seqcnthi_MASK   0x0000ffff
2605 #define xmit_bls_rsp64_seqcnthi_WORD   word2
2606 #define xmit_bls_rsp64_seqcntlo_SHIFT  16
2607 #define xmit_bls_rsp64_seqcntlo_MASK   0x0000ffff
2608 #define xmit_bls_rsp64_seqcntlo_WORD   word2
2609         uint32_t rsrvd3;
2610         uint32_t rsrvd4;
2611         struct wqe_did  wqe_dest;
2612         struct wqe_common wqe_com; /* words 6-11 */
2613         uint32_t rsvd_12_15[4];
2614 };
2615
2616 struct wqe_rctl_dfctl {
2617         uint32_t word5;
2618 #define wqe_si_SHIFT 2
2619 #define wqe_si_MASK  0x000000001
2620 #define wqe_si_WORD  word5
2621 #define wqe_la_SHIFT 3
2622 #define wqe_la_MASK  0x000000001
2623 #define wqe_la_WORD  word5
2624 #define wqe_ls_SHIFT 7
2625 #define wqe_ls_MASK  0x000000001
2626 #define wqe_ls_WORD  word5
2627 #define wqe_dfctl_SHIFT 8
2628 #define wqe_dfctl_MASK  0x0000000ff
2629 #define wqe_dfctl_WORD  word5
2630 #define wqe_type_SHIFT 16
2631 #define wqe_type_MASK  0x0000000ff
2632 #define wqe_type_WORD  word5
2633 #define wqe_rctl_SHIFT 24
2634 #define wqe_rctl_MASK  0x0000000ff
2635 #define wqe_rctl_WORD  word5
2636 };
2637
2638 struct xmit_seq64_wqe {
2639         struct ulp_bde64 bde;
2640         uint32_t rsvd3;
2641         uint32_t relative_offset;
2642         struct wqe_rctl_dfctl wge_ctl;
2643         struct wqe_common wqe_com; /* words 6-11 */
2644         uint32_t xmit_len;
2645         uint32_t rsvd_12_15[3];
2646 };
2647 struct xmit_bcast64_wqe {
2648         struct ulp_bde64 bde;
2649         uint32_t seq_payload_len;
2650         uint32_t rsvd4;
2651         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
2652         struct wqe_common wqe_com;     /* words 6-11 */
2653         uint32_t rsvd_12_15[4];
2654 };
2655
2656 struct gen_req64_wqe {
2657         struct ulp_bde64 bde;
2658         uint32_t request_payload_len;
2659         uint32_t relative_offset;
2660         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
2661         struct wqe_common wqe_com;     /* words 6-11 */
2662         uint32_t rsvd_12_15[4];
2663 };
2664
2665 struct create_xri_wqe {
2666         uint32_t rsrvd[5];           /* words 0-4 */
2667         struct wqe_did  wqe_dest;  /* word 5 */
2668         struct wqe_common wqe_com; /* words 6-11 */
2669         uint32_t rsvd_12_15[4];         /* word 12-15 */
2670 };
2671
2672 #define T_REQUEST_TAG 3
2673 #define T_XRI_TAG 1
2674
2675 struct abort_cmd_wqe {
2676         uint32_t rsrvd[3];
2677         uint32_t word3;
2678 #define abort_cmd_ia_SHIFT  0
2679 #define abort_cmd_ia_MASK  0x000000001
2680 #define abort_cmd_ia_WORD  word3
2681 #define abort_cmd_criteria_SHIFT  8
2682 #define abort_cmd_criteria_MASK  0x0000000ff
2683 #define abort_cmd_criteria_WORD  word3
2684         uint32_t rsrvd4;
2685         uint32_t rsrvd5;
2686         struct wqe_common wqe_com;     /* words 6-11 */
2687         uint32_t rsvd_12_15[4];         /* word 12-15 */
2688 };
2689
2690 struct fcp_iwrite64_wqe {
2691         struct ulp_bde64 bde;
2692         uint32_t payload_offset_len;
2693         uint32_t total_xfer_len;
2694         uint32_t initial_xfer_len;
2695         struct wqe_common wqe_com;     /* words 6-11 */
2696         uint32_t rsrvd12;
2697         struct ulp_bde64 ph_bde;       /* words 13-15 */
2698 };
2699
2700 struct fcp_iread64_wqe {
2701         struct ulp_bde64 bde;
2702         uint32_t payload_offset_len;   /* word 3 */
2703         uint32_t total_xfer_len;       /* word 4 */
2704         uint32_t rsrvd5;               /* word 5 */
2705         struct wqe_common wqe_com;     /* words 6-11 */
2706         uint32_t rsrvd12;
2707         struct ulp_bde64 ph_bde;       /* words 13-15 */
2708 };
2709
2710 struct fcp_icmnd64_wqe {
2711         struct ulp_bde64 bde;          /* words 0-2 */
2712         uint32_t rsrvd3;               /* word 3 */
2713         uint32_t rsrvd4;               /* word 4 */
2714         uint32_t rsrvd5;               /* word 5 */
2715         struct wqe_common wqe_com;     /* words 6-11 */
2716         uint32_t rsvd_12_15[4];        /* word 12-15 */
2717 };
2718
2719
2720 union lpfc_wqe {
2721         uint32_t words[16];
2722         struct lpfc_wqe_generic generic;
2723         struct fcp_icmnd64_wqe fcp_icmd;
2724         struct fcp_iread64_wqe fcp_iread;
2725         struct fcp_iwrite64_wqe fcp_iwrite;
2726         struct abort_cmd_wqe abort_cmd;
2727         struct create_xri_wqe create_xri;
2728         struct xmit_bcast64_wqe xmit_bcast64;
2729         struct xmit_seq64_wqe xmit_sequence;
2730         struct xmit_bls_rsp64_wqe xmit_bls_rsp;
2731         struct xmit_els_rsp64_wqe xmit_els_rsp;
2732         struct els_request64_wqe els_req;
2733         struct gen_req64_wqe gen_req;
2734 };
2735
2736 #define FCP_COMMAND 0x0
2737 #define FCP_COMMAND_DATA_OUT 0x1
2738 #define ELS_COMMAND_NON_FIP 0xC
2739 #define ELS_COMMAND_FIP 0xD
2740 #define OTHER_COMMAND 0x8
2741