2 * drivers/pci/setup-res.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/export.h>
22 #include <linux/pci.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/cache.h>
26 #include <linux/slab.h>
30 void pci_update_resource(struct pci_dev *dev, int resno)
32 struct pci_bus_region region;
35 enum pci_bar_type type;
36 struct resource *res = dev->resource + resno;
39 * Ignore resources for unimplemented BARs and unused resource slots
46 * Ignore non-moveable resources. This might be legacy resources for
47 * which no functional BAR register exists or another important
48 * system resource we shouldn't move around.
50 if (res->flags & IORESOURCE_PCI_FIXED)
53 pcibios_resource_to_bus(dev, ®ion, res);
55 new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
56 if (res->flags & IORESOURCE_IO)
57 mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
59 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
61 reg = pci_resource_bar(dev, resno, &type);
64 if (type != pci_bar_unknown) {
65 if (!(res->flags & IORESOURCE_ROM_ENABLE))
67 new |= PCI_ROM_ADDRESS_ENABLE;
70 pci_write_config_dword(dev, reg, new);
71 pci_read_config_dword(dev, reg, &check);
73 if ((new ^ check) & mask) {
74 dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
78 if (res->flags & IORESOURCE_MEM_64) {
79 new = region.start >> 16 >> 16;
80 pci_write_config_dword(dev, reg + 4, new);
81 pci_read_config_dword(dev, reg + 4, &check);
83 dev_err(&dev->dev, "BAR %d: error updating "
84 "(high %#08x != %#08x)\n", resno, new, check);
87 res->flags &= ~IORESOURCE_UNSET;
88 dev_info(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
89 resno, res, (unsigned long long)region.start,
90 (unsigned long long)region.end);
93 int pci_claim_resource(struct pci_dev *dev, int resource)
95 struct resource *res = &dev->resource[resource];
96 struct resource *root, *conflict;
98 root = pci_find_parent_resource(dev, res);
100 dev_info(&dev->dev, "no compatible bridge window for %pR\n",
105 conflict = request_resource_conflict(root, res);
108 "address space collision: %pR conflicts with %s %pR\n",
109 res, conflict->name, conflict);
115 EXPORT_SYMBOL(pci_claim_resource);
117 #ifdef CONFIG_PCI_QUIRKS
118 void pci_disable_bridge_window(struct pci_dev *dev)
120 dev_info(&dev->dev, "disabling bridge mem windows\n");
122 /* MMIO Base/Limit */
123 pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
125 /* Prefetchable MMIO Base/Limit */
126 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
127 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
128 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
130 #endif /* CONFIG_PCI_QUIRKS */
134 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
135 int resno, resource_size_t size, resource_size_t align)
137 struct resource *res = dev->resource + resno;
141 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
143 /* First, try exact prefetching match.. */
144 ret = pci_bus_alloc_resource(bus, res, size, align, min,
146 pcibios_align_resource, dev);
148 if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
152 * But a prefetching area can handle a non-prefetching
153 * window (it will just not perform as well).
155 ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
156 pcibios_align_resource, dev);
161 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
162 int resno, resource_size_t size)
164 struct resource *root, *conflict;
165 resource_size_t start, end;
168 if (res->flags & IORESOURCE_IO)
169 root = &ioport_resource;
171 root = &iomem_resource;
175 res->start = dev->fw_addr[resno];
176 res->end = res->start + size - 1;
177 dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
179 conflict = request_resource_conflict(root, res);
182 "BAR %d: %pR conflicts with %s %pR\n", resno,
183 res, conflict->name, conflict);
191 static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align)
193 struct resource *res = dev->resource + resno;
199 while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
200 if (!bus->parent || !bus->self->transparent)
206 if (res->flags & IORESOURCE_MEM)
207 if (res->flags & IORESOURCE_PREFETCH)
211 else if (res->flags & IORESOURCE_IO)
216 "BAR %d: can't assign %s (size %#llx)\n",
217 resno, type, (unsigned long long) resource_size(res));
223 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
224 resource_size_t min_align)
226 struct resource *res = dev->resource + resno;
227 resource_size_t new_size;
231 dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resouce %pR "
236 /* already aligned with min_align */
237 new_size = resource_size(res) + addsize;
238 ret = _pci_assign_resource(dev, resno, new_size, min_align);
240 res->flags &= ~IORESOURCE_STARTALIGN;
241 dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res);
242 if (resno < PCI_BRIDGE_RESOURCES)
243 pci_update_resource(dev, resno);
248 int pci_assign_resource(struct pci_dev *dev, int resno)
250 struct resource *res = dev->resource + resno;
251 resource_size_t align, size;
255 align = pci_resource_alignment(dev, res);
257 dev_info(&dev->dev, "BAR %d: can't assign %pR "
258 "(bogus alignment)\n", resno, res);
263 size = resource_size(res);
264 ret = _pci_assign_resource(dev, resno, size, align);
267 * If we failed to assign anything, let's try the address
268 * where firmware left it. That at least has a chance of
269 * working, which is better than just leaving it disabled.
271 if (ret < 0 && dev->fw_addr[resno])
272 ret = pci_revert_fw_address(res, dev, resno, size);
275 res->flags &= ~IORESOURCE_STARTALIGN;
276 dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
277 if (resno < PCI_BRIDGE_RESOURCES)
278 pci_update_resource(dev, resno);
284 /* Sort resources by alignment */
285 void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
289 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
291 struct resource_list *list, *tmp;
292 resource_size_t r_align;
294 r = &dev->resource[i];
296 if (r->flags & IORESOURCE_PCI_FIXED)
299 if (!(r->flags) || r->parent)
302 r_align = pci_resource_alignment(dev, r);
304 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
308 for (list = head; ; list = list->next) {
309 resource_size_t align = 0;
310 struct resource_list *ln = list->next;
313 align = pci_resource_alignment(ln->dev, ln->res);
315 if (r_align > align) {
316 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
318 panic("pdev_sort_resources(): "
319 "kmalloc() failed!\n");
330 int pci_enable_resources(struct pci_dev *dev, int mask)
336 pci_read_config_word(dev, PCI_COMMAND, &cmd);
339 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
340 if (!(mask & (1 << i)))
343 r = &dev->resource[i];
345 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
347 if ((i == PCI_ROM_RESOURCE) &&
348 (!(r->flags & IORESOURCE_ROM_ENABLE)))
352 dev_err(&dev->dev, "device not available "
353 "(can't reserve %pR)\n", r);
357 if (r->flags & IORESOURCE_IO)
358 cmd |= PCI_COMMAND_IO;
359 if (r->flags & IORESOURCE_MEM)
360 cmd |= PCI_COMMAND_MEMORY;
363 if (cmd != old_cmd) {
364 dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
366 pci_write_config_word(dev, PCI_COMMAND, cmd);