2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
28 const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31 EXPORT_SYMBOL_GPL(pci_power_names);
33 int isa_dma_bridge_buggy;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy);
37 EXPORT_SYMBOL(pci_pci_problems);
39 unsigned int pci_pm_d3_delay;
41 static void pci_pme_list_scan(struct work_struct *work);
43 static LIST_HEAD(pci_pme_list);
44 static DEFINE_MUTEX(pci_pme_list_mutex);
45 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
47 struct pci_pme_device {
48 struct list_head list;
52 #define PME_TIMEOUT 1000 /* How long between PME checks */
54 static void pci_dev_d3_sleep(struct pci_dev *dev)
56 unsigned int delay = dev->d3_delay;
58 if (delay < pci_pm_d3_delay)
59 delay = pci_pm_d3_delay;
64 #ifdef CONFIG_PCI_DOMAINS
65 int pci_domains_supported = 1;
68 #define DEFAULT_CARDBUS_IO_SIZE (256)
69 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
71 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
72 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
74 #define DEFAULT_HOTPLUG_IO_SIZE (256)
75 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
77 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
78 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
80 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
83 * The default CLS is used if arch didn't set CLS explicitly and not
84 * all pci devices agree on the same value. Arch can override either
85 * the dfl or actual value as it sees fit. Don't forget this is
86 * measured in 32-bit words, not bytes.
88 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
89 u8 pci_cache_line_size;
92 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
93 * @bus: pointer to PCI bus structure to search
95 * Given a PCI bus, returns the highest PCI bus number present in the set
96 * including the given PCI bus and its list of child PCI buses.
98 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
100 struct list_head *tmp;
101 unsigned char max, n;
103 max = bus->subordinate;
104 list_for_each(tmp, &bus->children) {
105 n = pci_bus_max_busnr(pci_bus_b(tmp));
111 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
113 #ifdef CONFIG_HAS_IOMEM
114 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
117 * Make sure the BAR is actually a memory resource, not an IO resource
119 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
123 return ioremap_nocache(pci_resource_start(pdev, bar),
124 pci_resource_len(pdev, bar));
126 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
131 * pci_max_busnr - returns maximum PCI bus number
133 * Returns the highest PCI bus number present in the system global list of
136 unsigned char __devinit
139 struct pci_bus *bus = NULL;
140 unsigned char max, n;
143 while ((bus = pci_find_next_bus(bus)) != NULL) {
144 n = pci_bus_max_busnr(bus);
153 #define PCI_FIND_CAP_TTL 48
155 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
156 u8 pos, int cap, int *ttl)
161 pci_bus_read_config_byte(bus, devfn, pos, &pos);
165 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
171 pos += PCI_CAP_LIST_NEXT;
176 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
179 int ttl = PCI_FIND_CAP_TTL;
181 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
184 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
186 return __pci_find_next_cap(dev->bus, dev->devfn,
187 pos + PCI_CAP_LIST_NEXT, cap);
189 EXPORT_SYMBOL_GPL(pci_find_next_capability);
191 static int __pci_bus_find_cap_start(struct pci_bus *bus,
192 unsigned int devfn, u8 hdr_type)
196 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
197 if (!(status & PCI_STATUS_CAP_LIST))
201 case PCI_HEADER_TYPE_NORMAL:
202 case PCI_HEADER_TYPE_BRIDGE:
203 return PCI_CAPABILITY_LIST;
204 case PCI_HEADER_TYPE_CARDBUS:
205 return PCI_CB_CAPABILITY_LIST;
214 * pci_find_capability - query for devices' capabilities
215 * @dev: PCI device to query
216 * @cap: capability code
218 * Tell if a device supports a given PCI capability.
219 * Returns the address of the requested capability structure within the
220 * device's PCI configuration space or 0 in case the device does not
221 * support it. Possible values for @cap:
223 * %PCI_CAP_ID_PM Power Management
224 * %PCI_CAP_ID_AGP Accelerated Graphics Port
225 * %PCI_CAP_ID_VPD Vital Product Data
226 * %PCI_CAP_ID_SLOTID Slot Identification
227 * %PCI_CAP_ID_MSI Message Signalled Interrupts
228 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
229 * %PCI_CAP_ID_PCIX PCI-X
230 * %PCI_CAP_ID_EXP PCI Express
232 int pci_find_capability(struct pci_dev *dev, int cap)
236 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
238 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
244 * pci_bus_find_capability - query for devices' capabilities
245 * @bus: the PCI bus to query
246 * @devfn: PCI device to query
247 * @cap: capability code
249 * Like pci_find_capability() but works for pci devices that do not have a
250 * pci_dev structure set up yet.
252 * Returns the address of the requested capability structure within the
253 * device's PCI configuration space or 0 in case the device does not
256 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
261 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
263 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
265 pos = __pci_find_next_cap(bus, devfn, pos, cap);
271 * pci_find_ext_capability - Find an extended capability
272 * @dev: PCI device to query
273 * @cap: capability code
275 * Returns the address of the requested extended capability structure
276 * within the device's PCI configuration space or 0 if the device does
277 * not support it. Possible values for @cap:
279 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
280 * %PCI_EXT_CAP_ID_VC Virtual Channel
281 * %PCI_EXT_CAP_ID_DSN Device Serial Number
282 * %PCI_EXT_CAP_ID_PWR Power Budgeting
284 int pci_find_ext_capability(struct pci_dev *dev, int cap)
288 int pos = PCI_CFG_SPACE_SIZE;
290 /* minimum 8 bytes per capability */
291 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
293 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
296 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
300 * If we have no capabilities, this is indicated by cap ID,
301 * cap version and next pointer all being 0.
307 if (PCI_EXT_CAP_ID(header) == cap)
310 pos = PCI_EXT_CAP_NEXT(header);
311 if (pos < PCI_CFG_SPACE_SIZE)
314 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
320 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
323 * pci_bus_find_ext_capability - find an extended capability
324 * @bus: the PCI bus to query
325 * @devfn: PCI device to query
326 * @cap: capability code
328 * Like pci_find_ext_capability() but works for pci devices that do not have a
329 * pci_dev structure set up yet.
331 * Returns the address of the requested capability structure within the
332 * device's PCI configuration space or 0 in case the device does not
335 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
340 int pos = PCI_CFG_SPACE_SIZE;
342 /* minimum 8 bytes per capability */
343 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
345 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
347 if (header == 0xffffffff || header == 0)
351 if (PCI_EXT_CAP_ID(header) == cap)
354 pos = PCI_EXT_CAP_NEXT(header);
355 if (pos < PCI_CFG_SPACE_SIZE)
358 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
365 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
367 int rc, ttl = PCI_FIND_CAP_TTL;
370 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
371 mask = HT_3BIT_CAP_MASK;
373 mask = HT_5BIT_CAP_MASK;
375 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
376 PCI_CAP_ID_HT, &ttl);
378 rc = pci_read_config_byte(dev, pos + 3, &cap);
379 if (rc != PCIBIOS_SUCCESSFUL)
382 if ((cap & mask) == ht_cap)
385 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
386 pos + PCI_CAP_LIST_NEXT,
387 PCI_CAP_ID_HT, &ttl);
393 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
394 * @dev: PCI device to query
395 * @pos: Position from which to continue searching
396 * @ht_cap: Hypertransport capability code
398 * To be used in conjunction with pci_find_ht_capability() to search for
399 * all capabilities matching @ht_cap. @pos should always be a value returned
400 * from pci_find_ht_capability().
402 * NB. To be 100% safe against broken PCI devices, the caller should take
403 * steps to avoid an infinite loop.
405 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
407 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
409 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
412 * pci_find_ht_capability - query a device's Hypertransport capabilities
413 * @dev: PCI device to query
414 * @ht_cap: Hypertransport capability code
416 * Tell if a device supports a given Hypertransport capability.
417 * Returns an address within the device's PCI configuration space
418 * or 0 in case the device does not support the request capability.
419 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
420 * which has a Hypertransport capability matching @ht_cap.
422 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
426 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
428 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
432 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
435 * pci_find_parent_resource - return resource region of parent bus of given region
436 * @dev: PCI device structure contains resources to be searched
437 * @res: child resource record for which parent is sought
439 * For given resource region of given device, return the resource
440 * region of parent bus the given region is contained in or where
441 * it should be allocated from.
444 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
446 const struct pci_bus *bus = dev->bus;
448 struct resource *best = NULL, *r;
450 pci_bus_for_each_resource(bus, r, i) {
453 if (res->start && !(res->start >= r->start && res->end <= r->end))
454 continue; /* Not contained */
455 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
456 continue; /* Wrong type */
457 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
458 return r; /* Exact match */
459 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
460 if (r->flags & IORESOURCE_PREFETCH)
462 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
470 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
471 * @dev: PCI device to have its BARs restored
473 * Restore the BAR values for a given device, so as to make it
474 * accessible by its driver.
477 pci_restore_bars(struct pci_dev *dev)
481 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
482 pci_update_resource(dev, i);
485 static struct pci_platform_pm_ops *pci_platform_pm;
487 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
489 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
490 || !ops->sleep_wake || !ops->can_wakeup)
492 pci_platform_pm = ops;
496 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
498 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
501 static inline int platform_pci_set_power_state(struct pci_dev *dev,
504 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
507 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
509 return pci_platform_pm ?
510 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
513 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
515 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
518 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
520 return pci_platform_pm ?
521 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
524 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
526 return pci_platform_pm ?
527 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
531 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
533 * @dev: PCI device to handle.
534 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
537 * -EINVAL if the requested state is invalid.
538 * -EIO if device does not support PCI PM or its PM capabilities register has a
539 * wrong version, or device doesn't support the requested state.
540 * 0 if device already is in the requested state.
541 * 0 if device's power state has been successfully changed.
543 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
546 bool need_restore = false;
548 /* Check if we're already there */
549 if (dev->current_state == state)
555 if (state < PCI_D0 || state > PCI_D3hot)
558 /* Validate current state:
559 * Can enter D0 from any state, but if we can only go deeper
560 * to sleep if we're already in a low power state
562 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
563 && dev->current_state > state) {
564 dev_err(&dev->dev, "invalid power transition "
565 "(from state %d to %d)\n", dev->current_state, state);
569 /* check if this device supports the desired state */
570 if ((state == PCI_D1 && !dev->d1_support)
571 || (state == PCI_D2 && !dev->d2_support))
574 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
576 /* If we're (effectively) in D3, force entire word to 0.
577 * This doesn't affect PME_Status, disables PME_En, and
578 * sets PowerState to 0.
580 switch (dev->current_state) {
584 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
589 case PCI_UNKNOWN: /* Boot-up */
590 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
591 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
593 /* Fall-through: force to D0 */
599 /* enter specified state */
600 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
602 /* Mandatory power management transition delays */
603 /* see PCI PM 1.1 5.6.1 table 18 */
604 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
605 pci_dev_d3_sleep(dev);
606 else if (state == PCI_D2 || dev->current_state == PCI_D2)
607 udelay(PCI_PM_D2_DELAY);
609 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
610 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
611 if (dev->current_state != state && printk_ratelimit())
612 dev_info(&dev->dev, "Refused to change power state, "
613 "currently in D%d\n", dev->current_state);
615 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
616 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
617 * from D3hot to D0 _may_ perform an internal reset, thereby
618 * going to "D0 Uninitialized" rather than "D0 Initialized".
619 * For example, at least some versions of the 3c905B and the
620 * 3c556B exhibit this behaviour.
622 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
623 * devices in a D3hot state at boot. Consequently, we need to
624 * restore at least the BARs so that the device will be
625 * accessible to its driver.
628 pci_restore_bars(dev);
631 pcie_aspm_pm_state_change(dev->bus->self);
637 * pci_update_current_state - Read PCI power state of given device from its
638 * PCI PM registers and cache it
639 * @dev: PCI device to handle.
640 * @state: State to cache in case the device doesn't have the PM capability
642 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
647 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
648 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
650 dev->current_state = state;
655 * pci_platform_power_transition - Use platform to change device power state
656 * @dev: PCI device to handle.
657 * @state: State to put the device into.
659 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
663 if (platform_pci_power_manageable(dev)) {
664 error = platform_pci_set_power_state(dev, state);
666 pci_update_current_state(dev, state);
670 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
671 dev->current_state = PCI_D0;
677 * __pci_start_power_transition - Start power transition of a PCI device
678 * @dev: PCI device to handle.
679 * @state: State to put the device into.
681 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
684 pci_platform_power_transition(dev, PCI_D0);
688 * __pci_complete_power_transition - Complete power transition of a PCI device
689 * @dev: PCI device to handle.
690 * @state: State to put the device into.
692 * This function should not be called directly by device drivers.
694 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
696 return state >= PCI_D0 ?
697 pci_platform_power_transition(dev, state) : -EINVAL;
699 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
702 * pci_set_power_state - Set the power state of a PCI device
703 * @dev: PCI device to handle.
704 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
706 * Transition a device to a new power state, using the platform firmware and/or
707 * the device's PCI PM registers.
710 * -EINVAL if the requested state is invalid.
711 * -EIO if device does not support PCI PM or its PM capabilities register has a
712 * wrong version, or device doesn't support the requested state.
713 * 0 if device already is in the requested state.
714 * 0 if device's power state has been successfully changed.
716 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
720 /* bound the state we're entering */
721 if (state > PCI_D3hot)
723 else if (state < PCI_D0)
725 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
727 * If the device or the parent bridge do not support PCI PM,
728 * ignore the request if we're doing anything other than putting
729 * it into D0 (which would only happen on boot).
733 __pci_start_power_transition(dev, state);
735 /* This device is quirked not to be put into D3, so
736 don't put it in D3 */
737 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
740 error = pci_raw_set_power_state(dev, state);
742 if (!__pci_complete_power_transition(dev, state))
745 * When aspm_policy is "powersave" this call ensures
746 * that ASPM is configured.
748 if (!error && dev->bus->self)
749 pcie_aspm_powersave_config_link(dev->bus->self);
755 * pci_choose_state - Choose the power state of a PCI device
756 * @dev: PCI device to be suspended
757 * @state: target sleep state for the whole system. This is the value
758 * that is passed to suspend() function.
760 * Returns PCI power state suitable for given device and given system
764 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
768 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
771 ret = platform_pci_choose_state(dev);
772 if (ret != PCI_POWER_ERROR)
775 switch (state.event) {
778 case PM_EVENT_FREEZE:
779 case PM_EVENT_PRETHAW:
780 /* REVISIT both freeze and pre-thaw "should" use D0 */
781 case PM_EVENT_SUSPEND:
782 case PM_EVENT_HIBERNATE:
785 dev_info(&dev->dev, "unrecognized suspend event %d\n",
792 EXPORT_SYMBOL(pci_choose_state);
794 #define PCI_EXP_SAVE_REGS 7
796 #define pcie_cap_has_devctl(type, flags) 1
797 #define pcie_cap_has_lnkctl(type, flags) \
798 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
799 (type == PCI_EXP_TYPE_ROOT_PORT || \
800 type == PCI_EXP_TYPE_ENDPOINT || \
801 type == PCI_EXP_TYPE_LEG_END))
802 #define pcie_cap_has_sltctl(type, flags) \
803 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
804 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
805 (type == PCI_EXP_TYPE_DOWNSTREAM && \
806 (flags & PCI_EXP_FLAGS_SLOT))))
807 #define pcie_cap_has_rtctl(type, flags) \
808 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
809 (type == PCI_EXP_TYPE_ROOT_PORT || \
810 type == PCI_EXP_TYPE_RC_EC))
811 #define pcie_cap_has_devctl2(type, flags) \
812 ((flags & PCI_EXP_FLAGS_VERS) > 1)
813 #define pcie_cap_has_lnkctl2(type, flags) \
814 ((flags & PCI_EXP_FLAGS_VERS) > 1)
815 #define pcie_cap_has_sltctl2(type, flags) \
816 ((flags & PCI_EXP_FLAGS_VERS) > 1)
818 static int pci_save_pcie_state(struct pci_dev *dev)
821 struct pci_cap_saved_state *save_state;
825 pos = pci_pcie_cap(dev);
829 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
831 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
834 cap = (u16 *)&save_state->cap.data[0];
836 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
838 if (pcie_cap_has_devctl(dev->pcie_type, flags))
839 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
840 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
841 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
842 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
843 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
844 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
845 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
846 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
847 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
848 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
849 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
850 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
851 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
856 static void pci_restore_pcie_state(struct pci_dev *dev)
859 struct pci_cap_saved_state *save_state;
863 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
864 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
865 if (!save_state || pos <= 0)
867 cap = (u16 *)&save_state->cap.data[0];
869 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
871 if (pcie_cap_has_devctl(dev->pcie_type, flags))
872 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
873 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
874 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
875 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
876 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
877 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
878 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
879 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
880 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
881 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
882 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
883 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
884 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
888 static int pci_save_pcix_state(struct pci_dev *dev)
891 struct pci_cap_saved_state *save_state;
893 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
897 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
899 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
903 pci_read_config_word(dev, pos + PCI_X_CMD,
904 (u16 *)save_state->cap.data);
909 static void pci_restore_pcix_state(struct pci_dev *dev)
912 struct pci_cap_saved_state *save_state;
915 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
916 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
917 if (!save_state || pos <= 0)
919 cap = (u16 *)&save_state->cap.data[0];
921 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
926 * pci_save_state - save the PCI configuration space of a device before suspending
927 * @dev: - PCI device that we're dealing with
930 pci_save_state(struct pci_dev *dev)
933 /* XXX: 100% dword access ok here? */
934 for (i = 0; i < 16; i++)
935 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
936 dev->state_saved = true;
937 if ((i = pci_save_pcie_state(dev)) != 0)
939 if ((i = pci_save_pcix_state(dev)) != 0)
945 * pci_restore_state - Restore the saved state of a PCI device
946 * @dev: - PCI device that we're dealing with
948 void pci_restore_state(struct pci_dev *dev)
953 if (!dev->state_saved)
956 /* PCI Express register must be restored first */
957 pci_restore_pcie_state(dev);
960 * The Base Address register should be programmed before the command
963 for (i = 15; i >= 0; i--) {
964 pci_read_config_dword(dev, i * 4, &val);
965 if (val != dev->saved_config_space[i]) {
966 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
967 "space at offset %#x (was %#x, writing %#x)\n",
968 i, val, (int)dev->saved_config_space[i]);
969 pci_write_config_dword(dev,i * 4,
970 dev->saved_config_space[i]);
973 pci_restore_pcix_state(dev);
974 pci_restore_msi_state(dev);
975 pci_restore_iov_state(dev);
977 dev->state_saved = false;
980 struct pci_saved_state {
981 u32 config_space[16];
982 struct pci_cap_saved_data cap[0];
986 * pci_store_saved_state - Allocate and return an opaque struct containing
987 * the device saved state.
988 * @dev: PCI device that we're dealing with
990 * Rerturn NULL if no state or error.
992 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
994 struct pci_saved_state *state;
995 struct pci_cap_saved_state *tmp;
996 struct pci_cap_saved_data *cap;
997 struct hlist_node *pos;
1000 if (!dev->state_saved)
1003 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1005 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
1006 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1008 state = kzalloc(size, GFP_KERNEL);
1012 memcpy(state->config_space, dev->saved_config_space,
1013 sizeof(state->config_space));
1016 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
1017 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1018 memcpy(cap, &tmp->cap, len);
1019 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1021 /* Empty cap_save terminates list */
1025 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1028 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1029 * @dev: PCI device that we're dealing with
1030 * @state: Saved state returned from pci_store_saved_state()
1032 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1034 struct pci_cap_saved_data *cap;
1036 dev->state_saved = false;
1041 memcpy(dev->saved_config_space, state->config_space,
1042 sizeof(state->config_space));
1046 struct pci_cap_saved_state *tmp;
1048 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1049 if (!tmp || tmp->cap.size != cap->size)
1052 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1053 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1054 sizeof(struct pci_cap_saved_data) + cap->size);
1057 dev->state_saved = true;
1060 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1063 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1064 * and free the memory allocated for it.
1065 * @dev: PCI device that we're dealing with
1066 * @state: Pointer to saved state returned from pci_store_saved_state()
1068 int pci_load_and_free_saved_state(struct pci_dev *dev,
1069 struct pci_saved_state **state)
1071 int ret = pci_load_saved_state(dev, *state);
1076 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1078 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1084 err = pci_set_power_state(dev, PCI_D0);
1085 if (err < 0 && err != -EIO)
1087 err = pcibios_enable_device(dev, bars);
1090 pci_fixup_device(pci_fixup_enable, dev);
1092 if (dev->msi_enabled || dev->msix_enabled)
1095 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1097 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1098 if (cmd & PCI_COMMAND_INTX_DISABLE)
1099 pci_write_config_word(dev, PCI_COMMAND,
1100 cmd & ~PCI_COMMAND_INTX_DISABLE);
1107 * pci_reenable_device - Resume abandoned device
1108 * @dev: PCI device to be resumed
1110 * Note this function is a backend of pci_default_resume and is not supposed
1111 * to be called by normal code, write proper resume handler and use it instead.
1113 int pci_reenable_device(struct pci_dev *dev)
1115 if (pci_is_enabled(dev))
1116 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1120 static int __pci_enable_device_flags(struct pci_dev *dev,
1121 resource_size_t flags)
1127 * Power state could be unknown at this point, either due to a fresh
1128 * boot or a device removal call. So get the current power state
1129 * so that things like MSI message writing will behave as expected
1130 * (e.g. if the device really is in D0 at enable time).
1134 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1135 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1138 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1139 return 0; /* already enabled */
1141 /* only skip sriov related */
1142 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1143 if (dev->resource[i].flags & flags)
1145 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1146 if (dev->resource[i].flags & flags)
1149 err = do_pci_enable_device(dev, bars);
1151 atomic_dec(&dev->enable_cnt);
1156 * pci_enable_device_io - Initialize a device for use with IO space
1157 * @dev: PCI device to be initialized
1159 * Initialize device before it's used by a driver. Ask low-level code
1160 * to enable I/O resources. Wake up the device if it was suspended.
1161 * Beware, this function can fail.
1163 int pci_enable_device_io(struct pci_dev *dev)
1165 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1169 * pci_enable_device_mem - Initialize a device for use with Memory space
1170 * @dev: PCI device to be initialized
1172 * Initialize device before it's used by a driver. Ask low-level code
1173 * to enable Memory resources. Wake up the device if it was suspended.
1174 * Beware, this function can fail.
1176 int pci_enable_device_mem(struct pci_dev *dev)
1178 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1182 * pci_enable_device - Initialize device before it's used by a driver.
1183 * @dev: PCI device to be initialized
1185 * Initialize device before it's used by a driver. Ask low-level code
1186 * to enable I/O and memory. Wake up the device if it was suspended.
1187 * Beware, this function can fail.
1189 * Note we don't actually enable the device many times if we call
1190 * this function repeatedly (we just increment the count).
1192 int pci_enable_device(struct pci_dev *dev)
1194 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1198 * Managed PCI resources. This manages device on/off, intx/msi/msix
1199 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1200 * there's no need to track it separately. pci_devres is initialized
1201 * when a device is enabled using managed PCI device enable interface.
1204 unsigned int enabled:1;
1205 unsigned int pinned:1;
1206 unsigned int orig_intx:1;
1207 unsigned int restore_intx:1;
1211 static void pcim_release(struct device *gendev, void *res)
1213 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1214 struct pci_devres *this = res;
1217 if (dev->msi_enabled)
1218 pci_disable_msi(dev);
1219 if (dev->msix_enabled)
1220 pci_disable_msix(dev);
1222 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1223 if (this->region_mask & (1 << i))
1224 pci_release_region(dev, i);
1226 if (this->restore_intx)
1227 pci_intx(dev, this->orig_intx);
1229 if (this->enabled && !this->pinned)
1230 pci_disable_device(dev);
1233 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1235 struct pci_devres *dr, *new_dr;
1237 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1241 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1244 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1247 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1249 if (pci_is_managed(pdev))
1250 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1255 * pcim_enable_device - Managed pci_enable_device()
1256 * @pdev: PCI device to be initialized
1258 * Managed pci_enable_device().
1260 int pcim_enable_device(struct pci_dev *pdev)
1262 struct pci_devres *dr;
1265 dr = get_pci_dr(pdev);
1271 rc = pci_enable_device(pdev);
1273 pdev->is_managed = 1;
1280 * pcim_pin_device - Pin managed PCI device
1281 * @pdev: PCI device to pin
1283 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1284 * driver detach. @pdev must have been enabled with
1285 * pcim_enable_device().
1287 void pcim_pin_device(struct pci_dev *pdev)
1289 struct pci_devres *dr;
1291 dr = find_pci_dr(pdev);
1292 WARN_ON(!dr || !dr->enabled);
1298 * pcibios_disable_device - disable arch specific PCI resources for device dev
1299 * @dev: the PCI device to disable
1301 * Disables architecture specific PCI resources for the device. This
1302 * is the default implementation. Architecture implementations can
1305 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1307 static void do_pci_disable_device(struct pci_dev *dev)
1311 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1312 if (pci_command & PCI_COMMAND_MASTER) {
1313 pci_command &= ~PCI_COMMAND_MASTER;
1314 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1317 pcibios_disable_device(dev);
1321 * pci_disable_enabled_device - Disable device without updating enable_cnt
1322 * @dev: PCI device to disable
1324 * NOTE: This function is a backend of PCI power management routines and is
1325 * not supposed to be called drivers.
1327 void pci_disable_enabled_device(struct pci_dev *dev)
1329 if (pci_is_enabled(dev))
1330 do_pci_disable_device(dev);
1334 * pci_disable_device - Disable PCI device after use
1335 * @dev: PCI device to be disabled
1337 * Signal to the system that the PCI device is not in use by the system
1338 * anymore. This only involves disabling PCI bus-mastering, if active.
1340 * Note we don't actually disable the device until all callers of
1341 * pci_enable_device() have called pci_disable_device().
1344 pci_disable_device(struct pci_dev *dev)
1346 struct pci_devres *dr;
1348 dr = find_pci_dr(dev);
1352 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1355 do_pci_disable_device(dev);
1357 dev->is_busmaster = 0;
1361 * pcibios_set_pcie_reset_state - set reset state for device dev
1362 * @dev: the PCIe device reset
1363 * @state: Reset state to enter into
1366 * Sets the PCIe reset state for the device. This is the default
1367 * implementation. Architecture implementations can override this.
1369 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1370 enum pcie_reset_state state)
1376 * pci_set_pcie_reset_state - set reset state for device dev
1377 * @dev: the PCIe device reset
1378 * @state: Reset state to enter into
1381 * Sets the PCI reset state for the device.
1383 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1385 return pcibios_set_pcie_reset_state(dev, state);
1389 * pci_check_pme_status - Check if given device has generated PME.
1390 * @dev: Device to check.
1392 * Check the PME status of the device and if set, clear it and clear PME enable
1393 * (if set). Return 'true' if PME status and PME enable were both set or
1394 * 'false' otherwise.
1396 bool pci_check_pme_status(struct pci_dev *dev)
1405 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1406 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1407 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1410 /* Clear PME status. */
1411 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1412 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1413 /* Disable PME to avoid interrupt flood. */
1414 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1418 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1424 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1425 * @dev: Device to handle.
1426 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1428 * Check if @dev has generated PME and queue a resume request for it in that
1431 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1433 if (pme_poll_reset && dev->pme_poll)
1434 dev->pme_poll = false;
1436 if (pci_check_pme_status(dev)) {
1437 pci_wakeup_event(dev);
1438 pm_request_resume(&dev->dev);
1444 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1445 * @bus: Top bus of the subtree to walk.
1447 void pci_pme_wakeup_bus(struct pci_bus *bus)
1450 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1454 * pci_pme_capable - check the capability of PCI device to generate PME#
1455 * @dev: PCI device to handle.
1456 * @state: PCI state from which device will issue PME#.
1458 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1463 return !!(dev->pme_support & (1 << state));
1466 static void pci_pme_list_scan(struct work_struct *work)
1468 struct pci_pme_device *pme_dev, *n;
1470 mutex_lock(&pci_pme_list_mutex);
1471 if (!list_empty(&pci_pme_list)) {
1472 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1473 if (pme_dev->dev->pme_poll) {
1474 pci_pme_wakeup(pme_dev->dev, NULL);
1476 list_del(&pme_dev->list);
1480 if (!list_empty(&pci_pme_list))
1481 schedule_delayed_work(&pci_pme_work,
1482 msecs_to_jiffies(PME_TIMEOUT));
1484 mutex_unlock(&pci_pme_list_mutex);
1488 * pci_pme_active - enable or disable PCI device's PME# function
1489 * @dev: PCI device to handle.
1490 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1492 * The caller must verify that the device is capable of generating PME# before
1493 * calling this function with @enable equal to 'true'.
1495 void pci_pme_active(struct pci_dev *dev, bool enable)
1502 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1503 /* Clear PME_Status by writing 1 to it and enable PME# */
1504 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1506 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1508 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1510 /* PCI (as opposed to PCIe) PME requires that the device have
1511 its PME# line hooked up correctly. Not all hardware vendors
1512 do this, so the PME never gets delivered and the device
1513 remains asleep. The easiest way around this is to
1514 periodically walk the list of suspended devices and check
1515 whether any have their PME flag set. The assumption is that
1516 we'll wake up often enough anyway that this won't be a huge
1517 hit, and the power savings from the devices will still be a
1520 if (dev->pme_poll) {
1521 struct pci_pme_device *pme_dev;
1523 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1528 mutex_lock(&pci_pme_list_mutex);
1529 list_add(&pme_dev->list, &pci_pme_list);
1530 if (list_is_singular(&pci_pme_list))
1531 schedule_delayed_work(&pci_pme_work,
1532 msecs_to_jiffies(PME_TIMEOUT));
1533 mutex_unlock(&pci_pme_list_mutex);
1535 mutex_lock(&pci_pme_list_mutex);
1536 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1537 if (pme_dev->dev == dev) {
1538 list_del(&pme_dev->list);
1543 mutex_unlock(&pci_pme_list_mutex);
1548 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
1549 enable ? "enabled" : "disabled");
1553 * __pci_enable_wake - enable PCI device as wakeup event source
1554 * @dev: PCI device affected
1555 * @state: PCI state from which device will issue wakeup events
1556 * @runtime: True if the events are to be generated at run time
1557 * @enable: True to enable event generation; false to disable
1559 * This enables the device as a wakeup event source, or disables it.
1560 * When such events involves platform-specific hooks, those hooks are
1561 * called automatically by this routine.
1563 * Devices with legacy power management (no standard PCI PM capabilities)
1564 * always require such platform hooks.
1567 * 0 is returned on success
1568 * -EINVAL is returned if device is not supposed to wake up the system
1569 * Error code depending on the platform is returned if both the platform and
1570 * the native mechanism fail to enable the generation of wake-up events
1572 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1573 bool runtime, bool enable)
1577 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1580 /* Don't do the same thing twice in a row for one device. */
1581 if (!!enable == !!dev->wakeup_prepared)
1585 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1586 * Anderson we should be doing PME# wake enable followed by ACPI wake
1587 * enable. To disable wake-up we call the platform first, for symmetry.
1593 if (pci_pme_capable(dev, state))
1594 pci_pme_active(dev, true);
1597 error = runtime ? platform_pci_run_wake(dev, true) :
1598 platform_pci_sleep_wake(dev, true);
1602 dev->wakeup_prepared = true;
1605 platform_pci_run_wake(dev, false);
1607 platform_pci_sleep_wake(dev, false);
1608 pci_pme_active(dev, false);
1609 dev->wakeup_prepared = false;
1614 EXPORT_SYMBOL(__pci_enable_wake);
1617 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1618 * @dev: PCI device to prepare
1619 * @enable: True to enable wake-up event generation; false to disable
1621 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1622 * and this function allows them to set that up cleanly - pci_enable_wake()
1623 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1624 * ordering constraints.
1626 * This function only returns error code if the device is not capable of
1627 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1628 * enable wake-up power for it.
1630 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1632 return pci_pme_capable(dev, PCI_D3cold) ?
1633 pci_enable_wake(dev, PCI_D3cold, enable) :
1634 pci_enable_wake(dev, PCI_D3hot, enable);
1638 * pci_target_state - find an appropriate low power state for a given PCI dev
1641 * Use underlying platform code to find a supported low power state for @dev.
1642 * If the platform can't manage @dev, return the deepest state from which it
1643 * can generate wake events, based on any available PME info.
1645 pci_power_t pci_target_state(struct pci_dev *dev)
1647 pci_power_t target_state = PCI_D3hot;
1649 if (platform_pci_power_manageable(dev)) {
1651 * Call the platform to choose the target state of the device
1652 * and enable wake-up from this state if supported.
1654 pci_power_t state = platform_pci_choose_state(dev);
1657 case PCI_POWER_ERROR:
1662 if (pci_no_d1d2(dev))
1665 target_state = state;
1667 } else if (!dev->pm_cap) {
1668 target_state = PCI_D0;
1669 } else if (device_may_wakeup(&dev->dev)) {
1671 * Find the deepest state from which the device can generate
1672 * wake-up events, make it the target state and enable device
1675 if (dev->pme_support) {
1677 && !(dev->pme_support & (1 << target_state)))
1682 return target_state;
1686 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1687 * @dev: Device to handle.
1689 * Choose the power state appropriate for the device depending on whether
1690 * it can wake up the system and/or is power manageable by the platform
1691 * (PCI_D3hot is the default) and put the device into that state.
1693 int pci_prepare_to_sleep(struct pci_dev *dev)
1695 pci_power_t target_state = pci_target_state(dev);
1698 if (target_state == PCI_POWER_ERROR)
1701 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1703 error = pci_set_power_state(dev, target_state);
1706 pci_enable_wake(dev, target_state, false);
1712 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1713 * @dev: Device to handle.
1715 * Disable device's system wake-up capability and put it into D0.
1717 int pci_back_from_sleep(struct pci_dev *dev)
1719 pci_enable_wake(dev, PCI_D0, false);
1720 return pci_set_power_state(dev, PCI_D0);
1724 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1725 * @dev: PCI device being suspended.
1727 * Prepare @dev to generate wake-up events at run time and put it into a low
1730 int pci_finish_runtime_suspend(struct pci_dev *dev)
1732 pci_power_t target_state = pci_target_state(dev);
1735 if (target_state == PCI_POWER_ERROR)
1738 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1740 error = pci_set_power_state(dev, target_state);
1743 __pci_enable_wake(dev, target_state, true, false);
1749 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1750 * @dev: Device to check.
1752 * Return true if the device itself is cabable of generating wake-up events
1753 * (through the platform or using the native PCIe PME) or if the device supports
1754 * PME and one of its upstream bridges can generate wake-up events.
1756 bool pci_dev_run_wake(struct pci_dev *dev)
1758 struct pci_bus *bus = dev->bus;
1760 if (device_run_wake(&dev->dev))
1763 if (!dev->pme_support)
1766 /* PME-capable in principle, but not from the intended sleep state */
1767 if (!pci_pme_capable(dev, pci_target_state(dev)))
1770 while (bus->parent) {
1771 struct pci_dev *bridge = bus->self;
1773 if (device_run_wake(&bridge->dev))
1779 /* We have reached the root bus. */
1781 return device_run_wake(bus->bridge);
1785 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1788 * pci_pm_init - Initialize PM functions of given PCI device
1789 * @dev: PCI device to handle.
1791 void pci_pm_init(struct pci_dev *dev)
1796 pm_runtime_forbid(&dev->dev);
1797 device_enable_async_suspend(&dev->dev);
1798 dev->wakeup_prepared = false;
1802 /* find PCI PM capability in list */
1803 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1806 /* Check device's ability to generate PME# */
1807 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1809 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1810 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1811 pmc & PCI_PM_CAP_VER_MASK);
1816 dev->d3_delay = PCI_PM_D3_WAIT;
1818 dev->d1_support = false;
1819 dev->d2_support = false;
1820 if (!pci_no_d1d2(dev)) {
1821 if (pmc & PCI_PM_CAP_D1)
1822 dev->d1_support = true;
1823 if (pmc & PCI_PM_CAP_D2)
1824 dev->d2_support = true;
1826 if (dev->d1_support || dev->d2_support)
1827 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1828 dev->d1_support ? " D1" : "",
1829 dev->d2_support ? " D2" : "");
1832 pmc &= PCI_PM_CAP_PME_MASK;
1834 dev_printk(KERN_DEBUG, &dev->dev,
1835 "PME# supported from%s%s%s%s%s\n",
1836 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1837 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1838 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1839 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1840 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1841 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1842 dev->pme_poll = true;
1844 * Make device's PM flags reflect the wake-up capability, but
1845 * let the user space enable it to wake up the system as needed.
1847 device_set_wakeup_capable(&dev->dev, true);
1848 /* Disable the PME# generation functionality */
1849 pci_pme_active(dev, false);
1851 dev->pme_support = 0;
1856 * platform_pci_wakeup_init - init platform wakeup if present
1859 * Some devices don't have PCI PM caps but can still generate wakeup
1860 * events through platform methods (like ACPI events). If @dev supports
1861 * platform wakeup events, set the device flag to indicate as much. This
1862 * may be redundant if the device also supports PCI PM caps, but double
1863 * initialization should be safe in that case.
1865 void platform_pci_wakeup_init(struct pci_dev *dev)
1867 if (!platform_pci_can_wakeup(dev))
1870 device_set_wakeup_capable(&dev->dev, true);
1871 platform_pci_sleep_wake(dev, false);
1875 * pci_add_save_buffer - allocate buffer for saving given capability registers
1876 * @dev: the PCI device
1877 * @cap: the capability to allocate the buffer for
1878 * @size: requested size of the buffer
1880 static int pci_add_cap_save_buffer(
1881 struct pci_dev *dev, char cap, unsigned int size)
1884 struct pci_cap_saved_state *save_state;
1886 pos = pci_find_capability(dev, cap);
1890 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1894 save_state->cap.cap_nr = cap;
1895 save_state->cap.size = size;
1896 pci_add_saved_cap(dev, save_state);
1902 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1903 * @dev: the PCI device
1905 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1909 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1910 PCI_EXP_SAVE_REGS * sizeof(u16));
1913 "unable to preallocate PCI Express save buffer\n");
1915 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1918 "unable to preallocate PCI-X save buffer\n");
1922 * pci_enable_ari - enable ARI forwarding if hardware support it
1923 * @dev: the PCI device
1925 void pci_enable_ari(struct pci_dev *dev)
1930 struct pci_dev *bridge;
1932 if (!pci_is_pcie(dev) || dev->devfn)
1935 bridge = dev->bus->self;
1936 if (!bridge || !pci_is_pcie(bridge))
1939 pos = pci_pcie_cap(bridge);
1943 /* ARI is a PCIe v2 feature */
1944 pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
1945 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
1948 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1949 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1952 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1953 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
1954 ctrl |= PCI_EXP_DEVCTL2_ARI;
1955 bridge->ari_enabled = 1;
1957 ctrl &= ~PCI_EXP_DEVCTL2_ARI;
1958 bridge->ari_enabled = 0;
1960 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1964 * pci_enable_ido - enable ID-based ordering on a device
1965 * @dev: the PCI device
1966 * @type: which types of IDO to enable
1968 * Enable ID-based ordering on @dev. @type can contain the bits
1969 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
1970 * which types of transactions are allowed to be re-ordered.
1972 void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1977 pos = pci_pcie_cap(dev);
1981 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1982 if (type & PCI_EXP_IDO_REQUEST)
1983 ctrl |= PCI_EXP_IDO_REQ_EN;
1984 if (type & PCI_EXP_IDO_COMPLETION)
1985 ctrl |= PCI_EXP_IDO_CMP_EN;
1986 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1988 EXPORT_SYMBOL(pci_enable_ido);
1991 * pci_disable_ido - disable ID-based ordering on a device
1992 * @dev: the PCI device
1993 * @type: which types of IDO to disable
1995 void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2000 if (!pci_is_pcie(dev))
2003 pos = pci_pcie_cap(dev);
2007 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2008 if (type & PCI_EXP_IDO_REQUEST)
2009 ctrl &= ~PCI_EXP_IDO_REQ_EN;
2010 if (type & PCI_EXP_IDO_COMPLETION)
2011 ctrl &= ~PCI_EXP_IDO_CMP_EN;
2012 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2014 EXPORT_SYMBOL(pci_disable_ido);
2017 * pci_enable_obff - enable optimized buffer flush/fill
2019 * @type: type of signaling to use
2021 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2022 * signaling if possible, falling back to message signaling only if
2023 * WAKE# isn't supported. @type should indicate whether the PCIe link
2024 * be brought out of L0s or L1 to send the message. It should be either
2025 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2027 * If your device can benefit from receiving all messages, even at the
2028 * power cost of bringing the link back up from a low power state, use
2029 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2033 * Zero on success, appropriate error number on failure.
2035 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2042 if (!pci_is_pcie(dev))
2045 pos = pci_pcie_cap(dev);
2049 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2050 if (!(cap & PCI_EXP_OBFF_MASK))
2051 return -ENOTSUPP; /* no OBFF support at all */
2053 /* Make sure the topology supports OBFF as well */
2055 ret = pci_enable_obff(dev->bus->self, type);
2060 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2061 if (cap & PCI_EXP_OBFF_WAKE)
2062 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2065 case PCI_EXP_OBFF_SIGNAL_L0:
2066 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2067 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2069 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2070 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2071 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2074 WARN(1, "bad OBFF signal type\n");
2078 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2082 EXPORT_SYMBOL(pci_enable_obff);
2085 * pci_disable_obff - disable optimized buffer flush/fill
2088 * Disable OBFF on @dev.
2090 void pci_disable_obff(struct pci_dev *dev)
2095 if (!pci_is_pcie(dev))
2098 pos = pci_pcie_cap(dev);
2102 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2103 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2104 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2106 EXPORT_SYMBOL(pci_disable_obff);
2109 * pci_ltr_supported - check whether a device supports LTR
2113 * True if @dev supports latency tolerance reporting, false otherwise.
2115 bool pci_ltr_supported(struct pci_dev *dev)
2120 if (!pci_is_pcie(dev))
2123 pos = pci_pcie_cap(dev);
2127 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2129 return cap & PCI_EXP_DEVCAP2_LTR;
2131 EXPORT_SYMBOL(pci_ltr_supported);
2134 * pci_enable_ltr - enable latency tolerance reporting
2137 * Enable LTR on @dev if possible, which means enabling it first on
2141 * Zero on success, errno on failure.
2143 int pci_enable_ltr(struct pci_dev *dev)
2149 if (!pci_ltr_supported(dev))
2152 pos = pci_pcie_cap(dev);
2156 /* Only primary function can enable/disable LTR */
2157 if (PCI_FUNC(dev->devfn) != 0)
2160 /* Enable upstream ports first */
2162 ret = pci_enable_ltr(dev->bus->self);
2167 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2168 ctrl |= PCI_EXP_LTR_EN;
2169 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2173 EXPORT_SYMBOL(pci_enable_ltr);
2176 * pci_disable_ltr - disable latency tolerance reporting
2179 void pci_disable_ltr(struct pci_dev *dev)
2184 if (!pci_ltr_supported(dev))
2187 pos = pci_pcie_cap(dev);
2191 /* Only primary function can enable/disable LTR */
2192 if (PCI_FUNC(dev->devfn) != 0)
2195 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2196 ctrl &= ~PCI_EXP_LTR_EN;
2197 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2199 EXPORT_SYMBOL(pci_disable_ltr);
2201 static int __pci_ltr_scale(int *val)
2205 while (*val > 1023) {
2206 *val = (*val + 31) / 32;
2213 * pci_set_ltr - set LTR latency values
2215 * @snoop_lat_ns: snoop latency in nanoseconds
2216 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2218 * Figure out the scale and set the LTR values accordingly.
2220 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2222 int pos, ret, snoop_scale, nosnoop_scale;
2225 if (!pci_ltr_supported(dev))
2228 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2229 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2231 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2232 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2235 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2236 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2239 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2243 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2244 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2248 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2249 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2255 EXPORT_SYMBOL(pci_set_ltr);
2257 static int pci_acs_enable;
2260 * pci_request_acs - ask for ACS to be enabled if supported
2262 void pci_request_acs(void)
2268 * pci_enable_acs - enable ACS if hardware support it
2269 * @dev: the PCI device
2271 void pci_enable_acs(struct pci_dev *dev)
2277 if (!pci_acs_enable)
2280 if (!pci_is_pcie(dev))
2283 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2287 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2288 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2290 /* Source Validation */
2291 ctrl |= (cap & PCI_ACS_SV);
2293 /* P2P Request Redirect */
2294 ctrl |= (cap & PCI_ACS_RR);
2296 /* P2P Completion Redirect */
2297 ctrl |= (cap & PCI_ACS_CR);
2299 /* Upstream Forwarding */
2300 ctrl |= (cap & PCI_ACS_UF);
2302 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2306 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2307 * @dev: the PCI device
2308 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2310 * Perform INTx swizzling for a device behind one level of bridge. This is
2311 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2312 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2313 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2314 * the PCI Express Base Specification, Revision 2.1)
2316 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
2320 if (pci_ari_enabled(dev->bus))
2323 slot = PCI_SLOT(dev->devfn);
2325 return (((pin - 1) + slot) % 4) + 1;
2329 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2337 while (!pci_is_root_bus(dev->bus)) {
2338 pin = pci_swizzle_interrupt_pin(dev, pin);
2339 dev = dev->bus->self;
2346 * pci_common_swizzle - swizzle INTx all the way to root bridge
2347 * @dev: the PCI device
2348 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2350 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2351 * bridges all the way up to a PCI root bus.
2353 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2357 while (!pci_is_root_bus(dev->bus)) {
2358 pin = pci_swizzle_interrupt_pin(dev, pin);
2359 dev = dev->bus->self;
2362 return PCI_SLOT(dev->devfn);
2366 * pci_release_region - Release a PCI bar
2367 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2368 * @bar: BAR to release
2370 * Releases the PCI I/O and memory resources previously reserved by a
2371 * successful call to pci_request_region. Call this function only
2372 * after all use of the PCI regions has ceased.
2374 void pci_release_region(struct pci_dev *pdev, int bar)
2376 struct pci_devres *dr;
2378 if (pci_resource_len(pdev, bar) == 0)
2380 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2381 release_region(pci_resource_start(pdev, bar),
2382 pci_resource_len(pdev, bar));
2383 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2384 release_mem_region(pci_resource_start(pdev, bar),
2385 pci_resource_len(pdev, bar));
2387 dr = find_pci_dr(pdev);
2389 dr->region_mask &= ~(1 << bar);
2393 * __pci_request_region - Reserved PCI I/O and memory resource
2394 * @pdev: PCI device whose resources are to be reserved
2395 * @bar: BAR to be reserved
2396 * @res_name: Name to be associated with resource.
2397 * @exclusive: whether the region access is exclusive or not
2399 * Mark the PCI region associated with PCI device @pdev BR @bar as
2400 * being reserved by owner @res_name. Do not access any
2401 * address inside the PCI regions unless this call returns
2404 * If @exclusive is set, then the region is marked so that userspace
2405 * is explicitly not allowed to map the resource via /dev/mem or
2406 * sysfs MMIO access.
2408 * Returns 0 on success, or %EBUSY on error. A warning
2409 * message is also printed on failure.
2411 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2414 struct pci_devres *dr;
2416 if (pci_resource_len(pdev, bar) == 0)
2419 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2420 if (!request_region(pci_resource_start(pdev, bar),
2421 pci_resource_len(pdev, bar), res_name))
2424 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2425 if (!__request_mem_region(pci_resource_start(pdev, bar),
2426 pci_resource_len(pdev, bar), res_name,
2431 dr = find_pci_dr(pdev);
2433 dr->region_mask |= 1 << bar;
2438 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2439 &pdev->resource[bar]);
2444 * pci_request_region - Reserve PCI I/O and memory resource
2445 * @pdev: PCI device whose resources are to be reserved
2446 * @bar: BAR to be reserved
2447 * @res_name: Name to be associated with resource
2449 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2450 * being reserved by owner @res_name. Do not access any
2451 * address inside the PCI regions unless this call returns
2454 * Returns 0 on success, or %EBUSY on error. A warning
2455 * message is also printed on failure.
2457 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2459 return __pci_request_region(pdev, bar, res_name, 0);
2463 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2464 * @pdev: PCI device whose resources are to be reserved
2465 * @bar: BAR to be reserved
2466 * @res_name: Name to be associated with resource.
2468 * Mark the PCI region associated with PCI device @pdev BR @bar as
2469 * being reserved by owner @res_name. Do not access any
2470 * address inside the PCI regions unless this call returns
2473 * Returns 0 on success, or %EBUSY on error. A warning
2474 * message is also printed on failure.
2476 * The key difference that _exclusive makes it that userspace is
2477 * explicitly not allowed to map the resource via /dev/mem or
2480 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2482 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2485 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2486 * @pdev: PCI device whose resources were previously reserved
2487 * @bars: Bitmask of BARs to be released
2489 * Release selected PCI I/O and memory resources previously reserved.
2490 * Call this function only after all use of the PCI regions has ceased.
2492 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2496 for (i = 0; i < 6; i++)
2497 if (bars & (1 << i))
2498 pci_release_region(pdev, i);
2501 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2502 const char *res_name, int excl)
2506 for (i = 0; i < 6; i++)
2507 if (bars & (1 << i))
2508 if (__pci_request_region(pdev, i, res_name, excl))
2514 if (bars & (1 << i))
2515 pci_release_region(pdev, i);
2522 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2523 * @pdev: PCI device whose resources are to be reserved
2524 * @bars: Bitmask of BARs to be requested
2525 * @res_name: Name to be associated with resource
2527 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2528 const char *res_name)
2530 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2533 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2534 int bars, const char *res_name)
2536 return __pci_request_selected_regions(pdev, bars, res_name,
2537 IORESOURCE_EXCLUSIVE);
2541 * pci_release_regions - Release reserved PCI I/O and memory resources
2542 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2544 * Releases all PCI I/O and memory resources previously reserved by a
2545 * successful call to pci_request_regions. Call this function only
2546 * after all use of the PCI regions has ceased.
2549 void pci_release_regions(struct pci_dev *pdev)
2551 pci_release_selected_regions(pdev, (1 << 6) - 1);
2555 * pci_request_regions - Reserved PCI I/O and memory resources
2556 * @pdev: PCI device whose resources are to be reserved
2557 * @res_name: Name to be associated with resource.
2559 * Mark all PCI regions associated with PCI device @pdev as
2560 * being reserved by owner @res_name. Do not access any
2561 * address inside the PCI regions unless this call returns
2564 * Returns 0 on success, or %EBUSY on error. A warning
2565 * message is also printed on failure.
2567 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2569 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2573 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2574 * @pdev: PCI device whose resources are to be reserved
2575 * @res_name: Name to be associated with resource.
2577 * Mark all PCI regions associated with PCI device @pdev as
2578 * being reserved by owner @res_name. Do not access any
2579 * address inside the PCI regions unless this call returns
2582 * pci_request_regions_exclusive() will mark the region so that
2583 * /dev/mem and the sysfs MMIO access will not be allowed.
2585 * Returns 0 on success, or %EBUSY on error. A warning
2586 * message is also printed on failure.
2588 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2590 return pci_request_selected_regions_exclusive(pdev,
2591 ((1 << 6) - 1), res_name);
2594 static void __pci_set_master(struct pci_dev *dev, bool enable)
2598 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2600 cmd = old_cmd | PCI_COMMAND_MASTER;
2602 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2603 if (cmd != old_cmd) {
2604 dev_dbg(&dev->dev, "%s bus mastering\n",
2605 enable ? "enabling" : "disabling");
2606 pci_write_config_word(dev, PCI_COMMAND, cmd);
2608 dev->is_busmaster = enable;
2612 * pci_set_master - enables bus-mastering for device dev
2613 * @dev: the PCI device to enable
2615 * Enables bus-mastering on the device and calls pcibios_set_master()
2616 * to do the needed arch specific settings.
2618 void pci_set_master(struct pci_dev *dev)
2620 __pci_set_master(dev, true);
2621 pcibios_set_master(dev);
2625 * pci_clear_master - disables bus-mastering for device dev
2626 * @dev: the PCI device to disable
2628 void pci_clear_master(struct pci_dev *dev)
2630 __pci_set_master(dev, false);
2634 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2635 * @dev: the PCI device for which MWI is to be enabled
2637 * Helper function for pci_set_mwi.
2638 * Originally copied from drivers/net/acenic.c.
2639 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2641 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2643 int pci_set_cacheline_size(struct pci_dev *dev)
2647 if (!pci_cache_line_size)
2650 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2651 equal to or multiple of the right value. */
2652 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2653 if (cacheline_size >= pci_cache_line_size &&
2654 (cacheline_size % pci_cache_line_size) == 0)
2657 /* Write the correct value. */
2658 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2660 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2661 if (cacheline_size == pci_cache_line_size)
2664 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2665 "supported\n", pci_cache_line_size << 2);
2669 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2671 #ifdef PCI_DISABLE_MWI
2672 int pci_set_mwi(struct pci_dev *dev)
2677 int pci_try_set_mwi(struct pci_dev *dev)
2682 void pci_clear_mwi(struct pci_dev *dev)
2689 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2690 * @dev: the PCI device for which MWI is enabled
2692 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2694 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2697 pci_set_mwi(struct pci_dev *dev)
2702 rc = pci_set_cacheline_size(dev);
2706 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2707 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2708 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2709 cmd |= PCI_COMMAND_INVALIDATE;
2710 pci_write_config_word(dev, PCI_COMMAND, cmd);
2717 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2718 * @dev: the PCI device for which MWI is enabled
2720 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2721 * Callers are not required to check the return value.
2723 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2725 int pci_try_set_mwi(struct pci_dev *dev)
2727 int rc = pci_set_mwi(dev);
2732 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2733 * @dev: the PCI device to disable
2735 * Disables PCI Memory-Write-Invalidate transaction on the device
2738 pci_clear_mwi(struct pci_dev *dev)
2742 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2743 if (cmd & PCI_COMMAND_INVALIDATE) {
2744 cmd &= ~PCI_COMMAND_INVALIDATE;
2745 pci_write_config_word(dev, PCI_COMMAND, cmd);
2748 #endif /* ! PCI_DISABLE_MWI */
2751 * pci_intx - enables/disables PCI INTx for device dev
2752 * @pdev: the PCI device to operate on
2753 * @enable: boolean: whether to enable or disable PCI INTx
2755 * Enables/disables PCI INTx for device dev
2758 pci_intx(struct pci_dev *pdev, int enable)
2760 u16 pci_command, new;
2762 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2765 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2767 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2770 if (new != pci_command) {
2771 struct pci_devres *dr;
2773 pci_write_config_word(pdev, PCI_COMMAND, new);
2775 dr = find_pci_dr(pdev);
2776 if (dr && !dr->restore_intx) {
2777 dr->restore_intx = 1;
2778 dr->orig_intx = !enable;
2784 * pci_msi_off - disables any msi or msix capabilities
2785 * @dev: the PCI device to operate on
2787 * If you want to use msi see pci_enable_msi and friends.
2788 * This is a lower level primitive that allows us to disable
2789 * msi operation at the device level.
2791 void pci_msi_off(struct pci_dev *dev)
2796 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2798 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2799 control &= ~PCI_MSI_FLAGS_ENABLE;
2800 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2802 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2804 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2805 control &= ~PCI_MSIX_FLAGS_ENABLE;
2806 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2809 EXPORT_SYMBOL_GPL(pci_msi_off);
2811 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2813 return dma_set_max_seg_size(&dev->dev, size);
2815 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2817 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2819 return dma_set_seg_boundary(&dev->dev, mask);
2821 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2823 static int pcie_flr(struct pci_dev *dev, int probe)
2828 u16 status, control;
2830 pos = pci_pcie_cap(dev);
2834 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2835 if (!(cap & PCI_EXP_DEVCAP_FLR))
2841 /* Wait for Transaction Pending bit clean */
2842 for (i = 0; i < 4; i++) {
2844 msleep((1 << (i - 1)) * 100);
2846 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2847 if (!(status & PCI_EXP_DEVSTA_TRPND))
2851 dev_err(&dev->dev, "transaction is not cleared; "
2852 "proceeding with reset anyway\n");
2855 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2856 control |= PCI_EXP_DEVCTL_BCR_FLR;
2857 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2864 static int pci_af_flr(struct pci_dev *dev, int probe)
2871 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2875 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2876 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2882 /* Wait for Transaction Pending bit clean */
2883 for (i = 0; i < 4; i++) {
2885 msleep((1 << (i - 1)) * 100);
2887 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2888 if (!(status & PCI_AF_STATUS_TP))
2892 dev_err(&dev->dev, "transaction is not cleared; "
2893 "proceeding with reset anyway\n");
2896 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2903 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
2904 * @dev: Device to reset.
2905 * @probe: If set, only check if the device can be reset this way.
2907 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
2908 * unset, it will be reinitialized internally when going from PCI_D3hot to
2909 * PCI_D0. If that's the case and the device is not in a low-power state
2910 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
2912 * NOTE: This causes the caller to sleep for twice the device power transition
2913 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
2914 * by devault (i.e. unless the @dev's d3_delay field has a different value).
2915 * Moreover, only devices in D0 can be reset by this function.
2917 static int pci_pm_reset(struct pci_dev *dev, int probe)
2924 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2925 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2931 if (dev->current_state != PCI_D0)
2934 csr &= ~PCI_PM_CTRL_STATE_MASK;
2936 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2937 pci_dev_d3_sleep(dev);
2939 csr &= ~PCI_PM_CTRL_STATE_MASK;
2941 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2942 pci_dev_d3_sleep(dev);
2947 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2950 struct pci_dev *pdev;
2952 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2955 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2962 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2963 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2964 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2967 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2968 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2974 static int pci_dev_reset(struct pci_dev *dev, int probe)
2981 pci_block_user_cfg_access(dev);
2982 /* block PM suspend, driver probe, etc. */
2983 device_lock(&dev->dev);
2986 rc = pci_dev_specific_reset(dev, probe);
2990 rc = pcie_flr(dev, probe);
2994 rc = pci_af_flr(dev, probe);
2998 rc = pci_pm_reset(dev, probe);
3002 rc = pci_parent_bus_reset(dev, probe);
3005 device_unlock(&dev->dev);
3006 pci_unblock_user_cfg_access(dev);
3013 * __pci_reset_function - reset a PCI device function
3014 * @dev: PCI device to reset
3016 * Some devices allow an individual function to be reset without affecting
3017 * other functions in the same device. The PCI device must be responsive
3018 * to PCI config space in order to use this function.
3020 * The device function is presumed to be unused when this function is called.
3021 * Resetting the device will make the contents of PCI configuration space
3022 * random, so any caller of this must be prepared to reinitialise the
3023 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3026 * Returns 0 if the device function was successfully reset or negative if the
3027 * device doesn't support resetting a single function.
3029 int __pci_reset_function(struct pci_dev *dev)
3031 return pci_dev_reset(dev, 0);
3033 EXPORT_SYMBOL_GPL(__pci_reset_function);
3036 * pci_probe_reset_function - check whether the device can be safely reset
3037 * @dev: PCI device to reset
3039 * Some devices allow an individual function to be reset without affecting
3040 * other functions in the same device. The PCI device must be responsive
3041 * to PCI config space in order to use this function.
3043 * Returns 0 if the device function can be reset or negative if the
3044 * device doesn't support resetting a single function.
3046 int pci_probe_reset_function(struct pci_dev *dev)
3048 return pci_dev_reset(dev, 1);
3052 * pci_reset_function - quiesce and reset a PCI device function
3053 * @dev: PCI device to reset
3055 * Some devices allow an individual function to be reset without affecting
3056 * other functions in the same device. The PCI device must be responsive
3057 * to PCI config space in order to use this function.
3059 * This function does not just reset the PCI portion of a device, but
3060 * clears all the state associated with the device. This function differs
3061 * from __pci_reset_function in that it saves and restores device state
3064 * Returns 0 if the device function was successfully reset or negative if the
3065 * device doesn't support resetting a single function.
3067 int pci_reset_function(struct pci_dev *dev)
3071 rc = pci_dev_reset(dev, 1);
3075 pci_save_state(dev);
3078 * both INTx and MSI are disabled after the Interrupt Disable bit
3079 * is set and the Bus Master bit is cleared.
3081 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3083 rc = pci_dev_reset(dev, 0);
3085 pci_restore_state(dev);
3089 EXPORT_SYMBOL_GPL(pci_reset_function);
3092 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3093 * @dev: PCI device to query
3095 * Returns mmrbc: maximum designed memory read count in bytes
3096 * or appropriate error value.
3098 int pcix_get_max_mmrbc(struct pci_dev *dev)
3103 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3107 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3110 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3112 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3115 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3116 * @dev: PCI device to query
3118 * Returns mmrbc: maximum memory read count in bytes
3119 * or appropriate error value.
3121 int pcix_get_mmrbc(struct pci_dev *dev)
3126 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3130 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3133 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3135 EXPORT_SYMBOL(pcix_get_mmrbc);
3138 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3139 * @dev: PCI device to query
3140 * @mmrbc: maximum memory read count in bytes
3141 * valid values are 512, 1024, 2048, 4096
3143 * If possible sets maximum memory read byte count, some bridges have erratas
3144 * that prevent this.
3146 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3152 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3155 v = ffs(mmrbc) - 10;
3157 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3161 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3164 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3167 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3170 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3172 if (v > o && dev->bus &&
3173 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3176 cmd &= ~PCI_X_CMD_MAX_READ;
3178 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3183 EXPORT_SYMBOL(pcix_set_mmrbc);
3186 * pcie_get_readrq - get PCI Express read request size
3187 * @dev: PCI device to query
3189 * Returns maximum memory read request in bytes
3190 * or appropriate error value.
3192 int pcie_get_readrq(struct pci_dev *dev)
3197 cap = pci_pcie_cap(dev);
3201 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3203 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3207 EXPORT_SYMBOL(pcie_get_readrq);
3210 * pcie_set_readrq - set PCI Express maximum memory read request
3211 * @dev: PCI device to query
3212 * @rq: maximum memory read count in bytes
3213 * valid values are 128, 256, 512, 1024, 2048, 4096
3215 * If possible sets maximum memory read request in bytes
3217 int pcie_set_readrq(struct pci_dev *dev, int rq)
3219 int cap, err = -EINVAL;
3222 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3225 cap = pci_pcie_cap(dev);
3229 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3233 * If using the "performance" PCIe config, we clamp the
3234 * read rq size to the max packet size to prevent the
3235 * host bridge generating requests larger than we can
3238 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3239 int mps = pcie_get_mps(dev);
3247 v = (ffs(rq) - 8) << 12;
3249 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
3250 ctl &= ~PCI_EXP_DEVCTL_READRQ;
3252 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3258 EXPORT_SYMBOL(pcie_set_readrq);
3261 * pcie_get_mps - get PCI Express maximum payload size
3262 * @dev: PCI device to query
3264 * Returns maximum payload size in bytes
3265 * or appropriate error value.
3267 int pcie_get_mps(struct pci_dev *dev)
3272 cap = pci_pcie_cap(dev);
3276 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3278 ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3284 * pcie_set_mps - set PCI Express maximum payload size
3285 * @dev: PCI device to query
3286 * @mps: maximum payload size in bytes
3287 * valid values are 128, 256, 512, 1024, 2048, 4096
3289 * If possible sets maximum payload size
3291 int pcie_set_mps(struct pci_dev *dev, int mps)
3293 int cap, err = -EINVAL;
3296 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3300 if (v > dev->pcie_mpss)
3304 cap = pci_pcie_cap(dev);
3308 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3312 if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
3313 ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
3315 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3322 * pci_select_bars - Make BAR mask from the type of resource
3323 * @dev: the PCI device for which BAR mask is made
3324 * @flags: resource type mask to be selected
3326 * This helper routine makes bar mask from the type of resource.
3328 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3331 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3332 if (pci_resource_flags(dev, i) & flags)
3338 * pci_resource_bar - get position of the BAR associated with a resource
3339 * @dev: the PCI device
3340 * @resno: the resource number
3341 * @type: the BAR type to be filled in
3343 * Returns BAR position in config space, or 0 if the BAR is invalid.
3345 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3349 if (resno < PCI_ROM_RESOURCE) {
3350 *type = pci_bar_unknown;
3351 return PCI_BASE_ADDRESS_0 + 4 * resno;
3352 } else if (resno == PCI_ROM_RESOURCE) {
3353 *type = pci_bar_mem32;
3354 return dev->rom_base_reg;
3355 } else if (resno < PCI_BRIDGE_RESOURCES) {
3356 /* device specific resource */
3357 reg = pci_iov_resource_bar(dev, resno, type);
3362 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
3366 /* Some architectures require additional programming to enable VGA */
3367 static arch_set_vga_state_t arch_set_vga_state;
3369 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3371 arch_set_vga_state = func; /* NULL disables */
3374 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3375 unsigned int command_bits, u32 flags)
3377 if (arch_set_vga_state)
3378 return arch_set_vga_state(dev, decode, command_bits,
3384 * pci_set_vga_state - set VGA decode state on device and parents if requested
3385 * @dev: the PCI device
3386 * @decode: true = enable decoding, false = disable decoding
3387 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3388 * @flags: traverse ancestors and change bridges
3389 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3391 int pci_set_vga_state(struct pci_dev *dev, bool decode,
3392 unsigned int command_bits, u32 flags)
3394 struct pci_bus *bus;
3395 struct pci_dev *bridge;
3399 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
3401 /* ARCH specific VGA enables */
3402 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
3406 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3407 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3409 cmd |= command_bits;
3411 cmd &= ~command_bits;
3412 pci_write_config_word(dev, PCI_COMMAND, cmd);
3415 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
3422 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3425 cmd |= PCI_BRIDGE_CTL_VGA;
3427 cmd &= ~PCI_BRIDGE_CTL_VGA;
3428 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3436 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3437 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
3438 static DEFINE_SPINLOCK(resource_alignment_lock);
3441 * pci_specified_resource_alignment - get resource alignment specified by user.
3442 * @dev: the PCI device to get
3444 * RETURNS: Resource alignment if it is specified.
3445 * Zero if it is not specified.
3447 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3449 int seg, bus, slot, func, align_order, count;
3450 resource_size_t align = 0;
3453 spin_lock(&resource_alignment_lock);
3454 p = resource_alignment_param;
3457 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3463 if (sscanf(p, "%x:%x:%x.%x%n",
3464 &seg, &bus, &slot, &func, &count) != 4) {
3466 if (sscanf(p, "%x:%x.%x%n",
3467 &bus, &slot, &func, &count) != 3) {
3468 /* Invalid format */
3469 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3475 if (seg == pci_domain_nr(dev->bus) &&
3476 bus == dev->bus->number &&
3477 slot == PCI_SLOT(dev->devfn) &&
3478 func == PCI_FUNC(dev->devfn)) {
3479 if (align_order == -1) {
3482 align = 1 << align_order;
3487 if (*p != ';' && *p != ',') {
3488 /* End of param or invalid format */
3493 spin_unlock(&resource_alignment_lock);
3498 * pci_is_reassigndev - check if specified PCI is target device to reassign
3499 * @dev: the PCI device to check
3501 * RETURNS: non-zero for PCI device is a target device to reassign,
3504 int pci_is_reassigndev(struct pci_dev *dev)
3506 return (pci_specified_resource_alignment(dev) != 0);
3509 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3511 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3512 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3513 spin_lock(&resource_alignment_lock);
3514 strncpy(resource_alignment_param, buf, count);
3515 resource_alignment_param[count] = '\0';
3516 spin_unlock(&resource_alignment_lock);
3520 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3523 spin_lock(&resource_alignment_lock);
3524 count = snprintf(buf, size, "%s", resource_alignment_param);
3525 spin_unlock(&resource_alignment_lock);
3529 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3531 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3534 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3535 const char *buf, size_t count)
3537 return pci_set_resource_alignment_param(buf, count);
3540 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3541 pci_resource_alignment_store);
3543 static int __init pci_resource_alignment_sysfs_init(void)
3545 return bus_create_file(&pci_bus_type,
3546 &bus_attr_resource_alignment);
3549 late_initcall(pci_resource_alignment_sysfs_init);
3551 static void __devinit pci_no_domains(void)
3553 #ifdef CONFIG_PCI_DOMAINS
3554 pci_domains_supported = 0;
3559 * pci_ext_cfg_enabled - can we access extended PCI config space?
3560 * @dev: The PCI device of the root bridge.
3562 * Returns 1 if we can access PCI extended config space (offsets
3563 * greater than 0xff). This is the default implementation. Architecture
3564 * implementations can override this.
3566 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
3571 void __weak pci_fixup_cardbus(struct pci_bus *bus)
3574 EXPORT_SYMBOL(pci_fixup_cardbus);
3576 static int __init pci_setup(char *str)
3579 char *k = strchr(str, ',');
3582 if (*str && (str = pcibios_setup(str)) && *str) {
3583 if (!strcmp(str, "nomsi")) {
3585 } else if (!strcmp(str, "noaer")) {
3587 } else if (!strncmp(str, "realloc", 7)) {
3589 } else if (!strcmp(str, "nodomains")) {
3591 } else if (!strncmp(str, "cbiosize=", 9)) {
3592 pci_cardbus_io_size = memparse(str + 9, &str);
3593 } else if (!strncmp(str, "cbmemsize=", 10)) {
3594 pci_cardbus_mem_size = memparse(str + 10, &str);
3595 } else if (!strncmp(str, "resource_alignment=", 19)) {
3596 pci_set_resource_alignment_param(str + 19,
3598 } else if (!strncmp(str, "ecrc=", 5)) {
3599 pcie_ecrc_get_policy(str + 5);
3600 } else if (!strncmp(str, "hpiosize=", 9)) {
3601 pci_hotplug_io_size = memparse(str + 9, &str);
3602 } else if (!strncmp(str, "hpmemsize=", 10)) {
3603 pci_hotplug_mem_size = memparse(str + 10, &str);
3604 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
3605 pcie_bus_config = PCIE_BUS_TUNE_OFF;
3606 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
3607 pcie_bus_config = PCIE_BUS_SAFE;
3608 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
3609 pcie_bus_config = PCIE_BUS_PERFORMANCE;
3610 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
3611 pcie_bus_config = PCIE_BUS_PEER2PEER;
3613 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3621 early_param("pci", pci_setup);
3623 EXPORT_SYMBOL(pci_reenable_device);
3624 EXPORT_SYMBOL(pci_enable_device_io);
3625 EXPORT_SYMBOL(pci_enable_device_mem);
3626 EXPORT_SYMBOL(pci_enable_device);
3627 EXPORT_SYMBOL(pcim_enable_device);
3628 EXPORT_SYMBOL(pcim_pin_device);
3629 EXPORT_SYMBOL(pci_disable_device);
3630 EXPORT_SYMBOL(pci_find_capability);
3631 EXPORT_SYMBOL(pci_bus_find_capability);
3632 EXPORT_SYMBOL(pci_release_regions);
3633 EXPORT_SYMBOL(pci_request_regions);
3634 EXPORT_SYMBOL(pci_request_regions_exclusive);
3635 EXPORT_SYMBOL(pci_release_region);
3636 EXPORT_SYMBOL(pci_request_region);
3637 EXPORT_SYMBOL(pci_request_region_exclusive);
3638 EXPORT_SYMBOL(pci_release_selected_regions);
3639 EXPORT_SYMBOL(pci_request_selected_regions);
3640 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3641 EXPORT_SYMBOL(pci_set_master);
3642 EXPORT_SYMBOL(pci_clear_master);
3643 EXPORT_SYMBOL(pci_set_mwi);
3644 EXPORT_SYMBOL(pci_try_set_mwi);
3645 EXPORT_SYMBOL(pci_clear_mwi);
3646 EXPORT_SYMBOL_GPL(pci_intx);
3647 EXPORT_SYMBOL(pci_assign_resource);
3648 EXPORT_SYMBOL(pci_find_parent_resource);
3649 EXPORT_SYMBOL(pci_select_bars);
3651 EXPORT_SYMBOL(pci_set_power_state);
3652 EXPORT_SYMBOL(pci_save_state);
3653 EXPORT_SYMBOL(pci_restore_state);
3654 EXPORT_SYMBOL(pci_pme_capable);
3655 EXPORT_SYMBOL(pci_pme_active);
3656 EXPORT_SYMBOL(pci_wake_from_d3);
3657 EXPORT_SYMBOL(pci_target_state);
3658 EXPORT_SYMBOL(pci_prepare_to_sleep);
3659 EXPORT_SYMBOL(pci_back_from_sleep);
3660 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);