drivers/pci/intr_remapping.c

   1 #include <linux/interrupt.h>
   2 #include <linux/dmar.h>
   3 #include <linux/spinlock.h>
   4 #include <linux/jiffies.h>
   5 #include <linux/pci.h>
   6 #include <linux/irq.h>
   7 #include <asm/io_apic.h>
   8 #include <asm/smp.h>
   9 #include <asm/cpu.h>
  10 #include <linux/intel-iommu.h>
  11 #include "intr_remapping.h"
  12
  13 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
  14 static int ir_ioapic_num;
  15 int intr_remapping_enabled;
  16
  17 struct irq_2_iommu {
  18         struct intel_iommu *iommu;
  19         u16 irte_index;
  20         u16 sub_handle;
  21         u8  irte_mask;
  22 };
  23
  24 #ifdef CONFIG_GENERIC_HARDIRQS
  25 static struct irq_2_iommu *get_one_free_irq_2_iommu(int cpu)
  26 {
  27         struct irq_2_iommu *iommu;
  28         int node;
  29
  30         node = cpu_to_node(cpu);
  31
  32         iommu = kzalloc_node(sizeof(*iommu), GFP_ATOMIC, node);
  33         printk(KERN_DEBUG "alloc irq_2_iommu on cpu %d node %d\n", cpu, node);
  34
  35         return iommu;
  36 }
  37
  38 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  39 {
  40         struct irq_desc *desc;
  41
  42         desc = irq_to_desc(irq);
  43
  44         if (WARN_ON_ONCE(!desc))
  45                 return NULL;
  46
  47         return desc->irq_2_iommu;
  48 }
  49
  50 static struct irq_2_iommu *irq_2_iommu_alloc_cpu(unsigned int irq, int cpu)
  51 {
  52         struct irq_desc *desc;
  53         struct irq_2_iommu *irq_iommu;
  54
  55         /*
  56          * alloc irq desc if not allocated already.
  57          */
  58         desc = irq_to_desc_alloc_cpu(irq, cpu);
  59         if (!desc) {
  60                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
  61                 return NULL;
  62         }
  63
  64         irq_iommu = desc->irq_2_iommu;
  65
  66         if (!irq_iommu)
  67                 desc->irq_2_iommu = get_one_free_irq_2_iommu(cpu);
  68
  69         return desc->irq_2_iommu;
  70 }
  71
  72 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
  73 {
  74         return irq_2_iommu_alloc_cpu(irq, boot_cpu_id);
  75 }
  76
  77 #else /* !CONFIG_SPARSE_IRQ */
  78
  79 static struct irq_2_iommu irq_2_iommuX[NR_IRQS];
  80
  81 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
  82 {
  83         if (irq < nr_irqs)
  84                 return &irq_2_iommuX[irq];
  85
  86         return NULL;
  87 }
  88 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
  89 {
  90         return irq_2_iommu(irq);
  91 }
  92 #endif
  93
  94 static DEFINE_SPINLOCK(irq_2_ir_lock);
  95
  96 static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
  97 {
  98         struct irq_2_iommu *irq_iommu;
  99
 100         irq_iommu = irq_2_iommu(irq);
 101
 102         if (!irq_iommu)
 103                 return NULL;
 104
 105         if (!irq_iommu->iommu)
 106                 return NULL;
 107
 108         return irq_iommu;
 109 }
 110
 111 int irq_remapped(int irq)
 112 {
 113         return valid_irq_2_iommu(irq) != NULL;
 114 }
 115
 116 int get_irte(int irq, struct irte *entry)
 117 {
 118         int index;
 119         struct irq_2_iommu *irq_iommu;
 120         unsigned long flags;
 121
 122         if (!entry)
 123                 return -1;
 124
 125         spin_lock_irqsave(&irq_2_ir_lock, flags);
 126         irq_iommu = valid_irq_2_iommu(irq);
 127         if (!irq_iommu) {
 128                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 129                 return -1;
 130         }
 131
 132         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 133         *entry = *(irq_iommu->iommu->ir_table->base + index);
 134
 135         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 136         return 0;
 137 }
 138
 139 int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
 140 {
 141         struct ir_table *table = iommu->ir_table;
 142         struct irq_2_iommu *irq_iommu;
 143         u16 index, start_index;
 144         unsigned int mask = 0;
 145         unsigned long flags;
 146         int i;
 147
 148         if (!count)
 149                 return -1;
 150
 151 #ifndef CONFIG_SPARSE_IRQ
 152         /* protect irq_2_iommu_alloc later */
 153         if (irq >= nr_irqs)
 154                 return -1;
 155 #endif
 156
 157         /*
 158          * start the IRTE search from index 0.
 159          */
 160         index = start_index = 0;
 161
 162         if (count > 1) {
 163                 count = __roundup_pow_of_two(count);
 164                 mask = ilog2(count);
 165         }
 166
 167         if (mask > ecap_max_handle_mask(iommu->ecap)) {
 168                 printk(KERN_ERR
 169                        "Requested mask %x exceeds the max invalidation handle"
 170                        " mask value %Lx\n", mask,
 171                        ecap_max_handle_mask(iommu->ecap));
 172                 return -1;
 173         }
 174
 175         spin_lock_irqsave(&irq_2_ir_lock, flags);
 176         do {
 177                 for (i = index; i < index + count; i++)
 178                         if  (table->base[i].present)
 179                                 break;
 180                 /* empty index found */
 181                 if (i == index + count)
 182                         break;
 183
 184                 index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
 185
 186                 if (index == start_index) {
 187                         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 188                         printk(KERN_ERR "can't allocate an IRTE\n");
 189                         return -1;
 190                 }
 191         } while (1);
 192
 193         for (i = index; i < index + count; i++)
 194                 table->base[i].present = 1;
 195
 196         irq_iommu = irq_2_iommu_alloc(irq);
 197         if (!irq_iommu) {
 198                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 199                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
 200                 return -1;
 201         }
 202
 203         irq_iommu->iommu = iommu;
 204         irq_iommu->irte_index =  index;
 205         irq_iommu->sub_handle = 0;
 206         irq_iommu->irte_mask = mask;
 207
 208         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 209
 210         return index;
 211 }
 212
 213 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
 214 {
 215         struct qi_desc desc;
 216
 217         desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
 218                    | QI_IEC_SELECTIVE;
 219         desc.high = 0;
 220
 221         return qi_submit_sync(&desc, iommu);
 222 }
 223
 224 int map_irq_to_irte_handle(int irq, u16 *sub_handle)
 225 {
 226         int index;
 227         struct irq_2_iommu *irq_iommu;
 228         unsigned long flags;
 229
 230         spin_lock_irqsave(&irq_2_ir_lock, flags);
 231         irq_iommu = valid_irq_2_iommu(irq);
 232         if (!irq_iommu) {
 233                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 234                 return -1;
 235         }
 236
 237         *sub_handle = irq_iommu->sub_handle;
 238         index = irq_iommu->irte_index;
 239         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 240         return index;
 241 }
 242
 243 int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
 244 {
 245         struct irq_2_iommu *irq_iommu;
 246         unsigned long flags;
 247
 248         spin_lock_irqsave(&irq_2_ir_lock, flags);
 249
 250         irq_iommu = irq_2_iommu_alloc(irq);
 251
 252         if (!irq_iommu) {
 253                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 254                 printk(KERN_ERR "can't allocate irq_2_iommu\n");
 255                 return -1;
 256         }
 257
 258         irq_iommu->iommu = iommu;
 259         irq_iommu->irte_index = index;
 260         irq_iommu->sub_handle = subhandle;
 261         irq_iommu->irte_mask = 0;
 262
 263         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 264
 265         return 0;
 266 }
 267
 268 int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
 269 {
 270         struct irq_2_iommu *irq_iommu;
 271         unsigned long flags;
 272
 273         spin_lock_irqsave(&irq_2_ir_lock, flags);
 274         irq_iommu = valid_irq_2_iommu(irq);
 275         if (!irq_iommu) {
 276                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 277                 return -1;
 278         }
 279
 280         irq_iommu->iommu = NULL;
 281         irq_iommu->irte_index = 0;
 282         irq_iommu->sub_handle = 0;
 283         irq_2_iommu(irq)->irte_mask = 0;
 284
 285         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 286
 287         return 0;
 288 }
 289
 290 int modify_irte(int irq, struct irte *irte_modified)
 291 {
 292         int rc;
 293         int index;
 294         struct irte *irte;
 295         struct intel_iommu *iommu;
 296         struct irq_2_iommu *irq_iommu;
 297         unsigned long flags;
 298
 299         spin_lock_irqsave(&irq_2_ir_lock, flags);
 300         irq_iommu = valid_irq_2_iommu(irq);
 301         if (!irq_iommu) {
 302                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 303                 return -1;
 304         }
 305
 306         iommu = irq_iommu->iommu;
 307
 308         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 309         irte = &iommu->ir_table->base[index];
 310
 311         set_64bit((unsigned long *)irte, irte_modified->low);
 312         __iommu_flush_cache(iommu, irte, sizeof(*irte));
 313
 314         rc = qi_flush_iec(iommu, index, 0);
 315         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 316
 317         return rc;
 318 }
 319
 320 int flush_irte(int irq)
 321 {
 322         int rc;
 323         int index;
 324         struct intel_iommu *iommu;
 325         struct irq_2_iommu *irq_iommu;
 326         unsigned long flags;
 327
 328         spin_lock_irqsave(&irq_2_ir_lock, flags);
 329         irq_iommu = valid_irq_2_iommu(irq);
 330         if (!irq_iommu) {
 331                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 332                 return -1;
 333         }
 334
 335         iommu = irq_iommu->iommu;
 336
 337         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 338
 339         rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 340         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 341
 342         return rc;
 343 }
 344
 345 struct intel_iommu *map_ioapic_to_ir(int apic)
 346 {
 347         int i;
 348
 349         for (i = 0; i < MAX_IO_APICS; i++)
 350                 if (ir_ioapic[i].id == apic)
 351                         return ir_ioapic[i].iommu;
 352         return NULL;
 353 }
 354
 355 struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
 356 {
 357         struct dmar_drhd_unit *drhd;
 358
 359         drhd = dmar_find_matched_drhd_unit(dev);
 360         if (!drhd)
 361                 return NULL;
 362
 363         return drhd->iommu;
 364 }
 365
 366 int free_irte(int irq)
 367 {
 368         int rc = 0;
 369         int index, i;
 370         struct irte *irte;
 371         struct intel_iommu *iommu;
 372         struct irq_2_iommu *irq_iommu;
 373         unsigned long flags;
 374
 375         spin_lock_irqsave(&irq_2_ir_lock, flags);
 376         irq_iommu = valid_irq_2_iommu(irq);
 377         if (!irq_iommu) {
 378                 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 379                 return -1;
 380         }
 381
 382         iommu = irq_iommu->iommu;
 383
 384         index = irq_iommu->irte_index + irq_iommu->sub_handle;
 385         irte = &iommu->ir_table->base[index];
 386
 387         if (!irq_iommu->sub_handle) {
 388                 for (i = 0; i < (1 << irq_iommu->irte_mask); i++)
 389                         set_64bit((unsigned long *)(irte + i), 0);
 390                 rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
 391         }
 392
 393         irq_iommu->iommu = NULL;
 394         irq_iommu->irte_index = 0;
 395         irq_iommu->sub_handle = 0;
 396         irq_iommu->irte_mask = 0;
 397
 398         spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 399
 400         return rc;
 401 }
 402
 403 static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
 404 {
 405         u64 addr;
 406         u32 cmd, sts;
 407         unsigned long flags;
 408
 409         addr = virt_to_phys((void *)iommu->ir_table->base);
 410
 411         spin_lock_irqsave(&iommu->register_lock, flags);
 412
 413         dmar_writeq(iommu->reg + DMAR_IRTA_REG,
 414                     (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
 415
 416         /* Set interrupt-remapping table pointer */
 417         cmd = iommu->gcmd | DMA_GCMD_SIRTP;
 418         writel(cmd, iommu->reg + DMAR_GCMD_REG);
 419
 420         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 421                       readl, (sts & DMA_GSTS_IRTPS), sts);
 422         spin_unlock_irqrestore(&iommu->register_lock, flags);
 423
 424         /*
 425          * global invalidation of interrupt entry cache before enabling
 426          * interrupt-remapping.
 427          */
 428         qi_global_iec(iommu);
 429
 430         spin_lock_irqsave(&iommu->register_lock, flags);
 431
 432         /* Enable interrupt-remapping */
 433         cmd = iommu->gcmd | DMA_GCMD_IRE;
 434         iommu->gcmd |= DMA_GCMD_IRE;
 435         writel(cmd, iommu->reg + DMAR_GCMD_REG);
 436
 437         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 438                       readl, (sts & DMA_GSTS_IRES), sts);
 439
 440         spin_unlock_irqrestore(&iommu->register_lock, flags);
 441 }
 442
 443
 444 static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
 445 {
 446         struct ir_table *ir_table;
 447         struct page *pages;
 448
 449         ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
 450                                              GFP_ATOMIC);
 451
 452         if (!iommu->ir_table)
 453                 return -ENOMEM;
 454
 455         pages = alloc_pages(GFP_ATOMIC | __GFP_ZERO, INTR_REMAP_PAGE_ORDER);
 456
 457         if (!pages) {
 458                 printk(KERN_ERR "failed to allocate pages of order %d\n",
 459                        INTR_REMAP_PAGE_ORDER);
 460                 kfree(iommu->ir_table);
 461                 return -ENOMEM;
 462         }
 463
 464         ir_table->base = page_address(pages);
 465
 466         iommu_set_intr_remapping(iommu, mode);
 467         return 0;
 468 }
 469
 470 /*
 471  * Disable Interrupt Remapping.
 472  */
 473 static void disable_intr_remapping(struct intel_iommu *iommu)
 474 {
 475         unsigned long flags;
 476         u32 sts;
 477
 478         if (!ecap_ir_support(iommu->ecap))
 479                 return;
 480
 481         spin_lock_irqsave(&iommu->register_lock, flags);
 482
 483         sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
 484         if (!(sts & DMA_GSTS_IRES))
 485                 goto end;
 486
 487         iommu->gcmd &= ~DMA_GCMD_IRE;
 488         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 489
 490         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 491                       readl, !(sts & DMA_GSTS_IRES), sts);
 492
 493 end:
 494         spin_unlock_irqrestore(&iommu->register_lock, flags);
 495 }
 496
 497 int __init enable_intr_remapping(int eim)
 498 {
 499         struct dmar_drhd_unit *drhd;
 500         int setup = 0;
 501
 502         for_each_drhd_unit(drhd) {
 503                 struct intel_iommu *iommu = drhd->iommu;
 504
 505                 /*
 506                  * Clear previous faults.
 507                  */
 508                 dmar_fault(-1, iommu);
 509
 510                 /*
 511                  * Disable intr remapping and queued invalidation, if already
 512                  * enabled prior to OS handover.
 513                  */
 514                 disable_intr_remapping(iommu);
 515
 516                 dmar_disable_qi(iommu);
 517         }
 518
 519         /*
 520          * check for the Interrupt-remapping support
 521          */
 522         for_each_drhd_unit(drhd) {
 523                 struct intel_iommu *iommu = drhd->iommu;
 524
 525                 if (!ecap_ir_support(iommu->ecap))
 526                         continue;
 527
 528                 if (eim && !ecap_eim_support(iommu->ecap)) {
 529                         printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
 530                                " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
 531                         return -1;
 532                 }
 533         }
 534
 535         /*
 536          * Enable queued invalidation for all the DRHD's.
 537          */
 538         for_each_drhd_unit(drhd) {
 539                 int ret;
 540                 struct intel_iommu *iommu = drhd->iommu;
 541                 ret = dmar_enable_qi(iommu);
 542
 543                 if (ret) {
 544                         printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
 545                                " invalidation, ecap %Lx, ret %d\n",
 546                                drhd->reg_base_addr, iommu->ecap, ret);
 547                         return -1;
 548                 }
 549         }
 550
 551         /*
 552          * Setup Interrupt-remapping for all the DRHD's now.
 553          */
 554         for_each_drhd_unit(drhd) {
 555                 struct intel_iommu *iommu = drhd->iommu;
 556
 557                 if (!ecap_ir_support(iommu->ecap))
 558                         continue;
 559
 560                 if (setup_intr_remapping(iommu, eim))
 561                         goto error;
 562
 563                 setup = 1;
 564         }
 565
 566         if (!setup)
 567                 goto error;
 568
 569         intr_remapping_enabled = 1;
 570
 571         return 0;
 572
 573 error:
 574         /*
 575          * handle error condition gracefully here!
 576          */
 577         return -1;
 578 }
 579
 580 static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
 581                                  struct intel_iommu *iommu)
 582 {
 583         struct acpi_dmar_hardware_unit *drhd;
 584         struct acpi_dmar_device_scope *scope;
 585         void *start, *end;
 586
 587         drhd = (struct acpi_dmar_hardware_unit *)header;
 588
 589         start = (void *)(drhd + 1);
 590         end = ((void *)drhd) + header->length;
 591
 592         while (start < end) {
 593                 scope = start;
 594                 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
 595                         if (ir_ioapic_num == MAX_IO_APICS) {
 596                                 printk(KERN_WARNING "Exceeded Max IO APICS\n");
 597                                 return -1;
 598                         }
 599
 600                         printk(KERN_INFO "IOAPIC id %d under DRHD base"
 601                                " 0x%Lx\n", scope->enumeration_id,
 602                                drhd->address);
 603
 604                         ir_ioapic[ir_ioapic_num].iommu = iommu;
 605                         ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
 606                         ir_ioapic_num++;
 607                 }
 608                 start += scope->length;
 609         }
 610
 611         return 0;
 612 }
 613
 614 /*
 615  * Finds the assocaition between IOAPIC's and its Interrupt-remapping
 616  * hardware unit.
 617  */
 618 int __init parse_ioapics_under_ir(void)
 619 {
 620         struct dmar_drhd_unit *drhd;
 621         int ir_supported = 0;
 622
 623         for_each_drhd_unit(drhd) {
 624                 struct intel_iommu *iommu = drhd->iommu;
 625
 626                 if (ecap_ir_support(iommu->ecap)) {
 627                         if (ir_parse_ioapic_scope(drhd->hdr, iommu))
 628                                 return -1;
 629
 630                         ir_supported = 1;
 631                 }
 632         }
 633
 634         if (ir_supported && ir_ioapic_num != nr_ioapics) {
 635                 printk(KERN_WARNING
 636                        "Not all IO-APIC's listed under remapping hardware\n");
 637                 return -1;
 638         }
 639
 640         return ir_supported;
 641 }