drivers/pci/intel-iommu.c

   1 /*
   2  * Copyright (c) 2006, Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  15  * Place - Suite 330, Boston, MA 02111-1307 USA.
  16  *
  17  * Copyright (C) 2006-2008 Intel Corporation
  18  * Author: Ashok Raj <ashok.raj@intel.com>
  19  * Author: Shaohua Li <shaohua.li@intel.com>
  20  * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
  21  * Author: Fenghua Yu <fenghua.yu@intel.com>
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/bitmap.h>
  26 #include <linux/debugfs.h>
  27 #include <linux/slab.h>
  28 #include <linux/irq.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/pci.h>
  32 #include <linux/dmar.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/mempool.h>
  35 #include <linux/timer.h>
  36 #include <linux/iova.h>
  37 #include <linux/iommu.h>
  38 #include <linux/intel-iommu.h>
  39 #include <linux/sysdev.h>
  40 #include <asm/cacheflush.h>
  41 #include <asm/iommu.h>
  42 #include "pci.h"
  43
  44 #define ROOT_SIZE               VTD_PAGE_SIZE
  45 #define CONTEXT_SIZE            VTD_PAGE_SIZE
  46
  47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
  48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
  49
  50 #define IOAPIC_RANGE_START      (0xfee00000)
  51 #define IOAPIC_RANGE_END        (0xfeefffff)
  52 #define IOVA_START_ADDR         (0x1000)
  53
  54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
  55
  56 #define MAX_AGAW_WIDTH 64
  57
  58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
  59 #define DOMAIN_MAX_PFN(gaw)  ((((u64)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
  60
  61 #define IOVA_PFN(addr)          ((addr) >> PAGE_SHIFT)
  62 #define DMA_32BIT_PFN           IOVA_PFN(DMA_BIT_MASK(32))
  63 #define DMA_64BIT_PFN           IOVA_PFN(DMA_BIT_MASK(64))
  64
  65
  66 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
  67    are never going to work. */
  68 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
  69 {
  70         return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
  71 }
  72
  73 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
  74 {
  75         return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
  76 }
  77 static inline unsigned long page_to_dma_pfn(struct page *pg)
  78 {
  79         return mm_to_dma_pfn(page_to_pfn(pg));
  80 }
  81 static inline unsigned long virt_to_dma_pfn(void *p)
  82 {
  83         return page_to_dma_pfn(virt_to_page(p));
  84 }
  85
  86 /* global iommu list, set NULL for ignored DMAR units */
  87 static struct intel_iommu **g_iommus;
  88
  89 static int rwbf_quirk;
  90
  91 /*
  92  * 0: Present
  93  * 1-11: Reserved
  94  * 12-63: Context Ptr (12 - (haw-1))
  95  * 64-127: Reserved
  96  */
  97 struct root_entry {
  98         u64     val;
  99         u64     rsvd1;
 100 };
 101 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
 102 static inline bool root_present(struct root_entry *root)
 103 {
 104         return (root->val & 1);
 105 }
 106 static inline void set_root_present(struct root_entry *root)
 107 {
 108         root->val |= 1;
 109 }
 110 static inline void set_root_value(struct root_entry *root, unsigned long value)
 111 {
 112         root->val |= value & VTD_PAGE_MASK;
 113 }
 114
 115 static inline struct context_entry *
 116 get_context_addr_from_root(struct root_entry *root)
 117 {
 118         return (struct context_entry *)
 119                 (root_present(root)?phys_to_virt(
 120                 root->val & VTD_PAGE_MASK) :
 121                 NULL);
 122 }
 123
 124 /*
 125  * low 64 bits:
 126  * 0: present
 127  * 1: fault processing disable
 128  * 2-3: translation type
 129  * 12-63: address space root
 130  * high 64 bits:
 131  * 0-2: address width
 132  * 3-6: aval
 133  * 8-23: domain id
 134  */
 135 struct context_entry {
 136         u64 lo;
 137         u64 hi;
 138 };
 139
 140 static inline bool context_present(struct context_entry *context)
 141 {
 142         return (context->lo & 1);
 143 }
 144 static inline void context_set_present(struct context_entry *context)
 145 {
 146         context->lo |= 1;
 147 }
 148
 149 static inline void context_set_fault_enable(struct context_entry *context)
 150 {
 151         context->lo &= (((u64)-1) << 2) | 1;
 152 }
 153
 154 static inline void context_set_translation_type(struct context_entry *context,
 155                                                 unsigned long value)
 156 {
 157         context->lo &= (((u64)-1) << 4) | 3;
 158         context->lo |= (value & 3) << 2;
 159 }
 160
 161 static inline void context_set_address_root(struct context_entry *context,
 162                                             unsigned long value)
 163 {
 164         context->lo |= value & VTD_PAGE_MASK;
 165 }
 166
 167 static inline void context_set_address_width(struct context_entry *context,
 168                                              unsigned long value)
 169 {
 170         context->hi |= value & 7;
 171 }
 172
 173 static inline void context_set_domain_id(struct context_entry *context,
 174                                          unsigned long value)
 175 {
 176         context->hi |= (value & ((1 << 16) - 1)) << 8;
 177 }
 178
 179 static inline void context_clear_entry(struct context_entry *context)
 180 {
 181         context->lo = 0;
 182         context->hi = 0;
 183 }
 184
 185 /*
 186  * 0: readable
 187  * 1: writable
 188  * 2-6: reserved
 189  * 7: super page
 190  * 8-10: available
 191  * 11: snoop behavior
 192  * 12-63: Host physcial address
 193  */
 194 struct dma_pte {
 195         u64 val;
 196 };
 197
 198 static inline void dma_clear_pte(struct dma_pte *pte)
 199 {
 200         pte->val = 0;
 201 }
 202
 203 static inline void dma_set_pte_readable(struct dma_pte *pte)
 204 {
 205         pte->val |= DMA_PTE_READ;
 206 }
 207
 208 static inline void dma_set_pte_writable(struct dma_pte *pte)
 209 {
 210         pte->val |= DMA_PTE_WRITE;
 211 }
 212
 213 static inline void dma_set_pte_snp(struct dma_pte *pte)
 214 {
 215         pte->val |= DMA_PTE_SNP;
 216 }
 217
 218 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
 219 {
 220         pte->val = (pte->val & ~3) | (prot & 3);
 221 }
 222
 223 static inline u64 dma_pte_addr(struct dma_pte *pte)
 224 {
 225 #ifdef CONFIG_64BIT
 226         return pte->val & VTD_PAGE_MASK;
 227 #else
 228         /* Must have a full atomic 64-bit read */
 229         return  __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK;
 230 #endif
 231 }
 232
 233 static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
 234 {
 235         pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
 236 }
 237
 238 static inline bool dma_pte_present(struct dma_pte *pte)
 239 {
 240         return (pte->val & 3) != 0;
 241 }
 242
 243 static inline int first_pte_in_page(struct dma_pte *pte)
 244 {
 245         return !((unsigned long)pte & ~VTD_PAGE_MASK);
 246 }
 247
 248 /*
 249  * This domain is a statically identity mapping domain.
 250  *      1. This domain creats a static 1:1 mapping to all usable memory.
 251  *      2. It maps to each iommu if successful.
 252  *      3. Each iommu mapps to this domain if successful.
 253  */
 254 struct dmar_domain *si_domain;
 255
 256 /* devices under the same p2p bridge are owned in one domain */
 257 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
 258
 259 /* domain represents a virtual machine, more than one devices
 260  * across iommus may be owned in one domain, e.g. kvm guest.
 261  */
 262 #define DOMAIN_FLAG_VIRTUAL_MACHINE     (1 << 1)
 263
 264 /* si_domain contains mulitple devices */
 265 #define DOMAIN_FLAG_STATIC_IDENTITY     (1 << 2)
 266
 267 struct dmar_domain {
 268         int     id;                     /* domain id */
 269         unsigned long iommu_bmp;        /* bitmap of iommus this domain uses*/
 270
 271         struct list_head devices;       /* all devices' list */
 272         struct iova_domain iovad;       /* iova's that belong to this domain */
 273
 274         struct dma_pte  *pgd;           /* virtual address */
 275         int             gaw;            /* max guest address width */
 276
 277         /* adjusted guest address width, 0 is level 2 30-bit */
 278         int             agaw;
 279
 280         int             flags;          /* flags to find out type of domain */
 281
 282         int             iommu_coherency;/* indicate coherency of iommu access */
 283         int             iommu_snooping; /* indicate snooping control feature*/
 284         int             iommu_count;    /* reference count of iommu */
 285         spinlock_t      iommu_lock;     /* protect iommu set in domain */
 286         u64             max_addr;       /* maximum mapped address */
 287 };
 288
 289 /* PCI domain-device relationship */
 290 struct device_domain_info {
 291         struct list_head link;  /* link to domain siblings */
 292         struct list_head global; /* link to global list */
 293         int segment;            /* PCI domain */
 294         u8 bus;                 /* PCI bus number */
 295         u8 devfn;               /* PCI devfn number */
 296         struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
 297         struct intel_iommu *iommu; /* IOMMU used by this device */
 298         struct dmar_domain *domain; /* pointer to domain */
 299 };
 300
 301 static void flush_unmaps_timeout(unsigned long data);
 302
 303 DEFINE_TIMER(unmap_timer,  flush_unmaps_timeout, 0, 0);
 304
 305 #define HIGH_WATER_MARK 250
 306 struct deferred_flush_tables {
 307         int next;
 308         struct iova *iova[HIGH_WATER_MARK];
 309         struct dmar_domain *domain[HIGH_WATER_MARK];
 310 };
 311
 312 static struct deferred_flush_tables *deferred_flush;
 313
 314 /* bitmap for indexing intel_iommus */
 315 static int g_num_of_iommus;
 316
 317 static DEFINE_SPINLOCK(async_umap_flush_lock);
 318 static LIST_HEAD(unmaps_to_do);
 319
 320 static int timer_on;
 321 static long list_size;
 322
 323 static void domain_remove_dev_info(struct dmar_domain *domain);
 324
 325 #ifdef CONFIG_DMAR_DEFAULT_ON
 326 int dmar_disabled = 0;
 327 #else
 328 int dmar_disabled = 1;
 329 #endif /*CONFIG_DMAR_DEFAULT_ON*/
 330
 331 static int __initdata dmar_map_gfx = 1;
 332 static int dmar_forcedac;
 333 static int intel_iommu_strict;
 334
 335 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
 336 static DEFINE_SPINLOCK(device_domain_lock);
 337 static LIST_HEAD(device_domain_list);
 338
 339 static struct iommu_ops intel_iommu_ops;
 340
 341 static int __init intel_iommu_setup(char *str)
 342 {
 343         if (!str)
 344                 return -EINVAL;
 345         while (*str) {
 346                 if (!strncmp(str, "on", 2)) {
 347                         dmar_disabled = 0;
 348                         printk(KERN_INFO "Intel-IOMMU: enabled\n");
 349                 } else if (!strncmp(str, "off", 3)) {
 350                         dmar_disabled = 1;
 351                         printk(KERN_INFO "Intel-IOMMU: disabled\n");
 352                 } else if (!strncmp(str, "igfx_off", 8)) {
 353                         dmar_map_gfx = 0;
 354                         printk(KERN_INFO
 355                                 "Intel-IOMMU: disable GFX device mapping\n");
 356                 } else if (!strncmp(str, "forcedac", 8)) {
 357                         printk(KERN_INFO
 358                                 "Intel-IOMMU: Forcing DAC for PCI devices\n");
 359                         dmar_forcedac = 1;
 360                 } else if (!strncmp(str, "strict", 6)) {
 361                         printk(KERN_INFO
 362                                 "Intel-IOMMU: disable batched IOTLB flush\n");
 363                         intel_iommu_strict = 1;
 364                 }
 365
 366                 str += strcspn(str, ",");
 367                 while (*str == ',')
 368                         str++;
 369         }
 370         return 0;
 371 }
 372 __setup("intel_iommu=", intel_iommu_setup);
 373
 374 static struct kmem_cache *iommu_domain_cache;
 375 static struct kmem_cache *iommu_devinfo_cache;
 376 static struct kmem_cache *iommu_iova_cache;
 377
 378 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
 379 {
 380         unsigned int flags;
 381         void *vaddr;
 382
 383         /* trying to avoid low memory issues */
 384         flags = current->flags & PF_MEMALLOC;
 385         current->flags |= PF_MEMALLOC;
 386         vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
 387         current->flags &= (~PF_MEMALLOC | flags);
 388         return vaddr;
 389 }
 390
 391
 392 static inline void *alloc_pgtable_page(void)
 393 {
 394         unsigned int flags;
 395         void *vaddr;
 396
 397         /* trying to avoid low memory issues */
 398         flags = current->flags & PF_MEMALLOC;
 399         current->flags |= PF_MEMALLOC;
 400         vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
 401         current->flags &= (~PF_MEMALLOC | flags);
 402         return vaddr;
 403 }
 404
 405 static inline void free_pgtable_page(void *vaddr)
 406 {
 407         free_page((unsigned long)vaddr);
 408 }
 409
 410 static inline void *alloc_domain_mem(void)
 411 {
 412         return iommu_kmem_cache_alloc(iommu_domain_cache);
 413 }
 414
 415 static void free_domain_mem(void *vaddr)
 416 {
 417         kmem_cache_free(iommu_domain_cache, vaddr);
 418 }
 419
 420 static inline void * alloc_devinfo_mem(void)
 421 {
 422         return iommu_kmem_cache_alloc(iommu_devinfo_cache);
 423 }
 424
 425 static inline void free_devinfo_mem(void *vaddr)
 426 {
 427         kmem_cache_free(iommu_devinfo_cache, vaddr);
 428 }
 429
 430 struct iova *alloc_iova_mem(void)
 431 {
 432         return iommu_kmem_cache_alloc(iommu_iova_cache);
 433 }
 434
 435 void free_iova_mem(struct iova *iova)
 436 {
 437         kmem_cache_free(iommu_iova_cache, iova);
 438 }
 439
 440
 441 static inline int width_to_agaw(int width);
 442
 443 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
 444 {
 445         unsigned long sagaw;
 446         int agaw = -1;
 447
 448         sagaw = cap_sagaw(iommu->cap);
 449         for (agaw = width_to_agaw(max_gaw);
 450              agaw >= 0; agaw--) {
 451                 if (test_bit(agaw, &sagaw))
 452                         break;
 453         }
 454
 455         return agaw;
 456 }
 457
 458 /*
 459  * Calculate max SAGAW for each iommu.
 460  */
 461 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
 462 {
 463         return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
 464 }
 465
 466 /*
 467  * calculate agaw for each iommu.
 468  * "SAGAW" may be different across iommus, use a default agaw, and
 469  * get a supported less agaw for iommus that don't support the default agaw.
 470  */
 471 int iommu_calculate_agaw(struct intel_iommu *iommu)
 472 {
 473         return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
 474 }
 475
 476 /* This functionin only returns single iommu in a domain */
 477 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
 478 {
 479         int iommu_id;
 480
 481         /* si_domain and vm domain should not get here. */
 482         BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
 483         BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
 484
 485         iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
 486         if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
 487                 return NULL;
 488
 489         return g_iommus[iommu_id];
 490 }
 491
 492 static void domain_update_iommu_coherency(struct dmar_domain *domain)
 493 {
 494         int i;
 495
 496         domain->iommu_coherency = 1;
 497
 498         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
 499         for (; i < g_num_of_iommus; ) {
 500                 if (!ecap_coherent(g_iommus[i]->ecap)) {
 501                         domain->iommu_coherency = 0;
 502                         break;
 503                 }
 504                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
 505         }
 506 }
 507
 508 static void domain_update_iommu_snooping(struct dmar_domain *domain)
 509 {
 510         int i;
 511
 512         domain->iommu_snooping = 1;
 513
 514         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
 515         for (; i < g_num_of_iommus; ) {
 516                 if (!ecap_sc_support(g_iommus[i]->ecap)) {
 517                         domain->iommu_snooping = 0;
 518                         break;
 519                 }
 520                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
 521         }
 522 }
 523
 524 /* Some capabilities may be different across iommus */
 525 static void domain_update_iommu_cap(struct dmar_domain *domain)
 526 {
 527         domain_update_iommu_coherency(domain);
 528         domain_update_iommu_snooping(domain);
 529 }
 530
 531 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
 532 {
 533         struct dmar_drhd_unit *drhd = NULL;
 534         int i;
 535
 536         for_each_drhd_unit(drhd) {
 537                 if (drhd->ignored)
 538                         continue;
 539                 if (segment != drhd->segment)
 540                         continue;
 541
 542                 for (i = 0; i < drhd->devices_cnt; i++) {
 543                         if (drhd->devices[i] &&
 544                             drhd->devices[i]->bus->number == bus &&
 545                             drhd->devices[i]->devfn == devfn)
 546                                 return drhd->iommu;
 547                         if (drhd->devices[i] &&
 548                             drhd->devices[i]->subordinate &&
 549                             drhd->devices[i]->subordinate->number <= bus &&
 550                             drhd->devices[i]->subordinate->subordinate >= bus)
 551                                 return drhd->iommu;
 552                 }
 553
 554                 if (drhd->include_all)
 555                         return drhd->iommu;
 556         }
 557
 558         return NULL;
 559 }
 560
 561 static void domain_flush_cache(struct dmar_domain *domain,
 562                                void *addr, int size)
 563 {
 564         if (!domain->iommu_coherency)
 565                 clflush_cache_range(addr, size);
 566 }
 567
 568 /* Gets context entry for a given bus and devfn */
 569 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
 570                 u8 bus, u8 devfn)
 571 {
 572         struct root_entry *root;
 573         struct context_entry *context;
 574         unsigned long phy_addr;
 575         unsigned long flags;
 576
 577         spin_lock_irqsave(&iommu->lock, flags);
 578         root = &iommu->root_entry[bus];
 579         context = get_context_addr_from_root(root);
 580         if (!context) {
 581                 context = (struct context_entry *)alloc_pgtable_page();
 582                 if (!context) {
 583                         spin_unlock_irqrestore(&iommu->lock, flags);
 584                         return NULL;
 585                 }
 586                 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
 587                 phy_addr = virt_to_phys((void *)context);
 588                 set_root_value(root, phy_addr);
 589                 set_root_present(root);
 590                 __iommu_flush_cache(iommu, root, sizeof(*root));
 591         }
 592         spin_unlock_irqrestore(&iommu->lock, flags);
 593         return &context[devfn];
 594 }
 595
 596 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
 597 {
 598         struct root_entry *root;
 599         struct context_entry *context;
 600         int ret;
 601         unsigned long flags;
 602
 603         spin_lock_irqsave(&iommu->lock, flags);
 604         root = &iommu->root_entry[bus];
 605         context = get_context_addr_from_root(root);
 606         if (!context) {
 607                 ret = 0;
 608                 goto out;
 609         }
 610         ret = context_present(&context[devfn]);
 611 out:
 612         spin_unlock_irqrestore(&iommu->lock, flags);
 613         return ret;
 614 }
 615
 616 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
 617 {
 618         struct root_entry *root;
 619         struct context_entry *context;
 620         unsigned long flags;
 621
 622         spin_lock_irqsave(&iommu->lock, flags);
 623         root = &iommu->root_entry[bus];
 624         context = get_context_addr_from_root(root);
 625         if (context) {
 626                 context_clear_entry(&context[devfn]);
 627                 __iommu_flush_cache(iommu, &context[devfn], \
 628                         sizeof(*context));
 629         }
 630         spin_unlock_irqrestore(&iommu->lock, flags);
 631 }
 632
 633 static void free_context_table(struct intel_iommu *iommu)
 634 {
 635         struct root_entry *root;
 636         int i;
 637         unsigned long flags;
 638         struct context_entry *context;
 639
 640         spin_lock_irqsave(&iommu->lock, flags);
 641         if (!iommu->root_entry) {
 642                 goto out;
 643         }
 644         for (i = 0; i < ROOT_ENTRY_NR; i++) {
 645                 root = &iommu->root_entry[i];
 646                 context = get_context_addr_from_root(root);
 647                 if (context)
 648                         free_pgtable_page(context);
 649         }
 650         free_pgtable_page(iommu->root_entry);
 651         iommu->root_entry = NULL;
 652 out:
 653         spin_unlock_irqrestore(&iommu->lock, flags);
 654 }
 655
 656 /* page table handling */
 657 #define LEVEL_STRIDE            (9)
 658 #define LEVEL_MASK              (((u64)1 << LEVEL_STRIDE) - 1)
 659
 660 static inline int agaw_to_level(int agaw)
 661 {
 662         return agaw + 2;
 663 }
 664
 665 static inline int agaw_to_width(int agaw)
 666 {
 667         return 30 + agaw * LEVEL_STRIDE;
 668
 669 }
 670
 671 static inline int width_to_agaw(int width)
 672 {
 673         return (width - 30) / LEVEL_STRIDE;
 674 }
 675
 676 static inline unsigned int level_to_offset_bits(int level)
 677 {
 678         return (level - 1) * LEVEL_STRIDE;
 679 }
 680
 681 static inline int pfn_level_offset(unsigned long pfn, int level)
 682 {
 683         return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
 684 }
 685
 686 static inline unsigned long level_mask(int level)
 687 {
 688         return -1UL << level_to_offset_bits(level);
 689 }
 690
 691 static inline unsigned long level_size(int level)
 692 {
 693         return 1UL << level_to_offset_bits(level);
 694 }
 695
 696 static inline unsigned long align_to_level(unsigned long pfn, int level)
 697 {
 698         return (pfn + level_size(level) - 1) & level_mask(level);
 699 }
 700
 701 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
 702                                       unsigned long pfn)
 703 {
 704         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
 705         struct dma_pte *parent, *pte = NULL;
 706         int level = agaw_to_level(domain->agaw);
 707         int offset;
 708
 709         BUG_ON(!domain->pgd);
 710         BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
 711         parent = domain->pgd;
 712
 713         while (level > 0) {
 714                 void *tmp_page;
 715
 716                 offset = pfn_level_offset(pfn, level);
 717                 pte = &parent[offset];
 718                 if (level == 1)
 719                         break;
 720
 721                 if (!dma_pte_present(pte)) {
 722                         uint64_t pteval;
 723
 724                         tmp_page = alloc_pgtable_page();
 725
 726                         if (!tmp_page)
 727                                 return NULL;
 728
 729                         domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
 730                         pteval = (virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
 731                         if (cmpxchg64(&pte->val, 0ULL, pteval)) {
 732                                 /* Someone else set it while we were thinking; use theirs. */
 733                                 free_pgtable_page(tmp_page);
 734                         } else {
 735                                 dma_pte_addr(pte);
 736                                 domain_flush_cache(domain, pte, sizeof(*pte));
 737                         }
 738                 }
 739                 parent = phys_to_virt(dma_pte_addr(pte));
 740                 level--;
 741         }
 742
 743         return pte;
 744 }
 745
 746 /* return address's pte at specific level */
 747 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
 748                                          unsigned long pfn,
 749                                          int level)
 750 {
 751         struct dma_pte *parent, *pte = NULL;
 752         int total = agaw_to_level(domain->agaw);
 753         int offset;
 754
 755         parent = domain->pgd;
 756         while (level <= total) {
 757                 offset = pfn_level_offset(pfn, total);
 758                 pte = &parent[offset];
 759                 if (level == total)
 760                         return pte;
 761
 762                 if (!dma_pte_present(pte))
 763                         break;
 764                 parent = phys_to_virt(dma_pte_addr(pte));
 765                 total--;
 766         }
 767         return NULL;
 768 }
 769
 770 /* clear last level pte, a tlb flush should be followed */
 771 static void dma_pte_clear_range(struct dmar_domain *domain,
 772                                 unsigned long start_pfn,
 773                                 unsigned long last_pfn)
 774 {
 775         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
 776         struct dma_pte *first_pte, *pte;
 777
 778         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
 779         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
 780
 781         /* we don't need lock here; nobody else touches the iova range */
 782         while (start_pfn <= last_pfn) {
 783                 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
 784                 if (!pte) {
 785                         start_pfn = align_to_level(start_pfn + 1, 2);
 786                         continue;
 787                 }
 788                 do {
 789                         dma_clear_pte(pte);
 790                         start_pfn++;
 791                         pte++;
 792                 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
 793
 794                 domain_flush_cache(domain, first_pte,
 795                                    (void *)pte - (void *)first_pte);
 796         }
 797 }
 798
 799 /* free page table pages. last level pte should already be cleared */
 800 static void dma_pte_free_pagetable(struct dmar_domain *domain,
 801                                    unsigned long start_pfn,
 802                                    unsigned long last_pfn)
 803 {
 804         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
 805         struct dma_pte *first_pte, *pte;
 806         int total = agaw_to_level(domain->agaw);
 807         int level;
 808         unsigned long tmp;
 809
 810         BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
 811         BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
 812
 813         /* We don't need lock here; nobody else touches the iova range */
 814         level = 2;
 815         while (level <= total) {
 816                 tmp = align_to_level(start_pfn, level);
 817
 818                 /* If we can't even clear one PTE at this level, we're done */
 819                 if (tmp + level_size(level) - 1 > last_pfn)
 820                         return;
 821
 822                 while (tmp + level_size(level) - 1 <= last_pfn) {
 823                         first_pte = pte = dma_pfn_level_pte(domain, tmp, level);
 824                         if (!pte) {
 825                                 tmp = align_to_level(tmp + 1, level + 1);
 826                                 continue;
 827                         }
 828                         do {
 829                                 if (dma_pte_present(pte)) {
 830                                         free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
 831                                         dma_clear_pte(pte);
 832                                 }
 833                                 pte++;
 834                                 tmp += level_size(level);
 835                         } while (!first_pte_in_page(pte) &&
 836                                  tmp + level_size(level) - 1 <= last_pfn);
 837
 838                         domain_flush_cache(domain, first_pte,
 839                                            (void *)pte - (void *)first_pte);
 840
 841                 }
 842                 level++;
 843         }
 844         /* free pgd */
 845         if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
 846                 free_pgtable_page(domain->pgd);
 847                 domain->pgd = NULL;
 848         }
 849 }
 850
 851 /* iommu handling */
 852 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
 853 {
 854         struct root_entry *root;
 855         unsigned long flags;
 856
 857         root = (struct root_entry *)alloc_pgtable_page();
 858         if (!root)
 859                 return -ENOMEM;
 860
 861         __iommu_flush_cache(iommu, root, ROOT_SIZE);
 862
 863         spin_lock_irqsave(&iommu->lock, flags);
 864         iommu->root_entry = root;
 865         spin_unlock_irqrestore(&iommu->lock, flags);
 866
 867         return 0;
 868 }
 869
 870 static void iommu_set_root_entry(struct intel_iommu *iommu)
 871 {
 872         void *addr;
 873         u32 sts;
 874         unsigned long flag;
 875
 876         addr = iommu->root_entry;
 877
 878         spin_lock_irqsave(&iommu->register_lock, flag);
 879         dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
 880
 881         writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
 882
 883         /* Make sure hardware complete it */
 884         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 885                       readl, (sts & DMA_GSTS_RTPS), sts);
 886
 887         spin_unlock_irqrestore(&iommu->register_lock, flag);
 888 }
 889
 890 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
 891 {
 892         u32 val;
 893         unsigned long flag;
 894
 895         if (!rwbf_quirk && !cap_rwbf(iommu->cap))
 896                 return;
 897
 898         spin_lock_irqsave(&iommu->register_lock, flag);
 899         writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
 900
 901         /* Make sure hardware complete it */
 902         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
 903                       readl, (!(val & DMA_GSTS_WBFS)), val);
 904
 905         spin_unlock_irqrestore(&iommu->register_lock, flag);
 906 }
 907
 908 /* return value determine if we need a write buffer flush */
 909 static void __iommu_flush_context(struct intel_iommu *iommu,
 910                                   u16 did, u16 source_id, u8 function_mask,
 911                                   u64 type)
 912 {
 913         u64 val = 0;
 914         unsigned long flag;
 915
 916         switch (type) {
 917         case DMA_CCMD_GLOBAL_INVL:
 918                 val = DMA_CCMD_GLOBAL_INVL;
 919                 break;
 920         case DMA_CCMD_DOMAIN_INVL:
 921                 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
 922                 break;
 923         case DMA_CCMD_DEVICE_INVL:
 924                 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
 925                         | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
 926                 break;
 927         default:
 928                 BUG();
 929         }
 930         val |= DMA_CCMD_ICC;
 931
 932         spin_lock_irqsave(&iommu->register_lock, flag);
 933         dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
 934
 935         /* Make sure hardware complete it */
 936         IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
 937                 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
 938
 939         spin_unlock_irqrestore(&iommu->register_lock, flag);
 940 }
 941
 942 /* return value determine if we need a write buffer flush */
 943 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
 944                                 u64 addr, unsigned int size_order, u64 type)
 945 {
 946         int tlb_offset = ecap_iotlb_offset(iommu->ecap);
 947         u64 val = 0, val_iva = 0;
 948         unsigned long flag;
 949
 950         switch (type) {
 951         case DMA_TLB_GLOBAL_FLUSH:
 952                 /* global flush doesn't need set IVA_REG */
 953                 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
 954                 break;
 955         case DMA_TLB_DSI_FLUSH:
 956                 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
 957                 break;
 958         case DMA_TLB_PSI_FLUSH:
 959                 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
 960                 /* Note: always flush non-leaf currently */
 961                 val_iva = size_order | addr;
 962                 break;
 963         default:
 964                 BUG();
 965         }
 966         /* Note: set drain read/write */
 967 #if 0
 968         /*
 969          * This is probably to be super secure.. Looks like we can
 970          * ignore it without any impact.
 971          */
 972         if (cap_read_drain(iommu->cap))
 973                 val |= DMA_TLB_READ_DRAIN;
 974 #endif
 975         if (cap_write_drain(iommu->cap))
 976                 val |= DMA_TLB_WRITE_DRAIN;
 977
 978         spin_lock_irqsave(&iommu->register_lock, flag);
 979         /* Note: Only uses first TLB reg currently */
 980         if (val_iva)
 981                 dmar_writeq(iommu->reg + tlb_offset, val_iva);
 982         dmar_writeq(iommu->reg + tlb_offset + 8, val);
 983
 984         /* Make sure hardware complete it */
 985         IOMMU_WAIT_OP(iommu, tlb_offset + 8,
 986                 dmar_readq, (!(val & DMA_TLB_IVT)), val);
 987
 988         spin_unlock_irqrestore(&iommu->register_lock, flag);
 989
 990         /* check IOTLB invalidation granularity */
 991         if (DMA_TLB_IAIG(val) == 0)
 992                 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
 993         if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
 994                 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
 995                         (unsigned long long)DMA_TLB_IIRG(type),
 996                         (unsigned long long)DMA_TLB_IAIG(val));
 997 }
 998
 999 static struct device_domain_info *iommu_support_dev_iotlb(
1000         struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1001 {
1002         int found = 0;
1003         unsigned long flags;
1004         struct device_domain_info *info;
1005         struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1006
1007         if (!ecap_dev_iotlb_support(iommu->ecap))
1008                 return NULL;
1009
1010         if (!iommu->qi)
1011                 return NULL;
1012
1013         spin_lock_irqsave(&device_domain_lock, flags);
1014         list_for_each_entry(info, &domain->devices, link)
1015                 if (info->bus == bus && info->devfn == devfn) {
1016                         found = 1;
1017                         break;
1018                 }
1019         spin_unlock_irqrestore(&device_domain_lock, flags);
1020
1021         if (!found || !info->dev)
1022                 return NULL;
1023
1024         if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1025                 return NULL;
1026
1027         if (!dmar_find_matched_atsr_unit(info->dev))
1028                 return NULL;
1029
1030         info->iommu = iommu;
1031
1032         return info;
1033 }
1034
1035 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1036 {
1037         if (!info)
1038                 return;
1039
1040         pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1041 }
1042
1043 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1044 {
1045         if (!info->dev || !pci_ats_enabled(info->dev))
1046                 return;
1047
1048         pci_disable_ats(info->dev);
1049 }
1050
1051 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1052                                   u64 addr, unsigned mask)
1053 {
1054         u16 sid, qdep;
1055         unsigned long flags;
1056         struct device_domain_info *info;
1057
1058         spin_lock_irqsave(&device_domain_lock, flags);
1059         list_for_each_entry(info, &domain->devices, link) {
1060                 if (!info->dev || !pci_ats_enabled(info->dev))
1061                         continue;
1062
1063                 sid = info->bus << 8 | info->devfn;
1064                 qdep = pci_ats_queue_depth(info->dev);
1065                 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1066         }
1067         spin_unlock_irqrestore(&device_domain_lock, flags);
1068 }
1069
1070 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1071                                   unsigned long pfn, unsigned int pages)
1072 {
1073         unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1074         uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1075
1076         BUG_ON(pages == 0);
1077
1078         /*
1079          * Fallback to domain selective flush if no PSI support or the size is
1080          * too big.
1081          * PSI requires page size to be 2 ^ x, and the base address is naturally
1082          * aligned to the size
1083          */
1084         if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1085                 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1086                                                 DMA_TLB_DSI_FLUSH);
1087         else
1088                 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1089                                                 DMA_TLB_PSI_FLUSH);
1090
1091         /*
1092          * In caching mode, domain ID 0 is reserved for non-present to present
1093          * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1094          */
1095         if (!cap_caching_mode(iommu->cap) || did)
1096                 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1097 }
1098
1099 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1100 {
1101         u32 pmen;
1102         unsigned long flags;
1103
1104         spin_lock_irqsave(&iommu->register_lock, flags);
1105         pmen = readl(iommu->reg + DMAR_PMEN_REG);
1106         pmen &= ~DMA_PMEN_EPM;
1107         writel(pmen, iommu->reg + DMAR_PMEN_REG);
1108
1109         /* wait for the protected region status bit to clear */
1110         IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1111                 readl, !(pmen & DMA_PMEN_PRS), pmen);
1112
1113         spin_unlock_irqrestore(&iommu->register_lock, flags);
1114 }
1115
1116 static int iommu_enable_translation(struct intel_iommu *iommu)
1117 {
1118         u32 sts;
1119         unsigned long flags;
1120
1121         spin_lock_irqsave(&iommu->register_lock, flags);
1122         iommu->gcmd |= DMA_GCMD_TE;
1123         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1124
1125         /* Make sure hardware complete it */
1126         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1127                       readl, (sts & DMA_GSTS_TES), sts);
1128
1129         spin_unlock_irqrestore(&iommu->register_lock, flags);
1130         return 0;
1131 }
1132
1133 static int iommu_disable_translation(struct intel_iommu *iommu)
1134 {
1135         u32 sts;
1136         unsigned long flag;
1137
1138         spin_lock_irqsave(&iommu->register_lock, flag);
1139         iommu->gcmd &= ~DMA_GCMD_TE;
1140         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1141
1142         /* Make sure hardware complete it */
1143         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1144                       readl, (!(sts & DMA_GSTS_TES)), sts);
1145
1146         spin_unlock_irqrestore(&iommu->register_lock, flag);
1147         return 0;
1148 }
1149
1150
1151 static int iommu_init_domains(struct intel_iommu *iommu)
1152 {
1153         unsigned long ndomains;
1154         unsigned long nlongs;
1155
1156         ndomains = cap_ndoms(iommu->cap);
1157         pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1158         nlongs = BITS_TO_LONGS(ndomains);
1159
1160         /* TBD: there might be 64K domains,
1161          * consider other allocation for future chip
1162          */
1163         iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1164         if (!iommu->domain_ids) {
1165                 printk(KERN_ERR "Allocating domain id array failed\n");
1166                 return -ENOMEM;
1167         }
1168         iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1169                         GFP_KERNEL);
1170         if (!iommu->domains) {
1171                 printk(KERN_ERR "Allocating domain array failed\n");
1172                 kfree(iommu->domain_ids);
1173                 return -ENOMEM;
1174         }
1175
1176         spin_lock_init(&iommu->lock);
1177
1178         /*
1179          * if Caching mode is set, then invalid translations are tagged
1180          * with domainid 0. Hence we need to pre-allocate it.
1181          */
1182         if (cap_caching_mode(iommu->cap))
1183                 set_bit(0, iommu->domain_ids);
1184         return 0;
1185 }
1186
1187
1188 static void domain_exit(struct dmar_domain *domain);
1189 static void vm_domain_exit(struct dmar_domain *domain);
1190
1191 void free_dmar_iommu(struct intel_iommu *iommu)
1192 {
1193         struct dmar_domain *domain;
1194         int i;
1195         unsigned long flags;
1196
1197         i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1198         for (; i < cap_ndoms(iommu->cap); ) {
1199                 domain = iommu->domains[i];
1200                 clear_bit(i, iommu->domain_ids);
1201
1202                 spin_lock_irqsave(&domain->iommu_lock, flags);
1203                 if (--domain->iommu_count == 0) {
1204                         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1205                                 vm_domain_exit(domain);
1206                         else
1207                                 domain_exit(domain);
1208                 }
1209                 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1210
1211                 i = find_next_bit(iommu->domain_ids,
1212                         cap_ndoms(iommu->cap), i+1);
1213         }
1214
1215         if (iommu->gcmd & DMA_GCMD_TE)
1216                 iommu_disable_translation(iommu);
1217
1218         if (iommu->irq) {
1219                 set_irq_data(iommu->irq, NULL);
1220                 /* This will mask the irq */
1221                 free_irq(iommu->irq, iommu);
1222                 destroy_irq(iommu->irq);
1223         }
1224
1225         kfree(iommu->domains);
1226         kfree(iommu->domain_ids);
1227
1228         g_iommus[iommu->seq_id] = NULL;
1229
1230         /* if all iommus are freed, free g_iommus */
1231         for (i = 0; i < g_num_of_iommus; i++) {
1232                 if (g_iommus[i])
1233                         break;
1234         }
1235
1236         if (i == g_num_of_iommus)
1237                 kfree(g_iommus);
1238
1239         /* free context mapping */
1240         free_context_table(iommu);
1241 }
1242
1243 static struct dmar_domain *alloc_domain(void)
1244 {
1245         struct dmar_domain *domain;
1246
1247         domain = alloc_domain_mem();
1248         if (!domain)
1249                 return NULL;
1250
1251         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1252         domain->flags = 0;
1253
1254         return domain;
1255 }
1256
1257 static int iommu_attach_domain(struct dmar_domain *domain,
1258                                struct intel_iommu *iommu)
1259 {
1260         int num;
1261         unsigned long ndomains;
1262         unsigned long flags;
1263
1264         ndomains = cap_ndoms(iommu->cap);
1265
1266         spin_lock_irqsave(&iommu->lock, flags);
1267
1268         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1269         if (num >= ndomains) {
1270                 spin_unlock_irqrestore(&iommu->lock, flags);
1271                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1272                 return -ENOMEM;
1273         }
1274
1275         domain->id = num;
1276         set_bit(num, iommu->domain_ids);
1277         set_bit(iommu->seq_id, &domain->iommu_bmp);
1278         iommu->domains[num] = domain;
1279         spin_unlock_irqrestore(&iommu->lock, flags);
1280
1281         return 0;
1282 }
1283
1284 static void iommu_detach_domain(struct dmar_domain *domain,
1285                                 struct intel_iommu *iommu)
1286 {
1287         unsigned long flags;
1288         int num, ndomains;
1289         int found = 0;
1290
1291         spin_lock_irqsave(&iommu->lock, flags);
1292         ndomains = cap_ndoms(iommu->cap);
1293         num = find_first_bit(iommu->domain_ids, ndomains);
1294         for (; num < ndomains; ) {
1295                 if (iommu->domains[num] == domain) {
1296                         found = 1;
1297                         break;
1298                 }
1299                 num = find_next_bit(iommu->domain_ids,
1300                                     cap_ndoms(iommu->cap), num+1);
1301         }
1302
1303         if (found) {
1304                 clear_bit(num, iommu->domain_ids);
1305                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1306                 iommu->domains[num] = NULL;
1307         }
1308         spin_unlock_irqrestore(&iommu->lock, flags);
1309 }
1310
1311 static struct iova_domain reserved_iova_list;
1312 static struct lock_class_key reserved_alloc_key;
1313 static struct lock_class_key reserved_rbtree_key;
1314
1315 static void dmar_init_reserved_ranges(void)
1316 {
1317         struct pci_dev *pdev = NULL;
1318         struct iova *iova;
1319         int i;
1320
1321         init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1322
1323         lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1324                 &reserved_alloc_key);
1325         lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1326                 &reserved_rbtree_key);
1327
1328         /* IOAPIC ranges shouldn't be accessed by DMA */
1329         iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1330                 IOVA_PFN(IOAPIC_RANGE_END));
1331         if (!iova)
1332                 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1333
1334         /* Reserve all PCI MMIO to avoid peer-to-peer access */
1335         for_each_pci_dev(pdev) {
1336                 struct resource *r;
1337
1338                 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1339                         r = &pdev->resource[i];
1340                         if (!r->flags || !(r->flags & IORESOURCE_MEM))
1341                                 continue;
1342                         iova = reserve_iova(&reserved_iova_list,
1343                                             IOVA_PFN(r->start),
1344                                             IOVA_PFN(r->end));
1345                         if (!iova)
1346                                 printk(KERN_ERR "Reserve iova failed\n");
1347                 }
1348         }
1349
1350 }
1351
1352 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1353 {
1354         copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1355 }
1356
1357 static inline int guestwidth_to_adjustwidth(int gaw)
1358 {
1359         int agaw;
1360         int r = (gaw - 12) % 9;
1361
1362         if (r == 0)
1363                 agaw = gaw;
1364         else
1365                 agaw = gaw + 9 - r;
1366         if (agaw > 64)
1367                 agaw = 64;
1368         return agaw;
1369 }
1370
1371 static int domain_init(struct dmar_domain *domain, int guest_width)
1372 {
1373         struct intel_iommu *iommu;
1374         int adjust_width, agaw;
1375         unsigned long sagaw;
1376
1377         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1378         spin_lock_init(&domain->iommu_lock);
1379
1380         domain_reserve_special_ranges(domain);
1381
1382         /* calculate AGAW */
1383         iommu = domain_get_iommu(domain);
1384         if (guest_width > cap_mgaw(iommu->cap))
1385                 guest_width = cap_mgaw(iommu->cap);
1386         domain->gaw = guest_width;
1387         adjust_width = guestwidth_to_adjustwidth(guest_width);
1388         agaw = width_to_agaw(adjust_width);
1389         sagaw = cap_sagaw(iommu->cap);
1390         if (!test_bit(agaw, &sagaw)) {
1391                 /* hardware doesn't support it, choose a bigger one */
1392                 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1393                 agaw = find_next_bit(&sagaw, 5, agaw);
1394                 if (agaw >= 5)
1395                         return -ENODEV;
1396         }
1397         domain->agaw = agaw;
1398         INIT_LIST_HEAD(&domain->devices);
1399
1400         if (ecap_coherent(iommu->ecap))
1401                 domain->iommu_coherency = 1;
1402         else
1403                 domain->iommu_coherency = 0;
1404
1405         if (ecap_sc_support(iommu->ecap))
1406                 domain->iommu_snooping = 1;
1407         else
1408                 domain->iommu_snooping = 0;
1409
1410         domain->iommu_count = 1;
1411
1412         /* always allocate the top pgd */
1413         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1414         if (!domain->pgd)
1415                 return -ENOMEM;
1416         __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1417         return 0;
1418 }
1419
1420 static void domain_exit(struct dmar_domain *domain)
1421 {
1422         struct dmar_drhd_unit *drhd;
1423         struct intel_iommu *iommu;
1424
1425         /* Domain 0 is reserved, so dont process it */
1426         if (!domain)
1427                 return;
1428
1429         domain_remove_dev_info(domain);
1430         /* destroy iovas */
1431         put_iova_domain(&domain->iovad);
1432
1433         /* clear ptes */
1434         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1435
1436         /* free page tables */
1437         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1438
1439         for_each_active_iommu(iommu, drhd)
1440                 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1441                         iommu_detach_domain(domain, iommu);
1442
1443         free_domain_mem(domain);
1444 }
1445
1446 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1447                                  u8 bus, u8 devfn, int translation)
1448 {
1449         struct context_entry *context;
1450         unsigned long flags;
1451         struct intel_iommu *iommu;
1452         struct dma_pte *pgd;
1453         unsigned long num;
1454         unsigned long ndomains;
1455         int id;
1456         int agaw;
1457         struct device_domain_info *info = NULL;
1458
1459         pr_debug("Set context mapping for %02x:%02x.%d\n",
1460                 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1461
1462         BUG_ON(!domain->pgd);
1463         BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1464                translation != CONTEXT_TT_MULTI_LEVEL);
1465
1466         iommu = device_to_iommu(segment, bus, devfn);
1467         if (!iommu)
1468                 return -ENODEV;
1469
1470         context = device_to_context_entry(iommu, bus, devfn);
1471         if (!context)
1472                 return -ENOMEM;
1473         spin_lock_irqsave(&iommu->lock, flags);
1474         if (context_present(context)) {
1475                 spin_unlock_irqrestore(&iommu->lock, flags);
1476                 return 0;
1477         }
1478
1479         id = domain->id;
1480         pgd = domain->pgd;
1481
1482         if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1483             domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1484                 int found = 0;
1485
1486                 /* find an available domain id for this device in iommu */
1487                 ndomains = cap_ndoms(iommu->cap);
1488                 num = find_first_bit(iommu->domain_ids, ndomains);
1489                 for (; num < ndomains; ) {
1490                         if (iommu->domains[num] == domain) {
1491                                 id = num;
1492                                 found = 1;
1493                                 break;
1494                         }
1495                         num = find_next_bit(iommu->domain_ids,
1496                                             cap_ndoms(iommu->cap), num+1);
1497                 }
1498
1499                 if (found == 0) {
1500                         num = find_first_zero_bit(iommu->domain_ids, ndomains);
1501                         if (num >= ndomains) {
1502                                 spin_unlock_irqrestore(&iommu->lock, flags);
1503                                 printk(KERN_ERR "IOMMU: no free domain ids\n");
1504                                 return -EFAULT;
1505                         }
1506
1507                         set_bit(num, iommu->domain_ids);
1508                         set_bit(iommu->seq_id, &domain->iommu_bmp);
1509                         iommu->domains[num] = domain;
1510                         id = num;
1511                 }
1512
1513                 /* Skip top levels of page tables for
1514                  * iommu which has less agaw than default.
1515                  */
1516                 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1517                         pgd = phys_to_virt(dma_pte_addr(pgd));
1518                         if (!dma_pte_present(pgd)) {
1519                                 spin_unlock_irqrestore(&iommu->lock, flags);
1520                                 return -ENOMEM;
1521                         }
1522                 }
1523         }
1524
1525         context_set_domain_id(context, id);
1526
1527         if (translation != CONTEXT_TT_PASS_THROUGH) {
1528                 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1529                 translation = info ? CONTEXT_TT_DEV_IOTLB :
1530                                      CONTEXT_TT_MULTI_LEVEL;
1531         }
1532         /*
1533          * In pass through mode, AW must be programmed to indicate the largest
1534          * AGAW value supported by hardware. And ASR is ignored by hardware.
1535          */
1536         if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1537                 context_set_address_width(context, iommu->msagaw);
1538         else {
1539                 context_set_address_root(context, virt_to_phys(pgd));
1540                 context_set_address_width(context, iommu->agaw);
1541         }
1542
1543         context_set_translation_type(context, translation);
1544         context_set_fault_enable(context);
1545         context_set_present(context);
1546         domain_flush_cache(domain, context, sizeof(*context));
1547
1548         /*
1549          * It's a non-present to present mapping. If hardware doesn't cache
1550          * non-present entry we only need to flush the write-buffer. If the
1551          * _does_ cache non-present entries, then it does so in the special
1552          * domain #0, which we have to flush:
1553          */
1554         if (cap_caching_mode(iommu->cap)) {
1555                 iommu->flush.flush_context(iommu, 0,
1556                                            (((u16)bus) << 8) | devfn,
1557                                            DMA_CCMD_MASK_NOBIT,
1558                                            DMA_CCMD_DEVICE_INVL);
1559                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1560         } else {
1561                 iommu_flush_write_buffer(iommu);
1562         }
1563         iommu_enable_dev_iotlb(info);
1564         spin_unlock_irqrestore(&iommu->lock, flags);
1565
1566         spin_lock_irqsave(&domain->iommu_lock, flags);
1567         if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1568                 domain->iommu_count++;
1569                 domain_update_iommu_cap(domain);
1570         }
1571         spin_unlock_irqrestore(&domain->iommu_lock, flags);
1572         return 0;
1573 }
1574
1575 static int
1576 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1577                         int translation)
1578 {
1579         int ret;
1580         struct pci_dev *tmp, *parent;
1581
1582         ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1583                                          pdev->bus->number, pdev->devfn,
1584                                          translation);
1585         if (ret)
1586                 return ret;
1587
1588         /* dependent device mapping */
1589         tmp = pci_find_upstream_pcie_bridge(pdev);
1590         if (!tmp)
1591                 return 0;
1592         /* Secondary interface's bus number and devfn 0 */
1593         parent = pdev->bus->self;
1594         while (parent != tmp) {
1595                 ret = domain_context_mapping_one(domain,
1596                                                  pci_domain_nr(parent->bus),
1597                                                  parent->bus->number,
1598                                                  parent->devfn, translation);
1599                 if (ret)
1600                         return ret;
1601                 parent = parent->bus->self;
1602         }
1603         if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1604                 return domain_context_mapping_one(domain,
1605                                         pci_domain_nr(tmp->subordinate),
1606                                         tmp->subordinate->number, 0,
1607                                         translation);
1608         else /* this is a legacy PCI bridge */
1609                 return domain_context_mapping_one(domain,
1610                                                   pci_domain_nr(tmp->bus),
1611                                                   tmp->bus->number,
1612                                                   tmp->devfn,
1613                                                   translation);
1614 }
1615
1616 static int domain_context_mapped(struct pci_dev *pdev)
1617 {
1618         int ret;
1619         struct pci_dev *tmp, *parent;
1620         struct intel_iommu *iommu;
1621
1622         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1623                                 pdev->devfn);
1624         if (!iommu)
1625                 return -ENODEV;
1626
1627         ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1628         if (!ret)
1629                 return ret;
1630         /* dependent device mapping */
1631         tmp = pci_find_upstream_pcie_bridge(pdev);
1632         if (!tmp)
1633                 return ret;
1634         /* Secondary interface's bus number and devfn 0 */
1635         parent = pdev->bus->self;
1636         while (parent != tmp) {
1637                 ret = device_context_mapped(iommu, parent->bus->number,
1638                                             parent->devfn);
1639                 if (!ret)
1640                         return ret;
1641                 parent = parent->bus->self;
1642         }
1643         if (tmp->is_pcie)
1644                 return device_context_mapped(iommu, tmp->subordinate->number,
1645                                              0);
1646         else
1647                 return device_context_mapped(iommu, tmp->bus->number,
1648                                              tmp->devfn);
1649 }
1650
1651 static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1652                             struct scatterlist *sg, unsigned long phys_pfn,
1653                             unsigned long nr_pages, int prot)
1654 {
1655         struct dma_pte *first_pte = NULL, *pte = NULL;
1656         phys_addr_t uninitialized_var(pteval);
1657         int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1658         unsigned long sg_res;
1659
1660         BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1661
1662         if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1663                 return -EINVAL;
1664
1665         prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1666
1667         if (sg)
1668                 sg_res = 0;
1669         else {
1670                 sg_res = nr_pages + 1;
1671                 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1672         }
1673
1674         while (nr_pages--) {
1675                 uint64_t tmp;
1676
1677                 if (!sg_res) {
1678                         sg_res = (sg->offset + sg->length + VTD_PAGE_SIZE - 1) >> VTD_PAGE_SHIFT;
1679                         sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1680                         sg->dma_length = sg->length;
1681                         pteval = page_to_phys(sg_page(sg)) | prot;
1682                 }
1683                 if (!pte) {
1684                         first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
1685                         if (!pte)
1686                                 return -ENOMEM;
1687                 }
1688                 /* We don't need lock here, nobody else
1689                  * touches the iova range
1690                  */
1691                 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
1692                 if (tmp) {
1693                         static int dumps = 5;
1694                         printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1695                                iov_pfn, tmp, (unsigned long long)pteval);
1696                         if (dumps) {
1697                                 dumps--;
1698                                 debug_dma_dump_mappings(NULL);
1699                         }
1700                         WARN_ON(1);
1701                 }
1702                 pte++;
1703                 if (!nr_pages || first_pte_in_page(pte)) {
1704                         domain_flush_cache(domain, first_pte,
1705                                            (void *)pte - (void *)first_pte);
1706                         pte = NULL;
1707                 }
1708                 iov_pfn++;
1709                 pteval += VTD_PAGE_SIZE;
1710                 sg_res--;
1711                 if (!sg_res)
1712                         sg = sg_next(sg);
1713         }
1714         return 0;
1715 }
1716
1717 static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1718                                     struct scatterlist *sg, unsigned long nr_pages,
1719                                     int prot)
1720 {
1721         return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1722 }
1723
1724 static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1725                                      unsigned long phys_pfn, unsigned long nr_pages,
1726                                      int prot)
1727 {
1728         return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
1729 }
1730
1731 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1732 {
1733         if (!iommu)
1734                 return;
1735
1736         clear_context_table(iommu, bus, devfn);
1737         iommu->flush.flush_context(iommu, 0, 0, 0,
1738                                            DMA_CCMD_GLOBAL_INVL);
1739         iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1740 }
1741
1742 static void domain_remove_dev_info(struct dmar_domain *domain)
1743 {
1744         struct device_domain_info *info;
1745         unsigned long flags;
1746         struct intel_iommu *iommu;
1747
1748         spin_lock_irqsave(&device_domain_lock, flags);
1749         while (!list_empty(&domain->devices)) {
1750                 info = list_entry(domain->devices.next,
1751                         struct device_domain_info, link);
1752                 list_del(&info->link);
1753                 list_del(&info->global);
1754                 if (info->dev)
1755                         info->dev->dev.archdata.iommu = NULL;
1756                 spin_unlock_irqrestore(&device_domain_lock, flags);
1757
1758                 iommu_disable_dev_iotlb(info);
1759                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1760                 iommu_detach_dev(iommu, info->bus, info->devfn);
1761                 free_devinfo_mem(info);
1762
1763                 spin_lock_irqsave(&device_domain_lock, flags);
1764         }
1765         spin_unlock_irqrestore(&device_domain_lock, flags);
1766 }
1767
1768 /*
1769  * find_domain
1770  * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1771  */
1772 static struct dmar_domain *
1773 find_domain(struct pci_dev *pdev)
1774 {
1775         struct device_domain_info *info;
1776
1777         /* No lock here, assumes no domain exit in normal case */
1778         info = pdev->dev.archdata.iommu;
1779         if (info)
1780                 return info->domain;
1781         return NULL;
1782 }
1783
1784 /* domain is initialized */
1785 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1786 {
1787         struct dmar_domain *domain, *found = NULL;
1788         struct intel_iommu *iommu;
1789         struct dmar_drhd_unit *drhd;
1790         struct device_domain_info *info, *tmp;
1791         struct pci_dev *dev_tmp;
1792         unsigned long flags;
1793         int bus = 0, devfn = 0;
1794         int segment;
1795         int ret;
1796
1797         domain = find_domain(pdev);
1798         if (domain)
1799                 return domain;
1800
1801         segment = pci_domain_nr(pdev->bus);
1802
1803         dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1804         if (dev_tmp) {
1805                 if (dev_tmp->is_pcie) {
1806                         bus = dev_tmp->subordinate->number;
1807                         devfn = 0;
1808                 } else {
1809                         bus = dev_tmp->bus->number;
1810                         devfn = dev_tmp->devfn;
1811                 }
1812                 spin_lock_irqsave(&device_domain_lock, flags);
1813                 list_for_each_entry(info, &device_domain_list, global) {
1814                         if (info->segment == segment &&
1815                             info->bus == bus && info->devfn == devfn) {
1816                                 found = info->domain;
1817                                 break;
1818                         }
1819                 }
1820                 spin_unlock_irqrestore(&device_domain_lock, flags);
1821                 /* pcie-pci bridge already has a domain, uses it */
1822                 if (found) {
1823                         domain = found;
1824                         goto found_domain;
1825                 }
1826         }
1827
1828         domain = alloc_domain();
1829         if (!domain)
1830                 goto error;
1831
1832         /* Allocate new domain for the device */
1833         drhd = dmar_find_matched_drhd_unit(pdev);
1834         if (!drhd) {
1835                 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1836                         pci_name(pdev));
1837                 return NULL;
1838         }
1839         iommu = drhd->iommu;
1840
1841         ret = iommu_attach_domain(domain, iommu);
1842         if (ret) {
1843                 domain_exit(domain);
1844                 goto error;
1845         }
1846
1847         if (domain_init(domain, gaw)) {
1848                 domain_exit(domain);
1849                 goto error;
1850         }
1851
1852         /* register pcie-to-pci device */
1853         if (dev_tmp) {
1854                 info = alloc_devinfo_mem();
1855                 if (!info) {
1856                         domain_exit(domain);
1857                         goto error;
1858                 }
1859                 info->segment = segment;
1860                 info->bus = bus;
1861                 info->devfn = devfn;
1862                 info->dev = NULL;
1863                 info->domain = domain;
1864                 /* This domain is shared by devices under p2p bridge */
1865                 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1866
1867                 /* pcie-to-pci bridge already has a domain, uses it */
1868                 found = NULL;
1869                 spin_lock_irqsave(&device_domain_lock, flags);
1870                 list_for_each_entry(tmp, &device_domain_list, global) {
1871                         if (tmp->segment == segment &&
1872                             tmp->bus == bus && tmp->devfn == devfn) {
1873                                 found = tmp->domain;
1874                                 break;
1875                         }
1876                 }
1877                 if (found) {
1878                         free_devinfo_mem(info);
1879                         domain_exit(domain);
1880                         domain = found;
1881                 } else {
1882                         list_add(&info->link, &domain->devices);
1883                         list_add(&info->global, &device_domain_list);
1884                 }
1885                 spin_unlock_irqrestore(&device_domain_lock, flags);
1886         }
1887
1888 found_domain:
1889         info = alloc_devinfo_mem();
1890         if (!info)
1891                 goto error;
1892         info->segment = segment;
1893         info->bus = pdev->bus->number;
1894         info->devfn = pdev->devfn;
1895         info->dev = pdev;
1896         info->domain = domain;
1897         spin_lock_irqsave(&device_domain_lock, flags);
1898         /* somebody is fast */
1899         found = find_domain(pdev);
1900         if (found != NULL) {
1901                 spin_unlock_irqrestore(&device_domain_lock, flags);
1902                 if (found != domain) {
1903                         domain_exit(domain);
1904                         domain = found;
1905                 }
1906                 free_devinfo_mem(info);
1907                 return domain;
1908         }
1909         list_add(&info->link, &domain->devices);
1910         list_add(&info->global, &device_domain_list);
1911         pdev->dev.archdata.iommu = info;
1912         spin_unlock_irqrestore(&device_domain_lock, flags);
1913         return domain;
1914 error:
1915         /* recheck it here, maybe others set it */
1916         return find_domain(pdev);
1917 }
1918
1919 static int iommu_identity_mapping;
1920
1921 static int iommu_domain_identity_map(struct dmar_domain *domain,
1922                                      unsigned long long start,
1923                                      unsigned long long end)
1924 {
1925         unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1926         unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1927
1928         if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1929                           dma_to_mm_pfn(last_vpfn))) {
1930                 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1931                 return -ENOMEM;
1932         }
1933
1934         pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1935                  start, end, domain->id);
1936         /*
1937          * RMRR range might have overlap with physical memory range,
1938          * clear it first
1939          */
1940         dma_pte_clear_range(domain, first_vpfn, last_vpfn);
1941
1942         return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1943                                   last_vpfn - first_vpfn + 1,
1944                                   DMA_PTE_READ|DMA_PTE_WRITE);
1945 }
1946
1947 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1948                                       unsigned long long start,
1949                                       unsigned long long end)
1950 {
1951         struct dmar_domain *domain;
1952         int ret;
1953
1954         printk(KERN_INFO
1955                "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1956                pci_name(pdev), start, end);
1957
1958         domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1959         if (!domain)
1960                 return -ENOMEM;
1961
1962         ret = iommu_domain_identity_map(domain, start, end);
1963         if (ret)
1964                 goto error;
1965
1966         /* context entry init */
1967         ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1968         if (ret)
1969                 goto error;
1970
1971         return 0;
1972
1973  error:
1974         domain_exit(domain);
1975         return ret;
1976 }
1977
1978 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1979         struct pci_dev *pdev)
1980 {
1981         if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1982                 return 0;
1983         return iommu_prepare_identity_map(pdev, rmrr->base_address,
1984                 rmrr->end_address + 1);
1985 }
1986
1987 #ifdef CONFIG_DMAR_FLOPPY_WA
1988 static inline void iommu_prepare_isa(void)
1989 {
1990         struct pci_dev *pdev;
1991         int ret;
1992
1993         pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1994         if (!pdev)
1995                 return;
1996
1997         printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
1998         ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1999
2000         if (ret)
2001                 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2002                        "floppy might not work\n");
2003
2004 }
2005 #else
2006 static inline void iommu_prepare_isa(void)
2007 {
2008         return;
2009 }
2010 #endif /* !CONFIG_DMAR_FLPY_WA */
2011
2012 /* Initialize each context entry as pass through.*/
2013 static int __init init_context_pass_through(void)
2014 {
2015         struct pci_dev *pdev = NULL;
2016         struct dmar_domain *domain;
2017         int ret;
2018
2019         for_each_pci_dev(pdev) {
2020                 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2021                 ret = domain_context_mapping(domain, pdev,
2022                                              CONTEXT_TT_PASS_THROUGH);
2023                 if (ret)
2024                         return ret;
2025         }
2026         return 0;
2027 }
2028
2029 static int md_domain_init(struct dmar_domain *domain, int guest_width);
2030
2031 static int __init si_domain_work_fn(unsigned long start_pfn,
2032                                     unsigned long end_pfn, void *datax)
2033 {
2034         int *ret = datax;
2035
2036         *ret = iommu_domain_identity_map(si_domain,
2037                                          (uint64_t)start_pfn << PAGE_SHIFT,
2038                                          (uint64_t)end_pfn << PAGE_SHIFT);
2039         return *ret;
2040
2041 }
2042
2043 static int si_domain_init(void)
2044 {
2045         struct dmar_drhd_unit *drhd;
2046         struct intel_iommu *iommu;
2047         int nid, ret = 0;
2048
2049         si_domain = alloc_domain();
2050         if (!si_domain)
2051                 return -EFAULT;
2052
2053         pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2054
2055         for_each_active_iommu(iommu, drhd) {
2056                 ret = iommu_attach_domain(si_domain, iommu);
2057                 if (ret) {
2058                         domain_exit(si_domain);
2059                         return -EFAULT;
2060                 }
2061         }
2062
2063         if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2064                 domain_exit(si_domain);
2065                 return -EFAULT;
2066         }
2067
2068         si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2069
2070         for_each_online_node(nid) {
2071                 work_with_active_regions(nid, si_domain_work_fn, &ret);
2072                 if (ret)
2073                         return ret;
2074         }
2075
2076         return 0;
2077 }
2078
2079 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2080                                           struct pci_dev *pdev);
2081 static int identity_mapping(struct pci_dev *pdev)
2082 {
2083         struct device_domain_info *info;
2084
2085         if (likely(!iommu_identity_mapping))
2086                 return 0;
2087
2088
2089         list_for_each_entry(info, &si_domain->devices, link)
2090                 if (info->dev == pdev)
2091                         return 1;
2092         return 0;
2093 }
2094
2095 static int domain_add_dev_info(struct dmar_domain *domain,
2096                                   struct pci_dev *pdev)
2097 {
2098         struct device_domain_info *info;
2099         unsigned long flags;
2100
2101         info = alloc_devinfo_mem();
2102         if (!info)
2103                 return -ENOMEM;
2104
2105         info->segment = pci_domain_nr(pdev->bus);
2106         info->bus = pdev->bus->number;
2107         info->devfn = pdev->devfn;
2108         info->dev = pdev;
2109         info->domain = domain;
2110
2111         spin_lock_irqsave(&device_domain_lock, flags);
2112         list_add(&info->link, &domain->devices);
2113         list_add(&info->global, &device_domain_list);
2114         pdev->dev.archdata.iommu = info;
2115         spin_unlock_irqrestore(&device_domain_lock, flags);
2116
2117         return 0;
2118 }
2119
2120 static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2121 {
2122         if (iommu_identity_mapping == 2)
2123                 return IS_GFX_DEVICE(pdev);
2124
2125         /*
2126          * We want to start off with all devices in the 1:1 domain, and
2127          * take them out later if we find they can't access all of memory.
2128          *
2129          * However, we can't do this for PCI devices behind bridges,
2130          * because all PCI devices behind the same bridge will end up
2131          * with the same source-id on their transactions.
2132          *
2133          * Practically speaking, we can't change things around for these
2134          * devices at run-time, because we can't be sure there'll be no
2135          * DMA transactions in flight for any of their siblings.
2136          *
2137          * So PCI devices (unless they're on the root bus) as well as
2138          * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2139          * the 1:1 domain, just in _case_ one of their siblings turns out
2140          * not to be able to map all of memory.
2141          */
2142         if (!pdev->is_pcie) {
2143                 if (!pci_is_root_bus(pdev->bus))
2144                         return 0;
2145                 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2146                         return 0;
2147         } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
2148                 return 0;
2149
2150         /*
2151          * At boot time, we don't yet know if devices will be 64-bit capable.
2152          * Assume that they will -- if they turn out not to be, then we can
2153          * take them out of the 1:1 domain later.
2154          */
2155         if (!startup)
2156                 return pdev->dma_mask > DMA_BIT_MASK(32);
2157
2158         return 1;
2159 }
2160
2161 static int iommu_prepare_static_identity_mapping(void)
2162 {
2163         struct pci_dev *pdev = NULL;
2164         int ret;
2165
2166         ret = si_domain_init();
2167         if (ret)
2168                 return -EFAULT;
2169
2170         for_each_pci_dev(pdev) {
2171                 if (iommu_should_identity_map(pdev, 1)) {
2172                         printk(KERN_INFO "IOMMU: identity mapping for device %s\n",
2173                                pci_name(pdev));
2174
2175                         ret = domain_context_mapping(si_domain, pdev,
2176                                                      CONTEXT_TT_MULTI_LEVEL);
2177                         if (ret)
2178                                 return ret;
2179                         ret = domain_add_dev_info(si_domain, pdev);
2180                         if (ret)
2181                                 return ret;
2182                 }
2183         }
2184
2185         return 0;
2186 }
2187
2188 int __init init_dmars(void)
2189 {
2190         struct dmar_drhd_unit *drhd;
2191         struct dmar_rmrr_unit *rmrr;
2192         struct pci_dev *pdev;
2193         struct intel_iommu *iommu;
2194         int i, ret;
2195         int pass_through = 1;
2196
2197         /*
2198          * In case pass through can not be enabled, iommu tries to use identity
2199          * mapping.
2200          */
2201         if (iommu_pass_through)
2202                 iommu_identity_mapping = 1;
2203
2204         /*
2205          * for each drhd
2206          *    allocate root
2207          *    initialize and program root entry to not present
2208          * endfor
2209          */
2210         for_each_drhd_unit(drhd) {
2211                 g_num_of_iommus++;
2212                 /*
2213                  * lock not needed as this is only incremented in the single
2214                  * threaded kernel __init code path all other access are read
2215                  * only
2216                  */
2217         }
2218
2219         g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2220                         GFP_KERNEL);
2221         if (!g_iommus) {
2222                 printk(KERN_ERR "Allocating global iommu array failed\n");
2223                 ret = -ENOMEM;
2224                 goto error;
2225         }
2226
2227         deferred_flush = kzalloc(g_num_of_iommus *
2228                 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2229         if (!deferred_flush) {
2230                 kfree(g_iommus);
2231                 ret = -ENOMEM;
2232                 goto error;
2233         }
2234
2235         for_each_drhd_unit(drhd) {
2236                 if (drhd->ignored)
2237                         continue;
2238
2239                 iommu = drhd->iommu;
2240                 g_iommus[iommu->seq_id] = iommu;
2241
2242                 ret = iommu_init_domains(iommu);
2243                 if (ret)
2244                         goto error;
2245
2246                 /*
2247                  * TBD:
2248                  * we could share the same root & context tables
2249                  * amoung all IOMMU's. Need to Split it later.
2250                  */
2251                 ret = iommu_alloc_root_entry(iommu);
2252                 if (ret) {
2253                         printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2254                         goto error;
2255                 }
2256                 if (!ecap_pass_through(iommu->ecap))
2257                         pass_through = 0;
2258         }
2259         if (iommu_pass_through)
2260                 if (!pass_through) {
2261                         printk(KERN_INFO
2262                                "Pass Through is not supported by hardware.\n");
2263                         iommu_pass_through = 0;
2264                 }
2265
2266         /*
2267          * Start from the sane iommu hardware state.
2268          */
2269         for_each_drhd_unit(drhd) {
2270                 if (drhd->ignored)
2271                         continue;
2272
2273                 iommu = drhd->iommu;
2274
2275                 /*
2276                  * If the queued invalidation is already initialized by us
2277                  * (for example, while enabling interrupt-remapping) then
2278                  * we got the things already rolling from a sane state.
2279                  */
2280                 if (iommu->qi)
2281                         continue;
2282
2283                 /*
2284                  * Clear any previous faults.
2285                  */
2286                 dmar_fault(-1, iommu);
2287                 /*
2288                  * Disable queued invalidation if supported and already enabled
2289                  * before OS handover.
2290                  */
2291                 dmar_disable_qi(iommu);
2292         }
2293
2294         for_each_drhd_unit(drhd) {
2295                 if (drhd->ignored)
2296                         continue;
2297
2298                 iommu = drhd->iommu;
2299
2300                 if (dmar_enable_qi(iommu)) {
2301                         /*
2302                          * Queued Invalidate not enabled, use Register Based
2303                          * Invalidate
2304                          */
2305                         iommu->flush.flush_context = __iommu_flush_context;
2306                         iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2307                         printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2308                                "invalidation\n",
2309                                (unsigned long long)drhd->reg_base_addr);
2310                 } else {
2311                         iommu->flush.flush_context = qi_flush_context;
2312                         iommu->flush.flush_iotlb = qi_flush_iotlb;
2313                         printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2314                                "invalidation\n",
2315                                (unsigned long long)drhd->reg_base_addr);
2316                 }
2317         }
2318
2319         /*
2320          * If pass through is set and enabled, context entries of all pci
2321          * devices are intialized by pass through translation type.
2322          */
2323         if (iommu_pass_through) {
2324                 ret = init_context_pass_through();
2325                 if (ret) {
2326                         printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2327                         iommu_pass_through = 0;
2328                 }
2329         }
2330
2331         /*
2332          * If pass through is not set or not enabled, setup context entries for
2333          * identity mappings for rmrr, gfx, and isa and may fall back to static
2334          * identity mapping if iommu_identity_mapping is set.
2335          */
2336         if (!iommu_pass_through) {
2337 #ifdef CONFIG_DMAR_BROKEN_GFX_WA
2338                 if (!iommu_identity_mapping)
2339                         iommu_identity_mapping = 2;
2340 #endif
2341                 if (iommu_identity_mapping)
2342                         iommu_prepare_static_identity_mapping();
2343                 /*
2344                  * For each rmrr
2345                  *   for each dev attached to rmrr
2346                  *   do
2347                  *     locate drhd for dev, alloc domain for dev
2348                  *     allocate free domain
2349                  *     allocate page table entries for rmrr
2350                  *     if context not allocated for bus
2351                  *           allocate and init context
2352                  *           set present in root table for this bus
2353                  *     init context with domain, translation etc
2354                  *    endfor
2355                  * endfor
2356                  */
2357                 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2358                 for_each_rmrr_units(rmrr) {
2359                         for (i = 0; i < rmrr->devices_cnt; i++) {
2360                                 pdev = rmrr->devices[i];
2361                                 /*
2362                                  * some BIOS lists non-exist devices in DMAR
2363                                  * table.
2364                                  */
2365                                 if (!pdev)
2366                                         continue;
2367                                 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2368                                 if (ret)
2369                                         printk(KERN_ERR
2370                                  "IOMMU: mapping reserved region failed\n");
2371                         }
2372                 }
2373
2374                 iommu_prepare_isa();
2375         }
2376
2377         /*
2378          * for each drhd
2379          *   enable fault log
2380          *   global invalidate context cache
2381          *   global invalidate iotlb
2382          *   enable translation
2383          */
2384         for_each_drhd_unit(drhd) {
2385                 if (drhd->ignored)
2386                         continue;
2387                 iommu = drhd->iommu;
2388
2389                 iommu_flush_write_buffer(iommu);
2390
2391                 ret = dmar_set_interrupt(iommu);
2392                 if (ret)
2393                         goto error;
2394
2395                 iommu_set_root_entry(iommu);
2396
2397                 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2398                 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2399                 iommu_disable_protect_mem_regions(iommu);
2400
2401                 ret = iommu_enable_translation(iommu);
2402                 if (ret)
2403                         goto error;
2404         }
2405
2406         return 0;
2407 error:
2408         for_each_drhd_unit(drhd) {
2409                 if (drhd->ignored)
2410                         continue;
2411                 iommu = drhd->iommu;
2412                 free_iommu(iommu);
2413         }
2414         kfree(g_iommus);
2415         return ret;
2416 }
2417
2418 /* Returns a number of VTD pages, but aligned to MM page size */
2419 static inline unsigned long aligned_nrpages(unsigned long host_addr,
2420                                             size_t size)
2421 {
2422         host_addr &= ~PAGE_MASK;
2423         return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
2424 }
2425
2426 /* This takes a number of _MM_ pages, not VTD pages */
2427 static struct iova *intel_alloc_iova(struct device *dev,
2428                                      struct dmar_domain *domain,
2429                                      unsigned long nrpages, uint64_t dma_mask)
2430 {
2431         struct pci_dev *pdev = to_pci_dev(dev);
2432         struct iova *iova = NULL;
2433
2434         /* Restrict dma_mask to the width that the iommu can handle */
2435         dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2436
2437         if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
2438                 /*
2439                  * First try to allocate an io virtual address in
2440                  * DMA_BIT_MASK(32) and if that fails then try allocating
2441                  * from higher range
2442                  */
2443                 iova = alloc_iova(&domain->iovad, nrpages,
2444                                   IOVA_PFN(DMA_BIT_MASK(32)), 1);
2445                 if (iova)
2446                         return iova;
2447         }
2448         iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2449         if (unlikely(!iova)) {
2450                 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2451                        nrpages, pci_name(pdev));
2452                 return NULL;
2453         }
2454
2455         return iova;
2456 }
2457
2458 static struct dmar_domain *
2459 get_valid_domain_for_dev(struct pci_dev *pdev)
2460 {
2461         struct dmar_domain *domain;
2462         int ret;
2463
2464         domain = get_domain_for_dev(pdev,
2465                         DEFAULT_DOMAIN_ADDRESS_WIDTH);
2466         if (!domain) {
2467                 printk(KERN_ERR
2468                         "Allocating domain for %s failed", pci_name(pdev));
2469                 return NULL;
2470         }
2471
2472         /* make sure context mapping is ok */
2473         if (unlikely(!domain_context_mapped(pdev))) {
2474                 ret = domain_context_mapping(domain, pdev,
2475                                              CONTEXT_TT_MULTI_LEVEL);
2476                 if (ret) {
2477                         printk(KERN_ERR
2478                                 "Domain context map for %s failed",
2479                                 pci_name(pdev));
2480                         return NULL;
2481                 }
2482         }
2483
2484         return domain;
2485 }
2486
2487 static int iommu_dummy(struct pci_dev *pdev)
2488 {
2489         return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2490 }
2491
2492 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2493 static int iommu_no_mapping(struct device *dev)
2494 {
2495         struct pci_dev *pdev;
2496         int found;
2497
2498         if (unlikely(dev->bus != &pci_bus_type))
2499                 return 1;
2500
2501         pdev = to_pci_dev(dev);
2502         if (iommu_dummy(pdev))
2503                 return 1;
2504
2505         if (!iommu_identity_mapping)
2506                 return 0;
2507
2508         found = identity_mapping(pdev);
2509         if (found) {
2510                 if (iommu_should_identity_map(pdev, 0))
2511                         return 1;
2512                 else {
2513                         /*
2514                          * 32 bit DMA is removed from si_domain and fall back
2515                          * to non-identity mapping.
2516                          */
2517                         domain_remove_one_dev_info(si_domain, pdev);
2518                         printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2519                                pci_name(pdev));
2520                         return 0;
2521                 }
2522         } else {
2523                 /*
2524                  * In case of a detached 64 bit DMA device from vm, the device
2525                  * is put into si_domain for identity mapping.
2526                  */
2527                 if (iommu_should_identity_map(pdev, 0)) {
2528                         int ret;
2529                         ret = domain_add_dev_info(si_domain, pdev);
2530                         if (ret)
2531                                 return 0;
2532                         ret = domain_context_mapping(si_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
2533                         if (!ret) {
2534                                 printk(KERN_INFO "64bit %s uses identity mapping\n",
2535                                        pci_name(pdev));
2536                                 return 1;
2537                         }
2538                 }
2539         }
2540
2541         return 0;
2542 }
2543
2544 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2545                                      size_t size, int dir, u64 dma_mask)
2546 {
2547         struct pci_dev *pdev = to_pci_dev(hwdev);
2548         struct dmar_domain *domain;
2549         phys_addr_t start_paddr;
2550         struct iova *iova;
2551         int prot = 0;
2552         int ret;
2553         struct intel_iommu *iommu;
2554
2555         BUG_ON(dir == DMA_NONE);
2556
2557         if (iommu_no_mapping(hwdev))
2558                 return paddr;
2559
2560         domain = get_valid_domain_for_dev(pdev);
2561         if (!domain)
2562                 return 0;
2563
2564         iommu = domain_get_iommu(domain);
2565         size = aligned_nrpages(paddr, size);
2566
2567         iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2568                                 pdev->dma_mask);
2569         if (!iova)
2570                 goto error;
2571
2572         /*
2573          * Check if DMAR supports zero-length reads on write only
2574          * mappings..
2575          */
2576         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2577                         !cap_zlr(iommu->cap))
2578                 prot |= DMA_PTE_READ;
2579         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2580                 prot |= DMA_PTE_WRITE;
2581         /*
2582          * paddr - (paddr + size) might be partial page, we should map the whole
2583          * page.  Note: if two part of one page are separately mapped, we
2584          * might have two guest_addr mapping to the same host paddr, but this
2585          * is not a big problem
2586          */
2587         ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2588                                  paddr >> VTD_PAGE_SHIFT, size, prot);
2589         if (ret)
2590                 goto error;
2591
2592         /* it's a non-present to present mapping. Only flush if caching mode */
2593         if (cap_caching_mode(iommu->cap))
2594                 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
2595         else
2596                 iommu_flush_write_buffer(iommu);
2597
2598         start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2599         start_paddr += paddr & ~PAGE_MASK;
2600         return start_paddr;
2601
2602 error:
2603         if (iova)
2604                 __free_iova(&domain->iovad, iova);
2605         printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2606                 pci_name(pdev), size, (unsigned long long)paddr, dir);
2607         return 0;
2608 }
2609
2610 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2611                                  unsigned long offset, size_t size,
2612                                  enum dma_data_direction dir,
2613                                  struct dma_attrs *attrs)
2614 {
2615         return __intel_map_single(dev, page_to_phys(page) + offset, size,
2616                                   dir, to_pci_dev(dev)->dma_mask);
2617 }
2618
2619 static void flush_unmaps(void)
2620 {
2621         int i, j;
2622
2623         timer_on = 0;
2624
2625         /* just flush them all */
2626         for (i = 0; i < g_num_of_iommus; i++) {
2627                 struct intel_iommu *iommu = g_iommus[i];
2628                 if (!iommu)
2629                         continue;
2630
2631                 if (!deferred_flush[i].next)
2632                         continue;
2633
2634                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2635                                          DMA_TLB_GLOBAL_FLUSH);
2636                 for (j = 0; j < deferred_flush[i].next; j++) {
2637                         unsigned long mask;
2638                         struct iova *iova = deferred_flush[i].iova[j];
2639
2640                         mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2641                         mask = ilog2(mask >> VTD_PAGE_SHIFT);
2642                         iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2643                                         iova->pfn_lo << PAGE_SHIFT, mask);
2644                         __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2645                 }
2646                 deferred_flush[i].next = 0;
2647         }
2648
2649         list_size = 0;
2650 }
2651
2652 static void flush_unmaps_timeout(unsigned long data)
2653 {
2654         unsigned long flags;
2655
2656         spin_lock_irqsave(&async_umap_flush_lock, flags);
2657         flush_unmaps();
2658         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2659 }
2660
2661 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2662 {
2663         unsigned long flags;
2664         int next, iommu_id;
2665         struct intel_iommu *iommu;
2666
2667         spin_lock_irqsave(&async_umap_flush_lock, flags);
2668         if (list_size == HIGH_WATER_MARK)
2669                 flush_unmaps();
2670
2671         iommu = domain_get_iommu(dom);
2672         iommu_id = iommu->seq_id;
2673
2674         next = deferred_flush[iommu_id].next;
2675         deferred_flush[iommu_id].domain[next] = dom;
2676         deferred_flush[iommu_id].iova[next] = iova;
2677         deferred_flush[iommu_id].next++;
2678
2679         if (!timer_on) {
2680                 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2681                 timer_on = 1;
2682         }
2683         list_size++;
2684         spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2685 }
2686
2687 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2688                              size_t size, enum dma_data_direction dir,
2689                              struct dma_attrs *attrs)
2690 {
2691         struct pci_dev *pdev = to_pci_dev(dev);
2692         struct dmar_domain *domain;
2693         unsigned long start_pfn, last_pfn;
2694         struct iova *iova;
2695         struct intel_iommu *iommu;
2696
2697         if (iommu_no_mapping(dev))
2698                 return;
2699
2700         domain = find_domain(pdev);
2701         BUG_ON(!domain);
2702
2703         iommu = domain_get_iommu(domain);
2704
2705         iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2706         if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2707                       (unsigned long long)dev_addr))
2708                 return;
2709
2710         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2711         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2712
2713         pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2714                  pci_name(pdev), start_pfn, last_pfn);
2715
2716         /*  clear the whole page */
2717         dma_pte_clear_range(domain, start_pfn, last_pfn);
2718
2719         /* free page tables */
2720         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2721
2722         if (intel_iommu_strict) {
2723                 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2724                                       last_pfn - start_pfn + 1);
2725                 /* free iova */
2726                 __free_iova(&domain->iovad, iova);
2727         } else {
2728                 add_unmap(domain, iova);
2729                 /*
2730                  * queue up the release of the unmap to save the 1/6th of the
2731                  * cpu used up by the iotlb flush operation...
2732                  */
2733         }
2734 }
2735
2736 static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2737                                int dir)
2738 {
2739         intel_unmap_page(dev, dev_addr, size, dir, NULL);
2740 }
2741
2742 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2743                                   dma_addr_t *dma_handle, gfp_t flags)
2744 {
2745         void *vaddr;
2746         int order;
2747
2748         size = PAGE_ALIGN(size);
2749         order = get_order(size);
2750         flags &= ~(GFP_DMA | GFP_DMA32);
2751
2752         vaddr = (void *)__get_free_pages(flags, order);
2753         if (!vaddr)
2754                 return NULL;
2755         memset(vaddr, 0, size);
2756
2757         *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2758                                          DMA_BIDIRECTIONAL,
2759                                          hwdev->coherent_dma_mask);
2760         if (*dma_handle)
2761                 return vaddr;
2762         free_pages((unsigned long)vaddr, order);
2763         return NULL;
2764 }
2765
2766 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2767                                 dma_addr_t dma_handle)
2768 {
2769         int order;
2770
2771         size = PAGE_ALIGN(size);
2772         order = get_order(size);
2773
2774         intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2775         free_pages((unsigned long)vaddr, order);
2776 }
2777
2778 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2779                            int nelems, enum dma_data_direction dir,
2780                            struct dma_attrs *attrs)
2781 {
2782         struct pci_dev *pdev = to_pci_dev(hwdev);
2783         struct dmar_domain *domain;
2784         unsigned long start_pfn, last_pfn;
2785         struct iova *iova;
2786         struct intel_iommu *iommu;
2787
2788         if (iommu_no_mapping(hwdev))
2789                 return;
2790
2791         domain = find_domain(pdev);
2792         BUG_ON(!domain);
2793
2794         iommu = domain_get_iommu(domain);
2795
2796         iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2797         if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2798                       (unsigned long long)sglist[0].dma_address))
2799                 return;
2800
2801         start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2802         last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2803
2804         /*  clear the whole page */
2805         dma_pte_clear_range(domain, start_pfn, last_pfn);
2806
2807         /* free page tables */
2808         dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2809
2810         iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2811                               (last_pfn - start_pfn + 1));
2812
2813         /* free iova */
2814         __free_iova(&domain->iovad, iova);
2815 }
2816
2817 static int intel_nontranslate_map_sg(struct device *hddev,
2818         struct scatterlist *sglist, int nelems, int dir)
2819 {
2820         int i;
2821         struct scatterlist *sg;
2822
2823         for_each_sg(sglist, sg, nelems, i) {
2824                 BUG_ON(!sg_page(sg));
2825                 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2826                 sg->dma_length = sg->length;
2827         }
2828         return nelems;
2829 }
2830
2831 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2832                         enum dma_data_direction dir, struct dma_attrs *attrs)
2833 {
2834         int i;
2835         struct pci_dev *pdev = to_pci_dev(hwdev);
2836         struct dmar_domain *domain;
2837         size_t size = 0;
2838         int prot = 0;
2839         size_t offset_pfn = 0;
2840         struct iova *iova = NULL;
2841         int ret;
2842         struct scatterlist *sg;
2843         unsigned long start_vpfn;
2844         struct intel_iommu *iommu;
2845
2846         BUG_ON(dir == DMA_NONE);
2847         if (iommu_no_mapping(hwdev))
2848                 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2849
2850         domain = get_valid_domain_for_dev(pdev);
2851         if (!domain)
2852                 return 0;
2853
2854         iommu = domain_get_iommu(domain);
2855
2856         for_each_sg(sglist, sg, nelems, i)
2857                 size += aligned_nrpages(sg->offset, sg->length);
2858
2859         iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2860                                 pdev->dma_mask);
2861         if (!iova) {
2862                 sglist->dma_length = 0;
2863                 return 0;
2864         }
2865
2866         /*
2867          * Check if DMAR supports zero-length reads on write only
2868          * mappings..
2869          */
2870         if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2871                         !cap_zlr(iommu->cap))
2872                 prot |= DMA_PTE_READ;
2873         if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2874                 prot |= DMA_PTE_WRITE;
2875
2876         start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
2877
2878         ret = domain_sg_mapping(domain, start_vpfn, sglist, mm_to_dma_pfn(size), prot);
2879         if (unlikely(ret)) {
2880                 /*  clear the page */
2881                 dma_pte_clear_range(domain, start_vpfn,
2882                                     start_vpfn + size - 1);
2883                 /* free page tables */
2884                 dma_pte_free_pagetable(domain, start_vpfn,
2885                                        start_vpfn + size - 1);
2886                 /* free iova */
2887                 __free_iova(&domain->iovad, iova);
2888                 return 0;
2889         }
2890
2891         /* it's a non-present to present mapping. Only flush if caching mode */
2892         if (cap_caching_mode(iommu->cap))
2893                 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
2894         else
2895                 iommu_flush_write_buffer(iommu);
2896
2897         return nelems;
2898 }
2899
2900 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2901 {
2902         return !dma_addr;
2903 }
2904
2905 struct dma_map_ops intel_dma_ops = {
2906         .alloc_coherent = intel_alloc_coherent,
2907         .free_coherent = intel_free_coherent,
2908         .map_sg = intel_map_sg,
2909         .unmap_sg = intel_unmap_sg,
2910         .map_page = intel_map_page,
2911         .unmap_page = intel_unmap_page,
2912         .mapping_error = intel_mapping_error,
2913 };
2914
2915 static inline int iommu_domain_cache_init(void)
2916 {
2917         int ret = 0;
2918
2919         iommu_domain_cache = kmem_cache_create("iommu_domain",
2920                                          sizeof(struct dmar_domain),
2921                                          0,
2922                                          SLAB_HWCACHE_ALIGN,
2923
2924                                          NULL);
2925         if (!iommu_domain_cache) {
2926                 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2927                 ret = -ENOMEM;
2928         }
2929
2930         return ret;
2931 }
2932
2933 static inline int iommu_devinfo_cache_init(void)
2934 {
2935         int ret = 0;
2936
2937         iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2938                                          sizeof(struct device_domain_info),
2939                                          0,
2940                                          SLAB_HWCACHE_ALIGN,
2941                                          NULL);
2942         if (!iommu_devinfo_cache) {
2943                 printk(KERN_ERR "Couldn't create devinfo cache\n");
2944                 ret = -ENOMEM;
2945         }
2946
2947         return ret;
2948 }
2949
2950 static inline int iommu_iova_cache_init(void)
2951 {
2952         int ret = 0;
2953
2954         iommu_iova_cache = kmem_cache_create("iommu_iova",
2955                                          sizeof(struct iova),
2956                                          0,
2957                                          SLAB_HWCACHE_ALIGN,
2958                                          NULL);
2959         if (!iommu_iova_cache) {
2960                 printk(KERN_ERR "Couldn't create iova cache\n");
2961                 ret = -ENOMEM;
2962         }
2963
2964         return ret;
2965 }
2966
2967 static int __init iommu_init_mempool(void)
2968 {
2969         int ret;
2970         ret = iommu_iova_cache_init();
2971         if (ret)
2972                 return ret;
2973
2974         ret = iommu_domain_cache_init();
2975         if (ret)
2976                 goto domain_error;
2977
2978         ret = iommu_devinfo_cache_init();
2979         if (!ret)
2980                 return ret;
2981
2982         kmem_cache_destroy(iommu_domain_cache);
2983 domain_error:
2984         kmem_cache_destroy(iommu_iova_cache);
2985
2986         return -ENOMEM;
2987 }
2988
2989 static void __init iommu_exit_mempool(void)
2990 {
2991         kmem_cache_destroy(iommu_devinfo_cache);
2992         kmem_cache_destroy(iommu_domain_cache);
2993         kmem_cache_destroy(iommu_iova_cache);
2994
2995 }
2996
2997 static void __init init_no_remapping_devices(void)
2998 {
2999         struct dmar_drhd_unit *drhd;
3000
3001         for_each_drhd_unit(drhd) {
3002                 if (!drhd->include_all) {
3003                         int i;
3004                         for (i = 0; i < drhd->devices_cnt; i++)
3005                                 if (drhd->devices[i] != NULL)
3006                                         break;
3007                         /* ignore DMAR unit if no pci devices exist */
3008                         if (i == drhd->devices_cnt)
3009                                 drhd->ignored = 1;
3010                 }
3011         }
3012
3013         if (dmar_map_gfx)
3014                 return;
3015
3016         for_each_drhd_unit(drhd) {
3017                 int i;
3018                 if (drhd->ignored || drhd->include_all)
3019                         continue;
3020
3021                 for (i = 0; i < drhd->devices_cnt; i++)
3022                         if (drhd->devices[i] &&
3023                                 !IS_GFX_DEVICE(drhd->devices[i]))
3024                                 break;
3025
3026                 if (i < drhd->devices_cnt)
3027                         continue;
3028
3029                 /* bypass IOMMU if it is just for gfx devices */
3030                 drhd->ignored = 1;
3031                 for (i = 0; i < drhd->devices_cnt; i++) {
3032                         if (!drhd->devices[i])
3033                                 continue;
3034                         drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3035                 }
3036         }
3037 }
3038
3039 #ifdef CONFIG_SUSPEND
3040 static int init_iommu_hw(void)
3041 {
3042         struct dmar_drhd_unit *drhd;
3043         struct intel_iommu *iommu = NULL;
3044
3045         for_each_active_iommu(iommu, drhd)
3046                 if (iommu->qi)
3047                         dmar_reenable_qi(iommu);
3048
3049         for_each_active_iommu(iommu, drhd) {
3050                 iommu_flush_write_buffer(iommu);
3051
3052                 iommu_set_root_entry(iommu);
3053
3054                 iommu->flush.flush_context(iommu, 0, 0, 0,
3055                                            DMA_CCMD_GLOBAL_INVL);
3056                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3057                                          DMA_TLB_GLOBAL_FLUSH);
3058                 iommu_disable_protect_mem_regions(iommu);
3059                 iommu_enable_translation(iommu);
3060         }
3061
3062         return 0;
3063 }
3064
3065 static void iommu_flush_all(void)
3066 {
3067         struct dmar_drhd_unit *drhd;
3068         struct intel_iommu *iommu;
3069
3070         for_each_active_iommu(iommu, drhd) {
3071                 iommu->flush.flush_context(iommu, 0, 0, 0,
3072                                            DMA_CCMD_GLOBAL_INVL);
3073                 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3074                                          DMA_TLB_GLOBAL_FLUSH);
3075         }
3076 }
3077
3078 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3079 {
3080         struct dmar_drhd_unit *drhd;
3081         struct intel_iommu *iommu = NULL;
3082         unsigned long flag;
3083
3084         for_each_active_iommu(iommu, drhd) {
3085                 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3086                                                  GFP_ATOMIC);
3087                 if (!iommu->iommu_state)
3088                         goto nomem;
3089         }
3090
3091         iommu_flush_all();
3092
3093         for_each_active_iommu(iommu, drhd) {
3094                 iommu_disable_translation(iommu);
3095
3096                 spin_lock_irqsave(&iommu->register_lock, flag);
3097
3098                 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3099                         readl(iommu->reg + DMAR_FECTL_REG);
3100                 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3101                         readl(iommu->reg + DMAR_FEDATA_REG);
3102                 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3103                         readl(iommu->reg + DMAR_FEADDR_REG);
3104                 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3105                         readl(iommu->reg + DMAR_FEUADDR_REG);
3106
3107                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3108         }
3109         return 0;
3110
3111 nomem:
3112         for_each_active_iommu(iommu, drhd)
3113                 kfree(iommu->iommu_state);
3114
3115         return -ENOMEM;
3116 }
3117
3118 static int iommu_resume(struct sys_device *dev)
3119 {
3120         struct dmar_drhd_unit *drhd;
3121         struct intel_iommu *iommu = NULL;
3122         unsigned long flag;
3123
3124         if (init_iommu_hw()) {
3125                 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3126                 return -EIO;
3127         }
3128
3129         for_each_active_iommu(iommu, drhd) {
3130
3131                 spin_lock_irqsave(&iommu->register_lock, flag);
3132
3133                 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3134                         iommu->reg + DMAR_FECTL_REG);
3135                 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3136                         iommu->reg + DMAR_FEDATA_REG);
3137                 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3138                         iommu->reg + DMAR_FEADDR_REG);
3139                 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3140                         iommu->reg + DMAR_FEUADDR_REG);
3141
3142                 spin_unlock_irqrestore(&iommu->register_lock, flag);
3143         }
3144
3145         for_each_active_iommu(iommu, drhd)
3146                 kfree(iommu->iommu_state);
3147
3148         return 0;
3149 }
3150
3151 static struct sysdev_class iommu_sysclass = {
3152         .name           = "iommu",
3153         .resume         = iommu_resume,
3154         .suspend        = iommu_suspend,
3155 };
3156
3157 static struct sys_device device_iommu = {
3158         .cls    = &iommu_sysclass,
3159 };
3160
3161 static int __init init_iommu_sysfs(void)
3162 {
3163         int error;
3164
3165         error = sysdev_class_register(&iommu_sysclass);
3166         if (error)
3167                 return error;
3168
3169         error = sysdev_register(&device_iommu);
3170         if (error)
3171                 sysdev_class_unregister(&iommu_sysclass);
3172
3173         return error;
3174 }
3175
3176 #else
3177 static int __init init_iommu_sysfs(void)
3178 {
3179         return 0;
3180 }
3181 #endif  /* CONFIG_PM */
3182
3183 int __init intel_iommu_init(void)
3184 {
3185         int ret = 0;
3186
3187         if (dmar_table_init())
3188                 return  -ENODEV;
3189
3190         if (dmar_dev_scope_init())
3191                 return  -ENODEV;
3192
3193         /*
3194          * Check the need for DMA-remapping initialization now.
3195          * Above initialization will also be used by Interrupt-remapping.
3196          */
3197         if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
3198                 return -ENODEV;
3199
3200         iommu_init_mempool();
3201         dmar_init_reserved_ranges();
3202
3203         init_no_remapping_devices();
3204
3205         ret = init_dmars();
3206         if (ret) {
3207                 printk(KERN_ERR "IOMMU: dmar init failed\n");
3208                 put_iova_domain(&reserved_iova_list);
3209                 iommu_exit_mempool();
3210                 return ret;
3211         }
3212         printk(KERN_INFO
3213         "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3214
3215         init_timer(&unmap_timer);
3216         force_iommu = 1;
3217
3218         if (!iommu_pass_through) {
3219                 printk(KERN_INFO
3220                        "Multi-level page-table translation for DMAR.\n");
3221                 dma_ops = &intel_dma_ops;
3222         } else
3223                 printk(KERN_INFO
3224                        "DMAR: Pass through translation for DMAR.\n");
3225
3226         init_iommu_sysfs();
3227
3228         register_iommu(&intel_iommu_ops);
3229
3230         return 0;
3231 }
3232
3233 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3234                                            struct pci_dev *pdev)
3235 {
3236         struct pci_dev *tmp, *parent;
3237
3238         if (!iommu || !pdev)
3239                 return;
3240
3241         /* dependent device detach */
3242         tmp = pci_find_upstream_pcie_bridge(pdev);
3243         /* Secondary interface's bus number and devfn 0 */
3244         if (tmp) {
3245                 parent = pdev->bus->self;
3246                 while (parent != tmp) {
3247                         iommu_detach_dev(iommu, parent->bus->number,
3248                                          parent->devfn);
3249                         parent = parent->bus->self;
3250                 }
3251                 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3252                         iommu_detach_dev(iommu,
3253                                 tmp->subordinate->number, 0);
3254                 else /* this is a legacy PCI bridge */
3255                         iommu_detach_dev(iommu, tmp->bus->number,
3256                                          tmp->devfn);
3257         }
3258 }
3259
3260 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3261                                           struct pci_dev *pdev)
3262 {
3263         struct device_domain_info *info;
3264         struct intel_iommu *iommu;
3265         unsigned long flags;
3266         int found = 0;
3267         struct list_head *entry, *tmp;
3268
3269         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3270                                 pdev->devfn);
3271         if (!iommu)
3272                 return;
3273
3274         spin_lock_irqsave(&device_domain_lock, flags);
3275         list_for_each_safe(entry, tmp, &domain->devices) {
3276                 info = list_entry(entry, struct device_domain_info, link);
3277                 /* No need to compare PCI domain; it has to be the same */
3278                 if (info->bus == pdev->bus->number &&
3279                     info->devfn == pdev->devfn) {
3280                         list_del(&info->link);
3281                         list_del(&info->global);
3282                         if (info->dev)
3283                                 info->dev->dev.archdata.iommu = NULL;
3284                         spin_unlock_irqrestore(&device_domain_lock, flags);
3285
3286                         iommu_disable_dev_iotlb(info);
3287                         iommu_detach_dev(iommu, info->bus, info->devfn);
3288                         iommu_detach_dependent_devices(iommu, pdev);
3289                         free_devinfo_mem(info);
3290
3291                         spin_lock_irqsave(&device_domain_lock, flags);
3292
3293                         if (found)
3294                                 break;
3295                         else
3296                                 continue;
3297                 }
3298
3299                 /* if there is no other devices under the same iommu
3300                  * owned by this domain, clear this iommu in iommu_bmp
3301                  * update iommu count and coherency
3302                  */
3303                 if (iommu == device_to_iommu(info->segment, info->bus,
3304                                             info->devfn))
3305                         found = 1;
3306         }
3307
3308         if (found == 0) {
3309                 unsigned long tmp_flags;
3310                 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3311                 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3312                 domain->iommu_count--;
3313                 domain_update_iommu_cap(domain);
3314                 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3315         }
3316
3317         spin_unlock_irqrestore(&device_domain_lock, flags);
3318 }
3319
3320 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3321 {
3322         struct device_domain_info *info;
3323         struct intel_iommu *iommu;
3324         unsigned long flags1, flags2;
3325
3326         spin_lock_irqsave(&device_domain_lock, flags1);
3327         while (!list_empty(&domain->devices)) {
3328                 info = list_entry(domain->devices.next,
3329                         struct device_domain_info, link);
3330                 list_del(&info->link);
3331                 list_del(&info->global);
3332                 if (info->dev)
3333                         info->dev->dev.archdata.iommu = NULL;
3334
3335                 spin_unlock_irqrestore(&device_domain_lock, flags1);
3336
3337                 iommu_disable_dev_iotlb(info);
3338                 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3339                 iommu_detach_dev(iommu, info->bus, info->devfn);
3340                 iommu_detach_dependent_devices(iommu, info->dev);
3341
3342                 /* clear this iommu in iommu_bmp, update iommu count
3343                  * and capabilities
3344                  */
3345                 spin_lock_irqsave(&domain->iommu_lock, flags2);
3346                 if (test_and_clear_bit(iommu->seq_id,
3347                                        &domain->iommu_bmp)) {
3348                         domain->iommu_count--;
3349                         domain_update_iommu_cap(domain);
3350                 }
3351                 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3352
3353                 free_devinfo_mem(info);
3354                 spin_lock_irqsave(&device_domain_lock, flags1);
3355         }
3356         spin_unlock_irqrestore(&device_domain_lock, flags1);
3357 }
3358
3359 /* domain id for virtual machine, it won't be set in context */
3360 static unsigned long vm_domid;
3361
3362 static int vm_domain_min_agaw(struct dmar_domain *domain)
3363 {
3364         int i;
3365         int min_agaw = domain->agaw;
3366
3367         i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3368         for (; i < g_num_of_iommus; ) {
3369                 if (min_agaw > g_iommus[i]->agaw)
3370                         min_agaw = g_iommus[i]->agaw;
3371
3372                 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3373         }
3374
3375         return min_agaw;
3376 }
3377
3378 static struct dmar_domain *iommu_alloc_vm_domain(void)
3379 {
3380         struct dmar_domain *domain;
3381
3382         domain = alloc_domain_mem();
3383         if (!domain)
3384                 return NULL;
3385
3386         domain->id = vm_domid++;
3387         memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3388         domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3389
3390         return domain;
3391 }
3392
3393 static int md_domain_init(struct dmar_domain *domain, int guest_width)
3394 {
3395         int adjust_width;
3396
3397         init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3398         spin_lock_init(&domain->iommu_lock);
3399
3400         domain_reserve_special_ranges(domain);
3401
3402         /* calculate AGAW */
3403         domain->gaw = guest_width;
3404         adjust_width = guestwidth_to_adjustwidth(guest_width);
3405         domain->agaw = width_to_agaw(adjust_width);
3406
3407         INIT_LIST_HEAD(&domain->devices);
3408
3409         domain->iommu_count = 0;
3410         domain->iommu_coherency = 0;
3411         domain->max_addr = 0;
3412
3413         /* always allocate the top pgd */
3414         domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3415         if (!domain->pgd)
3416                 return -ENOMEM;
3417         domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3418         return 0;
3419 }
3420
3421 static void iommu_free_vm_domain(struct dmar_domain *domain)
3422 {
3423         unsigned long flags;
3424         struct dmar_drhd_unit *drhd;
3425         struct intel_iommu *iommu;
3426         unsigned long i;
3427         unsigned long ndomains;
3428
3429         for_each_drhd_unit(drhd) {
3430                 if (drhd->ignored)
3431                         continue;
3432                 iommu = drhd->iommu;
3433
3434                 ndomains = cap_ndoms(iommu->cap);
3435                 i = find_first_bit(iommu->domain_ids, ndomains);
3436                 for (; i < ndomains; ) {
3437                         if (iommu->domains[i] == domain) {
3438                                 spin_lock_irqsave(&iommu->lock, flags);
3439                                 clear_bit(i, iommu->domain_ids);
3440                                 iommu->domains[i] = NULL;
3441                                 spin_unlock_irqrestore(&iommu->lock, flags);
3442                                 break;
3443                         }
3444                         i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3445                 }
3446         }
3447 }
3448
3449 static void vm_domain_exit(struct dmar_domain *domain)
3450 {
3451         /* Domain 0 is reserved, so dont process it */
3452         if (!domain)
3453                 return;
3454
3455         vm_domain_remove_all_dev_info(domain);
3456         /* destroy iovas */
3457         put_iova_domain(&domain->iovad);
3458
3459         /* clear ptes */
3460         dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3461
3462         /* free page tables */
3463         dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3464
3465         iommu_free_vm_domain(domain);
3466         free_domain_mem(domain);
3467 }
3468
3469 static int intel_iommu_domain_init(struct iommu_domain *domain)
3470 {
3471         struct dmar_domain *dmar_domain;
3472
3473         dmar_domain = iommu_alloc_vm_domain();
3474         if (!dmar_domain) {
3475                 printk(KERN_ERR
3476                         "intel_iommu_domain_init: dmar_domain == NULL\n");
3477                 return -ENOMEM;
3478         }
3479         if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3480                 printk(KERN_ERR
3481                         "intel_iommu_domain_init() failed\n");
3482                 vm_domain_exit(dmar_domain);
3483                 return -ENOMEM;
3484         }
3485         domain->priv = dmar_domain;
3486
3487         return 0;
3488 }
3489
3490 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3491 {
3492         struct dmar_domain *dmar_domain = domain->priv;
3493
3494         domain->priv = NULL;
3495         vm_domain_exit(dmar_domain);
3496 }
3497
3498 static int intel_iommu_attach_device(struct iommu_domain *domain,
3499                                      struct device *dev)
3500 {
3501         struct dmar_domain *dmar_domain = domain->priv;
3502         struct pci_dev *pdev = to_pci_dev(dev);
3503         struct intel_iommu *iommu;
3504         int addr_width;
3505         u64 end;
3506         int ret;
3507
3508         /* normally pdev is not mapped */
3509         if (unlikely(domain_context_mapped(pdev))) {
3510                 struct dmar_domain *old_domain;
3511
3512                 old_domain = find_domain(pdev);
3513                 if (old_domain) {
3514                         if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3515                             dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3516                                 domain_remove_one_dev_info(old_domain, pdev);
3517                         else
3518                                 domain_remove_dev_info(old_domain);
3519                 }
3520         }
3521
3522         iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3523                                 pdev->devfn);
3524         if (!iommu)
3525                 return -ENODEV;
3526
3527         /* check if this iommu agaw is sufficient for max mapped address */
3528         addr_width = agaw_to_width(iommu->agaw);
3529         end = DOMAIN_MAX_ADDR(addr_width);
3530         end = end & VTD_PAGE_MASK;
3531         if (end < dmar_domain->max_addr) {
3532                 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3533                        "sufficient for the mapped address (%llx)\n",
3534                        __func__, iommu->agaw, dmar_domain->max_addr);
3535                 return -EFAULT;
3536         }
3537
3538         ret = domain_add_dev_info(dmar_domain, pdev);
3539         if (ret)
3540                 return ret;
3541
3542         ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3543         return ret;
3544 }
3545
3546 static void intel_iommu_detach_device(struct iommu_domain *domain,
3547                                       struct device *dev)
3548 {
3549         struct dmar_domain *dmar_domain = domain->priv;
3550         struct pci_dev *pdev = to_pci_dev(dev);
3551
3552         domain_remove_one_dev_info(dmar_domain, pdev);
3553 }
3554
3555 static int intel_iommu_map_range(struct iommu_domain *domain,
3556                                  unsigned long iova, phys_addr_t hpa,
3557                                  size_t size, int iommu_prot)
3558 {
3559         struct dmar_domain *dmar_domain = domain->priv;
3560         u64 max_addr;
3561         int addr_width;
3562         int prot = 0;
3563         int ret;
3564
3565         if (iommu_prot & IOMMU_READ)
3566                 prot |= DMA_PTE_READ;
3567         if (iommu_prot & IOMMU_WRITE)
3568                 prot |= DMA_PTE_WRITE;
3569         if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3570                 prot |= DMA_PTE_SNP;
3571
3572         max_addr = iova + size;
3573         if (dmar_domain->max_addr < max_addr) {
3574                 int min_agaw;
3575                 u64 end;
3576
3577                 /* check if minimum agaw is sufficient for mapped address */
3578                 min_agaw = vm_domain_min_agaw(dmar_domain);
3579                 addr_width = agaw_to_width(min_agaw);
3580                 end = DOMAIN_MAX_ADDR(addr_width);
3581                 end = end & VTD_PAGE_MASK;
3582                 if (end < max_addr) {
3583                         printk(KERN_ERR "%s: iommu agaw (%d) is not "
3584                                "sufficient for the mapped address (%llx)\n",
3585                                __func__, min_agaw, max_addr);
3586                         return -EFAULT;
3587                 }
3588                 dmar_domain->max_addr = max_addr;
3589         }
3590         /* Round up size to next multiple of PAGE_SIZE, if it and
3591            the low bits of hpa would take us onto the next page */
3592         size = aligned_nrpages(hpa, size);
3593         ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3594                                  hpa >> VTD_PAGE_SHIFT, size, prot);
3595         return ret;
3596 }
3597
3598 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3599                                     unsigned long iova, size_t size)
3600 {
3601         struct dmar_domain *dmar_domain = domain->priv;
3602
3603         if (!size)
3604                 return;
3605
3606         dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3607                             (iova + size - 1) >> VTD_PAGE_SHIFT);
3608
3609         if (dmar_domain->max_addr == iova + size)
3610                 dmar_domain->max_addr = iova;
3611 }
3612
3613 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3614                                             unsigned long iova)
3615 {
3616         struct dmar_domain *dmar_domain = domain->priv;
3617         struct dma_pte *pte;
3618         u64 phys = 0;
3619
3620         pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
3621         if (pte)
3622                 phys = dma_pte_addr(pte);
3623
3624         return phys;
3625 }
3626
3627 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3628                                       unsigned long cap)
3629 {
3630         struct dmar_domain *dmar_domain = domain->priv;
3631
3632         if (cap == IOMMU_CAP_CACHE_COHERENCY)
3633                 return dmar_domain->iommu_snooping;
3634
3635         return 0;
3636 }
3637
3638 static struct iommu_ops intel_iommu_ops = {
3639         .domain_init    = intel_iommu_domain_init,
3640         .domain_destroy = intel_iommu_domain_destroy,
3641         .attach_dev     = intel_iommu_attach_device,
3642         .detach_dev     = intel_iommu_detach_device,
3643         .map            = intel_iommu_map_range,
3644         .unmap          = intel_iommu_unmap_range,
3645         .iova_to_phys   = intel_iommu_iova_to_phys,
3646         .domain_has_cap = intel_iommu_domain_has_cap,
3647 };
3648
3649 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3650 {
3651         /*
3652          * Mobile 4 Series Chipset neglects to set RWBF capability,
3653          * but needs it:
3654          */
3655         printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3656         rwbf_quirk = 1;
3657 }
3658
3659 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);