drivers/net/wireless/wl1251/boot.c

   1 /*
   2  * This file is part of wl1251
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #include <linux/slab.h>
  23
  24 #include "reg.h"
  25 #include "boot.h"
  26 #include "io.h"
  27 #include "spi.h"
  28 #include "event.h"
  29 #include "acx.h"
  30
  31 void wl1251_boot_target_enable_interrupts(struct wl1251 *wl)
  32 {
  33         wl1251_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
  34         wl1251_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
  35 }
  36
  37 int wl1251_boot_soft_reset(struct wl1251 *wl)
  38 {
  39         unsigned long timeout;
  40         u32 boot_data;
  41
  42         /* perform soft reset */
  43         wl1251_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
  44
  45         /* SOFT_RESET is self clearing */
  46         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
  47         while (1) {
  48                 boot_data = wl1251_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
  49                 wl1251_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
  50                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
  51                         break;
  52
  53                 if (time_after(jiffies, timeout)) {
  54                         /* 1.2 check pWhalBus->uSelfClearTime if the
  55                          * timeout was reached */
  56                         wl1251_error("soft reset timeout");
  57                         return -1;
  58                 }
  59
  60                 udelay(SOFT_RESET_STALL_TIME);
  61         }
  62
  63         /* disable Rx/Tx */
  64         wl1251_reg_write32(wl, ENABLE, 0x0);
  65
  66         /* disable auto calibration on start*/
  67         wl1251_reg_write32(wl, SPARE_A2, 0xffff);
  68
  69         return 0;
  70 }
  71
  72 int wl1251_boot_init_seq(struct wl1251 *wl)
  73 {
  74         u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq;
  75
  76         /*
  77          * col #1: INTEGER_DIVIDER
  78          * col #2: FRACTIONAL_DIVIDER
  79          * col #3: ATTN_BB
  80          * col #4: ALPHA_BB
  81          * col #5: STOP_TIME_BB
  82          * col #6: BB_PLL_LOOP_FILTER
  83          */
  84         static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = {
  85
  86                 {   83, 87381,  0xB, 5, 0xF00,  3}, /* REF_FREQ_19_2*/
  87                 {   61, 141154, 0xB, 5, 0x1450, 2}, /* REF_FREQ_26_0*/
  88                 {   41, 174763, 0xC, 6, 0x2D00, 1}, /* REF_FREQ_38_4*/
  89                 {   40, 0,      0xC, 6, 0x2EE0, 1}, /* REF_FREQ_40_0*/
  90                 {   47, 162280, 0xC, 6, 0x2760, 1}  /* REF_FREQ_33_6        */
  91         };
  92
  93         /* read NVS params */
  94         scr_pad6 = wl1251_reg_read32(wl, SCR_PAD6);
  95         wl1251_debug(DEBUG_BOOT, "scr_pad6 0x%x", scr_pad6);
  96
  97         /* read ELP_CMD */
  98         elp_cmd = wl1251_reg_read32(wl, ELP_CMD);
  99         wl1251_debug(DEBUG_BOOT, "elp_cmd 0x%x", elp_cmd);
 100
 101         /* set the BB calibration time to be 300 usec (PLL_CAL_TIME) */
 102         ref_freq = scr_pad6 & 0x000000FF;
 103         wl1251_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq);
 104
 105         wl1251_reg_write32(wl, PLL_CAL_TIME, 0x9);
 106
 107         /*
 108          * set the clock buffer time (CLK_BUF_TIME) to
 109          * PG 1.1 & 1.0: 760usec
 110          * PG 1.2: 210usec
 111          */
 112         if (wl->chip_id == CHIP_ID_1251_PG10 ||
 113             wl->chip_id == CHIP_ID_1251_PG11)
 114                 tmp = 0x19;
 115         else
 116                 tmp = 0x6;
 117         wl1251_reg_write32(wl, CLK_BUF_TIME, tmp);
 118
 119         /*
 120          * set the clock detect feature to work in the restart wu procedure
 121          * (ELP_CFG_MODE[14]) and Select the clock source type
 122          * (ELP_CFG_MODE[13:12])
 123          */
 124         tmp = ((scr_pad6 & 0x0000FF00) << 4) | 0x00004000;
 125         wl1251_reg_write32(wl, ELP_CFG_MODE, tmp);
 126
 127         /* PG 1.2: enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */
 128         if (wl->chip_id != CHIP_ID_1251_PG10 &&
 129             wl->chip_id != CHIP_ID_1251_PG11) {
 130                 elp_cmd |= 0x00000040;
 131                 wl1251_reg_write32(wl, ELP_CMD, elp_cmd);
 132         }
 133
 134         /* Set the BB PLL stable time (PLL_STABLE_TIME) to
 135          * PG 1.1 & 1.0: 30usec
 136          * PG 1.2: 1000usec */
 137         if (wl->chip_id == CHIP_ID_1251_PG10 ||
 138             wl->chip_id == CHIP_ID_1251_PG11)
 139                 tmp = 0x00;
 140         else
 141                 tmp = 0x20;
 142         wl1251_reg_write32(wl, CFG_PLL_SYNC_CNT, tmp);
 143
 144         if (wl->chip_id != CHIP_ID_1251_PG10 &&
 145             wl->chip_id != CHIP_ID_1251_PG11) {
 146                 /* PG 1.2: read clock request time */
 147                 init_data = wl1251_reg_read32(wl, CLK_REQ_TIME);
 148
 149                 /*
 150                  * PG 1.2: set the clock request time to be
 151                  * ref_clk_settling_time - 1ms = 4ms
 152                  */
 153                 if (init_data > 0x21)
 154                         tmp = init_data - 0x21;
 155                 else
 156                         tmp = 0;
 157                 wl1251_reg_write32(wl, CLK_REQ_TIME, tmp);
 158         }
 159
 160         /* set BB PLL configurations in RF AFE */
 161         wl1251_reg_write32(wl, 0x003058cc, 0x4B5);
 162
 163         /* set RF_AFE_REG_5 */
 164         wl1251_reg_write32(wl, 0x003058d4, 0x50);
 165
 166         /* set RF_AFE_CTRL_REG_2 */
 167         wl1251_reg_write32(wl, 0x00305948, 0x11c001);
 168
 169         /*
 170          * change RF PLL and BB PLL divider for VCO clock and adjust VCO
 171          * bais current(RF_AFE_REG_13)
 172          */
 173         wl1251_reg_write32(wl, 0x003058f4, 0x1e);
 174
 175         /* set BB PLL configurations */
 176         tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000;
 177         wl1251_reg_write32(wl, 0x00305840, tmp);
 178
 179         /* set fractional divider according to Appendix C-BB PLL
 180          * Calculations
 181          */
 182         tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER];
 183         wl1251_reg_write32(wl, 0x00305844, tmp);
 184
 185         /* set the initial data for the sigma delta */
 186         wl1251_reg_write32(wl, 0x00305848, 0x3039);
 187
 188         /*
 189          * set the accumulator attenuation value, calibration loop1
 190          * (alpha), calibration loop2 (beta), calibration loop3 (gamma) and
 191          * the VCO gain
 192          */
 193         tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) |
 194                 (LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1;
 195         wl1251_reg_write32(wl, 0x00305854, tmp);
 196
 197         /*
 198          * set the calibration stop time after holdoff time expires and set
 199          * settling time HOLD_OFF_TIME_BB
 200          */
 201         tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000;
 202         wl1251_reg_write32(wl, 0x00305858, tmp);
 203
 204         /*
 205          * set BB PLL Loop filter capacitor3- BB_C3[2:0] and set BB PLL
 206          * constant leakage current to linearize PFD to 0uA -
 207          * BB_ILOOPF[7:3]
 208          */
 209         tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030;
 210         wl1251_reg_write32(wl, 0x003058f8, tmp);
 211
 212         /*
 213          * set regulator output voltage for n divider to
 214          * 1.35-BB_REFDIV[1:0], set charge pump current- BB_CPGAIN[4:2],
 215          * set BB PLL Loop filter capacitor2- BB_C2[7:5], set gain of BB
 216          * PLL auto-call to normal mode- BB_CALGAIN_3DB[8]
 217          */
 218         wl1251_reg_write32(wl, 0x003058f0, 0x29);
 219
 220         /* enable restart wakeup sequence (ELP_CMD[0]) */
 221         wl1251_reg_write32(wl, ELP_CMD, elp_cmd | 0x1);
 222
 223         /* restart sequence completed */
 224         udelay(2000);
 225
 226         return 0;
 227 }
 228
 229 static void wl1251_boot_set_ecpu_ctrl(struct wl1251 *wl, u32 flag)
 230 {
 231         u32 cpu_ctrl;
 232
 233         /* 10.5.0 run the firmware (I) */
 234         cpu_ctrl = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
 235
 236         /* 10.5.1 run the firmware (II) */
 237         cpu_ctrl &= ~flag;
 238         wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
 239 }
 240
 241 int wl1251_boot_run_firmware(struct wl1251 *wl)
 242 {
 243         int loop, ret;
 244         u32 chip_id, acx_intr;
 245
 246         wl1251_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
 247
 248         chip_id = wl1251_reg_read32(wl, CHIP_ID_B);
 249
 250         wl1251_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
 251
 252         if (chip_id != wl->chip_id) {
 253                 wl1251_error("chip id doesn't match after firmware boot");
 254                 return -EIO;
 255         }
 256
 257         /* wait for init to complete */
 258         loop = 0;
 259         while (loop++ < INIT_LOOP) {
 260                 udelay(INIT_LOOP_DELAY);
 261                 acx_intr = wl1251_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
 262
 263                 if (acx_intr == 0xffffffff) {
 264                         wl1251_error("error reading hardware complete "
 265                                      "init indication");
 266                         return -EIO;
 267                 }
 268                 /* check that ACX_INTR_INIT_COMPLETE is enabled */
 269                 else if (acx_intr & WL1251_ACX_INTR_INIT_COMPLETE) {
 270                         wl1251_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
 271                                            WL1251_ACX_INTR_INIT_COMPLETE);
 272                         break;
 273                 }
 274         }
 275
 276         if (loop > INIT_LOOP) {
 277                 wl1251_error("timeout waiting for the hardware to "
 278                              "complete initialization");
 279                 return -EIO;
 280         }
 281
 282         /* get hardware config command mail box */
 283         wl->cmd_box_addr = wl1251_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);
 284
 285         /* get hardware config event mail box */
 286         wl->event_box_addr = wl1251_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
 287
 288         /* set the working partition to its "running" mode offset */
 289         wl1251_set_partition(wl, WL1251_PART_WORK_MEM_START,
 290                              WL1251_PART_WORK_MEM_SIZE,
 291                              WL1251_PART_WORK_REG_START,
 292                              WL1251_PART_WORK_REG_SIZE);
 293
 294         wl1251_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
 295                      wl->cmd_box_addr, wl->event_box_addr);
 296
 297         wl1251_acx_fw_version(wl, wl->fw_ver, sizeof(wl->fw_ver));
 298
 299         /*
 300          * in case of full asynchronous mode the firmware event must be
 301          * ready to receive event from the command mailbox
 302          */
 303
 304         /* enable gpio interrupts */
 305         wl1251_enable_interrupts(wl);
 306
 307         /* Enable target's interrupts */
 308         wl->intr_mask = WL1251_ACX_INTR_RX0_DATA |
 309                 WL1251_ACX_INTR_RX1_DATA |
 310                 WL1251_ACX_INTR_TX_RESULT |
 311                 WL1251_ACX_INTR_EVENT_A |
 312                 WL1251_ACX_INTR_EVENT_B |
 313                 WL1251_ACX_INTR_INIT_COMPLETE;
 314         wl1251_boot_target_enable_interrupts(wl);
 315
 316         wl->event_mask = SCAN_COMPLETE_EVENT_ID | BSS_LOSE_EVENT_ID |
 317                 SYNCHRONIZATION_TIMEOUT_EVENT_ID |
 318                 ROAMING_TRIGGER_LOW_RSSI_EVENT_ID |
 319                 ROAMING_TRIGGER_REGAINED_RSSI_EVENT_ID |
 320                 REGAINED_BSS_EVENT_ID | BT_PTA_SENSE_EVENT_ID |
 321                 BT_PTA_PREDICTION_EVENT_ID | JOIN_EVENT_COMPLETE_ID |
 322                 PS_REPORT_EVENT_ID;
 323
 324         ret = wl1251_event_unmask(wl);
 325         if (ret < 0) {
 326                 wl1251_error("EVENT mask setting failed");
 327                 return ret;
 328         }
 329
 330         wl1251_event_mbox_config(wl);
 331
 332         /* firmware startup completed */
 333         return 0;
 334 }
 335
 336 static int wl1251_boot_upload_firmware(struct wl1251 *wl)
 337 {
 338         int addr, chunk_num, partition_limit;
 339         size_t fw_data_len, len;
 340         u8 *p, *buf;
 341
 342         /* whal_FwCtrl_LoadFwImageSm() */
 343
 344         wl1251_debug(DEBUG_BOOT, "chip id before fw upload: 0x%x",
 345                      wl1251_reg_read32(wl, CHIP_ID_B));
 346
 347         /* 10.0 check firmware length and set partition */
 348         fw_data_len =  (wl->fw[4] << 24) | (wl->fw[5] << 16) |
 349                 (wl->fw[6] << 8) | (wl->fw[7]);
 350
 351         wl1251_debug(DEBUG_BOOT, "fw_data_len %zu chunk_size %d", fw_data_len,
 352                 CHUNK_SIZE);
 353
 354         if ((fw_data_len % 4) != 0) {
 355                 wl1251_error("firmware length not multiple of four");
 356                 return -EIO;
 357         }
 358
 359         buf = kmalloc(CHUNK_SIZE, GFP_KERNEL);
 360         if (!buf) {
 361                 wl1251_error("allocation for firmware upload chunk failed");
 362                 return -ENOMEM;
 363         }
 364
 365         wl1251_set_partition(wl, WL1251_PART_DOWN_MEM_START,
 366                              WL1251_PART_DOWN_MEM_SIZE,
 367                              WL1251_PART_DOWN_REG_START,
 368                              WL1251_PART_DOWN_REG_SIZE);
 369
 370         /* 10.1 set partition limit and chunk num */
 371         chunk_num = 0;
 372         partition_limit = WL1251_PART_DOWN_MEM_SIZE;
 373
 374         while (chunk_num < fw_data_len / CHUNK_SIZE) {
 375                 /* 10.2 update partition, if needed */
 376                 addr = WL1251_PART_DOWN_MEM_START +
 377                         (chunk_num + 2) * CHUNK_SIZE;
 378                 if (addr > partition_limit) {
 379                         addr = WL1251_PART_DOWN_MEM_START +
 380                                 chunk_num * CHUNK_SIZE;
 381                         partition_limit = chunk_num * CHUNK_SIZE +
 382                                 WL1251_PART_DOWN_MEM_SIZE;
 383                         wl1251_set_partition(wl,
 384                                              addr,
 385                                              WL1251_PART_DOWN_MEM_SIZE,
 386                                              WL1251_PART_DOWN_REG_START,
 387                                              WL1251_PART_DOWN_REG_SIZE);
 388                 }
 389
 390                 /* 10.3 upload the chunk */
 391                 addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
 392                 p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
 393                 wl1251_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
 394                              p, addr);
 395
 396                 /* need to copy the chunk for dma */
 397                 len = CHUNK_SIZE;
 398                 memcpy(buf, p, len);
 399                 wl1251_mem_write(wl, addr, buf, len);
 400
 401                 chunk_num++;
 402         }
 403
 404         /* 10.4 upload the last chunk */
 405         addr = WL1251_PART_DOWN_MEM_START + chunk_num * CHUNK_SIZE;
 406         p = wl->fw + FW_HDR_SIZE + chunk_num * CHUNK_SIZE;
 407
 408         /* need to copy the chunk for dma */
 409         len = fw_data_len % CHUNK_SIZE;
 410         memcpy(buf, p, len);
 411
 412         wl1251_debug(DEBUG_BOOT, "uploading fw last chunk (%zu B) 0x%p to 0x%x",
 413                      len, p, addr);
 414         wl1251_mem_write(wl, addr, buf, len);
 415
 416         kfree(buf);
 417
 418         return 0;
 419 }
 420
 421 static int wl1251_boot_upload_nvs(struct wl1251 *wl)
 422 {
 423         size_t nvs_len, nvs_bytes_written, burst_len;
 424         int nvs_start, i;
 425         u32 dest_addr, val;
 426         u8 *nvs_ptr, *nvs;
 427
 428         nvs = wl->nvs;
 429         if (nvs == NULL)
 430                 return -ENODEV;
 431
 432         nvs_ptr = nvs;
 433
 434         nvs_len = wl->nvs_len;
 435         nvs_start = wl->fw_len;
 436
 437         /*
 438          * Layout before the actual NVS tables:
 439          * 1 byte : burst length.
 440          * 2 bytes: destination address.
 441          * n bytes: data to burst copy.
 442          *
 443          * This is ended by a 0 length, then the NVS tables.
 444          */
 445
 446         while (nvs_ptr[0]) {
 447                 burst_len = nvs_ptr[0];
 448                 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
 449
 450                 /* We move our pointer to the data */
 451                 nvs_ptr += 3;
 452
 453                 for (i = 0; i < burst_len; i++) {
 454                         val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
 455                                | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
 456
 457                         wl1251_debug(DEBUG_BOOT,
 458                                      "nvs burst write 0x%x: 0x%x",
 459                                      dest_addr, val);
 460                         wl1251_mem_write32(wl, dest_addr, val);
 461
 462                         nvs_ptr += 4;
 463                         dest_addr += 4;
 464                 }
 465         }
 466
 467         /*
 468          * We've reached the first zero length, the first NVS table
 469          * is 7 bytes further.
 470          */
 471         nvs_ptr += 7;
 472         nvs_len -= nvs_ptr - nvs;
 473         nvs_len = ALIGN(nvs_len, 4);
 474
 475         /* Now we must set the partition correctly */
 476         wl1251_set_partition(wl, nvs_start,
 477                              WL1251_PART_DOWN_MEM_SIZE,
 478                              WL1251_PART_DOWN_REG_START,
 479                              WL1251_PART_DOWN_REG_SIZE);
 480
 481         /* And finally we upload the NVS tables */
 482         nvs_bytes_written = 0;
 483         while (nvs_bytes_written < nvs_len) {
 484                 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
 485                        | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
 486
 487                 val = cpu_to_le32(val);
 488
 489                 wl1251_debug(DEBUG_BOOT,
 490                              "nvs write table 0x%x: 0x%x",
 491                              nvs_start, val);
 492                 wl1251_mem_write32(wl, nvs_start, val);
 493
 494                 nvs_ptr += 4;
 495                 nvs_bytes_written += 4;
 496                 nvs_start += 4;
 497         }
 498
 499         return 0;
 500 }
 501
 502 int wl1251_boot(struct wl1251 *wl)
 503 {
 504         int ret = 0, minor_minor_e2_ver;
 505         u32 tmp, boot_data;
 506
 507         /* halt embedded ARM CPU while loading firmware */
 508         wl1251_reg_write32(wl, ACX_REG_ECPU_CONTROL, ECPU_CONTROL_HALT);
 509
 510         ret = wl1251_boot_soft_reset(wl);
 511         if (ret < 0)
 512                 goto out;
 513
 514         /* 2. start processing NVS file */
 515         if (wl->use_eeprom) {
 516                 wl1251_reg_write32(wl, ACX_REG_EE_START, START_EEPROM_MGR);
 517                 /* Wait for EEPROM NVS burst read to complete */
 518                 msleep(40);
 519                 wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, USE_EEPROM);
 520         } else {
 521                 ret = wl1251_boot_upload_nvs(wl);
 522                 if (ret < 0)
 523                         goto out;
 524
 525                 /* write firmware's last address (ie. it's length) to
 526                  * ACX_EEPROMLESS_IND_REG */
 527                 wl1251_reg_write32(wl, ACX_EEPROMLESS_IND_REG, wl->fw_len);
 528         }
 529
 530         /* 6. read the EEPROM parameters */
 531         tmp = wl1251_reg_read32(wl, SCR_PAD2);
 532
 533         /* 7. read bootdata */
 534         wl->boot_attr.radio_type = (tmp & 0x0000FF00) >> 8;
 535         wl->boot_attr.major = (tmp & 0x00FF0000) >> 16;
 536         tmp = wl1251_reg_read32(wl, SCR_PAD3);
 537
 538         /* 8. check bootdata and call restart sequence */
 539         wl->boot_attr.minor = (tmp & 0x00FF0000) >> 16;
 540         minor_minor_e2_ver = (tmp & 0xFF000000) >> 24;
 541
 542         wl1251_debug(DEBUG_BOOT, "radioType 0x%x majorE2Ver 0x%x "
 543                      "minorE2Ver 0x%x minor_minor_e2_ver 0x%x",
 544                      wl->boot_attr.radio_type, wl->boot_attr.major,
 545                      wl->boot_attr.minor, minor_minor_e2_ver);
 546
 547         ret = wl1251_boot_init_seq(wl);
 548         if (ret < 0)
 549                 goto out;
 550
 551         /* 9. NVS processing done */
 552         boot_data = wl1251_reg_read32(wl, ACX_REG_ECPU_CONTROL);
 553
 554         wl1251_debug(DEBUG_BOOT, "halt boot_data 0x%x", boot_data);
 555
 556         /* 10. check that ECPU_CONTROL_HALT bits are set in
 557          * pWhalBus->uBootData and start uploading firmware
 558          */
 559         if ((boot_data & ECPU_CONTROL_HALT) == 0) {
 560                 wl1251_error("boot failed, ECPU_CONTROL_HALT not set");
 561                 ret = -EIO;
 562                 goto out;
 563         }
 564
 565         ret = wl1251_boot_upload_firmware(wl);
 566         if (ret < 0)
 567                 goto out;
 568
 569         /* 10.5 start firmware */
 570         ret = wl1251_boot_run_firmware(wl);
 571         if (ret < 0)
 572                 goto out;
 573
 574 out:
 575         return ret;
 576 }