drivers/net/wireless/rtlwifi/rtl8192ce/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "../rtl8192c/fw_common.h"
  41 #include "dm.h"
  42 #include "led.h"
  43 #include "hw.h"
  44
  45 #define LLT_CONFIG      5
  46
  47 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  48                                       u8 set_bits, u8 clear_bits)
  49 {
  50         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  51         struct rtl_priv *rtlpriv = rtl_priv(hw);
  52
  53         rtlpci->reg_bcn_ctrl_val |= set_bits;
  54         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  55
  56         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  57 }
  58
  59 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
  60 {
  61         struct rtl_priv *rtlpriv = rtl_priv(hw);
  62         u8 tmp1byte;
  63
  64         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  65         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  66         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  67         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  68         tmp1byte &= ~(BIT(0));
  69         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  70 }
  71
  72 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
  73 {
  74         struct rtl_priv *rtlpriv = rtl_priv(hw);
  75         u8 tmp1byte;
  76
  77         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  78         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  79         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  80         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  81         tmp1byte |= BIT(0);
  82         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  83 }
  84
  85 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
  86 {
  87         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
  88 }
  89
  90 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
  91 {
  92         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
  93 }
  94
  95 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  96 {
  97         struct rtl_priv *rtlpriv = rtl_priv(hw);
  98         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  99         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 100
 101         switch (variable) {
 102         case HW_VAR_RCR:
 103                 *((u32 *) (val)) = rtlpci->receive_config;
 104                 break;
 105         case HW_VAR_RF_STATE:
 106                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 107                 break;
 108         case HW_VAR_FWLPS_RF_ON:{
 109                         enum rf_pwrstate rfState;
 110                         u32 val_rcr;
 111
 112                         rtlpriv->cfg->ops->get_hw_reg(hw,
 113                                                       HW_VAR_RF_STATE,
 114                                                       (u8 *) (&rfState));
 115                         if (rfState == ERFOFF) {
 116                                 *((bool *) (val)) = true;
 117                         } else {
 118                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 119                                 val_rcr &= 0x00070000;
 120                                 if (val_rcr)
 121                                         *((bool *) (val)) = false;
 122                                 else
 123                                         *((bool *) (val)) = true;
 124                         }
 125                         break;
 126                 }
 127         case HW_VAR_FW_PSMODE_STATUS:
 128                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
 129                 break;
 130         case HW_VAR_CORRECT_TSF:{
 131                 u64 tsf;
 132                 u32 *ptsf_low = (u32 *)&tsf;
 133                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 134
 135                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 136                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 137
 138                 *((u64 *) (val)) = tsf;
 139
 140                 break;
 141                 }
 142         default:
 143                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 144                          ("switch case not process\n"));
 145                 break;
 146         }
 147 }
 148
 149 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 150 {
 151         struct rtl_priv *rtlpriv = rtl_priv(hw);
 152         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 153         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 154         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 155         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 156         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 157         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 158         u8 idx;
 159
 160         switch (variable) {
 161         case HW_VAR_ETHER_ADDR:{
 162                         for (idx = 0; idx < ETH_ALEN; idx++) {
 163                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 164                                                val[idx]);
 165                         }
 166                         break;
 167                 }
 168         case HW_VAR_BASIC_RATE:{
 169                         u16 rate_cfg = ((u16 *) val)[0];
 170                         u8 rate_index = 0;
 171                         rate_cfg &= 0x15f;
 172                         rate_cfg |= 0x01;
 173                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
 174                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
 175                                        (rate_cfg >> 8) & 0xff);
 176                         while (rate_cfg > 0x1) {
 177                                 rate_cfg = (rate_cfg >> 1);
 178                                 rate_index++;
 179                         }
 180                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 181                                        rate_index);
 182                         break;
 183                 }
 184         case HW_VAR_BSSID:{
 185                         for (idx = 0; idx < ETH_ALEN; idx++) {
 186                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 187                                                val[idx]);
 188                         }
 189                         break;
 190                 }
 191         case HW_VAR_SIFS:{
 192                         rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 193                         rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 194
 195                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 196                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 197
 198                         if (!mac->ht_enable)
 199                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 200                                                0x0e0e);
 201                         else
 202                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 203                                                *((u16 *) val));
 204                         break;
 205                 }
 206         case HW_VAR_SLOT_TIME:{
 207                         u8 e_aci;
 208
 209                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 210                                  ("HW_VAR_SLOT_TIME %x\n", val[0]));
 211
 212                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 213
 214                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 215                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 216                                                               HW_VAR_AC_PARAM,
 217                                                               (u8 *) (&e_aci));
 218                         }
 219                         break;
 220                 }
 221         case HW_VAR_ACK_PREAMBLE:{
 222                         u8 reg_tmp;
 223                         u8 short_preamble = (bool) (*(u8 *) val);
 224                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 225                         if (short_preamble)
 226                                 reg_tmp |= 0x80;
 227
 228                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 229                         break;
 230                 }
 231         case HW_VAR_AMPDU_MIN_SPACE:{
 232                         u8 min_spacing_to_set;
 233                         u8 sec_min_space;
 234
 235                         min_spacing_to_set = *((u8 *) val);
 236                         if (min_spacing_to_set <= 7) {
 237                                 sec_min_space = 0;
 238
 239                                 if (min_spacing_to_set < sec_min_space)
 240                                         min_spacing_to_set = sec_min_space;
 241
 242                                 mac->min_space_cfg = ((mac->min_space_cfg &
 243                                                        0xf8) |
 244                                                       min_spacing_to_set);
 245
 246                                 *val = min_spacing_to_set;
 247
 248                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 249                                          ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 250                                           mac->min_space_cfg));
 251
 252                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 253                                                mac->min_space_cfg);
 254                         }
 255                         break;
 256                 }
 257         case HW_VAR_SHORTGI_DENSITY:{
 258                         u8 density_to_set;
 259
 260                         density_to_set = *((u8 *) val);
 261                         mac->min_space_cfg |= (density_to_set << 3);
 262
 263                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 264                                  ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 265                                   mac->min_space_cfg));
 266
 267                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 268                                        mac->min_space_cfg);
 269
 270                         break;
 271                 }
 272         case HW_VAR_AMPDU_FACTOR:{
 273                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
 274                         u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
 275
 276                         u8 factor_toset;
 277                         u8 *p_regtoset = NULL;
 278                         u8 index = 0;
 279
 280                         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 281                             (rtlpcipriv->bt_coexist.bt_coexist_type ==
 282                             BT_CSR_BC4))
 283                                 p_regtoset = regtoset_bt;
 284                         else
 285                                 p_regtoset = regtoset_normal;
 286
 287                         factor_toset = *((u8 *) val);
 288                         if (factor_toset <= 3) {
 289                                 factor_toset = (1 << (factor_toset + 2));
 290                                 if (factor_toset > 0xf)
 291                                         factor_toset = 0xf;
 292
 293                                 for (index = 0; index < 4; index++) {
 294                                         if ((p_regtoset[index] & 0xf0) >
 295                                             (factor_toset << 4))
 296                                                 p_regtoset[index] =
 297                                                     (p_regtoset[index] & 0x0f) |
 298                                                     (factor_toset << 4);
 299
 300                                         if ((p_regtoset[index] & 0x0f) >
 301                                             factor_toset)
 302                                                 p_regtoset[index] =
 303                                                     (p_regtoset[index] & 0xf0) |
 304                                                     (factor_toset);
 305
 306                                         rtl_write_byte(rtlpriv,
 307                                                        (REG_AGGLEN_LMT + index),
 308                                                        p_regtoset[index]);
 309
 310                                 }
 311
 312                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 313                                          ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
 314                                           factor_toset));
 315                         }
 316                         break;
 317                 }
 318         case HW_VAR_AC_PARAM:{
 319                         u8 e_aci = *((u8 *) val);
 320                         rtl92c_dm_init_edca_turbo(hw);
 321
 322                         if (rtlpci->acm_method != eAcmWay2_SW)
 323                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 324                                                               HW_VAR_ACM_CTRL,
 325                                                               (u8 *) (&e_aci));
 326                         break;
 327                 }
 328         case HW_VAR_ACM_CTRL:{
 329                         u8 e_aci = *((u8 *) val);
 330                         union aci_aifsn *p_aci_aifsn =
 331                             (union aci_aifsn *)(&(mac->ac[0].aifs));
 332                         u8 acm = p_aci_aifsn->f.acm;
 333                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 334
 335                         acm_ctrl =
 336                             acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 337
 338                         if (acm) {
 339                                 switch (e_aci) {
 340                                 case AC0_BE:
 341                                         acm_ctrl |= AcmHw_BeqEn;
 342                                         break;
 343                                 case AC2_VI:
 344                                         acm_ctrl |= AcmHw_ViqEn;
 345                                         break;
 346                                 case AC3_VO:
 347                                         acm_ctrl |= AcmHw_VoqEn;
 348                                         break;
 349                                 default:
 350                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 351                                                  ("HW_VAR_ACM_CTRL acm set "
 352                                                   "failed: eACI is %d\n", acm));
 353                                         break;
 354                                 }
 355                         } else {
 356                                 switch (e_aci) {
 357                                 case AC0_BE:
 358                                         acm_ctrl &= (~AcmHw_BeqEn);
 359                                         break;
 360                                 case AC2_VI:
 361                                         acm_ctrl &= (~AcmHw_ViqEn);
 362                                         break;
 363                                 case AC3_VO:
 364                                         acm_ctrl &= (~AcmHw_BeqEn);
 365                                         break;
 366                                 default:
 367                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 368                                                  ("switch case not process\n"));
 369                                         break;
 370                                 }
 371                         }
 372
 373                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 374                                  ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
 375                                   "Write 0x%X\n", acm_ctrl));
 376                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 377                         break;
 378                 }
 379         case HW_VAR_RCR:{
 380                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
 381                         rtlpci->receive_config = ((u32 *) (val))[0];
 382                         break;
 383                 }
 384         case HW_VAR_RETRY_LIMIT:{
 385                         u8 retry_limit = ((u8 *) (val))[0];
 386
 387                         rtl_write_word(rtlpriv, REG_RL,
 388                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 389                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 390                         break;
 391                 }
 392         case HW_VAR_DUAL_TSF_RST:
 393                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 394                 break;
 395         case HW_VAR_EFUSE_BYTES:
 396                 rtlefuse->efuse_usedbytes = *((u16 *) val);
 397                 break;
 398         case HW_VAR_EFUSE_USAGE:
 399                 rtlefuse->efuse_usedpercentage = *((u8 *) val);
 400                 break;
 401         case HW_VAR_IO_CMD:
 402                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
 403                 break;
 404         case HW_VAR_WPA_CONFIG:
 405                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
 406                 break;
 407         case HW_VAR_SET_RPWM:{
 408                         u8 rpwm_val;
 409
 410                         rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 411                         udelay(1);
 412
 413                         if (rpwm_val & BIT(7)) {
 414                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 415                                                (*(u8 *) val));
 416                         } else {
 417                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 418                                                ((*(u8 *) val) | BIT(7)));
 419                         }
 420
 421                         break;
 422                 }
 423         case HW_VAR_H2C_FW_PWRMODE:{
 424                         u8 psmode = (*(u8 *) val);
 425
 426                         if ((psmode != FW_PS_ACTIVE_MODE) &&
 427                             (!IS_92C_SERIAL(rtlhal->version))) {
 428                                 rtl92c_dm_rf_saving(hw, true);
 429                         }
 430
 431                         rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
 432                         break;
 433                 }
 434         case HW_VAR_FW_PSMODE_STATUS:
 435                 ppsc->fw_current_inpsmode = *((bool *) val);
 436                 break;
 437         case HW_VAR_H2C_FW_JOINBSSRPT:{
 438                         u8 mstatus = (*(u8 *) val);
 439                         u8 tmp_regcr, tmp_reg422;
 440                         bool recover = false;
 441
 442                         if (mstatus == RT_MEDIA_CONNECT) {
 443                                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 444                                                               NULL);
 445
 446                                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 447                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 448                                                (tmp_regcr | BIT(0)));
 449
 450                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 451                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
 452
 453                                 tmp_reg422 =
 454                                     rtl_read_byte(rtlpriv,
 455                                                   REG_FWHW_TXQ_CTRL + 2);
 456                                 if (tmp_reg422 & BIT(6))
 457                                         recover = true;
 458                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 459                                                tmp_reg422 & (~BIT(6)));
 460
 461                                 rtl92c_set_fw_rsvdpagepkt(hw, 0);
 462
 463                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 464                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
 465
 466                                 if (recover) {
 467                                         rtl_write_byte(rtlpriv,
 468                                                        REG_FWHW_TXQ_CTRL + 2,
 469                                                        tmp_reg422);
 470                                 }
 471
 472                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 473                                                (tmp_regcr & ~(BIT(0))));
 474                         }
 475                         rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
 476
 477                         break;
 478                 }
 479         case HW_VAR_AID:{
 480                         u16 u2btmp;
 481                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 482                         u2btmp &= 0xC000;
 483                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 484                                                 mac->assoc_id));
 485
 486                         break;
 487                 }
 488         case HW_VAR_CORRECT_TSF:{
 489                         u8 btype_ibss = ((u8 *) (val))[0];
 490
 491                         if (btype_ibss)
 492                                 _rtl92ce_stop_tx_beacon(hw);
 493
 494                         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 495
 496                         rtl_write_dword(rtlpriv, REG_TSFTR,
 497                                         (u32) (mac->tsf & 0xffffffff));
 498                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 499                                         (u32) ((mac->tsf >> 32) & 0xffffffff));
 500
 501                         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 502
 503                         if (btype_ibss)
 504                                 _rtl92ce_resume_tx_beacon(hw);
 505
 506                         break;
 507
 508                 }
 509         default:
 510                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
 511                                                         "not process\n"));
 512                 break;
 513         }
 514 }
 515
 516 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 517 {
 518         struct rtl_priv *rtlpriv = rtl_priv(hw);
 519         bool status = true;
 520         long count = 0;
 521         u32 value = _LLT_INIT_ADDR(address) |
 522             _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 523
 524         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 525
 526         do {
 527                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 528                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 529                         break;
 530
 531                 if (count > POLLING_LLT_THRESHOLD) {
 532                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 533                                  ("Failed to polling write LLT done at "
 534                                   "address %d!\n", address));
 535                         status = false;
 536                         break;
 537                 }
 538         } while (++count);
 539
 540         return status;
 541 }
 542
 543 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
 544 {
 545         struct rtl_priv *rtlpriv = rtl_priv(hw);
 546         unsigned short i;
 547         u8 txpktbuf_bndy;
 548         u8 maxPage;
 549         bool status;
 550
 551 #if LLT_CONFIG == 1
 552         maxPage = 255;
 553         txpktbuf_bndy = 252;
 554 #elif LLT_CONFIG == 2
 555         maxPage = 127;
 556         txpktbuf_bndy = 124;
 557 #elif LLT_CONFIG == 3
 558         maxPage = 255;
 559         txpktbuf_bndy = 174;
 560 #elif LLT_CONFIG == 4
 561         maxPage = 255;
 562         txpktbuf_bndy = 246;
 563 #elif LLT_CONFIG == 5
 564         maxPage = 255;
 565         txpktbuf_bndy = 246;
 566 #endif
 567
 568 #if LLT_CONFIG == 1
 569         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
 570         rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
 571 #elif LLT_CONFIG == 2
 572         rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
 573 #elif LLT_CONFIG == 3
 574         rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
 575 #elif LLT_CONFIG == 4
 576         rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
 577 #elif LLT_CONFIG == 5
 578         rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
 579
 580         rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
 581 #endif
 582
 583         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
 584         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 585
 586         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 587         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 588
 589         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 590         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 591         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 592
 593         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 594                 status = _rtl92ce_llt_write(hw, i, i + 1);
 595                 if (true != status)
 596                         return status;
 597         }
 598
 599         status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 600         if (true != status)
 601                 return status;
 602
 603         for (i = txpktbuf_bndy; i < maxPage; i++) {
 604                 status = _rtl92ce_llt_write(hw, i, (i + 1));
 605                 if (true != status)
 606                         return status;
 607         }
 608
 609         status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
 610         if (true != status)
 611                 return status;
 612
 613         return true;
 614 }
 615
 616 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
 617 {
 618         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 619         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 620         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 621         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 622
 623         if (rtlpci->up_first_time)
 624                 return;
 625
 626         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 627                 rtl92ce_sw_led_on(hw, pLed0);
 628         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 629                 rtl92ce_sw_led_on(hw, pLed0);
 630         else
 631                 rtl92ce_sw_led_off(hw, pLed0);
 632 }
 633
 634 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
 635 {
 636         struct rtl_priv *rtlpriv = rtl_priv(hw);
 637         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 638         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 639         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 640
 641         unsigned char bytetmp;
 642         unsigned short wordtmp;
 643         u16 retry;
 644
 645         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 646         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 647                 u32 value32;
 648                 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
 649                 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
 650                 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
 651         }
 652         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 653         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
 654
 655         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 656                 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
 657
 658                 u4b_tmp &= (~0x00024800);
 659                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
 660         }
 661
 662         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
 663         udelay(2);
 664
 665         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 666         udelay(2);
 667
 668         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 669         udelay(2);
 670
 671         retry = 0;
 672         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
 673                                                 rtl_read_dword(rtlpriv, 0xEC),
 674                                                 bytetmp));
 675
 676         while ((bytetmp & BIT(0)) && retry < 1000) {
 677                 retry++;
 678                 udelay(50);
 679                 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 680                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
 681                                                         rtl_read_dword(rtlpriv,
 682                                                                        0xEC),
 683                                                         bytetmp));
 684                 udelay(50);
 685         }
 686
 687         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
 688
 689         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
 690         udelay(2);
 691
 692         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 693                 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
 694                 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
 695         }
 696
 697         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 698
 699         if (_rtl92ce_llt_table_init(hw) == false)
 700                 return false;
 701
 702         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 703         rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
 704
 705         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
 706
 707         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 708         wordtmp &= 0xf;
 709         wordtmp |= 0xF771;
 710         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 711
 712         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 713         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 714         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 715
 716         rtl_write_byte(rtlpriv, 0x4d0, 0x0);
 717
 718         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 719                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 720                         DMA_BIT_MASK(32));
 721         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 722                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 723                         DMA_BIT_MASK(32));
 724         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 725                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 726         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 727                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 728         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 729                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 730         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 731                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 732         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 733                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 734                         DMA_BIT_MASK(32));
 735         rtl_write_dword(rtlpriv, REG_RX_DESA,
 736                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 737                         DMA_BIT_MASK(32));
 738
 739         if (IS_92C_SERIAL(rtlhal->version))
 740                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
 741         else
 742                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
 743
 744         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 745
 746         bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 747         rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
 748         do {
 749                 retry++;
 750                 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 751         } while ((retry < 200) && (bytetmp & BIT(7)));
 752
 753         _rtl92ce_gen_refresh_led_state(hw);
 754
 755         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 756
 757         return true;
 758 }
 759
 760 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
 761 {
 762         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 763         struct rtl_priv *rtlpriv = rtl_priv(hw);
 764         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 765         u8 reg_bw_opmode;
 766         u32 reg_prsr;
 767
 768         reg_bw_opmode = BW_OPMODE_20MHZ;
 769         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 770
 771         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
 772
 773         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 774
 775         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 776
 777         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 778
 779         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
 780
 781         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 782
 783         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 784
 785         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
 786
 787         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 788
 789         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 790         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 791         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 792         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 793
 794         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 795             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
 796                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
 797         else
 798                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
 799
 800         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 801
 802         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 803
 804         rtlpci->reg_bcn_ctrl_val = 0x1f;
 805         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 806
 807         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 808
 809         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 810
 811         rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
 812         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 813
 814         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 815             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
 816                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 817                 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
 818         } else {
 819                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 820                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 821         }
 822
 823         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 824              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
 825                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 826         else
 827                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
 828
 829         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 830
 831         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
 832         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
 833
 834         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
 835
 836         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
 837
 838         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
 839         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
 840
 841 }
 842
 843 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
 844 {
 845         struct rtl_priv *rtlpriv = rtl_priv(hw);
 846         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 847
 848         rtl_write_byte(rtlpriv, 0x34b, 0x93);
 849         rtl_write_word(rtlpriv, 0x350, 0x870c);
 850         rtl_write_byte(rtlpriv, 0x352, 0x1);
 851
 852         if (ppsc->support_backdoor)
 853                 rtl_write_byte(rtlpriv, 0x349, 0x1b);
 854         else
 855                 rtl_write_byte(rtlpriv, 0x349, 0x03);
 856
 857         rtl_write_word(rtlpriv, 0x350, 0x2718);
 858         rtl_write_byte(rtlpriv, 0x352, 0x1);
 859 }
 860
 861 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
 862 {
 863         struct rtl_priv *rtlpriv = rtl_priv(hw);
 864         u8 sec_reg_value;
 865
 866         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 867                  ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 868                   rtlpriv->sec.pairwise_enc_algorithm,
 869                   rtlpriv->sec.group_enc_algorithm));
 870
 871         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 872                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("not open "
 873                                                         "hw encryption\n"));
 874                 return;
 875         }
 876
 877         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
 878
 879         if (rtlpriv->sec.use_defaultkey) {
 880                 sec_reg_value |= SCR_TxUseDK;
 881                 sec_reg_value |= SCR_RxUseDK;
 882         }
 883
 884         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 885
 886         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 887
 888         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
 889                  ("The SECR-value %x\n", sec_reg_value));
 890
 891         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 892
 893 }
 894
 895 int rtl92ce_hw_init(struct ieee80211_hw *hw)
 896 {
 897         struct rtl_priv *rtlpriv = rtl_priv(hw);
 898         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 899         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 900         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 901         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 902         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 903         static bool iqk_initialized; /* initialized to false */
 904         bool rtstatus = true;
 905         bool is92c;
 906         int err;
 907         u8 tmp_u1b;
 908
 909         rtlpci->being_init_adapter = true;
 910         rtlpriv->intf_ops->disable_aspm(hw);
 911         rtstatus = _rtl92ce_init_mac(hw);
 912         if (rtstatus != true) {
 913                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Init MAC failed\n"));
 914                 err = 1;
 915                 return err;
 916         }
 917
 918         err = rtl92c_download_fw(hw);
 919         if (err) {
 920                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 921                          ("Failed to download FW. Init HW "
 922                           "without FW now..\n"));
 923                 err = 1;
 924                 rtlhal->fw_ready = false;
 925                 return err;
 926         } else {
 927                 rtlhal->fw_ready = true;
 928         }
 929
 930         rtlhal->last_hmeboxnum = 0;
 931         rtl92c_phy_mac_config(hw);
 932         rtl92c_phy_bb_config(hw);
 933         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 934         rtl92c_phy_rf_config(hw);
 935         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
 936                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 937         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
 938                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 939         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 940         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 941         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 942         _rtl92ce_hw_configure(hw);
 943         rtl_cam_reset_all_entry(hw);
 944         rtl92ce_enable_hw_security_config(hw);
 945
 946         ppsc->rfpwr_state = ERFON;
 947
 948         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
 949         _rtl92ce_enable_aspm_back_door(hw);
 950         rtlpriv->intf_ops->enable_aspm(hw);
 951
 952         rtl8192ce_bt_hw_init(hw);
 953
 954         if (ppsc->rfpwr_state == ERFON) {
 955                 rtl92c_phy_set_rfpath_switch(hw, 1);
 956                 if (iqk_initialized) {
 957                         rtl92c_phy_iq_calibrate(hw, true);
 958                 } else {
 959                         rtl92c_phy_iq_calibrate(hw, false);
 960                         iqk_initialized = true;
 961                 }
 962
 963                 rtl92c_dm_check_txpower_tracking(hw);
 964                 rtl92c_phy_lc_calibrate(hw);
 965         }
 966
 967         is92c = IS_92C_SERIAL(rtlhal->version);
 968         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
 969         if (!(tmp_u1b & BIT(0))) {
 970                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
 971                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path A\n"));
 972         }
 973
 974         if (!(tmp_u1b & BIT(1)) && is92c) {
 975                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
 976                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path B\n"));
 977         }
 978
 979         if (!(tmp_u1b & BIT(4))) {
 980                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
 981                 tmp_u1b &= 0x0F;
 982                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
 983                 udelay(10);
 984                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
 985                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("under 1.5V\n"));
 986         }
 987         rtl92c_dm_init(hw);
 988         rtlpci->being_init_adapter = false;
 989         return err;
 990 }
 991
 992 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
 993 {
 994         struct rtl_priv *rtlpriv = rtl_priv(hw);
 995         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 996         enum version_8192c version = VERSION_UNKNOWN;
 997         u32 value32;
 998
 999         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1000         if (value32 & TRP_VAUX_EN) {
1001                 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1002                            VERSION_A_CHIP_88C;
1003         } else {
1004                 version = (value32 & TYPE_ID) ? VERSION_B_CHIP_92C :
1005                            VERSION_B_CHIP_88C;
1006         }
1007
1008         switch (version) {
1009         case VERSION_B_CHIP_92C:
1010                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1011                          ("Chip Version ID: VERSION_B_CHIP_92C.\n"));
1012                 break;
1013         case VERSION_B_CHIP_88C:
1014                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1015                          ("Chip Version ID: VERSION_B_CHIP_88C.\n"));
1016                 break;
1017         case VERSION_A_CHIP_92C:
1018                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1019                          ("Chip Version ID: VERSION_A_CHIP_92C.\n"));
1020                 break;
1021         case VERSION_A_CHIP_88C:
1022                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1023                          ("Chip Version ID: VERSION_A_CHIP_88C.\n"));
1024                 break;
1025         default:
1026                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1027                          ("Chip Version ID: Unknown. Bug?\n"));
1028                 break;
1029         }
1030
1031         switch (version & 0x3) {
1032         case CHIP_88C:
1033                 rtlphy->rf_type = RF_1T1R;
1034                 break;
1035         case CHIP_92C:
1036                 rtlphy->rf_type = RF_2T2R;
1037                 break;
1038         case CHIP_92C_1T2R:
1039                 rtlphy->rf_type = RF_1T2R;
1040                 break;
1041         default:
1042                 rtlphy->rf_type = RF_1T1R;
1043                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1044                          ("ERROR RF_Type is set!!"));
1045                 break;
1046         }
1047
1048         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1049                  ("Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1050                   "RF_2T2R" : "RF_1T1R"));
1051
1052         return version;
1053 }
1054
1055 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1056                                      enum nl80211_iftype type)
1057 {
1058         struct rtl_priv *rtlpriv = rtl_priv(hw);
1059         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1060         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1061         bt_msr &= 0xfc;
1062
1063         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1064             type == NL80211_IFTYPE_STATION) {
1065                 _rtl92ce_stop_tx_beacon(hw);
1066                 _rtl92ce_enable_bcn_sub_func(hw);
1067         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1068                 _rtl92ce_resume_tx_beacon(hw);
1069                 _rtl92ce_disable_bcn_sub_func(hw);
1070         } else {
1071                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1072                          ("Set HW_VAR_MEDIA_STATUS: "
1073                           "No such media status(%x).\n", type));
1074         }
1075
1076         switch (type) {
1077         case NL80211_IFTYPE_UNSPECIFIED:
1078                 bt_msr |= MSR_NOLINK;
1079                 ledaction = LED_CTL_LINK;
1080                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1081                          ("Set Network type to NO LINK!\n"));
1082                 break;
1083         case NL80211_IFTYPE_ADHOC:
1084                 bt_msr |= MSR_ADHOC;
1085                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1086                          ("Set Network type to Ad Hoc!\n"));
1087                 break;
1088         case NL80211_IFTYPE_STATION:
1089                 bt_msr |= MSR_INFRA;
1090                 ledaction = LED_CTL_LINK;
1091                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1092                          ("Set Network type to STA!\n"));
1093                 break;
1094         case NL80211_IFTYPE_AP:
1095                 bt_msr |= MSR_AP;
1096                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1097                          ("Set Network type to AP!\n"));
1098                 break;
1099         default:
1100                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1101                          ("Network type %d not support!\n", type));
1102                 return 1;
1103                 break;
1104
1105         }
1106
1107         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1108         rtlpriv->cfg->ops->led_control(hw, ledaction);
1109         if ((bt_msr & 0xfc) == MSR_AP)
1110                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1111         else
1112                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1113         return 0;
1114 }
1115
1116 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1117 {
1118         struct rtl_priv *rtlpriv = rtl_priv(hw);
1119         u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1120
1121         if (rtlpriv->psc.rfpwr_state != ERFON)
1122                 return;
1123
1124         if (check_bssid) {
1125                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1126                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1127                                               (u8 *) (&reg_rcr));
1128                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1129         } else if (check_bssid == false) {
1130                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1131                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1132                 rtlpriv->cfg->ops->set_hw_reg(hw,
1133                                               HW_VAR_RCR, (u8 *) (&reg_rcr));
1134         }
1135
1136 }
1137
1138 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1139 {
1140         struct rtl_priv *rtlpriv = rtl_priv(hw);
1141
1142         if (_rtl92ce_set_media_status(hw, type))
1143                 return -EOPNOTSUPP;
1144
1145         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1146                 if (type != NL80211_IFTYPE_AP)
1147                         rtl92ce_set_check_bssid(hw, true);
1148         } else {
1149                 rtl92ce_set_check_bssid(hw, false);
1150         }
1151
1152         return 0;
1153 }
1154
1155 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1156 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1157 {
1158         struct rtl_priv *rtlpriv = rtl_priv(hw);
1159         rtl92c_dm_init_edca_turbo(hw);
1160         switch (aci) {
1161         case AC1_BK:
1162                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1163                 break;
1164         case AC0_BE:
1165                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1166                 break;
1167         case AC2_VI:
1168                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1169                 break;
1170         case AC3_VO:
1171                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1172                 break;
1173         default:
1174                 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1175                 break;
1176         }
1177 }
1178
1179 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1180 {
1181         struct rtl_priv *rtlpriv = rtl_priv(hw);
1182         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1183
1184         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1185         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1186 }
1187
1188 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1189 {
1190         struct rtl_priv *rtlpriv = rtl_priv(hw);
1191         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1192
1193         rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1194         rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1195         synchronize_irq(rtlpci->pdev->irq);
1196 }
1197
1198 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1199 {
1200         struct rtl_priv *rtlpriv = rtl_priv(hw);
1201         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1202         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1203         u8 u1b_tmp;
1204         u32 u4b_tmp;
1205
1206         rtlpriv->intf_ops->enable_aspm(hw);
1207         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1208         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1209         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1210         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1211         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1212         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1213         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1214                 rtl92c_firmware_selfreset(hw);
1215         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1216         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1217         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1218         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1219         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1220              ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
1221              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) {
1222                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1223                                 (u1b_tmp << 8));
1224         } else {
1225                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1226                                 (u1b_tmp << 8));
1227         }
1228         rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1229         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1230         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1231         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1232         if (rtlpcipriv->bt_coexist.bt_coexistence) {
1233                 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1234                 u4b_tmp |= 0x03824800;
1235                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1236         } else {
1237                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1238         }
1239
1240         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1241         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1242 }
1243
1244 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1245 {
1246         struct rtl_priv *rtlpriv = rtl_priv(hw);
1247         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1248         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1249         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1250         enum nl80211_iftype opmode;
1251
1252         mac->link_state = MAC80211_NOLINK;
1253         opmode = NL80211_IFTYPE_UNSPECIFIED;
1254         _rtl92ce_set_media_status(hw, opmode);
1255         if (rtlpci->driver_is_goingto_unload ||
1256             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1257                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1258         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1259         _rtl92ce_poweroff_adapter(hw);
1260 }
1261
1262 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1263                                   u32 *p_inta, u32 *p_intb)
1264 {
1265         struct rtl_priv *rtlpriv = rtl_priv(hw);
1266         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1267
1268         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1269         rtl_write_dword(rtlpriv, ISR, *p_inta);
1270
1271         /*
1272          * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1273          * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1274          */
1275 }
1276
1277 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1278 {
1279
1280         struct rtl_priv *rtlpriv = rtl_priv(hw);
1281         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1282         u16 bcn_interval, atim_window;
1283
1284         bcn_interval = mac->beacon_interval;
1285         atim_window = 2;        /*FIX MERGE */
1286         rtl92ce_disable_interrupt(hw);
1287         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1288         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1289         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1290         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1291         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1292         rtl_write_byte(rtlpriv, 0x606, 0x30);
1293         rtl92ce_enable_interrupt(hw);
1294 }
1295
1296 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1297 {
1298         struct rtl_priv *rtlpriv = rtl_priv(hw);
1299         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1300         u16 bcn_interval = mac->beacon_interval;
1301
1302         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1303                  ("beacon_interval:%d\n", bcn_interval));
1304         rtl92ce_disable_interrupt(hw);
1305         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1306         rtl92ce_enable_interrupt(hw);
1307 }
1308
1309 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1310                                    u32 add_msr, u32 rm_msr)
1311 {
1312         struct rtl_priv *rtlpriv = rtl_priv(hw);
1313         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1314
1315         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1316                  ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1317
1318         if (add_msr)
1319                 rtlpci->irq_mask[0] |= add_msr;
1320         if (rm_msr)
1321                 rtlpci->irq_mask[0] &= (~rm_msr);
1322         rtl92ce_disable_interrupt(hw);
1323         rtl92ce_enable_interrupt(hw);
1324 }
1325
1326 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1327                                                  bool autoload_fail,
1328                                                  u8 *hwinfo)
1329 {
1330         struct rtl_priv *rtlpriv = rtl_priv(hw);
1331         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1332         u8 rf_path, index, tempval;
1333         u16 i;
1334
1335         for (rf_path = 0; rf_path < 2; rf_path++) {
1336                 for (i = 0; i < 3; i++) {
1337                         if (!autoload_fail) {
1338                                 rtlefuse->
1339                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1340                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1341                                 rtlefuse->
1342                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1343                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1344                                            i];
1345                         } else {
1346                                 rtlefuse->
1347                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1348                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1349                                 rtlefuse->
1350                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1351                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1352                         }
1353                 }
1354         }
1355
1356         for (i = 0; i < 3; i++) {
1357                 if (!autoload_fail)
1358                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1359                 else
1360                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1361                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
1362                     (tempval & 0xf);
1363                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
1364                     ((tempval & 0xf0) >> 4);
1365         }
1366
1367         for (rf_path = 0; rf_path < 2; rf_path++)
1368                 for (i = 0; i < 3; i++)
1369                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1370                                 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1371                                  i,
1372                                  rtlefuse->
1373                                  eeprom_chnlarea_txpwr_cck[rf_path][i]));
1374         for (rf_path = 0; rf_path < 2; rf_path++)
1375                 for (i = 0; i < 3; i++)
1376                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1377                                 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1378                                  rf_path, i,
1379                                  rtlefuse->
1380                                  eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
1381         for (rf_path = 0; rf_path < 2; rf_path++)
1382                 for (i = 0; i < 3; i++)
1383                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1384                                 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1385                                  rf_path, i,
1386                                  rtlefuse->
1387                                  eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1388                                  [i]));
1389
1390         for (rf_path = 0; rf_path < 2; rf_path++) {
1391                 for (i = 0; i < 14; i++) {
1392                         index = _rtl92c_get_chnl_group((u8) i);
1393
1394                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1395                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1396                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1397                             rtlefuse->
1398                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1399
1400                         if ((rtlefuse->
1401                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1402                              rtlefuse->
1403                              eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
1404                             > 0) {
1405                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1406                                     rtlefuse->
1407                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1408                                     [index] -
1409                                     rtlefuse->
1410                                     eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1411                                     [index];
1412                         } else {
1413                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1414                         }
1415                 }
1416
1417                 for (i = 0; i < 14; i++) {
1418                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1419                                 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1420                                  "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1421                                  rtlefuse->txpwrlevel_cck[rf_path][i],
1422                                  rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1423                                  rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
1424                 }
1425         }
1426
1427         for (i = 0; i < 3; i++) {
1428                 if (!autoload_fail) {
1429                         rtlefuse->eeprom_pwrlimit_ht40[i] =
1430                             hwinfo[EEPROM_TXPWR_GROUP + i];
1431                         rtlefuse->eeprom_pwrlimit_ht20[i] =
1432                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1433                 } else {
1434                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1435                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1436                 }
1437         }
1438
1439         for (rf_path = 0; rf_path < 2; rf_path++) {
1440                 for (i = 0; i < 14; i++) {
1441                         index = _rtl92c_get_chnl_group((u8) i);
1442
1443                         if (rf_path == RF90_PATH_A) {
1444                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1445                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
1446                                      & 0xf);
1447                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1448                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
1449                                      & 0xf);
1450                         } else if (rf_path == RF90_PATH_B) {
1451                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1452                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
1453                                       & 0xf0) >> 4);
1454                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1455                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
1456                                       & 0xf0) >> 4);
1457                         }
1458
1459                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1460                                 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1461                                  rf_path, i,
1462                                  rtlefuse->pwrgroup_ht20[rf_path][i]));
1463                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1464                                 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1465                                  rf_path, i,
1466                                  rtlefuse->pwrgroup_ht40[rf_path][i]));
1467                 }
1468         }
1469
1470         for (i = 0; i < 14; i++) {
1471                 index = _rtl92c_get_chnl_group((u8) i);
1472
1473                 if (!autoload_fail)
1474                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1475                 else
1476                         tempval = EEPROM_DEFAULT_HT20_DIFF;
1477
1478                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1479                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1480                     ((tempval >> 4) & 0xF);
1481
1482                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1483                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1484
1485                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1486                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1487
1488                 index = _rtl92c_get_chnl_group((u8) i);
1489
1490                 if (!autoload_fail)
1491                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1492                 else
1493                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1494
1495                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1496                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1497                     ((tempval >> 4) & 0xF);
1498         }
1499
1500         rtlefuse->legacy_ht_txpowerdiff =
1501             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1502
1503         for (i = 0; i < 14; i++)
1504                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1505                         ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1506                          rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
1507         for (i = 0; i < 14; i++)
1508                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1509                         ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1510                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
1511         for (i = 0; i < 14; i++)
1512                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1513                         ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1514                          rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
1515         for (i = 0; i < 14; i++)
1516                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1517                         ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1518                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
1519
1520         if (!autoload_fail)
1521                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1522         else
1523                 rtlefuse->eeprom_regulatory = 0;
1524         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1525                 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
1526
1527         if (!autoload_fail) {
1528                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1529                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1530         } else {
1531                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1532                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1533         }
1534         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1535                 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1536                  rtlefuse->eeprom_tssi[RF90_PATH_A],
1537                  rtlefuse->eeprom_tssi[RF90_PATH_B]));
1538
1539         if (!autoload_fail)
1540                 tempval = hwinfo[EEPROM_THERMAL_METER];
1541         else
1542                 tempval = EEPROM_DEFAULT_THERMALMETER;
1543         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1544
1545         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1546                 rtlefuse->apk_thermalmeterignore = true;
1547
1548         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1549         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1550                 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
1551 }
1552
1553 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1554 {
1555         struct rtl_priv *rtlpriv = rtl_priv(hw);
1556         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1557         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1558         u16 i, usvalue;
1559         u8 hwinfo[HWSET_MAX_SIZE];
1560         u16 eeprom_id;
1561
1562         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1563                 rtl_efuse_shadow_map_update(hw);
1564
1565                 memcpy((void *)hwinfo,
1566                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1567                        HWSET_MAX_SIZE);
1568         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1569                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1570                          ("RTL819X Not boot from eeprom, check it !!"));
1571         }
1572
1573         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1574                       hwinfo, HWSET_MAX_SIZE);
1575
1576         eeprom_id = *((u16 *)&hwinfo[0]);
1577         if (eeprom_id != RTL8190_EEPROM_ID) {
1578                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1579                          ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
1580                 rtlefuse->autoload_failflag = true;
1581         } else {
1582                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1583                 rtlefuse->autoload_failflag = false;
1584         }
1585
1586         if (rtlefuse->autoload_failflag)
1587                 return;
1588
1589         for (i = 0; i < 6; i += 2) {
1590                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1591                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1592         }
1593
1594         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1595                  (MAC_FMT "\n", MAC_ARG(rtlefuse->dev_addr)));
1596
1597         _rtl92ce_read_txpower_info_from_hwpg(hw,
1598                                              rtlefuse->autoload_failflag,
1599                                              hwinfo);
1600
1601         rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1602                                                  rtlefuse->autoload_failflag,
1603                                                  hwinfo);
1604
1605         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1606         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1607         rtlefuse->txpwr_fromeprom = true;
1608         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1609
1610         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1611                  ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
1612
1613         /* set channel paln to world wide 13 */
1614         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1615
1616         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1617                 switch (rtlefuse->eeprom_oemid) {
1618                 case EEPROM_CID_DEFAULT:
1619                         if (rtlefuse->eeprom_did == 0x8176) {
1620                                 if ((rtlefuse->eeprom_svid == 0x103C &&
1621                                      rtlefuse->eeprom_smid == 0x1629))
1622                                         rtlhal->oem_id = RT_CID_819x_HP;
1623                                 else
1624                                         rtlhal->oem_id = RT_CID_DEFAULT;
1625                         } else {
1626                                 rtlhal->oem_id = RT_CID_DEFAULT;
1627                         }
1628                         break;
1629                 case EEPROM_CID_TOSHIBA:
1630                         rtlhal->oem_id = RT_CID_TOSHIBA;
1631                         break;
1632                 case EEPROM_CID_QMI:
1633                         rtlhal->oem_id = RT_CID_819x_QMI;
1634                         break;
1635                 case EEPROM_CID_WHQL:
1636                 default:
1637                         rtlhal->oem_id = RT_CID_DEFAULT;
1638                         break;
1639
1640                 }
1641         }
1642
1643 }
1644
1645 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1646 {
1647         struct rtl_priv *rtlpriv = rtl_priv(hw);
1648         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1649         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1650
1651         switch (rtlhal->oem_id) {
1652         case RT_CID_819x_HP:
1653                 pcipriv->ledctl.led_opendrain = true;
1654                 break;
1655         case RT_CID_819x_Lenovo:
1656         case RT_CID_DEFAULT:
1657         case RT_CID_TOSHIBA:
1658         case RT_CID_CCX:
1659         case RT_CID_819x_Acer:
1660         case RT_CID_WHQL:
1661         default:
1662                 break;
1663         }
1664         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1665                  ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
1666 }
1667
1668 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1669 {
1670         struct rtl_priv *rtlpriv = rtl_priv(hw);
1671         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1672         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1673         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1674         u8 tmp_u1b;
1675
1676         rtlhal->version = _rtl92ce_read_chip_version(hw);
1677         if (get_rf_type(rtlphy) == RF_1T1R)
1678                 rtlpriv->dm.rfpath_rxenable[0] = true;
1679         else
1680                 rtlpriv->dm.rfpath_rxenable[0] =
1681                     rtlpriv->dm.rfpath_rxenable[1] = true;
1682         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
1683                                                 rtlhal->version));
1684         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1685         if (tmp_u1b & BIT(4)) {
1686                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
1687                 rtlefuse->epromtype = EEPROM_93C46;
1688         } else {
1689                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
1690                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1691         }
1692         if (tmp_u1b & BIT(5)) {
1693                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1694                 rtlefuse->autoload_failflag = false;
1695                 _rtl92ce_read_adapter_info(hw);
1696         } else {
1697                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
1698         }
1699         _rtl92ce_hal_customized_behavior(hw);
1700 }
1701
1702 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1703                 struct ieee80211_sta *sta)
1704 {
1705         struct rtl_priv *rtlpriv = rtl_priv(hw);
1706         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1707         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1708         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1709         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1710         u32 ratr_value;
1711         u8 ratr_index = 0;
1712         u8 nmode = mac->ht_enable;
1713         u8 mimo_ps = IEEE80211_SMPS_OFF;
1714         u16 shortgi_rate;
1715         u32 tmp_ratr_value;
1716         u8 curtxbw_40mhz = mac->bw_40;
1717         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1718                                1 : 0;
1719         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1720                                1 : 0;
1721         enum wireless_mode wirelessmode = mac->mode;
1722
1723         if (rtlhal->current_bandtype == BAND_ON_5G)
1724                 ratr_value = sta->supp_rates[1] << 4;
1725         else
1726                 ratr_value = sta->supp_rates[0];
1727         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1728                         sta->ht_cap.mcs.rx_mask[0] << 12);
1729         switch (wirelessmode) {
1730         case WIRELESS_MODE_B:
1731                 if (ratr_value & 0x0000000c)
1732                         ratr_value &= 0x0000000d;
1733                 else
1734                         ratr_value &= 0x0000000f;
1735                 break;
1736         case WIRELESS_MODE_G:
1737                 ratr_value &= 0x00000FF5;
1738                 break;
1739         case WIRELESS_MODE_N_24G:
1740         case WIRELESS_MODE_N_5G:
1741                 nmode = 1;
1742                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1743                         ratr_value &= 0x0007F005;
1744                 } else {
1745                         u32 ratr_mask;
1746
1747                         if (get_rf_type(rtlphy) == RF_1T2R ||
1748                             get_rf_type(rtlphy) == RF_1T1R)
1749                                 ratr_mask = 0x000ff005;
1750                         else
1751                                 ratr_mask = 0x0f0ff005;
1752
1753                         ratr_value &= ratr_mask;
1754                 }
1755                 break;
1756         default:
1757                 if (rtlphy->rf_type == RF_1T2R)
1758                         ratr_value &= 0x000ff0ff;
1759                 else
1760                         ratr_value &= 0x0f0ff0ff;
1761
1762                 break;
1763         }
1764
1765         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1766             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1767             (rtlpcipriv->bt_coexist.bt_cur_state) &&
1768             (rtlpcipriv->bt_coexist.bt_ant_isolation) &&
1769             ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ||
1770             (rtlpcipriv->bt_coexist.bt_service == BT_BUSY)))
1771                 ratr_value &= 0x0fffcfc0;
1772         else
1773                 ratr_value &= 0x0FFFFFFF;
1774
1775         if (nmode && ((curtxbw_40mhz &&
1776                          curshortgi_40mhz) || (!curtxbw_40mhz &&
1777                                                curshortgi_20mhz))) {
1778
1779                 ratr_value |= 0x10000000;
1780                 tmp_ratr_value = (ratr_value >> 12);
1781
1782                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1783                         if ((1 << shortgi_rate) & tmp_ratr_value)
1784                                 break;
1785                 }
1786
1787                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1788                     (shortgi_rate << 4) | (shortgi_rate);
1789         }
1790
1791         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1792
1793         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1794                  ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)));
1795 }
1796
1797 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1798                 struct ieee80211_sta *sta, u8 rssi_level)
1799 {
1800         struct rtl_priv *rtlpriv = rtl_priv(hw);
1801         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1802         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1803         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1804         struct rtl_sta_info *sta_entry = NULL;
1805         u32 ratr_bitmap;
1806         u8 ratr_index;
1807         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1808                                 ? 1 : 0;
1809         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1810                                 1 : 0;
1811         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1812                                 1 : 0;
1813         enum wireless_mode wirelessmode = 0;
1814         bool shortgi = false;
1815         u8 rate_mask[5];
1816         u8 macid = 0;
1817         u8 mimo_ps = IEEE80211_SMPS_OFF;
1818
1819         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1820         wirelessmode = sta_entry->wireless_mode;
1821         if (mac->opmode == NL80211_IFTYPE_STATION)
1822                 curtxbw_40mhz = mac->bw_40;
1823         else if (mac->opmode == NL80211_IFTYPE_AP ||
1824                 mac->opmode == NL80211_IFTYPE_ADHOC)
1825                 macid = sta->aid + 1;
1826
1827         if (rtlhal->current_bandtype == BAND_ON_5G)
1828                 ratr_bitmap = sta->supp_rates[1] << 4;
1829         else
1830                 ratr_bitmap = sta->supp_rates[0];
1831         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1832                         sta->ht_cap.mcs.rx_mask[0] << 12);
1833         switch (wirelessmode) {
1834         case WIRELESS_MODE_B:
1835                 ratr_index = RATR_INX_WIRELESS_B;
1836                 if (ratr_bitmap & 0x0000000c)
1837                         ratr_bitmap &= 0x0000000d;
1838                 else
1839                         ratr_bitmap &= 0x0000000f;
1840                 break;
1841         case WIRELESS_MODE_G:
1842                 ratr_index = RATR_INX_WIRELESS_GB;
1843
1844                 if (rssi_level == 1)
1845                         ratr_bitmap &= 0x00000f00;
1846                 else if (rssi_level == 2)
1847                         ratr_bitmap &= 0x00000ff0;
1848                 else
1849                         ratr_bitmap &= 0x00000ff5;
1850                 break;
1851         case WIRELESS_MODE_A:
1852                 ratr_index = RATR_INX_WIRELESS_A;
1853                 ratr_bitmap &= 0x00000ff0;
1854                 break;
1855         case WIRELESS_MODE_N_24G:
1856         case WIRELESS_MODE_N_5G:
1857                 ratr_index = RATR_INX_WIRELESS_NGB;
1858
1859                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1860                         if (rssi_level == 1)
1861                                 ratr_bitmap &= 0x00070000;
1862                         else if (rssi_level == 2)
1863                                 ratr_bitmap &= 0x0007f000;
1864                         else
1865                                 ratr_bitmap &= 0x0007f005;
1866                 } else {
1867                         if (rtlphy->rf_type == RF_1T2R ||
1868                             rtlphy->rf_type == RF_1T1R) {
1869                                 if (curtxbw_40mhz) {
1870                                         if (rssi_level == 1)
1871                                                 ratr_bitmap &= 0x000f0000;
1872                                         else if (rssi_level == 2)
1873                                                 ratr_bitmap &= 0x000ff000;
1874                                         else
1875                                                 ratr_bitmap &= 0x000ff015;
1876                                 } else {
1877                                         if (rssi_level == 1)
1878                                                 ratr_bitmap &= 0x000f0000;
1879                                         else if (rssi_level == 2)
1880                                                 ratr_bitmap &= 0x000ff000;
1881                                         else
1882                                                 ratr_bitmap &= 0x000ff005;
1883                                 }
1884                         } else {
1885                                 if (curtxbw_40mhz) {
1886                                         if (rssi_level == 1)
1887                                                 ratr_bitmap &= 0x0f0f0000;
1888                                         else if (rssi_level == 2)
1889                                                 ratr_bitmap &= 0x0f0ff000;
1890                                         else
1891                                                 ratr_bitmap &= 0x0f0ff015;
1892                                 } else {
1893                                         if (rssi_level == 1)
1894                                                 ratr_bitmap &= 0x0f0f0000;
1895                                         else if (rssi_level == 2)
1896                                                 ratr_bitmap &= 0x0f0ff000;
1897                                         else
1898                                                 ratr_bitmap &= 0x0f0ff005;
1899                                 }
1900                         }
1901                 }
1902
1903                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1904                     (!curtxbw_40mhz && curshortgi_20mhz)) {
1905
1906                         if (macid == 0)
1907                                 shortgi = true;
1908                         else if (macid == 1)
1909                                 shortgi = false;
1910                 }
1911                 break;
1912         default:
1913                 ratr_index = RATR_INX_WIRELESS_NGB;
1914
1915                 if (rtlphy->rf_type == RF_1T2R)
1916                         ratr_bitmap &= 0x000ff0ff;
1917                 else
1918                         ratr_bitmap &= 0x0f0ff0ff;
1919                 break;
1920         }
1921         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1922                  ("ratr_bitmap :%x\n", ratr_bitmap));
1923         *(u32 *)&rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
1924                                      (ratr_index << 28));
1925         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1926         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
1927                                                  "ratr_val:%x, %x:%x:%x:%x:%x\n",
1928                                                  ratr_index, ratr_bitmap,
1929                                                  rate_mask[0], rate_mask[1],
1930                                                  rate_mask[2], rate_mask[3],
1931                                                  rate_mask[4]));
1932         rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1933
1934         if (macid != 0)
1935                 sta_entry->ratr_index = ratr_index;
1936 }
1937
1938 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
1939                 struct ieee80211_sta *sta, u8 rssi_level)
1940 {
1941         struct rtl_priv *rtlpriv = rtl_priv(hw);
1942
1943         if (rtlpriv->dm.useramask)
1944                 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level);
1945         else
1946                 rtl92ce_update_hal_rate_table(hw, sta);
1947 }
1948
1949 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1950 {
1951         struct rtl_priv *rtlpriv = rtl_priv(hw);
1952         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1953         u16 sifs_timer;
1954
1955         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1956                                       (u8 *)&mac->slot_time);
1957         if (!mac->ht_enable)
1958                 sifs_timer = 0x0a0a;
1959         else
1960                 sifs_timer = 0x1010;
1961         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
1962 }
1963
1964 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
1965 {
1966         struct rtl_priv *rtlpriv = rtl_priv(hw);
1967         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1968         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1969         enum rf_pwrstate e_rfpowerstate_toset;
1970         u8 u1tmp;
1971         bool actuallyset = false;
1972         unsigned long flag;
1973
1974         if (rtlpci->being_init_adapter)
1975                 return false;
1976
1977         if (ppsc->swrf_processing)
1978                 return false;
1979
1980         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
1981         if (ppsc->rfchange_inprogress) {
1982                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1983                 return false;
1984         } else {
1985                 ppsc->rfchange_inprogress = true;
1986                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1987         }
1988
1989         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
1990                        REG_MAC_PINMUX_CFG)&~(BIT(3)));
1991
1992         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1993         e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
1994
1995         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
1996                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1997                          ("GPIOChangeRF  - HW Radio ON, RF ON\n"));
1998
1999                 e_rfpowerstate_toset = ERFON;
2000                 ppsc->hwradiooff = false;
2001                 actuallyset = true;
2002         } else if ((ppsc->hwradiooff == false)
2003                    && (e_rfpowerstate_toset == ERFOFF)) {
2004                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2005                          ("GPIOChangeRF  - HW Radio OFF, RF OFF\n"));
2006
2007                 e_rfpowerstate_toset = ERFOFF;
2008                 ppsc->hwradiooff = true;
2009                 actuallyset = true;
2010         }
2011
2012         if (actuallyset) {
2013                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2014                 ppsc->rfchange_inprogress = false;
2015                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2016         } else {
2017                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2018                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2019
2020                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2021                 ppsc->rfchange_inprogress = false;
2022                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2023         }
2024
2025         *valid = 1;
2026         return !ppsc->hwradiooff;
2027
2028 }
2029
2030 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2031                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2032                      bool is_wepkey, bool clear_all)
2033 {
2034         struct rtl_priv *rtlpriv = rtl_priv(hw);
2035         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2036         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2037         u8 *macaddr = p_macaddr;
2038         u32 entry_id = 0;
2039         bool is_pairwise = false;
2040
2041         static u8 cam_const_addr[4][6] = {
2042                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2043                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2044                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2045                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2046         };
2047         static u8 cam_const_broad[] = {
2048                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2049         };
2050
2051         if (clear_all) {
2052                 u8 idx = 0;
2053                 u8 cam_offset = 0;
2054                 u8 clear_number = 5;
2055
2056                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
2057
2058                 for (idx = 0; idx < clear_number; idx++) {
2059                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2060                         rtl_cam_empty_entry(hw, cam_offset + idx);
2061
2062                         if (idx < 5) {
2063                                 memset(rtlpriv->sec.key_buf[idx], 0,
2064                                        MAX_KEY_LEN);
2065                                 rtlpriv->sec.key_len[idx] = 0;
2066                         }
2067                 }
2068
2069         } else {
2070                 switch (enc_algo) {
2071                 case WEP40_ENCRYPTION:
2072                         enc_algo = CAM_WEP40;
2073                         break;
2074                 case WEP104_ENCRYPTION:
2075                         enc_algo = CAM_WEP104;
2076                         break;
2077                 case TKIP_ENCRYPTION:
2078                         enc_algo = CAM_TKIP;
2079                         break;
2080                 case AESCCMP_ENCRYPTION:
2081                         enc_algo = CAM_AES;
2082                         break;
2083                 default:
2084                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2085                                         "not process\n"));
2086                         enc_algo = CAM_TKIP;
2087                         break;
2088                 }
2089
2090                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2091                         macaddr = cam_const_addr[key_index];
2092                         entry_id = key_index;
2093                 } else {
2094                         if (is_group) {
2095                                 macaddr = cam_const_broad;
2096                                 entry_id = key_index;
2097                         } else {
2098                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2099                                         entry_id = rtl_cam_get_free_entry(hw,
2100                                                                  p_macaddr);
2101                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2102                                                 RT_TRACE(rtlpriv, COMP_SEC,
2103                                                      DBG_EMERG,
2104                                                      ("Can not find free hw"
2105                                                      " security cam entry\n"));
2106                                                 return;
2107                                         }
2108                                 } else {
2109                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2110                                 }
2111
2112                                 key_index = PAIRWISE_KEYIDX;
2113                                 is_pairwise = true;
2114                         }
2115                 }
2116
2117                 if (rtlpriv->sec.key_len[key_index] == 0) {
2118                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2119                                  ("delete one entry, entry_id is %d\n",
2120                                  entry_id));
2121                         if (mac->opmode == NL80211_IFTYPE_AP)
2122                                 rtl_cam_del_entry(hw, p_macaddr);
2123                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2124                 } else {
2125                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2126                                  ("The insert KEY length is %d\n",
2127                                   rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
2128                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2129                                  ("The insert KEY  is %x %x\n",
2130                                   rtlpriv->sec.key_buf[0][0],
2131                                   rtlpriv->sec.key_buf[0][1]));
2132
2133                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2134                                  ("add one entry\n"));
2135                         if (is_pairwise) {
2136                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2137                                               "Pairwiase Key content :",
2138                                               rtlpriv->sec.pairwise_key,
2139                                               rtlpriv->sec.
2140                                               key_len[PAIRWISE_KEYIDX]);
2141
2142                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2143                                          ("set Pairwiase key\n"));
2144
2145                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2146                                                       entry_id, enc_algo,
2147                                                       CAM_CONFIG_NO_USEDK,
2148                                                       rtlpriv->sec.
2149                                                       key_buf[key_index]);
2150                         } else {
2151                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2152                                          ("set group key\n"));
2153
2154                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2155                                         rtl_cam_add_one_entry(hw,
2156                                                 rtlefuse->dev_addr,
2157                                                 PAIRWISE_KEYIDX,
2158                                                 CAM_PAIRWISE_KEY_POSITION,
2159                                                 enc_algo,
2160                                                 CAM_CONFIG_NO_USEDK,
2161                                                 rtlpriv->sec.key_buf
2162                                                 [entry_id]);
2163                                 }
2164
2165                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2166                                                 entry_id, enc_algo,
2167                                                 CAM_CONFIG_NO_USEDK,
2168                                                 rtlpriv->sec.key_buf[entry_id]);
2169                         }
2170
2171                 }
2172         }
2173 }
2174
2175 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2176 {
2177         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2178
2179         rtlpcipriv->bt_coexist.bt_coexistence =
2180                         rtlpcipriv->bt_coexist.eeprom_bt_coexist;
2181         rtlpcipriv->bt_coexist.bt_ant_num =
2182                         rtlpcipriv->bt_coexist.eeprom_bt_ant_num;
2183         rtlpcipriv->bt_coexist.bt_coexist_type =
2184                         rtlpcipriv->bt_coexist.eeprom_bt_type;
2185
2186         if (rtlpcipriv->bt_coexist.reg_bt_iso == 2)
2187                 rtlpcipriv->bt_coexist.bt_ant_isolation =
2188                         rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation;
2189         else
2190                 rtlpcipriv->bt_coexist.bt_ant_isolation =
2191                         rtlpcipriv->bt_coexist.reg_bt_iso;
2192
2193         rtlpcipriv->bt_coexist.bt_radio_shared_type =
2194                         rtlpcipriv->bt_coexist.eeprom_bt_radio_shared;
2195
2196         if (rtlpcipriv->bt_coexist.bt_coexistence) {
2197
2198                 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1)
2199                         rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION;
2200                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2)
2201                         rtlpcipriv->bt_coexist.bt_service = BT_SCO;
2202                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4)
2203                         rtlpcipriv->bt_coexist.bt_service = BT_BUSY;
2204                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5)
2205                         rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY;
2206                 else
2207                         rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
2208
2209                 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
2210                 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
2211                 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff;
2212         }
2213 }
2214
2215 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2216                                               bool auto_load_fail, u8 *hwinfo)
2217 {
2218         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2219         u8 value;
2220
2221         if (!auto_load_fail) {
2222                 rtlpcipriv->bt_coexist.eeprom_bt_coexist =
2223                                         ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2224                 value = hwinfo[RF_OPTION4];
2225                 rtlpcipriv->bt_coexist.eeprom_bt_type = ((value & 0xe) >> 1);
2226                 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (value & 0x1);
2227                 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation =
2228                                                          ((value & 0x10) >> 4);
2229                 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared =
2230                                                          ((value & 0x20) >> 5);
2231         } else {
2232                 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0;
2233                 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE;
2234                 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2235                 rtlpcipriv->bt_coexist.eeprom_bt_ant_isolation = 0;
2236                 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2237         }
2238
2239         rtl8192ce_bt_var_init(hw);
2240 }
2241
2242 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2243 {
2244         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2245
2246         /* 0:Low, 1:High, 2:From Efuse. */
2247         rtlpcipriv->bt_coexist.reg_bt_iso = 2;
2248         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2249         rtlpcipriv->bt_coexist.reg_bt_sco = 3;
2250         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2251         rtlpcipriv->bt_coexist.reg_bt_sco = 0;
2252 }
2253
2254
2255 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2256 {
2257         struct rtl_priv *rtlpriv = rtl_priv(hw);
2258         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2259         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2260
2261         u8 u1_tmp;
2262
2263         if (rtlpcipriv->bt_coexist.bt_coexistence &&
2264             ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
2265               rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) {
2266
2267                 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
2268                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2269
2270                 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2271                          BIT_OFFSET_LEN_MASK_32(0, 1);
2272                 u1_tmp = u1_tmp |
2273                          ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
2274                          0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2275                          ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ?
2276                          0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2277                 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2278
2279                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2280                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2281                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2282
2283                 /* Config to 1T1R. */
2284                 if (rtlphy->rf_type == RF_1T1R) {
2285                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2286                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2287                         rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2288
2289                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2290                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2291                         rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2292                 }
2293         }
2294 }
2295
2296 void rtl92ce_suspend(struct ieee80211_hw *hw)
2297 {
2298 }
2299
2300 void rtl92ce_resume(struct ieee80211_hw *hw)
2301 {
2302 }