drivers/net/wireless/rtlwifi/pci.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "core.h"
  31 #include "wifi.h"
  32 #include "pci.h"
  33 #include "base.h"
  34 #include "ps.h"
  35
  36 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
  37         INTEL_VENDOR_ID,
  38         ATI_VENDOR_ID,
  39         AMD_VENDOR_ID,
  40         SIS_VENDOR_ID
  41 };
  42
  43 /* Update PCI dependent default settings*/
  44 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
  45 {
  46         struct rtl_priv *rtlpriv = rtl_priv(hw);
  47         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
  48         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50         u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
  51
  52         ppsc->reg_rfps_level = 0;
  53         ppsc->support_aspm = 0;
  54
  55         /*Update PCI ASPM setting */
  56         ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
  57         switch (rtlpci->const_pci_aspm) {
  58         case 0:
  59                 /*No ASPM */
  60                 break;
  61
  62         case 1:
  63                 /*ASPM dynamically enabled/disable. */
  64                 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
  65                 break;
  66
  67         case 2:
  68                 /*ASPM with Clock Req dynamically enabled/disable. */
  69                 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
  70                                          RT_RF_OFF_LEVL_CLK_REQ);
  71                 break;
  72
  73         case 3:
  74                 /*
  75                  * Always enable ASPM and Clock Req
  76                  * from initialization to halt.
  77                  * */
  78                 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
  79                 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
  80                                          RT_RF_OFF_LEVL_CLK_REQ);
  81                 break;
  82
  83         case 4:
  84                 /*
  85                  * Always enable ASPM without Clock Req
  86                  * from initialization to halt.
  87                  * */
  88                 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
  89                                           RT_RF_OFF_LEVL_CLK_REQ);
  90                 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
  91                 break;
  92         }
  93
  94         ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
  95
  96         /*Update Radio OFF setting */
  97         switch (rtlpci->const_hwsw_rfoff_d3) {
  98         case 1:
  99                 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
 100                         ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
 101                 break;
 102
 103         case 2:
 104                 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
 105                         ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
 106                 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
 107                 break;
 108
 109         case 3:
 110                 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
 111                 break;
 112         }
 113
 114         /*Set HW definition to determine if it supports ASPM. */
 115         switch (rtlpci->const_support_pciaspm) {
 116         case 0:
 117                 /*Not support ASPM. */
 118                 ppsc->support_aspm = false;
 119                 break;
 120         case 1:
 121                 /*Support ASPM. */
 122                 ppsc->support_aspm = true;
 123                 ppsc->support_backdoor = true;
 124                 break;
 125         case 2:
 126                 /*ASPM value set by chipset. */
 127                 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
 128                         ppsc->support_aspm = true;
 129                 break;
 130         default:
 131                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 132                          ("switch case not process\n"));
 133                 break;
 134         }
 135 }
 136
 137 static bool _rtl_pci_platform_switch_device_pci_aspm(
 138                         struct ieee80211_hw *hw,
 139                         u8 value)
 140 {
 141         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 142
 143         value |= 0x40;
 144         pci_write_config_byte(rtlpci->pdev, 0x80, value);
 145
 146         return false;
 147 }
 148
 149 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
 150 static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
 151 {
 152         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 153         u8 buffer;
 154
 155         buffer = value;
 156         pci_write_config_byte(rtlpci->pdev, 0x81, value);
 157
 158         return true;
 159 }
 160
 161 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
 162 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
 163 {
 164         struct rtl_priv *rtlpriv = rtl_priv(hw);
 165         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 166         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 167         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 168         u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
 169         u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
 170         u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
 171         /*Retrieve original configuration settings. */
 172         u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
 173         u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
 174                                 pcibridge_linkctrlreg;
 175         u16 aspmlevel = 0;
 176         u8 tmp_u1b = 0;
 177
 178         if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
 179                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
 180                          ("PCI(Bridge) UNKNOWN.\n"));
 181
 182                 return;
 183         }
 184
 185         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
 186                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
 187                 _rtl_pci_switch_clk_req(hw, 0x0);
 188         }
 189
 190         /*for promising device will in L0 state after an I/O. */
 191         pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
 192
 193         /*Set corresponding value. */
 194         aspmlevel |= BIT(0) | BIT(1);
 195         linkctrl_reg &= ~aspmlevel;
 196         pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
 197
 198         _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
 199         udelay(50);
 200
 201         /*4 Disable Pci Bridge ASPM */
 202         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 203                                      pcicfg_addrport + (num4bytes << 2));
 204         rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
 205
 206         udelay(50);
 207 }
 208
 209 /*
 210  *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
 211  *power saving We should follow the sequence to enable
 212  *RTL8192SE first then enable Pci Bridge ASPM
 213  *or the system will show bluescreen.
 214  */
 215 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
 216 {
 217         struct rtl_priv *rtlpriv = rtl_priv(hw);
 218         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 219         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 220         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 221         u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
 222         u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
 223         u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
 224         u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
 225         u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
 226         u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
 227         u16 aspmlevel;
 228         u8 u_pcibridge_aspmsetting;
 229         u8 u_device_aspmsetting;
 230
 231         if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
 232                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
 233                          ("PCI(Bridge) UNKNOWN.\n"));
 234                 return;
 235         }
 236
 237         /*4 Enable Pci Bridge ASPM */
 238         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 239                                      pcicfg_addrport + (num4bytes << 2));
 240
 241         u_pcibridge_aspmsetting =
 242             pcipriv->ndis_adapter.pcibridge_linkctrlreg |
 243             rtlpci->const_hostpci_aspm_setting;
 244
 245         if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
 246                 u_pcibridge_aspmsetting &= ~BIT(0);
 247
 248         rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
 249
 250         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 251                  ("PlatformEnableASPM():PciBridge busnumber[%x], "
 252                   "DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
 253                   pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
 254                   (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
 255                   u_pcibridge_aspmsetting));
 256
 257         udelay(50);
 258
 259         /*Get ASPM level (with/without Clock Req) */
 260         aspmlevel = rtlpci->const_devicepci_aspm_setting;
 261         u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
 262
 263         /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
 264         /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
 265
 266         u_device_aspmsetting |= aspmlevel;
 267
 268         _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
 269
 270         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
 271                 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
 272                                              RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
 273                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
 274         }
 275         udelay(200);
 276 }
 277
 278 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
 279 {
 280         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 281         u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
 282
 283         bool status = false;
 284         u8 offset_e0;
 285         unsigned offset_e4;
 286
 287         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 288                         pcicfg_addrport + 0xE0);
 289         rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
 290
 291         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 292                         pcicfg_addrport + 0xE0);
 293         rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
 294
 295         if (offset_e0 == 0xA0) {
 296                 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 297                                              pcicfg_addrport + 0xE4);
 298                 rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
 299                 if (offset_e4 & BIT(23))
 300                         status = true;
 301         }
 302
 303         return status;
 304 }
 305
 306 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
 307 {
 308         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 309         u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
 310         u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
 311         u8 linkctrl_reg;
 312         u8 num4bBytes;
 313
 314         num4bBytes = (capabilityoffset + 0x10) / 4;
 315
 316         /*Read  Link Control Register */
 317         rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
 318                                      pcicfg_addrport + (num4bBytes << 2));
 319         rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
 320
 321         pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
 322 }
 323
 324 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
 325                 struct ieee80211_hw *hw)
 326 {
 327         struct rtl_priv *rtlpriv = rtl_priv(hw);
 328         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 329
 330         u8 tmp;
 331         int pos;
 332         u8 linkctrl_reg;
 333
 334         /*Link Control Register */
 335         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
 336         pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
 337         pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
 338
 339         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 340                  ("Link Control Register =%x\n",
 341                   pcipriv->ndis_adapter.linkctrl_reg));
 342
 343         pci_read_config_byte(pdev, 0x98, &tmp);
 344         tmp |= BIT(4);
 345         pci_write_config_byte(pdev, 0x98, tmp);
 346
 347         tmp = 0x17;
 348         pci_write_config_byte(pdev, 0x70f, tmp);
 349 }
 350
 351 static void _rtl_pci_initialize_adapter_common(struct ieee80211_hw *hw)
 352 {
 353         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 354
 355         _rtl_pci_update_default_setting(hw);
 356
 357         if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
 358                 /*Always enable ASPM & Clock Req. */
 359                 rtl_pci_enable_aspm(hw);
 360                 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
 361         }
 362
 363 }
 364
 365 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
 366 {
 367         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 368
 369         /*close ASPM for AMD defaultly */
 370         rtlpci->const_amdpci_aspm = 0;
 371
 372         /*
 373          * ASPM PS mode.
 374          * 0 - Disable ASPM,
 375          * 1 - Enable ASPM without Clock Req,
 376          * 2 - Enable ASPM with Clock Req,
 377          * 3 - Always Enable ASPM with Clock Req,
 378          * 4 - Always Enable ASPM without Clock Req.
 379          * set defult to RTL8192CE:3 RTL8192E:2
 380          * */
 381         rtlpci->const_pci_aspm = 3;
 382
 383         /*Setting for PCI-E device */
 384         rtlpci->const_devicepci_aspm_setting = 0x03;
 385
 386         /*Setting for PCI-E bridge */
 387         rtlpci->const_hostpci_aspm_setting = 0x02;
 388
 389         /*
 390          * In Hw/Sw Radio Off situation.
 391          * 0 - Default,
 392          * 1 - From ASPM setting without low Mac Pwr,
 393          * 2 - From ASPM setting with low Mac Pwr,
 394          * 3 - Bus D3
 395          * set default to RTL8192CE:0 RTL8192SE:2
 396          */
 397         rtlpci->const_hwsw_rfoff_d3 = 0;
 398
 399         /*
 400          * This setting works for those device with
 401          * backdoor ASPM setting such as EPHY setting.
 402          * 0 - Not support ASPM,
 403          * 1 - Support ASPM,
 404          * 2 - According to chipset.
 405          */
 406         rtlpci->const_support_pciaspm = 1;
 407
 408         _rtl_pci_initialize_adapter_common(hw);
 409 }
 410
 411 static void _rtl_pci_io_handler_init(struct device *dev,
 412                                      struct ieee80211_hw *hw)
 413 {
 414         struct rtl_priv *rtlpriv = rtl_priv(hw);
 415
 416         rtlpriv->io.dev = dev;
 417
 418         rtlpriv->io.write8_async = pci_write8_async;
 419         rtlpriv->io.write16_async = pci_write16_async;
 420         rtlpriv->io.write32_async = pci_write32_async;
 421
 422         rtlpriv->io.read8_sync = pci_read8_sync;
 423         rtlpriv->io.read16_sync = pci_read16_sync;
 424         rtlpriv->io.read32_sync = pci_read32_sync;
 425
 426 }
 427
 428 static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
 429 {
 430 }
 431
 432 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
 433 {
 434         struct rtl_priv *rtlpriv = rtl_priv(hw);
 435         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 436
 437         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
 438
 439         while (skb_queue_len(&ring->queue)) {
 440                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
 441                 struct sk_buff *skb;
 442                 struct ieee80211_tx_info *info;
 443
 444                 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
 445                                                           HW_DESC_OWN);
 446
 447                 /*
 448                  *beacon packet will only use the first
 449                  *descriptor defautly,and the own may not
 450                  *be cleared by the hardware
 451                  */
 452                 if (own)
 453                         return;
 454                 ring->idx = (ring->idx + 1) % ring->entries;
 455
 456                 skb = __skb_dequeue(&ring->queue);
 457                 pci_unmap_single(rtlpci->pdev,
 458                                  rtlpriv->cfg->ops->
 459                                              get_desc((u8 *) entry, true,
 460                                                       HW_DESC_TXBUFF_ADDR),
 461                                  skb->len, PCI_DMA_TODEVICE);
 462
 463                 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
 464                          ("new ring->idx:%d, "
 465                           "free: skb_queue_len:%d, free: seq:%x\n",
 466                           ring->idx,
 467                           skb_queue_len(&ring->queue),
 468                           *(u16 *) (skb->data + 22)));
 469
 470                 info = IEEE80211_SKB_CB(skb);
 471                 ieee80211_tx_info_clear_status(info);
 472
 473                 info->flags |= IEEE80211_TX_STAT_ACK;
 474                 /*info->status.rates[0].count = 1; */
 475
 476                 ieee80211_tx_status_irqsafe(hw, skb);
 477
 478                 if ((ring->entries - skb_queue_len(&ring->queue))
 479                                 == 2) {
 480
 481                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 482                                         ("more desc left, wake"
 483                                          "skb_queue@%d,ring->idx = %d,"
 484                                          "skb_queue_len = 0x%d\n",
 485                                          prio, ring->idx,
 486                                          skb_queue_len(&ring->queue)));
 487
 488                         ieee80211_wake_queue(hw,
 489                                         skb_get_queue_mapping
 490                                         (skb));
 491                 }
 492
 493                 skb = NULL;
 494         }
 495
 496         if (((rtlpriv->link_info.num_rx_inperiod +
 497                 rtlpriv->link_info.num_tx_inperiod) > 8) ||
 498                 (rtlpriv->link_info.num_rx_inperiod > 2)) {
 499                 rtl_lps_leave(hw);
 500         }
 501 }
 502
 503 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
 504 {
 505         struct rtl_priv *rtlpriv = rtl_priv(hw);
 506         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 507         int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
 508
 509         struct ieee80211_rx_status rx_status = { 0 };
 510         unsigned int count = rtlpci->rxringcount;
 511         u8 own;
 512         u8 tmp_one;
 513         u32 bufferaddress;
 514         bool unicast = false;
 515
 516         struct rtl_stats stats = {
 517                 .signal = 0,
 518                 .noise = -98,
 519                 .rate = 0,
 520         };
 521
 522         /*RX NORMAL PKT */
 523         while (count--) {
 524                 /*rx descriptor */
 525                 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
 526                                 rtlpci->rx_ring[rx_queue_idx].idx];
 527                 /*rx pkt */
 528                 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
 529                                 rtlpci->rx_ring[rx_queue_idx].idx];
 530
 531                 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
 532                                                        false, HW_DESC_OWN);
 533
 534                 if (own) {
 535                         /*wait data to be filled by hardware */
 536                         return;
 537                 } else {
 538                         struct ieee80211_hdr *hdr;
 539                         __le16 fc;
 540                         struct sk_buff *new_skb = NULL;
 541
 542                         rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
 543                                                          &rx_status,
 544                                                          (u8 *) pdesc, skb);
 545
 546                         pci_unmap_single(rtlpci->pdev,
 547                                          *((dma_addr_t *) skb->cb),
 548                                          rtlpci->rxbuffersize,
 549                                          PCI_DMA_FROMDEVICE);
 550
 551                         skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
 552                                                          false,
 553                                                          HW_DESC_RXPKT_LEN));
 554                         skb_reserve(skb,
 555                                     stats.rx_drvinfo_size + stats.rx_bufshift);
 556
 557                         /*
 558                          *NOTICE This can not be use for mac80211,
 559                          *this is done in mac80211 code,
 560                          *if you done here sec DHCP will fail
 561                          *skb_trim(skb, skb->len - 4);
 562                          */
 563
 564                         hdr = (struct ieee80211_hdr *)(skb->data);
 565                         fc = hdr->frame_control;
 566
 567                         if (!stats.crc) {
 568                                 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
 569                                        sizeof(rx_status));
 570
 571                                 if (is_broadcast_ether_addr(hdr->addr1))
 572                                         ;/*TODO*/
 573                                 else {
 574                                         if (is_multicast_ether_addr(hdr->addr1))
 575                                                 ;/*TODO*/
 576                                         else {
 577                                                 unicast = true;
 578                                                 rtlpriv->stats.rxbytesunicast +=
 579                                                     skb->len;
 580                                         }
 581                                 }
 582
 583                                 rtl_is_special_data(hw, skb, false);
 584
 585                                 if (ieee80211_is_data(fc)) {
 586                                         rtlpriv->cfg->ops->led_control(hw,
 587                                                                LED_CTL_RX);
 588
 589                                         if (unicast)
 590                                                 rtlpriv->link_info.
 591                                                     num_rx_inperiod++;
 592                                 }
 593
 594                                 if (unlikely(!rtl_action_proc(hw, skb,
 595                                     false))) {
 596                                         dev_kfree_skb_any(skb);
 597                                 } else {
 598                                         struct sk_buff *uskb = NULL;
 599                                         u8 *pdata;
 600                                         uskb = dev_alloc_skb(skb->len + 128);
 601                                         if (!uskb) {
 602                                                 RT_TRACE(rtlpriv,
 603                                                         (COMP_INTR | COMP_RECV),
 604                                                         DBG_EMERG,
 605                                                         ("can't alloc rx skb\n"));
 606                                                 goto done;
 607                                         }
 608                                         memcpy(IEEE80211_SKB_RXCB(uskb),
 609                                                         &rx_status,
 610                                                         sizeof(rx_status));
 611                                         pdata = (u8 *)skb_put(uskb, skb->len);
 612                                         memcpy(pdata, skb->data, skb->len);
 613                                         dev_kfree_skb_any(skb);
 614
 615                                         ieee80211_rx_irqsafe(hw, uskb);
 616                                 }
 617                         } else {
 618                                 dev_kfree_skb_any(skb);
 619                         }
 620
 621                         if (((rtlpriv->link_info.num_rx_inperiod +
 622                                 rtlpriv->link_info.num_tx_inperiod) > 8) ||
 623                                 (rtlpriv->link_info.num_rx_inperiod > 2)) {
 624                                 rtl_lps_leave(hw);
 625                         }
 626
 627                         new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
 628                         if (unlikely(!new_skb)) {
 629                                 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
 630                                          DBG_EMERG,
 631                                          ("can't alloc skb for rx\n"));
 632                                 goto done;
 633                         }
 634                         skb = new_skb;
 635                         /*skb->dev = dev; */
 636
 637                         rtlpci->rx_ring[rx_queue_idx].rx_buf[rtlpci->
 638                                                              rx_ring
 639                                                              [rx_queue_idx].
 640                                                              idx] = skb;
 641                         *((dma_addr_t *) skb->cb) =
 642                             pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
 643                                            rtlpci->rxbuffersize,
 644                                            PCI_DMA_FROMDEVICE);
 645
 646                 }
 647 done:
 648                 bufferaddress = (u32)(*((dma_addr_t *) skb->cb));
 649                 tmp_one = 1;
 650                 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
 651                                             HW_DESC_RXBUFF_ADDR,
 652                                             (u8 *)&bufferaddress);
 653                 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
 654                                             (u8 *)&tmp_one);
 655                 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
 656                                             HW_DESC_RXPKT_LEN,
 657                                             (u8 *)&rtlpci->rxbuffersize);
 658
 659                 if (rtlpci->rx_ring[rx_queue_idx].idx ==
 660                     rtlpci->rxringcount - 1)
 661                         rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
 662                                                     HW_DESC_RXERO,
 663                                                     (u8 *)&tmp_one);
 664
 665                 rtlpci->rx_ring[rx_queue_idx].idx =
 666                     (rtlpci->rx_ring[rx_queue_idx].idx + 1) %
 667                     rtlpci->rxringcount;
 668         }
 669
 670 }
 671
 672 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
 673 {
 674         struct ieee80211_hw *hw = dev_id;
 675         struct rtl_priv *rtlpriv = rtl_priv(hw);
 676         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 677         unsigned long flags;
 678         u32 inta = 0;
 679         u32 intb = 0;
 680
 681         if (rtlpci->irq_enabled == 0)
 682                 return IRQ_HANDLED;
 683
 684         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
 685
 686         /*read ISR: 4/8bytes */
 687         rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
 688
 689         /*Shared IRQ or HW disappared */
 690         if (!inta || inta == 0xffff)
 691                 goto done;
 692
 693         /*<1> beacon related */
 694         if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
 695                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 696                          ("beacon ok interrupt!\n"));
 697         }
 698
 699         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
 700                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 701                          ("beacon err interrupt!\n"));
 702         }
 703
 704         if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
 705                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 706                          ("beacon interrupt!\n"));
 707         }
 708
 709         if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
 710                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 711                          ("prepare beacon for interrupt!\n"));
 712                 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
 713         }
 714
 715         /*<3> Tx related */
 716         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
 717                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
 718
 719         if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
 720                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 721                          ("Manage ok interrupt!\n"));
 722                 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
 723         }
 724
 725         if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
 726                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 727                          ("HIGH_QUEUE ok interrupt!\n"));
 728                 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
 729         }
 730
 731         if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
 732                 rtlpriv->link_info.num_tx_inperiod++;
 733
 734                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 735                          ("BK Tx OK interrupt!\n"));
 736                 _rtl_pci_tx_isr(hw, BK_QUEUE);
 737         }
 738
 739         if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
 740                 rtlpriv->link_info.num_tx_inperiod++;
 741
 742                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 743                          ("BE TX OK interrupt!\n"));
 744                 _rtl_pci_tx_isr(hw, BE_QUEUE);
 745         }
 746
 747         if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
 748                 rtlpriv->link_info.num_tx_inperiod++;
 749
 750                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 751                          ("VI TX OK interrupt!\n"));
 752                 _rtl_pci_tx_isr(hw, VI_QUEUE);
 753         }
 754
 755         if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
 756                 rtlpriv->link_info.num_tx_inperiod++;
 757
 758                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
 759                          ("Vo TX OK interrupt!\n"));
 760                 _rtl_pci_tx_isr(hw, VO_QUEUE);
 761         }
 762
 763         /*<2> Rx related */
 764         if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
 765                 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
 766                 tasklet_schedule(&rtlpriv->works.irq_tasklet);
 767         }
 768
 769         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
 770                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 771                          ("rx descriptor unavailable!\n"));
 772                 tasklet_schedule(&rtlpriv->works.irq_tasklet);
 773         }
 774
 775         if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
 776                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
 777                 tasklet_schedule(&rtlpriv->works.irq_tasklet);
 778         }
 779
 780         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
 781         return IRQ_HANDLED;
 782
 783 done:
 784         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
 785         return IRQ_HANDLED;
 786 }
 787
 788 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
 789 {
 790         _rtl_pci_rx_interrupt(hw);
 791 }
 792
 793 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
 794 {
 795         struct rtl_priv *rtlpriv = rtl_priv(hw);
 796         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 797         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 798         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
 799         struct ieee80211_hdr *hdr = NULL;
 800         struct ieee80211_tx_info *info = NULL;
 801         struct sk_buff *pskb = NULL;
 802         struct rtl_tx_desc *pdesc = NULL;
 803         unsigned int queue_index;
 804         u8 temp_one = 1;
 805
 806         ring = &rtlpci->tx_ring[BEACON_QUEUE];
 807         pskb = __skb_dequeue(&ring->queue);
 808         if (pskb)
 809                 kfree_skb(pskb);
 810
 811         /*NB: the beacon data buffer must be 32-bit aligned. */
 812         pskb = ieee80211_beacon_get(hw, mac->vif);
 813         if (pskb == NULL)
 814                 return;
 815         hdr = (struct ieee80211_hdr *)(pskb->data);
 816         info = IEEE80211_SKB_CB(pskb);
 817
 818         queue_index = BEACON_QUEUE;
 819
 820         pdesc = &ring->desc[0];
 821         rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
 822                                         info, pskb, queue_index);
 823
 824         __skb_queue_tail(&ring->queue, pskb);
 825
 826         rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
 827                                     (u8 *)&temp_one);
 828
 829         return;
 830 }
 831
 832 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
 833 {
 834         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 835         u8 i;
 836
 837         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
 838                 rtlpci->txringcount[i] = RT_TXDESC_NUM;
 839
 840         /*
 841          *we just alloc 2 desc for beacon queue,
 842          *because we just need first desc in hw beacon.
 843          */
 844         rtlpci->txringcount[BEACON_QUEUE] = 2;
 845
 846         /*
 847          *BE queue need more descriptor for performance
 848          *consideration or, No more tx desc will happen,
 849          *and may cause mac80211 mem leakage.
 850          */
 851         rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
 852
 853         rtlpci->rxbuffersize = 9100;    /*2048/1024; */
 854         rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT;     /*64; */
 855 }
 856
 857 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
 858                 struct pci_dev *pdev)
 859 {
 860         struct rtl_priv *rtlpriv = rtl_priv(hw);
 861         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 862         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 863         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 864         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 865
 866         rtlpci->up_first_time = true;
 867         rtlpci->being_init_adapter = false;
 868
 869         rtlhal->hw = hw;
 870         rtlpci->pdev = pdev;
 871
 872         ppsc->inactiveps = false;
 873         ppsc->leisure_ps = true;
 874         ppsc->fwctrl_lps = true;
 875         ppsc->reg_fwctrl_lps = 3;
 876         ppsc->reg_max_lps_awakeintvl = 5;
 877
 878         if (ppsc->reg_fwctrl_lps == 1)
 879                 ppsc->fwctrl_psmode = FW_PS_MIN_MODE;
 880         else if (ppsc->reg_fwctrl_lps == 2)
 881                 ppsc->fwctrl_psmode = FW_PS_MAX_MODE;
 882         else if (ppsc->reg_fwctrl_lps == 3)
 883                 ppsc->fwctrl_psmode = FW_PS_DTIM_MODE;
 884
 885         /*Tx/Rx related var */
 886         _rtl_pci_init_trx_var(hw);
 887
 888          /*IBSS*/ mac->beacon_interval = 100;
 889
 890          /*AMPDU*/ mac->min_space_cfg = 0;
 891         mac->max_mss_density = 0;
 892         /*set sane AMPDU defaults */
 893         mac->current_ampdu_density = 7;
 894         mac->current_ampdu_factor = 3;
 895
 896          /*QOS*/ rtlpci->acm_method = eAcmWay2_SW;
 897
 898         /*task */
 899         tasklet_init(&rtlpriv->works.irq_tasklet,
 900                      (void (*)(unsigned long))_rtl_pci_irq_tasklet,
 901                      (unsigned long)hw);
 902         tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
 903                      (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
 904                      (unsigned long)hw);
 905 }
 906
 907 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
 908                                  unsigned int prio, unsigned int entries)
 909 {
 910         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 911         struct rtl_priv *rtlpriv = rtl_priv(hw);
 912         struct rtl_tx_desc *ring;
 913         dma_addr_t dma;
 914         u32 nextdescaddress;
 915         int i;
 916
 917         ring = pci_alloc_consistent(rtlpci->pdev,
 918                                     sizeof(*ring) * entries, &dma);
 919
 920         if (!ring || (unsigned long)ring & 0xFF) {
 921                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 922                          ("Cannot allocate TX ring (prio = %d)\n", prio));
 923                 return -ENOMEM;
 924         }
 925
 926         memset(ring, 0, sizeof(*ring) * entries);
 927         rtlpci->tx_ring[prio].desc = ring;
 928         rtlpci->tx_ring[prio].dma = dma;
 929         rtlpci->tx_ring[prio].idx = 0;
 930         rtlpci->tx_ring[prio].entries = entries;
 931         skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
 932
 933         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 934                  ("queue:%d, ring_addr:%p\n", prio, ring));
 935
 936         for (i = 0; i < entries; i++) {
 937                 nextdescaddress = (u32) dma + ((i + 1) % entries) *
 938                                               sizeof(*ring);
 939
 940                 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
 941                                             true, HW_DESC_TX_NEXTDESC_ADDR,
 942                                             (u8 *)&nextdescaddress);
 943         }
 944
 945         return 0;
 946 }
 947
 948 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
 949 {
 950         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 951         struct rtl_priv *rtlpriv = rtl_priv(hw);
 952         struct rtl_rx_desc *entry = NULL;
 953         int i, rx_queue_idx;
 954         u8 tmp_one = 1;
 955
 956         /*
 957          *rx_queue_idx 0:RX_MPDU_QUEUE
 958          *rx_queue_idx 1:RX_CMD_QUEUE
 959          */
 960         for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
 961              rx_queue_idx++) {
 962                 rtlpci->rx_ring[rx_queue_idx].desc =
 963                     pci_alloc_consistent(rtlpci->pdev,
 964                                          sizeof(*rtlpci->rx_ring[rx_queue_idx].
 965                                                 desc) * rtlpci->rxringcount,
 966                                          &rtlpci->rx_ring[rx_queue_idx].dma);
 967
 968                 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
 969                     (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
 970                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 971                                  ("Cannot allocate RX ring\n"));
 972                         return -ENOMEM;
 973                 }
 974
 975                 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
 976                        sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
 977                        rtlpci->rxringcount);
 978
 979                 rtlpci->rx_ring[rx_queue_idx].idx = 0;
 980
 981                 for (i = 0; i < rtlpci->rxringcount; i++) {
 982                         struct sk_buff *skb =
 983                             dev_alloc_skb(rtlpci->rxbuffersize);
 984                         u32 bufferaddress;
 985                         if (!skb)
 986                                 return 0;
 987                         entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
 988
 989                         /*skb->dev = dev; */
 990
 991                         rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
 992
 993                         /*
 994                          *just set skb->cb to mapping addr
 995                          *for pci_unmap_single use
 996                          */
 997                         *((dma_addr_t *) skb->cb) =
 998                             pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
 999                                            rtlpci->rxbuffersize,
1000                                            PCI_DMA_FROMDEVICE);
1001
1002                         bufferaddress = (u32)(*((dma_addr_t *)skb->cb));
1003                         rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1004                                                     HW_DESC_RXBUFF_ADDR,
1005                                                     (u8 *)&bufferaddress);
1006                         rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1007                                                     HW_DESC_RXPKT_LEN,
1008                                                     (u8 *)&rtlpci->
1009                                                     rxbuffersize);
1010                         rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1011                                                     HW_DESC_RXOWN,
1012                                                     (u8 *)&tmp_one);
1013                 }
1014
1015                 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1016                                             HW_DESC_RXERO, (u8 *)&tmp_one);
1017         }
1018         return 0;
1019 }
1020
1021 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1022                 unsigned int prio)
1023 {
1024         struct rtl_priv *rtlpriv = rtl_priv(hw);
1025         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1026         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1027
1028         while (skb_queue_len(&ring->queue)) {
1029                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1030                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1031
1032                 pci_unmap_single(rtlpci->pdev,
1033                                  rtlpriv->cfg->
1034                                              ops->get_desc((u8 *) entry, true,
1035                                                    HW_DESC_TXBUFF_ADDR),
1036                                  skb->len, PCI_DMA_TODEVICE);
1037                 kfree_skb(skb);
1038                 ring->idx = (ring->idx + 1) % ring->entries;
1039         }
1040
1041         pci_free_consistent(rtlpci->pdev,
1042                             sizeof(*ring->desc) * ring->entries,
1043                             ring->desc, ring->dma);
1044         ring->desc = NULL;
1045 }
1046
1047 static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1048 {
1049         int i, rx_queue_idx;
1050
1051         /*rx_queue_idx 0:RX_MPDU_QUEUE */
1052         /*rx_queue_idx 1:RX_CMD_QUEUE */
1053         for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1054              rx_queue_idx++) {
1055                 for (i = 0; i < rtlpci->rxringcount; i++) {
1056                         struct sk_buff *skb =
1057                             rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1058                         if (!skb)
1059                                 continue;
1060
1061                         pci_unmap_single(rtlpci->pdev,
1062                                          *((dma_addr_t *) skb->cb),
1063                                          rtlpci->rxbuffersize,
1064                                          PCI_DMA_FROMDEVICE);
1065                         kfree_skb(skb);
1066                 }
1067
1068                 pci_free_consistent(rtlpci->pdev,
1069                                     sizeof(*rtlpci->rx_ring[rx_queue_idx].
1070                                            desc) * rtlpci->rxringcount,
1071                                     rtlpci->rx_ring[rx_queue_idx].desc,
1072                                     rtlpci->rx_ring[rx_queue_idx].dma);
1073                 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1074         }
1075 }
1076
1077 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1078 {
1079         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1080         int ret;
1081         int i;
1082
1083         ret = _rtl_pci_init_rx_ring(hw);
1084         if (ret)
1085                 return ret;
1086
1087         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1088                 ret = _rtl_pci_init_tx_ring(hw, i,
1089                                  rtlpci->txringcount[i]);
1090                 if (ret)
1091                         goto err_free_rings;
1092         }
1093
1094         return 0;
1095
1096 err_free_rings:
1097         _rtl_pci_free_rx_ring(rtlpci);
1098
1099         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1100                 if (rtlpci->tx_ring[i].desc)
1101                         _rtl_pci_free_tx_ring(hw, i);
1102
1103         return 1;
1104 }
1105
1106 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1107 {
1108         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1109         u32 i;
1110
1111         /*free rx rings */
1112         _rtl_pci_free_rx_ring(rtlpci);
1113
1114         /*free tx rings */
1115         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1116                 _rtl_pci_free_tx_ring(hw, i);
1117
1118         return 0;
1119 }
1120
1121 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1122 {
1123         struct rtl_priv *rtlpriv = rtl_priv(hw);
1124         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1125         int i, rx_queue_idx;
1126         unsigned long flags;
1127         u8 tmp_one = 1;
1128
1129         /*rx_queue_idx 0:RX_MPDU_QUEUE */
1130         /*rx_queue_idx 1:RX_CMD_QUEUE */
1131         for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1132              rx_queue_idx++) {
1133                 /*
1134                  *force the rx_ring[RX_MPDU_QUEUE/
1135                  *RX_CMD_QUEUE].idx to the first one
1136                  */
1137                 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1138                         struct rtl_rx_desc *entry = NULL;
1139
1140                         for (i = 0; i < rtlpci->rxringcount; i++) {
1141                                 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1142                                 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1143                                                             false,
1144                                                             HW_DESC_RXOWN,
1145                                                             (u8 *)&tmp_one);
1146                         }
1147                         rtlpci->rx_ring[rx_queue_idx].idx = 0;
1148                 }
1149         }
1150
1151         /*
1152          *after reset, release previous pending packet,
1153          *and force the  tx idx to the first one
1154          */
1155         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1156         for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1157                 if (rtlpci->tx_ring[i].desc) {
1158                         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1159
1160                         while (skb_queue_len(&ring->queue)) {
1161                                 struct rtl_tx_desc *entry =
1162                                     &ring->desc[ring->idx];
1163                                 struct sk_buff *skb =
1164                                     __skb_dequeue(&ring->queue);
1165
1166                                 pci_unmap_single(rtlpci->pdev,
1167                                                  rtlpriv->cfg->ops->
1168                                                          get_desc((u8 *)
1169                                                          entry,
1170                                                          true,
1171                                                          HW_DESC_TXBUFF_ADDR),
1172                                                  skb->len, PCI_DMA_TODEVICE);
1173                                 kfree_skb(skb);
1174                                 ring->idx = (ring->idx + 1) % ring->entries;
1175                         }
1176                         ring->idx = 0;
1177                 }
1178         }
1179
1180         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1181
1182         return 0;
1183 }
1184
1185 static unsigned int _rtl_mac_to_hwqueue(__le16 fc,
1186                 unsigned int mac80211_queue_index)
1187 {
1188         unsigned int hw_queue_index;
1189
1190         if (unlikely(ieee80211_is_beacon(fc))) {
1191                 hw_queue_index = BEACON_QUEUE;
1192                 goto out;
1193         }
1194
1195         if (ieee80211_is_mgmt(fc)) {
1196                 hw_queue_index = MGNT_QUEUE;
1197                 goto out;
1198         }
1199
1200         switch (mac80211_queue_index) {
1201         case 0:
1202                 hw_queue_index = VO_QUEUE;
1203                 break;
1204         case 1:
1205                 hw_queue_index = VI_QUEUE;
1206                 break;
1207         case 2:
1208                 hw_queue_index = BE_QUEUE;;
1209                 break;
1210         case 3:
1211                 hw_queue_index = BK_QUEUE;
1212                 break;
1213         default:
1214                 hw_queue_index = BE_QUEUE;
1215                 RT_ASSERT(false, ("QSLT_BE queue, skb_queue:%d\n",
1216                                   mac80211_queue_index));
1217                 break;
1218         }
1219
1220 out:
1221         return hw_queue_index;
1222 }
1223
1224 static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1225 {
1226         struct rtl_priv *rtlpriv = rtl_priv(hw);
1227         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1228         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1229         struct rtl8192_tx_ring *ring;
1230         struct rtl_tx_desc *pdesc;
1231         u8 idx;
1232         unsigned int queue_index, hw_queue;
1233         unsigned long flags;
1234         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
1235         __le16 fc = hdr->frame_control;
1236         u8 *pda_addr = hdr->addr1;
1237         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1238         /*ssn */
1239         u8 *qc = NULL;
1240         u8 tid = 0;
1241         u16 seq_number = 0;
1242         u8 own;
1243         u8 temp_one = 1;
1244
1245         if (ieee80211_is_mgmt(fc))
1246                 rtl_tx_mgmt_proc(hw, skb);
1247         rtl_action_proc(hw, skb, true);
1248
1249         queue_index = skb_get_queue_mapping(skb);
1250         hw_queue = _rtl_mac_to_hwqueue(fc, queue_index);
1251
1252         if (is_multicast_ether_addr(pda_addr))
1253                 rtlpriv->stats.txbytesmulticast += skb->len;
1254         else if (is_broadcast_ether_addr(pda_addr))
1255                 rtlpriv->stats.txbytesbroadcast += skb->len;
1256         else
1257                 rtlpriv->stats.txbytesunicast += skb->len;
1258
1259         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1260
1261         ring = &rtlpci->tx_ring[hw_queue];
1262         if (hw_queue != BEACON_QUEUE)
1263                 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1264                                 ring->entries;
1265         else
1266                 idx = 0;
1267
1268         pdesc = &ring->desc[idx];
1269         own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1270                         true, HW_DESC_OWN);
1271
1272         if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1273                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1274                          ("No more TX desc@%d, ring->idx = %d,"
1275                           "idx = %d, skb_queue_len = 0x%d\n",
1276                           hw_queue, ring->idx, idx,
1277                           skb_queue_len(&ring->queue)));
1278
1279                 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1280                 return skb->len;
1281         }
1282
1283         /*
1284          *if(ieee80211_is_nullfunc(fc)) {
1285          *      spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1286          *      return 1;
1287          *}
1288          */
1289
1290         if (ieee80211_is_data_qos(fc)) {
1291                 qc = ieee80211_get_qos_ctl(hdr);
1292                 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1293
1294                 seq_number = mac->tids[tid].seq_number;
1295                 seq_number &= IEEE80211_SCTL_SEQ;
1296                 /*
1297                  *hdr->seq_ctrl = hdr->seq_ctrl &
1298                  *cpu_to_le16(IEEE80211_SCTL_FRAG);
1299                  *hdr->seq_ctrl |= cpu_to_le16(seq_number);
1300                  */
1301
1302                 seq_number += 1;
1303         }
1304
1305         if (ieee80211_is_data(fc))
1306                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1307
1308         rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1309                                         info, skb, hw_queue);
1310
1311         __skb_queue_tail(&ring->queue, skb);
1312
1313         rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true,
1314                                     HW_DESC_OWN, (u8 *)&temp_one);
1315
1316         if (!ieee80211_has_morefrags(hdr->frame_control)) {
1317                 if (qc)
1318                         mac->tids[tid].seq_number = seq_number;
1319         }
1320
1321         if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1322             hw_queue != BEACON_QUEUE) {
1323
1324                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1325                          ("less desc left, stop skb_queue@%d, "
1326                           "ring->idx = %d,"
1327                           "idx = %d, skb_queue_len = 0x%d\n",
1328                           hw_queue, ring->idx, idx,
1329                           skb_queue_len(&ring->queue)));
1330
1331                 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1332         }
1333
1334         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1335
1336         rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1337
1338         return 0;
1339 }
1340
1341 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1342 {
1343         struct rtl_priv *rtlpriv = rtl_priv(hw);
1344         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1345
1346         _rtl_pci_deinit_trx_ring(hw);
1347
1348         synchronize_irq(rtlpci->pdev->irq);
1349         tasklet_kill(&rtlpriv->works.irq_tasklet);
1350
1351         flush_workqueue(rtlpriv->works.rtl_wq);
1352         destroy_workqueue(rtlpriv->works.rtl_wq);
1353
1354 }
1355
1356 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1357 {
1358         struct rtl_priv *rtlpriv = rtl_priv(hw);
1359         int err;
1360
1361         _rtl_pci_init_struct(hw, pdev);
1362
1363         err = _rtl_pci_init_trx_ring(hw);
1364         if (err) {
1365                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1366                          ("tx ring initialization failed"));
1367                 return err;
1368         }
1369
1370         return 1;
1371 }
1372
1373 static int rtl_pci_start(struct ieee80211_hw *hw)
1374 {
1375         struct rtl_priv *rtlpriv = rtl_priv(hw);
1376         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1377         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1378         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1379
1380         int err;
1381
1382         rtl_pci_reset_trx_ring(hw);
1383
1384         rtlpci->driver_is_goingto_unload = false;
1385         err = rtlpriv->cfg->ops->hw_init(hw);
1386         if (err) {
1387                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1388                          ("Failed to config hardware!\n"));
1389                 return err;
1390         }
1391
1392         rtlpriv->cfg->ops->enable_interrupt(hw);
1393         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1394
1395         rtl_init_rx_config(hw);
1396
1397         /*should after adapter start and interrupt enable. */
1398         set_hal_start(rtlhal);
1399
1400         RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1401
1402         rtlpci->up_first_time = false;
1403
1404         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
1405         return 0;
1406 }
1407
1408 static void rtl_pci_stop(struct ieee80211_hw *hw)
1409 {
1410         struct rtl_priv *rtlpriv = rtl_priv(hw);
1411         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1412         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1413         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1414         unsigned long flags;
1415         u8 RFInProgressTimeOut = 0;
1416
1417         /*
1418          *should before disable interrrupt&adapter
1419          *and will do it immediately.
1420          */
1421         set_hal_stop(rtlhal);
1422
1423         rtlpriv->cfg->ops->disable_interrupt(hw);
1424
1425         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1426         while (ppsc->rfchange_inprogress) {
1427                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1428                 if (RFInProgressTimeOut > 100) {
1429                         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1430                         break;
1431                 }
1432                 mdelay(1);
1433                 RFInProgressTimeOut++;
1434                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1435         }
1436         ppsc->rfchange_inprogress = true;
1437         spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1438
1439         rtlpci->driver_is_goingto_unload = true;
1440         rtlpriv->cfg->ops->hw_disable(hw);
1441         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1442
1443         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1444         ppsc->rfchange_inprogress = false;
1445         spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1446
1447         rtl_pci_enable_aspm(hw);
1448 }
1449
1450 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1451                 struct ieee80211_hw *hw)
1452 {
1453         struct rtl_priv *rtlpriv = rtl_priv(hw);
1454         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1455         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1456         struct pci_dev *bridge_pdev = pdev->bus->self;
1457         u16 venderid;
1458         u16 deviceid;
1459         u16 irqline;
1460         u8 tmp;
1461
1462         venderid = pdev->vendor;
1463         deviceid = pdev->device;
1464         pci_read_config_word(pdev, 0x3C, &irqline);
1465
1466         if (deviceid == RTL_PCI_8192_DID ||
1467             deviceid == RTL_PCI_0044_DID ||
1468             deviceid == RTL_PCI_0047_DID ||
1469             deviceid == RTL_PCI_8192SE_DID ||
1470             deviceid == RTL_PCI_8174_DID ||
1471             deviceid == RTL_PCI_8173_DID ||
1472             deviceid == RTL_PCI_8172_DID ||
1473             deviceid == RTL_PCI_8171_DID) {
1474                 switch (pdev->revision) {
1475                 case RTL_PCI_REVISION_ID_8192PCIE:
1476                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1477                                  ("8192 PCI-E is found - "
1478                                   "vid/did=%x/%x\n", venderid, deviceid));
1479                         rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1480                         break;
1481                 case RTL_PCI_REVISION_ID_8192SE:
1482                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1483                                  ("8192SE is found - "
1484                                   "vid/did=%x/%x\n", venderid, deviceid));
1485                         rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1486                         break;
1487                 default:
1488                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1489                                  ("Err: Unknown device - "
1490                                   "vid/did=%x/%x\n", venderid, deviceid));
1491                         rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1492                         break;
1493
1494                 }
1495         } else if (deviceid == RTL_PCI_8192CET_DID ||
1496                    deviceid == RTL_PCI_8192CE_DID ||
1497                    deviceid == RTL_PCI_8191CE_DID ||
1498                    deviceid == RTL_PCI_8188CE_DID) {
1499                 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1500                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1501                          ("8192C PCI-E is found - "
1502                           "vid/did=%x/%x\n", venderid, deviceid));
1503         } else {
1504                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1505                          ("Err: Unknown device -"
1506                           " vid/did=%x/%x\n", venderid, deviceid));
1507
1508                 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1509         }
1510
1511         /*find bus info */
1512         pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1513         pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1514         pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1515
1516         /*find bridge info */
1517         pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1518         for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1519                 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1520                         pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1521                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1522                                  ("Pci Bridge Vendor is found index: %d\n",
1523                                   tmp));
1524                         break;
1525                 }
1526         }
1527
1528         if (pcipriv->ndis_adapter.pcibridge_vendor !=
1529                 PCI_BRIDGE_VENDOR_UNKNOWN) {
1530                 pcipriv->ndis_adapter.pcibridge_busnum =
1531                     bridge_pdev->bus->number;
1532                 pcipriv->ndis_adapter.pcibridge_devnum =
1533                     PCI_SLOT(bridge_pdev->devfn);
1534                 pcipriv->ndis_adapter.pcibridge_funcnum =
1535                     PCI_FUNC(bridge_pdev->devfn);
1536                 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1537                     pci_pcie_cap(bridge_pdev);
1538                 pcipriv->ndis_adapter.pcicfg_addrport =
1539                     (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
1540                     (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
1541                     (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
1542                 pcipriv->ndis_adapter.num4bytes =
1543                     (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1544
1545                 rtl_pci_get_linkcontrol_field(hw);
1546
1547                 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1548                     PCI_BRIDGE_VENDOR_AMD) {
1549                         pcipriv->ndis_adapter.amd_l1_patch =
1550                             rtl_pci_get_amd_l1_patch(hw);
1551                 }
1552         }
1553
1554         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1555                  ("pcidev busnumber:devnumber:funcnumber:"
1556                   "vendor:link_ctl %d:%d:%d:%x:%x\n",
1557                   pcipriv->ndis_adapter.busnumber,
1558                   pcipriv->ndis_adapter.devnumber,
1559                   pcipriv->ndis_adapter.funcnumber,
1560                   pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
1561
1562         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1563                  ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
1564                   "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1565                   pcipriv->ndis_adapter.pcibridge_busnum,
1566                   pcipriv->ndis_adapter.pcibridge_devnum,
1567                   pcipriv->ndis_adapter.pcibridge_funcnum,
1568                   pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1569                   pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1570                   pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1571                   pcipriv->ndis_adapter.amd_l1_patch));
1572
1573         rtl_pci_parse_configuration(pdev, hw);
1574
1575         return true;
1576 }
1577
1578 int __devinit rtl_pci_probe(struct pci_dev *pdev,
1579                             const struct pci_device_id *id)
1580 {
1581         struct ieee80211_hw *hw = NULL;
1582
1583         struct rtl_priv *rtlpriv = NULL;
1584         struct rtl_pci_priv *pcipriv = NULL;
1585         struct rtl_pci *rtlpci;
1586         unsigned long pmem_start, pmem_len, pmem_flags;
1587         int err;
1588
1589         err = pci_enable_device(pdev);
1590         if (err) {
1591                 RT_ASSERT(false,
1592                           ("%s : Cannot enable new PCI device\n",
1593                            pci_name(pdev)));
1594                 return err;
1595         }
1596
1597         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1598                 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1599                         RT_ASSERT(false, ("Unable to obtain 32bit DMA "
1600                                           "for consistent allocations\n"));
1601                         pci_disable_device(pdev);
1602                         return -ENOMEM;
1603                 }
1604         }
1605
1606         pci_set_master(pdev);
1607
1608         hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1609                                 sizeof(struct rtl_priv), &rtl_ops);
1610         if (!hw) {
1611                 RT_ASSERT(false,
1612                           ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
1613                 err = -ENOMEM;
1614                 goto fail1;
1615         }
1616
1617         SET_IEEE80211_DEV(hw, &pdev->dev);
1618         pci_set_drvdata(pdev, hw);
1619
1620         rtlpriv = hw->priv;
1621         pcipriv = (void *)rtlpriv->priv;
1622         pcipriv->dev.pdev = pdev;
1623
1624         /*
1625          *init dbgp flags before all
1626          *other functions, because we will
1627          *use it in other funtions like
1628          *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1629          *you can not use these macro
1630          *before this
1631          */
1632         rtl_dbgp_flag_init(hw);
1633
1634         /* MEM map */
1635         err = pci_request_regions(pdev, KBUILD_MODNAME);
1636         if (err) {
1637                 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
1638                 return err;
1639         }
1640
1641         pmem_start = pci_resource_start(pdev, 2);
1642         pmem_len = pci_resource_len(pdev, 2);
1643         pmem_flags = pci_resource_flags(pdev, 2);
1644
1645         /*shared mem start */
1646         rtlpriv->io.pci_mem_start =
1647                         (unsigned long)pci_iomap(pdev, 2, pmem_len);
1648         if (rtlpriv->io.pci_mem_start == 0) {
1649                 RT_ASSERT(false, ("Can't map PCI mem\n"));
1650                 goto fail2;
1651         }
1652
1653         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1654                  ("mem mapped space: start: 0x%08lx len:%08lx "
1655                   "flags:%08lx, after map:0x%08lx\n",
1656                   pmem_start, pmem_len, pmem_flags,
1657                   rtlpriv->io.pci_mem_start));
1658
1659         /* Disable Clk Request */
1660         pci_write_config_byte(pdev, 0x81, 0);
1661         /* leave D3 mode */
1662         pci_write_config_byte(pdev, 0x44, 0);
1663         pci_write_config_byte(pdev, 0x04, 0x06);
1664         pci_write_config_byte(pdev, 0x04, 0x07);
1665
1666         /* init cfg & intf_ops */
1667         rtlpriv->rtlhal.interface = INTF_PCI;
1668         rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1669         rtlpriv->intf_ops = &rtl_pci_ops;
1670
1671         /* find adapter */
1672         _rtl_pci_find_adapter(pdev, hw);
1673
1674         /* Init IO handler */
1675         _rtl_pci_io_handler_init(&pdev->dev, hw);
1676
1677         /*like read eeprom and so on */
1678         rtlpriv->cfg->ops->read_eeprom_info(hw);
1679
1680         if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1681                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1682                          ("Can't init_sw_vars.\n"));
1683                 goto fail3;
1684         }
1685
1686         rtlpriv->cfg->ops->init_sw_leds(hw);
1687
1688         /*aspm */
1689         rtl_pci_init_aspm(hw);
1690
1691         /* Init mac80211 sw */
1692         err = rtl_init_core(hw);
1693         if (err) {
1694                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1695                          ("Can't allocate sw for mac80211.\n"));
1696                 goto fail3;
1697         }
1698
1699         /* Init PCI sw */
1700         err = !rtl_pci_init(hw, pdev);
1701         if (err) {
1702                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1703                          ("Failed to init PCI.\n"));
1704                 goto fail3;
1705         }
1706
1707         err = ieee80211_register_hw(hw);
1708         if (err) {
1709                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1710                          ("Can't register mac80211 hw.\n"));
1711                 goto fail3;
1712         } else {
1713                 rtlpriv->mac80211.mac80211_registered = 1;
1714         }
1715
1716         err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1717         if (err) {
1718                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1719                          ("failed to create sysfs device attributes\n"));
1720                 goto fail3;
1721         }
1722
1723         /*init rfkill */
1724         rtl_init_rfkill(hw);
1725
1726         rtlpci = rtl_pcidev(pcipriv);
1727         err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1728                           IRQF_SHARED, KBUILD_MODNAME, hw);
1729         if (err) {
1730                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1731                          ("%s: failed to register IRQ handler\n",
1732                           wiphy_name(hw->wiphy)));
1733                 goto fail3;
1734         } else {
1735                 rtlpci->irq_alloc = 1;
1736         }
1737
1738         set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1739         return 0;
1740
1741 fail3:
1742         pci_set_drvdata(pdev, NULL);
1743         rtl_deinit_core(hw);
1744         _rtl_pci_io_handler_release(hw);
1745         ieee80211_free_hw(hw);
1746
1747         if (rtlpriv->io.pci_mem_start != 0)
1748                 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1749
1750 fail2:
1751         pci_release_regions(pdev);
1752
1753 fail1:
1754
1755         pci_disable_device(pdev);
1756
1757         return -ENODEV;
1758
1759 }
1760 EXPORT_SYMBOL(rtl_pci_probe);
1761
1762 void rtl_pci_disconnect(struct pci_dev *pdev)
1763 {
1764         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1765         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1766         struct rtl_priv *rtlpriv = rtl_priv(hw);
1767         struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1768         struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1769
1770         clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1771
1772         sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1773
1774         /*ieee80211_unregister_hw will call ops_stop */
1775         if (rtlmac->mac80211_registered == 1) {
1776                 ieee80211_unregister_hw(hw);
1777                 rtlmac->mac80211_registered = 0;
1778         } else {
1779                 rtl_deinit_deferred_work(hw);
1780                 rtlpriv->intf_ops->adapter_stop(hw);
1781         }
1782
1783         /*deinit rfkill */
1784         rtl_deinit_rfkill(hw);
1785
1786         rtl_pci_deinit(hw);
1787         rtl_deinit_core(hw);
1788         if (rtlpriv->cfg->ops->deinit_sw_leds)
1789                 rtlpriv->cfg->ops->deinit_sw_leds(hw);
1790         _rtl_pci_io_handler_release(hw);
1791         rtlpriv->cfg->ops->deinit_sw_vars(hw);
1792
1793         if (rtlpci->irq_alloc) {
1794                 free_irq(rtlpci->pdev->irq, hw);
1795                 rtlpci->irq_alloc = 0;
1796         }
1797
1798         if (rtlpriv->io.pci_mem_start != 0) {
1799                 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1800                 pci_release_regions(pdev);
1801         }
1802
1803         pci_disable_device(pdev);
1804         pci_set_drvdata(pdev, NULL);
1805
1806         ieee80211_free_hw(hw);
1807 }
1808 EXPORT_SYMBOL(rtl_pci_disconnect);
1809
1810 /***************************************
1811 kernel pci power state define:
1812 PCI_D0         ((pci_power_t __force) 0)
1813 PCI_D1         ((pci_power_t __force) 1)
1814 PCI_D2         ((pci_power_t __force) 2)
1815 PCI_D3hot      ((pci_power_t __force) 3)
1816 PCI_D3cold     ((pci_power_t __force) 4)
1817 PCI_UNKNOWN    ((pci_power_t __force) 5)
1818
1819 This function is called when system
1820 goes into suspend state mac80211 will
1821 call rtl_mac_stop() from the mac80211
1822 suspend function first, So there is
1823 no need to call hw_disable here.
1824 ****************************************/
1825 int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1826 {
1827         pci_save_state(pdev);
1828         pci_disable_device(pdev);
1829         pci_set_power_state(pdev, PCI_D3hot);
1830
1831         return 0;
1832 }
1833 EXPORT_SYMBOL(rtl_pci_suspend);
1834
1835 int rtl_pci_resume(struct pci_dev *pdev)
1836 {
1837         int ret;
1838
1839         pci_set_power_state(pdev, PCI_D0);
1840         ret = pci_enable_device(pdev);
1841         if (ret) {
1842                 RT_ASSERT(false, ("ERR: <======\n"));
1843                 return ret;
1844         }
1845
1846         pci_restore_state(pdev);
1847
1848         return 0;
1849 }
1850 EXPORT_SYMBOL(rtl_pci_resume);
1851
1852 struct rtl_intf_ops rtl_pci_ops = {
1853         .adapter_start = rtl_pci_start,
1854         .adapter_stop = rtl_pci_stop,
1855         .adapter_tx = rtl_pci_tx,
1856         .reset_trx_ring = rtl_pci_reset_trx_ring,
1857
1858         .disable_aspm = rtl_pci_disable_aspm,
1859         .enable_aspm = rtl_pci_enable_aspm,
1860 };