drivers/net/wireless/rt2x00/rt73usb.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt73usb
  23         Abstract: rt73usb device specific routines.
  24         Supported chipsets: rt2571W & rt2671.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/slab.h>
  34 #include <linux/usb.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00usb.h"
  38 #include "rt73usb.h"
  39
  40 /*
  41  * Allow hardware encryption to be disabled.
  42  */
  43 static int modparam_nohwcrypt = 0;
  44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  46
  47 /*
  48  * Register access.
  49  * All access to the CSR registers will go through the methods
  50  * rt2x00usb_register_read and rt2x00usb_register_write.
  51  * BBP and RF register require indirect register access,
  52  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  53  * These indirect registers work with busy bits,
  54  * and we will try maximal REGISTER_BUSY_COUNT times to access
  55  * the register while taking a REGISTER_BUSY_DELAY us delay
  56  * between each attampt. When the busy bit is still set at that time,
  57  * the access attempt is considered to have failed,
  58  * and we will print an error.
  59  * The _lock versions must be used if you already hold the csr_mutex
  60  */
  61 #define WAIT_FOR_BBP(__dev, __reg) \
  62         rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
  63 #define WAIT_FOR_RF(__dev, __reg) \
  64         rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
  65
  66 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
  67                               const unsigned int word, const u8 value)
  68 {
  69         u32 reg;
  70
  71         mutex_lock(&rt2x00dev->csr_mutex);
  72
  73         /*
  74          * Wait until the BBP becomes available, afterwards we
  75          * can safely write the new data into the register.
  76          */
  77         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  78                 reg = 0;
  79                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  80                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  81                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  82                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  83
  84                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
  85         }
  86
  87         mutex_unlock(&rt2x00dev->csr_mutex);
  88 }
  89
  90 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
  91                              const unsigned int word, u8 *value)
  92 {
  93         u32 reg;
  94
  95         mutex_lock(&rt2x00dev->csr_mutex);
  96
  97         /*
  98          * Wait until the BBP becomes available, afterwards we
  99          * can safely write the read request into the register.
 100          * After the data has been written, we wait until hardware
 101          * returns the correct value, if at any time the register
 102          * doesn't become available in time, reg will be 0xffffffff
 103          * which means we return 0xff to the caller.
 104          */
 105         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 106                 reg = 0;
 107                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 108                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 109                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 110
 111                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
 112
 113                 WAIT_FOR_BBP(rt2x00dev, &reg);
 114         }
 115
 116         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 117
 118         mutex_unlock(&rt2x00dev->csr_mutex);
 119 }
 120
 121 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
 122                              const unsigned int word, const u32 value)
 123 {
 124         u32 reg;
 125
 126         mutex_lock(&rt2x00dev->csr_mutex);
 127
 128         /*
 129          * Wait until the RF becomes available, afterwards we
 130          * can safely write the new data into the register.
 131          */
 132         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 133                 reg = 0;
 134                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 135                 /*
 136                  * RF5225 and RF2527 contain 21 bits per RF register value,
 137                  * all others contain 20 bits.
 138                  */
 139                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
 140                                    20 + (rt2x00_rf(rt2x00dev, RF5225) ||
 141                                          rt2x00_rf(rt2x00dev, RF2527)));
 142                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 143                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 144
 145                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
 146                 rt2x00_rf_write(rt2x00dev, word, value);
 147         }
 148
 149         mutex_unlock(&rt2x00dev->csr_mutex);
 150 }
 151
 152 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 153 static const struct rt2x00debug rt73usb_rt2x00debug = {
 154         .owner  = THIS_MODULE,
 155         .csr    = {
 156                 .read           = rt2x00usb_register_read,
 157                 .write          = rt2x00usb_register_write,
 158                 .flags          = RT2X00DEBUGFS_OFFSET,
 159                 .word_base      = CSR_REG_BASE,
 160                 .word_size      = sizeof(u32),
 161                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 162         },
 163         .eeprom = {
 164                 .read           = rt2x00_eeprom_read,
 165                 .write          = rt2x00_eeprom_write,
 166                 .word_base      = EEPROM_BASE,
 167                 .word_size      = sizeof(u16),
 168                 .word_count     = EEPROM_SIZE / sizeof(u16),
 169         },
 170         .bbp    = {
 171                 .read           = rt73usb_bbp_read,
 172                 .write          = rt73usb_bbp_write,
 173                 .word_base      = BBP_BASE,
 174                 .word_size      = sizeof(u8),
 175                 .word_count     = BBP_SIZE / sizeof(u8),
 176         },
 177         .rf     = {
 178                 .read           = rt2x00_rf_read,
 179                 .write          = rt73usb_rf_write,
 180                 .word_base      = RF_BASE,
 181                 .word_size      = sizeof(u32),
 182                 .word_count     = RF_SIZE / sizeof(u32),
 183         },
 184 };
 185 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 186
 187 static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 188 {
 189         u32 reg;
 190
 191         rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
 192         return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
 193 }
 194
 195 #ifdef CONFIG_RT2X00_LIB_LEDS
 196 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
 197                                    enum led_brightness brightness)
 198 {
 199         struct rt2x00_led *led =
 200            container_of(led_cdev, struct rt2x00_led, led_dev);
 201         unsigned int enabled = brightness != LED_OFF;
 202         unsigned int a_mode =
 203             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 204         unsigned int bg_mode =
 205             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 206
 207         if (led->type == LED_TYPE_RADIO) {
 208                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 209                                    MCU_LEDCS_RADIO_STATUS, enabled);
 210
 211                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 212                                             0, led->rt2x00dev->led_mcu_reg,
 213                                             REGISTER_TIMEOUT);
 214         } else if (led->type == LED_TYPE_ASSOC) {
 215                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 216                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 217                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 218                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 219
 220                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 221                                             0, led->rt2x00dev->led_mcu_reg,
 222                                             REGISTER_TIMEOUT);
 223         } else if (led->type == LED_TYPE_QUALITY) {
 224                 /*
 225                  * The brightness is divided into 6 levels (0 - 5),
 226                  * this means we need to convert the brightness
 227                  * argument into the matching level within that range.
 228                  */
 229                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
 230                                             brightness / (LED_FULL / 6),
 231                                             led->rt2x00dev->led_mcu_reg,
 232                                             REGISTER_TIMEOUT);
 233         }
 234 }
 235
 236 static int rt73usb_blink_set(struct led_classdev *led_cdev,
 237                              unsigned long *delay_on,
 238                              unsigned long *delay_off)
 239 {
 240         struct rt2x00_led *led =
 241             container_of(led_cdev, struct rt2x00_led, led_dev);
 242         u32 reg;
 243
 244         rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 245         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 246         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 247         rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
 248
 249         return 0;
 250 }
 251
 252 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
 253                              struct rt2x00_led *led,
 254                              enum led_type type)
 255 {
 256         led->rt2x00dev = rt2x00dev;
 257         led->type = type;
 258         led->led_dev.brightness_set = rt73usb_brightness_set;
 259         led->led_dev.blink_set = rt73usb_blink_set;
 260         led->flags = LED_INITIALIZED;
 261 }
 262 #endif /* CONFIG_RT2X00_LIB_LEDS */
 263
 264 /*
 265  * Configuration handlers.
 266  */
 267 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 268                                      struct rt2x00lib_crypto *crypto,
 269                                      struct ieee80211_key_conf *key)
 270 {
 271         struct hw_key_entry key_entry;
 272         struct rt2x00_field32 field;
 273         int timeout;
 274         u32 mask;
 275         u32 reg;
 276
 277         if (crypto->cmd == SET_KEY) {
 278                 /*
 279                  * rt2x00lib can't determine the correct free
 280                  * key_idx for shared keys. We have 1 register
 281                  * with key valid bits. The goal is simple, read
 282                  * the register, if that is full we have no slots
 283                  * left.
 284                  * Note that each BSS is allowed to have up to 4
 285                  * shared keys, so put a mask over the allowed
 286                  * entries.
 287                  */
 288                 mask = (0xf << crypto->bssidx);
 289
 290                 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
 291                 reg &= mask;
 292
 293                 if (reg && reg == mask)
 294                         return -ENOSPC;
 295
 296                 key->hw_key_idx += reg ? ffz(reg) : 0;
 297
 298                 /*
 299                  * Upload key to hardware
 300                  */
 301                 memcpy(key_entry.key, crypto->key,
 302                        sizeof(key_entry.key));
 303                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 304                        sizeof(key_entry.tx_mic));
 305                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 306                        sizeof(key_entry.rx_mic));
 307
 308                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 309                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 310                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 311                                                     USB_VENDOR_REQUEST_OUT, reg,
 312                                                     &key_entry,
 313                                                     sizeof(key_entry),
 314                                                     timeout);
 315
 316                 /*
 317                  * The cipher types are stored over 2 registers.
 318                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 319                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 320                  * Using the correct defines correctly will cause overhead,
 321                  * so just calculate the correct offset.
 322                  */
 323                 if (key->hw_key_idx < 8) {
 324                         field.bit_offset = (3 * key->hw_key_idx);
 325                         field.bit_mask = 0x7 << field.bit_offset;
 326
 327                         rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
 328                         rt2x00_set_field32(&reg, field, crypto->cipher);
 329                         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
 330                 } else {
 331                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 332                         field.bit_mask = 0x7 << field.bit_offset;
 333
 334                         rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
 335                         rt2x00_set_field32(&reg, field, crypto->cipher);
 336                         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
 337                 }
 338
 339                 /*
 340                  * The driver does not support the IV/EIV generation
 341                  * in hardware. However it doesn't support the IV/EIV
 342                  * inside the ieee80211 frame either, but requires it
 343                  * to be provided separately for the descriptor.
 344                  * rt2x00lib will cut the IV/EIV data out of all frames
 345                  * given to us by mac80211, but we must tell mac80211
 346                  * to generate the IV/EIV data.
 347                  */
 348                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 349         }
 350
 351         /*
 352          * SEC_CSR0 contains only single-bit fields to indicate
 353          * a particular key is valid. Because using the FIELD32()
 354          * defines directly will cause a lot of overhead we use
 355          * a calculation to determine the correct bit directly.
 356          */
 357         mask = 1 << key->hw_key_idx;
 358
 359         rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
 360         if (crypto->cmd == SET_KEY)
 361                 reg |= mask;
 362         else if (crypto->cmd == DISABLE_KEY)
 363                 reg &= ~mask;
 364         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
 365
 366         return 0;
 367 }
 368
 369 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 370                                        struct rt2x00lib_crypto *crypto,
 371                                        struct ieee80211_key_conf *key)
 372 {
 373         struct hw_pairwise_ta_entry addr_entry;
 374         struct hw_key_entry key_entry;
 375         int timeout;
 376         u32 mask;
 377         u32 reg;
 378
 379         if (crypto->cmd == SET_KEY) {
 380                 /*
 381                  * rt2x00lib can't determine the correct free
 382                  * key_idx for pairwise keys. We have 2 registers
 383                  * with key valid bits. The goal is simple, read
 384                  * the first register, if that is full move to
 385                  * the next register.
 386                  * When both registers are full, we drop the key,
 387                  * otherwise we use the first invalid entry.
 388                  */
 389                 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
 390                 if (reg && reg == ~0) {
 391                         key->hw_key_idx = 32;
 392                         rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
 393                         if (reg && reg == ~0)
 394                                 return -ENOSPC;
 395                 }
 396
 397                 key->hw_key_idx += reg ? ffz(reg) : 0;
 398
 399                 /*
 400                  * Upload key to hardware
 401                  */
 402                 memcpy(key_entry.key, crypto->key,
 403                        sizeof(key_entry.key));
 404                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 405                        sizeof(key_entry.tx_mic));
 406                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 407                        sizeof(key_entry.rx_mic));
 408
 409                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 410                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 411                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 412                                                     USB_VENDOR_REQUEST_OUT, reg,
 413                                                     &key_entry,
 414                                                     sizeof(key_entry),
 415                                                     timeout);
 416
 417                 /*
 418                  * Send the address and cipher type to the hardware register.
 419                  * This data fits within the CSR cache size, so we can use
 420                  * rt2x00usb_register_multiwrite() directly.
 421                  */
 422                 memset(&addr_entry, 0, sizeof(addr_entry));
 423                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 424                 addr_entry.cipher = crypto->cipher;
 425
 426                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 427                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
 428                                             &addr_entry, sizeof(addr_entry));
 429
 430                 /*
 431                  * Enable pairwise lookup table for given BSS idx,
 432                  * without this received frames will not be decrypted
 433                  * by the hardware.
 434                  */
 435                 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
 436                 reg |= (1 << crypto->bssidx);
 437                 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
 438
 439                 /*
 440                  * The driver does not support the IV/EIV generation
 441                  * in hardware. However it doesn't support the IV/EIV
 442                  * inside the ieee80211 frame either, but requires it
 443                  * to be provided separately for the descriptor.
 444                  * rt2x00lib will cut the IV/EIV data out of all frames
 445                  * given to us by mac80211, but we must tell mac80211
 446                  * to generate the IV/EIV data.
 447                  */
 448                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 449         }
 450
 451         /*
 452          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 453          * a particular key is valid. Because using the FIELD32()
 454          * defines directly will cause a lot of overhead we use
 455          * a calculation to determine the correct bit directly.
 456          */
 457         if (key->hw_key_idx < 32) {
 458                 mask = 1 << key->hw_key_idx;
 459
 460                 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
 461                 if (crypto->cmd == SET_KEY)
 462                         reg |= mask;
 463                 else if (crypto->cmd == DISABLE_KEY)
 464                         reg &= ~mask;
 465                 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
 466         } else {
 467                 mask = 1 << (key->hw_key_idx - 32);
 468
 469                 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
 470                 if (crypto->cmd == SET_KEY)
 471                         reg |= mask;
 472                 else if (crypto->cmd == DISABLE_KEY)
 473                         reg &= ~mask;
 474                 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
 475         }
 476
 477         return 0;
 478 }
 479
 480 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
 481                                   const unsigned int filter_flags)
 482 {
 483         u32 reg;
 484
 485         /*
 486          * Start configuration steps.
 487          * Note that the version error will always be dropped
 488          * and broadcast frames will always be accepted since
 489          * there is no filter for it at this time.
 490          */
 491         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 492         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 493                            !(filter_flags & FIF_FCSFAIL));
 494         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 495                            !(filter_flags & FIF_PLCPFAIL));
 496         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 497                            !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
 498         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 499                            !(filter_flags & FIF_PROMISC_IN_BSS));
 500         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 501                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 502                            !rt2x00dev->intf_ap_count);
 503         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 504         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 505                            !(filter_flags & FIF_ALLMULTI));
 506         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 507         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 508                            !(filter_flags & FIF_CONTROL));
 509         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 510 }
 511
 512 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
 513                                 struct rt2x00_intf *intf,
 514                                 struct rt2x00intf_conf *conf,
 515                                 const unsigned int flags)
 516 {
 517         unsigned int beacon_base;
 518         u32 reg;
 519
 520         if (flags & CONFIG_UPDATE_TYPE) {
 521                 /*
 522                  * Clear current synchronisation setup.
 523                  * For the Beacon base registers we only need to clear
 524                  * the first byte since that byte contains the VALID and OWNER
 525                  * bits which (when set to 0) will invalidate the entire beacon.
 526                  */
 527                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 528                 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
 529
 530                 /*
 531                  * Enable synchronisation.
 532                  */
 533                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 534                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 535                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 536                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 537                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 538         }
 539
 540         if (flags & CONFIG_UPDATE_MAC) {
 541                 reg = le32_to_cpu(conf->mac[1]);
 542                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 543                 conf->mac[1] = cpu_to_le32(reg);
 544
 545                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
 546                                             conf->mac, sizeof(conf->mac));
 547         }
 548
 549         if (flags & CONFIG_UPDATE_BSSID) {
 550                 reg = le32_to_cpu(conf->bssid[1]);
 551                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 552                 conf->bssid[1] = cpu_to_le32(reg);
 553
 554                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
 555                                             conf->bssid, sizeof(conf->bssid));
 556         }
 557 }
 558
 559 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
 560                                struct rt2x00lib_erp *erp)
 561 {
 562         u32 reg;
 563
 564         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
 565         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
 566         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 567         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
 568
 569         rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 570         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 571         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 572                            !!erp->short_preamble);
 573         rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 574
 575         rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
 576
 577         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
 578         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 579                            erp->beacon_int * 16);
 580         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
 581
 582         rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
 583         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
 584         rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
 585
 586         rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
 587         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
 588         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 589         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
 590         rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
 591 }
 592
 593 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 594                                       struct antenna_setup *ant)
 595 {
 596         u8 r3;
 597         u8 r4;
 598         u8 r77;
 599         u8 temp;
 600
 601         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 602         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 603         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 604
 605         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 606
 607         /*
 608          * Configure the RX antenna.
 609          */
 610         switch (ant->rx) {
 611         case ANTENNA_HW_DIVERSITY:
 612                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 613                 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
 614                        && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
 615                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
 616                 break;
 617         case ANTENNA_A:
 618                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 619                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 620                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 621                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 622                 else
 623                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 624                 break;
 625         case ANTENNA_B:
 626         default:
 627                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 628                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 629                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 630                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 631                 else
 632                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 633                 break;
 634         }
 635
 636         rt73usb_bbp_write(rt2x00dev, 77, r77);
 637         rt73usb_bbp_write(rt2x00dev, 3, r3);
 638         rt73usb_bbp_write(rt2x00dev, 4, r4);
 639 }
 640
 641 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 642                                       struct antenna_setup *ant)
 643 {
 644         u8 r3;
 645         u8 r4;
 646         u8 r77;
 647
 648         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 649         rt73usb_bbp_read(rt2x00dev, 4, &r4);
 650         rt73usb_bbp_read(rt2x00dev, 77, &r77);
 651
 652         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
 653         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 654                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 655
 656         /*
 657          * Configure the RX antenna.
 658          */
 659         switch (ant->rx) {
 660         case ANTENNA_HW_DIVERSITY:
 661                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 662                 break;
 663         case ANTENNA_A:
 664                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 665                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 666                 break;
 667         case ANTENNA_B:
 668         default:
 669                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 670                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 671                 break;
 672         }
 673
 674         rt73usb_bbp_write(rt2x00dev, 77, r77);
 675         rt73usb_bbp_write(rt2x00dev, 3, r3);
 676         rt73usb_bbp_write(rt2x00dev, 4, r4);
 677 }
 678
 679 struct antenna_sel {
 680         u8 word;
 681         /*
 682          * value[0] -> non-LNA
 683          * value[1] -> LNA
 684          */
 685         u8 value[2];
 686 };
 687
 688 static const struct antenna_sel antenna_sel_a[] = {
 689         { 96,  { 0x58, 0x78 } },
 690         { 104, { 0x38, 0x48 } },
 691         { 75,  { 0xfe, 0x80 } },
 692         { 86,  { 0xfe, 0x80 } },
 693         { 88,  { 0xfe, 0x80 } },
 694         { 35,  { 0x60, 0x60 } },
 695         { 97,  { 0x58, 0x58 } },
 696         { 98,  { 0x58, 0x58 } },
 697 };
 698
 699 static const struct antenna_sel antenna_sel_bg[] = {
 700         { 96,  { 0x48, 0x68 } },
 701         { 104, { 0x2c, 0x3c } },
 702         { 75,  { 0xfe, 0x80 } },
 703         { 86,  { 0xfe, 0x80 } },
 704         { 88,  { 0xfe, 0x80 } },
 705         { 35,  { 0x50, 0x50 } },
 706         { 97,  { 0x48, 0x48 } },
 707         { 98,  { 0x48, 0x48 } },
 708 };
 709
 710 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
 711                                struct antenna_setup *ant)
 712 {
 713         const struct antenna_sel *sel;
 714         unsigned int lna;
 715         unsigned int i;
 716         u32 reg;
 717
 718         /*
 719          * We should never come here because rt2x00lib is supposed
 720          * to catch this and send us the correct antenna explicitely.
 721          */
 722         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 723                ant->tx == ANTENNA_SW_DIVERSITY);
 724
 725         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 726                 sel = antenna_sel_a;
 727                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 728         } else {
 729                 sel = antenna_sel_bg;
 730                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 731         }
 732
 733         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 734                 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 735
 736         rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
 737
 738         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 739                            (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
 740         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 741                            (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
 742
 743         rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
 744
 745         if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225))
 746                 rt73usb_config_antenna_5x(rt2x00dev, ant);
 747         else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527))
 748                 rt73usb_config_antenna_2x(rt2x00dev, ant);
 749 }
 750
 751 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 752                                     struct rt2x00lib_conf *libconf)
 753 {
 754         u16 eeprom;
 755         short lna_gain = 0;
 756
 757         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
 758                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
 759                         lna_gain += 14;
 760
 761                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 762                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 763         } else {
 764                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 765                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 766         }
 767
 768         rt2x00dev->lna_gain = lna_gain;
 769 }
 770
 771 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
 772                                    struct rf_channel *rf, const int txpower)
 773 {
 774         u8 r3;
 775         u8 r94;
 776         u8 smart;
 777
 778         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 779         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 780
 781         smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
 782
 783         rt73usb_bbp_read(rt2x00dev, 3, &r3);
 784         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 785         rt73usb_bbp_write(rt2x00dev, 3, r3);
 786
 787         r94 = 6;
 788         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 789                 r94 += txpower - MAX_TXPOWER;
 790         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 791                 r94 += txpower;
 792         rt73usb_bbp_write(rt2x00dev, 94, r94);
 793
 794         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 795         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 796         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 797         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 798
 799         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 800         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 801         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 802         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 803
 804         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
 805         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
 806         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 807         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
 808
 809         udelay(10);
 810 }
 811
 812 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 813                                    const int txpower)
 814 {
 815         struct rf_channel rf;
 816
 817         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 818         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 819         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 820         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 821
 822         rt73usb_config_channel(rt2x00dev, &rf, txpower);
 823 }
 824
 825 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 826                                        struct rt2x00lib_conf *libconf)
 827 {
 828         u32 reg;
 829
 830         rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
 831         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
 832                            libconf->conf->long_frame_max_tx_count);
 833         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
 834                            libconf->conf->short_frame_max_tx_count);
 835         rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
 836 }
 837
 838 static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
 839                                 struct rt2x00lib_conf *libconf)
 840 {
 841         enum dev_state state =
 842             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 843                 STATE_SLEEP : STATE_AWAKE;
 844         u32 reg;
 845
 846         if (state == STATE_SLEEP) {
 847                 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
 848                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
 849                                    rt2x00dev->beacon_int - 10);
 850                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
 851                                    libconf->conf->listen_interval - 1);
 852                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
 853
 854                 /* We must first disable autowake before it can be enabled */
 855                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 856                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
 857
 858                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
 859                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
 860
 861                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
 862                                             USB_MODE_SLEEP, REGISTER_TIMEOUT);
 863         } else {
 864                 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
 865                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
 866                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
 867                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 868                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
 869                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
 870
 871                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
 872                                             USB_MODE_WAKEUP, REGISTER_TIMEOUT);
 873         }
 874 }
 875
 876 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
 877                            struct rt2x00lib_conf *libconf,
 878                            const unsigned int flags)
 879 {
 880         /* Always recalculate LNA gain before changing configuration */
 881         rt73usb_config_lna_gain(rt2x00dev, libconf);
 882
 883         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 884                 rt73usb_config_channel(rt2x00dev, &libconf->rf,
 885                                        libconf->conf->power_level);
 886         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 887             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 888                 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
 889         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 890                 rt73usb_config_retry_limit(rt2x00dev, libconf);
 891         if (flags & IEEE80211_CONF_CHANGE_PS)
 892                 rt73usb_config_ps(rt2x00dev, libconf);
 893 }
 894
 895 /*
 896  * Link tuning
 897  */
 898 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
 899                                struct link_qual *qual)
 900 {
 901         u32 reg;
 902
 903         /*
 904          * Update FCS error count from register.
 905          */
 906         rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
 907         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
 908
 909         /*
 910          * Update False CCA count from register.
 911          */
 912         rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
 913         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
 914 }
 915
 916 static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
 917                                    struct link_qual *qual, u8 vgc_level)
 918 {
 919         if (qual->vgc_level != vgc_level) {
 920                 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
 921                 qual->vgc_level = vgc_level;
 922                 qual->vgc_level_reg = vgc_level;
 923         }
 924 }
 925
 926 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
 927                                 struct link_qual *qual)
 928 {
 929         rt73usb_set_vgc(rt2x00dev, qual, 0x20);
 930 }
 931
 932 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
 933                                struct link_qual *qual, const u32 count)
 934 {
 935         u8 up_bound;
 936         u8 low_bound;
 937
 938         /*
 939          * Determine r17 bounds.
 940          */
 941         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
 942                 low_bound = 0x28;
 943                 up_bound = 0x48;
 944
 945                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
 946                         low_bound += 0x10;
 947                         up_bound += 0x10;
 948                 }
 949         } else {
 950                 if (qual->rssi > -82) {
 951                         low_bound = 0x1c;
 952                         up_bound = 0x40;
 953                 } else if (qual->rssi > -84) {
 954                         low_bound = 0x1c;
 955                         up_bound = 0x20;
 956                 } else {
 957                         low_bound = 0x1c;
 958                         up_bound = 0x1c;
 959                 }
 960
 961                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 962                         low_bound += 0x14;
 963                         up_bound += 0x10;
 964                 }
 965         }
 966
 967         /*
 968          * If we are not associated, we should go straight to the
 969          * dynamic CCA tuning.
 970          */
 971         if (!rt2x00dev->intf_associated)
 972                 goto dynamic_cca_tune;
 973
 974         /*
 975          * Special big-R17 for very short distance
 976          */
 977         if (qual->rssi > -35) {
 978                 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
 979                 return;
 980         }
 981
 982         /*
 983          * Special big-R17 for short distance
 984          */
 985         if (qual->rssi >= -58) {
 986                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
 987                 return;
 988         }
 989
 990         /*
 991          * Special big-R17 for middle-short distance
 992          */
 993         if (qual->rssi >= -66) {
 994                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
 995                 return;
 996         }
 997
 998         /*
 999          * Special mid-R17 for middle distance
1000          */
1001         if (qual->rssi >= -74) {
1002                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1003                 return;
1004         }
1005
1006         /*
1007          * Special case: Change up_bound based on the rssi.
1008          * Lower up_bound when rssi is weaker then -74 dBm.
1009          */
1010         up_bound -= 2 * (-74 - qual->rssi);
1011         if (low_bound > up_bound)
1012                 up_bound = low_bound;
1013
1014         if (qual->vgc_level > up_bound) {
1015                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
1016                 return;
1017         }
1018
1019 dynamic_cca_tune:
1020
1021         /*
1022          * r17 does not yet exceed upper limit, continue and base
1023          * the r17 tuning on the false CCA count.
1024          */
1025         if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1026                 rt73usb_set_vgc(rt2x00dev, qual,
1027                                 min_t(u8, qual->vgc_level + 4, up_bound));
1028         else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1029                 rt73usb_set_vgc(rt2x00dev, qual,
1030                                 max_t(u8, qual->vgc_level - 4, low_bound));
1031 }
1032
1033 /*
1034  * Firmware functions
1035  */
1036 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1037 {
1038         return FIRMWARE_RT2571;
1039 }
1040
1041 static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1042                                   const u8 *data, const size_t len)
1043 {
1044         u16 fw_crc;
1045         u16 crc;
1046
1047         /*
1048          * Only support 2kb firmware files.
1049          */
1050         if (len != 2048)
1051                 return FW_BAD_LENGTH;
1052
1053         /*
1054          * The last 2 bytes in the firmware array are the crc checksum itself,
1055          * this means that we should never pass those 2 bytes to the crc
1056          * algorithm.
1057          */
1058         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1059
1060         /*
1061          * Use the crc itu-t algorithm.
1062          */
1063         crc = crc_itu_t(0, data, len - 2);
1064         crc = crc_itu_t_byte(crc, 0);
1065         crc = crc_itu_t_byte(crc, 0);
1066
1067         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1068 }
1069
1070 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1071                                  const u8 *data, const size_t len)
1072 {
1073         unsigned int i;
1074         int status;
1075         u32 reg;
1076
1077         /*
1078          * Wait for stable hardware.
1079          */
1080         for (i = 0; i < 100; i++) {
1081                 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1082                 if (reg)
1083                         break;
1084                 msleep(1);
1085         }
1086
1087         if (!reg) {
1088                 ERROR(rt2x00dev, "Unstable hardware.\n");
1089                 return -EBUSY;
1090         }
1091
1092         /*
1093          * Write firmware to device.
1094          */
1095         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1096                                             USB_VENDOR_REQUEST_OUT,
1097                                             FIRMWARE_IMAGE_BASE,
1098                                             data, len,
1099                                             REGISTER_TIMEOUT32(len));
1100
1101         /*
1102          * Send firmware request to device to load firmware,
1103          * we need to specify a long timeout time.
1104          */
1105         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1106                                              0, USB_MODE_FIRMWARE,
1107                                              REGISTER_TIMEOUT_FIRMWARE);
1108         if (status < 0) {
1109                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1110                 return status;
1111         }
1112
1113         return 0;
1114 }
1115
1116 /*
1117  * Initialization functions.
1118  */
1119 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1120 {
1121         u32 reg;
1122
1123         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1124         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1125         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1126         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1127         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1128
1129         rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1130         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1131         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1132         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1133         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1134         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1135         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1136         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1137         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1138         rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1139
1140         /*
1141          * CCK TXD BBP registers
1142          */
1143         rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1144         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1145         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1146         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1147         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1148         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1149         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1150         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1151         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1152         rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1153
1154         /*
1155          * OFDM TXD BBP registers
1156          */
1157         rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1158         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1159         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1160         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1161         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1162         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1163         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1164         rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1165
1166         rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1167         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1168         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1169         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1170         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1171         rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1172
1173         rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1174         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1175         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1176         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1177         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1178         rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1179
1180         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1181         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1182         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1183         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1184         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1185         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1186         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1187         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1188
1189         rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1190
1191         rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1192         rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1193         rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1194
1195         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1196
1197         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1198                 return -EBUSY;
1199
1200         rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1201
1202         /*
1203          * Invalidate all Shared Keys (SEC_CSR0),
1204          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1205          */
1206         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1207         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1208         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1209
1210         reg = 0x000023b0;
1211         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527))
1212                 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1213         rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1214
1215         rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1216         rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1217         rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1218
1219         rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1220         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1221         rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1222
1223         /*
1224          * Clear all beacons
1225          * For the Beacon base registers we only need to clear
1226          * the first byte since that byte contains the VALID and OWNER
1227          * bits which (when set to 0) will invalidate the entire beacon.
1228          */
1229         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1230         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1231         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1232         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1233
1234         /*
1235          * We must clear the error counters.
1236          * These registers are cleared on read,
1237          * so we may pass a useless variable to store the value.
1238          */
1239         rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1240         rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1241         rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
1242
1243         /*
1244          * Reset MAC and BBP registers.
1245          */
1246         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1247         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1248         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1249         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1250
1251         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1252         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1253         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1254         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1255
1256         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1257         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1258         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1259
1260         return 0;
1261 }
1262
1263 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1264 {
1265         unsigned int i;
1266         u8 value;
1267
1268         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1269                 rt73usb_bbp_read(rt2x00dev, 0, &value);
1270                 if ((value != 0xff) && (value != 0x00))
1271                         return 0;
1272                 udelay(REGISTER_BUSY_DELAY);
1273         }
1274
1275         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1276         return -EACCES;
1277 }
1278
1279 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1280 {
1281         unsigned int i;
1282         u16 eeprom;
1283         u8 reg_id;
1284         u8 value;
1285
1286         if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1287                 return -EACCES;
1288
1289         rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1290         rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1291         rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1292         rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1293         rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1294         rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1295         rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1296         rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1297         rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1298         rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1299         rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1300         rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1301         rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1302         rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1303         rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1304         rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1305         rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1306         rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1307         rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1308         rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1309         rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1310         rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1311         rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1312         rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1313         rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1314
1315         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1316                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1317
1318                 if (eeprom != 0xffff && eeprom != 0x0000) {
1319                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1320                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1321                         rt73usb_bbp_write(rt2x00dev, reg_id, value);
1322                 }
1323         }
1324
1325         return 0;
1326 }
1327
1328 /*
1329  * Device state switch handlers.
1330  */
1331 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1332                               enum dev_state state)
1333 {
1334         u32 reg;
1335
1336         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1337         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1338                            (state == STATE_RADIO_RX_OFF) ||
1339                            (state == STATE_RADIO_RX_OFF_LINK));
1340         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1341 }
1342
1343 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1344 {
1345         /*
1346          * Initialize all registers.
1347          */
1348         if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1349                      rt73usb_init_bbp(rt2x00dev)))
1350                 return -EIO;
1351
1352         return 0;
1353 }
1354
1355 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1356 {
1357         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1358
1359         /*
1360          * Disable synchronisation.
1361          */
1362         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1363
1364         rt2x00usb_disable_radio(rt2x00dev);
1365 }
1366
1367 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1368 {
1369         u32 reg;
1370         unsigned int i;
1371         char put_to_sleep;
1372
1373         put_to_sleep = (state != STATE_AWAKE);
1374
1375         rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1376         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1377         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1378         rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1379
1380         /*
1381          * Device is not guaranteed to be in the requested state yet.
1382          * We must wait until the register indicates that the
1383          * device has entered the correct state.
1384          */
1385         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1386                 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1387                 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1388                 if (state == !put_to_sleep)
1389                         return 0;
1390                 msleep(10);
1391         }
1392
1393         return -EBUSY;
1394 }
1395
1396 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1397                                     enum dev_state state)
1398 {
1399         int retval = 0;
1400
1401         switch (state) {
1402         case STATE_RADIO_ON:
1403                 retval = rt73usb_enable_radio(rt2x00dev);
1404                 break;
1405         case STATE_RADIO_OFF:
1406                 rt73usb_disable_radio(rt2x00dev);
1407                 break;
1408         case STATE_RADIO_RX_ON:
1409         case STATE_RADIO_RX_ON_LINK:
1410         case STATE_RADIO_RX_OFF:
1411         case STATE_RADIO_RX_OFF_LINK:
1412                 rt73usb_toggle_rx(rt2x00dev, state);
1413                 break;
1414         case STATE_RADIO_IRQ_ON:
1415         case STATE_RADIO_IRQ_OFF:
1416                 /* No support, but no error either */
1417                 break;
1418         case STATE_DEEP_SLEEP:
1419         case STATE_SLEEP:
1420         case STATE_STANDBY:
1421         case STATE_AWAKE:
1422                 retval = rt73usb_set_state(rt2x00dev, state);
1423                 break;
1424         default:
1425                 retval = -ENOTSUPP;
1426                 break;
1427         }
1428
1429         if (unlikely(retval))
1430                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1431                       state, retval);
1432
1433         return retval;
1434 }
1435
1436 /*
1437  * TX descriptor initialization
1438  */
1439 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1440                                   struct sk_buff *skb,
1441                                   struct txentry_desc *txdesc)
1442 {
1443         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1444         __le32 *txd = (__le32 *)(skb->data - TXD_DESC_SIZE);
1445         u32 word;
1446
1447         /*
1448          * Start writing the descriptor words.
1449          */
1450         rt2x00_desc_read(txd, 0, &word);
1451         rt2x00_set_field32(&word, TXD_W0_BURST,
1452                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1453         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1454         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1455                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1456         rt2x00_set_field32(&word, TXD_W0_ACK,
1457                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1458         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1459                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1460         rt2x00_set_field32(&word, TXD_W0_OFDM,
1461                            (txdesc->rate_mode == RATE_MODE_OFDM));
1462         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1463         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1464                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1465         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1466                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1467         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1468                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1469         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1470         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1471         rt2x00_set_field32(&word, TXD_W0_BURST2,
1472                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1473         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1474         rt2x00_desc_write(txd, 0, word);
1475
1476         rt2x00_desc_read(txd, 1, &word);
1477         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1478         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1479         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1480         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1481         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1482         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1483                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1484         rt2x00_desc_write(txd, 1, word);
1485
1486         rt2x00_desc_read(txd, 2, &word);
1487         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1488         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1489         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1490         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1491         rt2x00_desc_write(txd, 2, word);
1492
1493         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1494                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1495                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1496         }
1497
1498         rt2x00_desc_read(txd, 5, &word);
1499         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1500                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1501         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1502         rt2x00_desc_write(txd, 5, word);
1503
1504         /*
1505          * Register descriptor details in skb frame descriptor.
1506          */
1507         skbdesc->desc = txd;
1508         skbdesc->desc_len = TXD_DESC_SIZE;
1509 }
1510
1511 /*
1512  * TX data initialization
1513  */
1514 static void rt73usb_write_beacon(struct queue_entry *entry,
1515                                  struct txentry_desc *txdesc)
1516 {
1517         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1518         unsigned int beacon_base;
1519         u32 reg;
1520
1521         /*
1522          * Disable beaconing while we are reloading the beacon data,
1523          * otherwise we might be sending out invalid data.
1524          */
1525         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1526         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1527         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1528
1529         /*
1530          * Take the descriptor in front of the skb into account.
1531          */
1532         skb_push(entry->skb, TXD_DESC_SIZE);
1533
1534         /*
1535          * Write entire beacon with descriptor to register.
1536          */
1537         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1538         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1539                                             USB_VENDOR_REQUEST_OUT, beacon_base,
1540                                             entry->skb->data, entry->skb->len,
1541                                             REGISTER_TIMEOUT32(entry->skb->len));
1542
1543         /*
1544          * Enable beaconing again.
1545          *
1546          * For Wi-Fi faily generated beacons between participating stations.
1547          * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1548          */
1549         rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1550
1551         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1552         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1553         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1554         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1555
1556         /*
1557          * Clean up the beacon skb.
1558          */
1559         dev_kfree_skb(entry->skb);
1560         entry->skb = NULL;
1561 }
1562
1563 static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1564 {
1565         int length;
1566
1567         /*
1568          * The length _must_ be a multiple of 4,
1569          * but it must _not_ be a multiple of the USB packet size.
1570          */
1571         length = roundup(entry->skb->len, 4);
1572         length += (4 * !(length % entry->queue->usb_maxpacket));
1573
1574         return length;
1575 }
1576
1577 /*
1578  * RX control handlers
1579  */
1580 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1581 {
1582         u8 offset = rt2x00dev->lna_gain;
1583         u8 lna;
1584
1585         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1586         switch (lna) {
1587         case 3:
1588                 offset += 90;
1589                 break;
1590         case 2:
1591                 offset += 74;
1592                 break;
1593         case 1:
1594                 offset += 64;
1595                 break;
1596         default:
1597                 return 0;
1598         }
1599
1600         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1601                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1602                         if (lna == 3 || lna == 2)
1603                                 offset += 10;
1604                 } else {
1605                         if (lna == 3)
1606                                 offset += 6;
1607                         else if (lna == 2)
1608                                 offset += 8;
1609                 }
1610         }
1611
1612         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1613 }
1614
1615 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1616                                 struct rxdone_entry_desc *rxdesc)
1617 {
1618         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1619         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1620         __le32 *rxd = (__le32 *)entry->skb->data;
1621         u32 word0;
1622         u32 word1;
1623
1624         /*
1625          * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1626          * frame data in rt2x00usb.
1627          */
1628         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1629         rxd = (__le32 *)skbdesc->desc;
1630
1631         /*
1632          * It is now safe to read the descriptor on all architectures.
1633          */
1634         rt2x00_desc_read(rxd, 0, &word0);
1635         rt2x00_desc_read(rxd, 1, &word1);
1636
1637         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1638                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1639
1640         rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1641         rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1642
1643         if (rxdesc->cipher != CIPHER_NONE) {
1644                 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1645                 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
1646                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1647
1648                 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1649                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1650
1651                 /*
1652                  * Hardware has stripped IV/EIV data from 802.11 frame during
1653                  * decryption. It has provided the data separately but rt2x00lib
1654                  * should decide if it should be reinserted.
1655                  */
1656                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1657
1658                 /*
1659                  * FIXME: Legacy driver indicates that the frame does
1660                  * contain the Michael Mic. Unfortunately, in rt2x00
1661                  * the MIC seems to be missing completely...
1662                  */
1663                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1664
1665                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1666                         rxdesc->flags |= RX_FLAG_DECRYPTED;
1667                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1668                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1669         }
1670
1671         /*
1672          * Obtain the status about this packet.
1673          * When frame was received with an OFDM bitrate,
1674          * the signal is the PLCP value. If it was received with
1675          * a CCK bitrate the signal is the rate in 100kbit/s.
1676          */
1677         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1678         rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1679         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1680
1681         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1682                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1683         else
1684                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1685         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1686                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1687
1688         /*
1689          * Set skb pointers, and update frame information.
1690          */
1691         skb_pull(entry->skb, entry->queue->desc_size);
1692         skb_trim(entry->skb, rxdesc->size);
1693 }
1694
1695 /*
1696  * Device probe functions.
1697  */
1698 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1699 {
1700         u16 word;
1701         u8 *mac;
1702         s8 value;
1703
1704         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1705
1706         /*
1707          * Start validation of the data that has been read.
1708          */
1709         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1710         if (!is_valid_ether_addr(mac)) {
1711                 random_ether_addr(mac);
1712                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1713         }
1714
1715         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1716         if (word == 0xffff) {
1717                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1718                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1719                                    ANTENNA_B);
1720                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1721                                    ANTENNA_B);
1722                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1723                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1724                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1725                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1726                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1727                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1728         }
1729
1730         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1731         if (word == 0xffff) {
1732                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1733                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1734                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1735         }
1736
1737         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1738         if (word == 0xffff) {
1739                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1740                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1741                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1742                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1743                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1744                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1745                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1746                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1747                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1748                                    LED_MODE_DEFAULT);
1749                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1750                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1751         }
1752
1753         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1754         if (word == 0xffff) {
1755                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1756                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1757                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1758                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1759         }
1760
1761         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1762         if (word == 0xffff) {
1763                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1764                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1765                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1766                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1767         } else {
1768                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1769                 if (value < -10 || value > 10)
1770                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1771                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1772                 if (value < -10 || value > 10)
1773                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1774                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1775         }
1776
1777         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1778         if (word == 0xffff) {
1779                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1780                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1781                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1782                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1783         } else {
1784                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1785                 if (value < -10 || value > 10)
1786                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1787                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1788                 if (value < -10 || value > 10)
1789                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1790                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1791         }
1792
1793         return 0;
1794 }
1795
1796 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1797 {
1798         u32 reg;
1799         u16 value;
1800         u16 eeprom;
1801
1802         /*
1803          * Read EEPROM word for configuration.
1804          */
1805         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1806
1807         /*
1808          * Identify RF chipset.
1809          */
1810         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1811         rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1812         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1813                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
1814
1815         if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) {
1816                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1817                 return -ENODEV;
1818         }
1819
1820         if (!rt2x00_rf(rt2x00dev, RF5226) &&
1821             !rt2x00_rf(rt2x00dev, RF2528) &&
1822             !rt2x00_rf(rt2x00dev, RF5225) &&
1823             !rt2x00_rf(rt2x00dev, RF2527)) {
1824                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1825                 return -ENODEV;
1826         }
1827
1828         /*
1829          * Identify default antenna configuration.
1830          */
1831         rt2x00dev->default_ant.tx =
1832             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1833         rt2x00dev->default_ant.rx =
1834             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1835
1836         /*
1837          * Read the Frame type.
1838          */
1839         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1840                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1841
1842         /*
1843          * Detect if this device has an hardware controlled radio.
1844          */
1845         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1846                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1847
1848         /*
1849          * Read frequency offset.
1850          */
1851         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1852         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1853
1854         /*
1855          * Read external LNA informations.
1856          */
1857         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1858
1859         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1860                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1861                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1862         }
1863
1864         /*
1865          * Store led settings, for correct led behaviour.
1866          */
1867 #ifdef CONFIG_RT2X00_LIB_LEDS
1868         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1869
1870         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1871         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1872         if (value == LED_MODE_SIGNAL_STRENGTH)
1873                 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1874                                  LED_TYPE_QUALITY);
1875
1876         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1877         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1878                            rt2x00_get_field16(eeprom,
1879                                               EEPROM_LED_POLARITY_GPIO_0));
1880         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1881                            rt2x00_get_field16(eeprom,
1882                                               EEPROM_LED_POLARITY_GPIO_1));
1883         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1884                            rt2x00_get_field16(eeprom,
1885                                               EEPROM_LED_POLARITY_GPIO_2));
1886         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1887                            rt2x00_get_field16(eeprom,
1888                                               EEPROM_LED_POLARITY_GPIO_3));
1889         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1890                            rt2x00_get_field16(eeprom,
1891                                               EEPROM_LED_POLARITY_GPIO_4));
1892         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1893                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1894         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1895                            rt2x00_get_field16(eeprom,
1896                                               EEPROM_LED_POLARITY_RDY_G));
1897         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1898                            rt2x00_get_field16(eeprom,
1899                                               EEPROM_LED_POLARITY_RDY_A));
1900 #endif /* CONFIG_RT2X00_LIB_LEDS */
1901
1902         return 0;
1903 }
1904
1905 /*
1906  * RF value list for RF2528
1907  * Supports: 2.4 GHz
1908  */
1909 static const struct rf_channel rf_vals_bg_2528[] = {
1910         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1911         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1912         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1913         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1914         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1915         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1916         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1917         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1918         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1919         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1920         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1921         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1922         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1923         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1924 };
1925
1926 /*
1927  * RF value list for RF5226
1928  * Supports: 2.4 GHz & 5.2 GHz
1929  */
1930 static const struct rf_channel rf_vals_5226[] = {
1931         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1932         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1933         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1934         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1935         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1936         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1937         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1938         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1939         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1940         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1941         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1942         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1943         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1944         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1945
1946         /* 802.11 UNI / HyperLan 2 */
1947         { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1948         { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1949         { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1950         { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1951         { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1952         { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1953         { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1954         { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1955
1956         /* 802.11 HyperLan 2 */
1957         { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1958         { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1959         { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1960         { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1961         { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1962         { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1963         { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1964         { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1965         { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1966         { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1967
1968         /* 802.11 UNII */
1969         { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1970         { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1971         { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1972         { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1973         { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1974         { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1975
1976         /* MMAC(Japan)J52 ch 34,38,42,46 */
1977         { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1978         { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1979         { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1980         { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1981 };
1982
1983 /*
1984  * RF value list for RF5225 & RF2527
1985  * Supports: 2.4 GHz & 5.2 GHz
1986  */
1987 static const struct rf_channel rf_vals_5225_2527[] = {
1988         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1989         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1990         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1991         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1992         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1993         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1994         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1995         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1996         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1997         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1998         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1999         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2000         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2001         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2002
2003         /* 802.11 UNI / HyperLan 2 */
2004         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2005         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2006         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2007         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2008         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2009         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2010         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2011         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2012
2013         /* 802.11 HyperLan 2 */
2014         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2015         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2016         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2017         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2018         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2019         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2020         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2021         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2022         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2023         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2024
2025         /* 802.11 UNII */
2026         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2027         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2028         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2029         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2030         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2031         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2032
2033         /* MMAC(Japan)J52 ch 34,38,42,46 */
2034         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2035         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2036         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2037         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2038 };
2039
2040
2041 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2042 {
2043         struct hw_mode_spec *spec = &rt2x00dev->spec;
2044         struct channel_info *info;
2045         char *tx_power;
2046         unsigned int i;
2047
2048         /*
2049          * Initialize all hw fields.
2050          */
2051         rt2x00dev->hw->flags =
2052             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2053             IEEE80211_HW_SIGNAL_DBM |
2054             IEEE80211_HW_SUPPORTS_PS |
2055             IEEE80211_HW_PS_NULLFUNC_STACK;
2056
2057         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2058         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2059                                 rt2x00_eeprom_addr(rt2x00dev,
2060                                                    EEPROM_MAC_ADDR_0));
2061
2062         /*
2063          * Initialize hw_mode information.
2064          */
2065         spec->supported_bands = SUPPORT_BAND_2GHZ;
2066         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2067
2068         if (rt2x00_rf(rt2x00dev, RF2528)) {
2069                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2070                 spec->channels = rf_vals_bg_2528;
2071         } else if (rt2x00_rf(rt2x00dev, RF5226)) {
2072                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2073                 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2074                 spec->channels = rf_vals_5226;
2075         } else if (rt2x00_rf(rt2x00dev, RF2527)) {
2076                 spec->num_channels = 14;
2077                 spec->channels = rf_vals_5225_2527;
2078         } else if (rt2x00_rf(rt2x00dev, RF5225)) {
2079                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2080                 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2081                 spec->channels = rf_vals_5225_2527;
2082         }
2083
2084         /*
2085          * Create channel information array
2086          */
2087         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2088         if (!info)
2089                 return -ENOMEM;
2090
2091         spec->channels_info = info;
2092
2093         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2094         for (i = 0; i < 14; i++)
2095                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2096
2097         if (spec->num_channels > 14) {
2098                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2099                 for (i = 14; i < spec->num_channels; i++)
2100                         info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2101         }
2102
2103         return 0;
2104 }
2105
2106 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2107 {
2108         int retval;
2109
2110         /*
2111          * Allocate eeprom data.
2112          */
2113         retval = rt73usb_validate_eeprom(rt2x00dev);
2114         if (retval)
2115                 return retval;
2116
2117         retval = rt73usb_init_eeprom(rt2x00dev);
2118         if (retval)
2119                 return retval;
2120
2121         /*
2122          * Initialize hw specifications.
2123          */
2124         retval = rt73usb_probe_hw_mode(rt2x00dev);
2125         if (retval)
2126                 return retval;
2127
2128         /*
2129          * This device has multiple filters for control frames,
2130          * but has no a separate filter for PS Poll frames.
2131          */
2132         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2133
2134         /*
2135          * This device requires firmware.
2136          */
2137         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2138         if (!modparam_nohwcrypt)
2139                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2140
2141         /*
2142          * Set the rssi offset.
2143          */
2144         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2145
2146         return 0;
2147 }
2148
2149 /*
2150  * IEEE80211 stack callback functions.
2151  */
2152 static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2153                            const struct ieee80211_tx_queue_params *params)
2154 {
2155         struct rt2x00_dev *rt2x00dev = hw->priv;
2156         struct data_queue *queue;
2157         struct rt2x00_field32 field;
2158         int retval;
2159         u32 reg;
2160         u32 offset;
2161
2162         /*
2163          * First pass the configuration through rt2x00lib, that will
2164          * update the queue settings and validate the input. After that
2165          * we are free to update the registers based on the value
2166          * in the queue parameter.
2167          */
2168         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2169         if (retval)
2170                 return retval;
2171
2172         /*
2173          * We only need to perform additional register initialization
2174          * for WMM queues/
2175          */
2176         if (queue_idx >= 4)
2177                 return 0;
2178
2179         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2180
2181         /* Update WMM TXOP register */
2182         offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2183         field.bit_offset = (queue_idx & 1) * 16;
2184         field.bit_mask = 0xffff << field.bit_offset;
2185
2186         rt2x00usb_register_read(rt2x00dev, offset, &reg);
2187         rt2x00_set_field32(&reg, field, queue->txop);
2188         rt2x00usb_register_write(rt2x00dev, offset, reg);
2189
2190         /* Update WMM registers */
2191         field.bit_offset = queue_idx * 4;
2192         field.bit_mask = 0xf << field.bit_offset;
2193
2194         rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2195         rt2x00_set_field32(&reg, field, queue->aifs);
2196         rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2197
2198         rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2199         rt2x00_set_field32(&reg, field, queue->cw_min);
2200         rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2201
2202         rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2203         rt2x00_set_field32(&reg, field, queue->cw_max);
2204         rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2205
2206         return 0;
2207 }
2208
2209 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2210 {
2211         struct rt2x00_dev *rt2x00dev = hw->priv;
2212         u64 tsf;
2213         u32 reg;
2214
2215         rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2216         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2217         rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2218         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2219
2220         return tsf;
2221 }
2222
2223 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2224         .tx                     = rt2x00mac_tx,
2225         .start                  = rt2x00mac_start,
2226         .stop                   = rt2x00mac_stop,
2227         .add_interface          = rt2x00mac_add_interface,
2228         .remove_interface       = rt2x00mac_remove_interface,
2229         .config                 = rt2x00mac_config,
2230         .configure_filter       = rt2x00mac_configure_filter,
2231         .set_tim                = rt2x00mac_set_tim,
2232         .set_key                = rt2x00mac_set_key,
2233         .get_stats              = rt2x00mac_get_stats,
2234         .bss_info_changed       = rt2x00mac_bss_info_changed,
2235         .conf_tx                = rt73usb_conf_tx,
2236         .get_tsf                = rt73usb_get_tsf,
2237         .rfkill_poll            = rt2x00mac_rfkill_poll,
2238 };
2239
2240 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2241         .probe_hw               = rt73usb_probe_hw,
2242         .get_firmware_name      = rt73usb_get_firmware_name,
2243         .check_firmware         = rt73usb_check_firmware,
2244         .load_firmware          = rt73usb_load_firmware,
2245         .initialize             = rt2x00usb_initialize,
2246         .uninitialize           = rt2x00usb_uninitialize,
2247         .clear_entry            = rt2x00usb_clear_entry,
2248         .set_device_state       = rt73usb_set_device_state,
2249         .rfkill_poll            = rt73usb_rfkill_poll,
2250         .link_stats             = rt73usb_link_stats,
2251         .reset_tuner            = rt73usb_reset_tuner,
2252         .link_tuner             = rt73usb_link_tuner,
2253         .write_tx_desc          = rt73usb_write_tx_desc,
2254         .write_tx_data          = rt2x00usb_write_tx_data,
2255         .write_beacon           = rt73usb_write_beacon,
2256         .get_tx_data_len        = rt73usb_get_tx_data_len,
2257         .kick_tx_queue          = rt2x00usb_kick_tx_queue,
2258         .kill_tx_queue          = rt2x00usb_kill_tx_queue,
2259         .fill_rxdone            = rt73usb_fill_rxdone,
2260         .config_shared_key      = rt73usb_config_shared_key,
2261         .config_pairwise_key    = rt73usb_config_pairwise_key,
2262         .config_filter          = rt73usb_config_filter,
2263         .config_intf            = rt73usb_config_intf,
2264         .config_erp             = rt73usb_config_erp,
2265         .config_ant             = rt73usb_config_ant,
2266         .config                 = rt73usb_config,
2267 };
2268
2269 static const struct data_queue_desc rt73usb_queue_rx = {
2270         .entry_num              = RX_ENTRIES,
2271         .data_size              = DATA_FRAME_SIZE,
2272         .desc_size              = RXD_DESC_SIZE,
2273         .priv_size              = sizeof(struct queue_entry_priv_usb),
2274 };
2275
2276 static const struct data_queue_desc rt73usb_queue_tx = {
2277         .entry_num              = TX_ENTRIES,
2278         .data_size              = DATA_FRAME_SIZE,
2279         .desc_size              = TXD_DESC_SIZE,
2280         .priv_size              = sizeof(struct queue_entry_priv_usb),
2281 };
2282
2283 static const struct data_queue_desc rt73usb_queue_bcn = {
2284         .entry_num              = 4 * BEACON_ENTRIES,
2285         .data_size              = MGMT_FRAME_SIZE,
2286         .desc_size              = TXINFO_SIZE,
2287         .priv_size              = sizeof(struct queue_entry_priv_usb),
2288 };
2289
2290 static const struct rt2x00_ops rt73usb_ops = {
2291         .name                   = KBUILD_MODNAME,
2292         .max_sta_intf           = 1,
2293         .max_ap_intf            = 4,
2294         .eeprom_size            = EEPROM_SIZE,
2295         .rf_size                = RF_SIZE,
2296         .tx_queues              = NUM_TX_QUEUES,
2297         .extra_tx_headroom      = TXD_DESC_SIZE,
2298         .rx                     = &rt73usb_queue_rx,
2299         .tx                     = &rt73usb_queue_tx,
2300         .bcn                    = &rt73usb_queue_bcn,
2301         .lib                    = &rt73usb_rt2x00_ops,
2302         .hw                     = &rt73usb_mac80211_ops,
2303 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2304         .debugfs                = &rt73usb_rt2x00debug,
2305 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2306 };
2307
2308 /*
2309  * rt73usb module information.
2310  */
2311 static struct usb_device_id rt73usb_device_table[] = {
2312         /* AboCom */
2313         { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) },
2314         { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) },
2315         { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2316         { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) },
2317         { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) },
2318         /* AL */
2319         { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) },
2320         /* Amigo */
2321         { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2322         { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2323         /* AMIT  */
2324         { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) },
2325         /* Askey */
2326         { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2327         /* ASUS */
2328         { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2329         { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2330         /* Belkin */
2331         { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2332         { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2333         { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2334         { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2335         /* Billionton */
2336         { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2337         { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) },
2338         /* Buffalo */
2339         { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
2340         { USB_DEVICE(0x0411, 0x00d9), USB_DEVICE_DATA(&rt73usb_ops) },
2341         { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2342         { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) },
2343         { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) },
2344         /* CEIVA */
2345         { USB_DEVICE(0x178d, 0x02be), USB_DEVICE_DATA(&rt73usb_ops) },
2346         /* CNet */
2347         { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2348         { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2349         /* Conceptronic */
2350         { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2351         /* Corega */
2352         { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2353         /* D-Link */
2354         { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2355         { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2356         { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2357         { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2358         /* Edimax */
2359         { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2360         { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) },
2361         /* EnGenius */
2362         { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) },
2363         /* Gemtek */
2364         { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2365         /* Gigabyte */
2366         { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2367         { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2368         /* Huawei-3Com */
2369         { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2370         /* Hercules */
2371         { USB_DEVICE(0x06f8, 0xe002), USB_DEVICE_DATA(&rt73usb_ops) },
2372         { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2373         { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2374         /* Linksys */
2375         { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2376         { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2377         { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
2378         /* MSI */
2379         { USB_DEVICE(0x0db0, 0x4600), USB_DEVICE_DATA(&rt73usb_ops) },
2380         { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2381         { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2382         { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2383         { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2384         /* Ovislink */
2385         { USB_DEVICE(0x1b75, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2386         /* Ralink */
2387         { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) },
2388         { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2389         { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2390         /* Qcom */
2391         { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2392         { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2393         { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2394         /* Samsung */
2395         { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) },
2396         /* Senao */
2397         { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2398         /* Sitecom */
2399         { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) },
2400         { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) },
2401         { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) },
2402         { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2403         { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2404         /* Surecom */
2405         { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2406         /* Tilgin */
2407         { USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops) },
2408         /* Philips */
2409         { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) },
2410         /* Planex */
2411         { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2412         { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2413         /* WideTell */
2414         { USB_DEVICE(0x7167, 0x3840), USB_DEVICE_DATA(&rt73usb_ops) },
2415         /* Zcom */
2416         { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) },
2417         /* ZyXEL */
2418         { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) },
2419         { 0, }
2420 };
2421
2422 MODULE_AUTHOR(DRV_PROJECT);
2423 MODULE_VERSION(DRV_VERSION);
2424 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2425 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2426 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2427 MODULE_FIRMWARE(FIRMWARE_RT2571);
2428 MODULE_LICENSE("GPL");
2429
2430 static struct usb_driver rt73usb_driver = {
2431         .name           = KBUILD_MODNAME,
2432         .id_table       = rt73usb_device_table,
2433         .probe          = rt2x00usb_probe,
2434         .disconnect     = rt2x00usb_disconnect,
2435         .suspend        = rt2x00usb_suspend,
2436         .resume         = rt2x00usb_resume,
2437 };
2438
2439 static int __init rt73usb_init(void)
2440 {
2441         return usb_register(&rt73usb_driver);
2442 }
2443
2444 static void __exit rt73usb_exit(void)
2445 {
2446         usb_deregister(&rt73usb_driver);
2447 }
2448
2449 module_init(rt73usb_init);
2450 module_exit(rt73usb_exit);