drivers/net/wireless/rt2x00/rt61pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: rt61pci device specific routines.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/slab.h>
  34 #include <linux/pci.h>
  35 #include <linux/eeprom_93cx6.h>
  36
  37 #include "rt2x00.h"
  38 #include "rt2x00pci.h"
  39 #include "rt61pci.h"
  40
  41 /*
  42  * Allow hardware encryption to be disabled.
  43  */
  44 static int modparam_nohwcrypt = 0;
  45 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  47
  48 /*
  49  * Register access.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attempt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  */
  59 #define WAIT_FOR_BBP(__dev, __reg) \
  60         rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
  61 #define WAIT_FOR_RF(__dev, __reg) \
  62         rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
  63 #define WAIT_FOR_MCU(__dev, __reg) \
  64         rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  65                                H2M_MAILBOX_CSR_OWNER, (__reg))
  66
  67 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                               const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         mutex_lock(&rt2x00dev->csr_mutex);
  73
  74         /*
  75          * Wait until the BBP becomes available, afterwards we
  76          * can safely write the new data into the register.
  77          */
  78         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  79                 reg = 0;
  80                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  81                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  82                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  83                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  84
  85                 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  86         }
  87
  88         mutex_unlock(&rt2x00dev->csr_mutex);
  89 }
  90
  91 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  92                              const unsigned int word, u8 *value)
  93 {
  94         u32 reg;
  95
  96         mutex_lock(&rt2x00dev->csr_mutex);
  97
  98         /*
  99          * Wait until the BBP becomes available, afterwards we
 100          * can safely write the read request into the register.
 101          * After the data has been written, we wait until hardware
 102          * returns the correct value, if at any time the register
 103          * doesn't become available in time, reg will be 0xffffffff
 104          * which means we return 0xff to the caller.
 105          */
 106         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 107                 reg = 0;
 108                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 109                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 110                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 111
 112                 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
 113
 114                 WAIT_FOR_BBP(rt2x00dev, &reg);
 115         }
 116
 117         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 118
 119         mutex_unlock(&rt2x00dev->csr_mutex);
 120 }
 121
 122 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
 123                              const unsigned int word, const u32 value)
 124 {
 125         u32 reg;
 126
 127         mutex_lock(&rt2x00dev->csr_mutex);
 128
 129         /*
 130          * Wait until the RF becomes available, afterwards we
 131          * can safely write the new data into the register.
 132          */
 133         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 134                 reg = 0;
 135                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 136                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
 137                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 138                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 139
 140                 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
 141                 rt2x00_rf_write(rt2x00dev, word, value);
 142         }
 143
 144         mutex_unlock(&rt2x00dev->csr_mutex);
 145 }
 146
 147 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 148                                 const u8 command, const u8 token,
 149                                 const u8 arg0, const u8 arg1)
 150 {
 151         u32 reg;
 152
 153         mutex_lock(&rt2x00dev->csr_mutex);
 154
 155         /*
 156          * Wait until the MCU becomes available, afterwards we
 157          * can safely write the new data into the register.
 158          */
 159         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 160                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 161                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 162                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 163                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 164                 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 165
 166                 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
 167                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 168                 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
 169                 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 170         }
 171
 172         mutex_unlock(&rt2x00dev->csr_mutex);
 173
 174 }
 175
 176 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 177 {
 178         struct rt2x00_dev *rt2x00dev = eeprom->data;
 179         u32 reg;
 180
 181         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 182
 183         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 184         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 185         eeprom->reg_data_clock =
 186             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 187         eeprom->reg_chip_select =
 188             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 189 }
 190
 191 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 192 {
 193         struct rt2x00_dev *rt2x00dev = eeprom->data;
 194         u32 reg = 0;
 195
 196         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 197         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 198         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 199                            !!eeprom->reg_data_clock);
 200         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 201                            !!eeprom->reg_chip_select);
 202
 203         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 204 }
 205
 206 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 207 static const struct rt2x00debug rt61pci_rt2x00debug = {
 208         .owner  = THIS_MODULE,
 209         .csr    = {
 210                 .read           = rt2x00pci_register_read,
 211                 .write          = rt2x00pci_register_write,
 212                 .flags          = RT2X00DEBUGFS_OFFSET,
 213                 .word_base      = CSR_REG_BASE,
 214                 .word_size      = sizeof(u32),
 215                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 216         },
 217         .eeprom = {
 218                 .read           = rt2x00_eeprom_read,
 219                 .write          = rt2x00_eeprom_write,
 220                 .word_base      = EEPROM_BASE,
 221                 .word_size      = sizeof(u16),
 222                 .word_count     = EEPROM_SIZE / sizeof(u16),
 223         },
 224         .bbp    = {
 225                 .read           = rt61pci_bbp_read,
 226                 .write          = rt61pci_bbp_write,
 227                 .word_base      = BBP_BASE,
 228                 .word_size      = sizeof(u8),
 229                 .word_count     = BBP_SIZE / sizeof(u8),
 230         },
 231         .rf     = {
 232                 .read           = rt2x00_rf_read,
 233                 .write          = rt61pci_rf_write,
 234                 .word_base      = RF_BASE,
 235                 .word_size      = sizeof(u32),
 236                 .word_count     = RF_SIZE / sizeof(u32),
 237         },
 238 };
 239 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 240
 241 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 242 {
 243         u32 reg;
 244
 245         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 246         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
 247 }
 248
 249 #ifdef CONFIG_RT2X00_LIB_LEDS
 250 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
 251                                    enum led_brightness brightness)
 252 {
 253         struct rt2x00_led *led =
 254             container_of(led_cdev, struct rt2x00_led, led_dev);
 255         unsigned int enabled = brightness != LED_OFF;
 256         unsigned int a_mode =
 257             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 258         unsigned int bg_mode =
 259             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 260
 261         if (led->type == LED_TYPE_RADIO) {
 262                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 263                                    MCU_LEDCS_RADIO_STATUS, enabled);
 264
 265                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 266                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 267                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 268         } else if (led->type == LED_TYPE_ASSOC) {
 269                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 270                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 271                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 272                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 273
 274                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 275                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 276                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 277         } else if (led->type == LED_TYPE_QUALITY) {
 278                 /*
 279                  * The brightness is divided into 6 levels (0 - 5),
 280                  * this means we need to convert the brightness
 281                  * argument into the matching level within that range.
 282                  */
 283                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 284                                     brightness / (LED_FULL / 6), 0);
 285         }
 286 }
 287
 288 static int rt61pci_blink_set(struct led_classdev *led_cdev,
 289                              unsigned long *delay_on,
 290                              unsigned long *delay_off)
 291 {
 292         struct rt2x00_led *led =
 293             container_of(led_cdev, struct rt2x00_led, led_dev);
 294         u32 reg;
 295
 296         rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 297         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 298         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 299         rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
 300
 301         return 0;
 302 }
 303
 304 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
 305                              struct rt2x00_led *led,
 306                              enum led_type type)
 307 {
 308         led->rt2x00dev = rt2x00dev;
 309         led->type = type;
 310         led->led_dev.brightness_set = rt61pci_brightness_set;
 311         led->led_dev.blink_set = rt61pci_blink_set;
 312         led->flags = LED_INITIALIZED;
 313 }
 314 #endif /* CONFIG_RT2X00_LIB_LEDS */
 315
 316 /*
 317  * Configuration handlers.
 318  */
 319 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 320                                      struct rt2x00lib_crypto *crypto,
 321                                      struct ieee80211_key_conf *key)
 322 {
 323         struct hw_key_entry key_entry;
 324         struct rt2x00_field32 field;
 325         u32 mask;
 326         u32 reg;
 327
 328         if (crypto->cmd == SET_KEY) {
 329                 /*
 330                  * rt2x00lib can't determine the correct free
 331                  * key_idx for shared keys. We have 1 register
 332                  * with key valid bits. The goal is simple, read
 333                  * the register, if that is full we have no slots
 334                  * left.
 335                  * Note that each BSS is allowed to have up to 4
 336                  * shared keys, so put a mask over the allowed
 337                  * entries.
 338                  */
 339                 mask = (0xf << crypto->bssidx);
 340
 341                 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 342                 reg &= mask;
 343
 344                 if (reg && reg == mask)
 345                         return -ENOSPC;
 346
 347                 key->hw_key_idx += reg ? ffz(reg) : 0;
 348
 349                 /*
 350                  * Upload key to hardware
 351                  */
 352                 memcpy(key_entry.key, crypto->key,
 353                        sizeof(key_entry.key));
 354                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 355                        sizeof(key_entry.tx_mic));
 356                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 357                        sizeof(key_entry.rx_mic));
 358
 359                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 360                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 361                                               &key_entry, sizeof(key_entry));
 362
 363                 /*
 364                  * The cipher types are stored over 2 registers.
 365                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 366                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 367                  * Using the correct defines correctly will cause overhead,
 368                  * so just calculate the correct offset.
 369                  */
 370                 if (key->hw_key_idx < 8) {
 371                         field.bit_offset = (3 * key->hw_key_idx);
 372                         field.bit_mask = 0x7 << field.bit_offset;
 373
 374                         rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
 375                         rt2x00_set_field32(&reg, field, crypto->cipher);
 376                         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
 377                 } else {
 378                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 379                         field.bit_mask = 0x7 << field.bit_offset;
 380
 381                         rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
 382                         rt2x00_set_field32(&reg, field, crypto->cipher);
 383                         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
 384                 }
 385
 386                 /*
 387                  * The driver does not support the IV/EIV generation
 388                  * in hardware. However it doesn't support the IV/EIV
 389                  * inside the ieee80211 frame either, but requires it
 390                  * to be provided separately for the descriptor.
 391                  * rt2x00lib will cut the IV/EIV data out of all frames
 392                  * given to us by mac80211, but we must tell mac80211
 393                  * to generate the IV/EIV data.
 394                  */
 395                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 396         }
 397
 398         /*
 399          * SEC_CSR0 contains only single-bit fields to indicate
 400          * a particular key is valid. Because using the FIELD32()
 401          * defines directly will cause a lot of overhead, we use
 402          * a calculation to determine the correct bit directly.
 403          */
 404         mask = 1 << key->hw_key_idx;
 405
 406         rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 407         if (crypto->cmd == SET_KEY)
 408                 reg |= mask;
 409         else if (crypto->cmd == DISABLE_KEY)
 410                 reg &= ~mask;
 411         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
 412
 413         return 0;
 414 }
 415
 416 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 417                                        struct rt2x00lib_crypto *crypto,
 418                                        struct ieee80211_key_conf *key)
 419 {
 420         struct hw_pairwise_ta_entry addr_entry;
 421         struct hw_key_entry key_entry;
 422         u32 mask;
 423         u32 reg;
 424
 425         if (crypto->cmd == SET_KEY) {
 426                 /*
 427                  * rt2x00lib can't determine the correct free
 428                  * key_idx for pairwise keys. We have 2 registers
 429                  * with key valid bits. The goal is simple: read
 430                  * the first register. If that is full, move to
 431                  * the next register.
 432                  * When both registers are full, we drop the key.
 433                  * Otherwise, we use the first invalid entry.
 434                  */
 435                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 436                 if (reg && reg == ~0) {
 437                         key->hw_key_idx = 32;
 438                         rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 439                         if (reg && reg == ~0)
 440                                 return -ENOSPC;
 441                 }
 442
 443                 key->hw_key_idx += reg ? ffz(reg) : 0;
 444
 445                 /*
 446                  * Upload key to hardware
 447                  */
 448                 memcpy(key_entry.key, crypto->key,
 449                        sizeof(key_entry.key));
 450                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 451                        sizeof(key_entry.tx_mic));
 452                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 453                        sizeof(key_entry.rx_mic));
 454
 455                 memset(&addr_entry, 0, sizeof(addr_entry));
 456                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 457                 addr_entry.cipher = crypto->cipher;
 458
 459                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 460                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 461                                               &key_entry, sizeof(key_entry));
 462
 463                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 464                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 465                                               &addr_entry, sizeof(addr_entry));
 466
 467                 /*
 468                  * Enable pairwise lookup table for given BSS idx.
 469                  * Without this, received frames will not be decrypted
 470                  * by the hardware.
 471                  */
 472                 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
 473                 reg |= (1 << crypto->bssidx);
 474                 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
 475
 476                 /*
 477                  * The driver does not support the IV/EIV generation
 478                  * in hardware. However it doesn't support the IV/EIV
 479                  * inside the ieee80211 frame either, but requires it
 480                  * to be provided separately for the descriptor.
 481                  * rt2x00lib will cut the IV/EIV data out of all frames
 482                  * given to us by mac80211, but we must tell mac80211
 483                  * to generate the IV/EIV data.
 484                  */
 485                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 486         }
 487
 488         /*
 489          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 490          * a particular key is valid. Because using the FIELD32()
 491          * defines directly will cause a lot of overhead, we use
 492          * a calculation to determine the correct bit directly.
 493          */
 494         if (key->hw_key_idx < 32) {
 495                 mask = 1 << key->hw_key_idx;
 496
 497                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 498                 if (crypto->cmd == SET_KEY)
 499                         reg |= mask;
 500                 else if (crypto->cmd == DISABLE_KEY)
 501                         reg &= ~mask;
 502                 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
 503         } else {
 504                 mask = 1 << (key->hw_key_idx - 32);
 505
 506                 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 507                 if (crypto->cmd == SET_KEY)
 508                         reg |= mask;
 509                 else if (crypto->cmd == DISABLE_KEY)
 510                         reg &= ~mask;
 511                 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
 512         }
 513
 514         return 0;
 515 }
 516
 517 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
 518                                   const unsigned int filter_flags)
 519 {
 520         u32 reg;
 521
 522         /*
 523          * Start configuration steps.
 524          * Note that the version error will always be dropped
 525          * and broadcast frames will always be accepted since
 526          * there is no filter for it at this time.
 527          */
 528         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 529         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 530                            !(filter_flags & FIF_FCSFAIL));
 531         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 532                            !(filter_flags & FIF_PLCPFAIL));
 533         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 534                            !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
 535         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 536                            !(filter_flags & FIF_PROMISC_IN_BSS));
 537         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 538                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 539                            !rt2x00dev->intf_ap_count);
 540         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 541         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 542                            !(filter_flags & FIF_ALLMULTI));
 543         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 544         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 545                            !(filter_flags & FIF_CONTROL));
 546         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 547 }
 548
 549 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
 550                                 struct rt2x00_intf *intf,
 551                                 struct rt2x00intf_conf *conf,
 552                                 const unsigned int flags)
 553 {
 554         u32 reg;
 555
 556         if (flags & CONFIG_UPDATE_TYPE) {
 557                 /*
 558                  * Enable synchronisation.
 559                  */
 560                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 561                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 562                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 563         }
 564
 565         if (flags & CONFIG_UPDATE_MAC) {
 566                 reg = le32_to_cpu(conf->mac[1]);
 567                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 568                 conf->mac[1] = cpu_to_le32(reg);
 569
 570                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
 571                                               conf->mac, sizeof(conf->mac));
 572         }
 573
 574         if (flags & CONFIG_UPDATE_BSSID) {
 575                 reg = le32_to_cpu(conf->bssid[1]);
 576                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 577                 conf->bssid[1] = cpu_to_le32(reg);
 578
 579                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
 580                                               conf->bssid, sizeof(conf->bssid));
 581         }
 582 }
 583
 584 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
 585                                struct rt2x00lib_erp *erp,
 586                                u32 changed)
 587 {
 588         u32 reg;
 589
 590         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 591         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
 592         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 593         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 594
 595         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
 596                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 597                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 598                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 599                                    !!erp->short_preamble);
 600                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 601         }
 602
 603         if (changed & BSS_CHANGED_BASIC_RATES)
 604                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5,
 605                                          erp->basic_rates);
 606
 607         if (changed & BSS_CHANGED_BEACON_INT) {
 608                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 609                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 610                                    erp->beacon_int * 16);
 611                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 612         }
 613
 614         if (changed & BSS_CHANGED_ERP_SLOT) {
 615                 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
 616                 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
 617                 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
 618
 619                 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
 620                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
 621                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 622                 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
 623                 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
 624         }
 625 }
 626
 627 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 628                                       struct antenna_setup *ant)
 629 {
 630         u8 r3;
 631         u8 r4;
 632         u8 r77;
 633
 634         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 635         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 636         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 637
 638         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
 639
 640         /*
 641          * Configure the RX antenna.
 642          */
 643         switch (ant->rx) {
 644         case ANTENNA_HW_DIVERSITY:
 645                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 646                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 647                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
 648                 break;
 649         case ANTENNA_A:
 650                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 651                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 652                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 653                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 654                 else
 655                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 656                 break;
 657         case ANTENNA_B:
 658         default:
 659                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 660                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 661                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 662                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 663                 else
 664                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 665                 break;
 666         }
 667
 668         rt61pci_bbp_write(rt2x00dev, 77, r77);
 669         rt61pci_bbp_write(rt2x00dev, 3, r3);
 670         rt61pci_bbp_write(rt2x00dev, 4, r4);
 671 }
 672
 673 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 674                                       struct antenna_setup *ant)
 675 {
 676         u8 r3;
 677         u8 r4;
 678         u8 r77;
 679
 680         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 681         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 682         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 683
 684         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
 685         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 686                           !test_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags));
 687
 688         /*
 689          * Configure the RX antenna.
 690          */
 691         switch (ant->rx) {
 692         case ANTENNA_HW_DIVERSITY:
 693                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 694                 break;
 695         case ANTENNA_A:
 696                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 697                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 698                 break;
 699         case ANTENNA_B:
 700         default:
 701                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 702                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 703                 break;
 704         }
 705
 706         rt61pci_bbp_write(rt2x00dev, 77, r77);
 707         rt61pci_bbp_write(rt2x00dev, 3, r3);
 708         rt61pci_bbp_write(rt2x00dev, 4, r4);
 709 }
 710
 711 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 712                                            const int p1, const int p2)
 713 {
 714         u32 reg;
 715
 716         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 717
 718         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
 719         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
 720
 721         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
 722         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
 723
 724         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 725 }
 726
 727 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
 728                                         struct antenna_setup *ant)
 729 {
 730         u8 r3;
 731         u8 r4;
 732         u8 r77;
 733
 734         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 735         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 736         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 737
 738         /*
 739          * Configure the RX antenna.
 740          */
 741         switch (ant->rx) {
 742         case ANTENNA_A:
 743                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 744                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 745                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
 746                 break;
 747         case ANTENNA_HW_DIVERSITY:
 748                 /*
 749                  * FIXME: Antenna selection for the rf 2529 is very confusing
 750                  * in the legacy driver. Just default to antenna B until the
 751                  * legacy code can be properly translated into rt2x00 code.
 752                  */
 753         case ANTENNA_B:
 754         default:
 755                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 756                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 757                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
 758                 break;
 759         }
 760
 761         rt61pci_bbp_write(rt2x00dev, 77, r77);
 762         rt61pci_bbp_write(rt2x00dev, 3, r3);
 763         rt61pci_bbp_write(rt2x00dev, 4, r4);
 764 }
 765
 766 struct antenna_sel {
 767         u8 word;
 768         /*
 769          * value[0] -> non-LNA
 770          * value[1] -> LNA
 771          */
 772         u8 value[2];
 773 };
 774
 775 static const struct antenna_sel antenna_sel_a[] = {
 776         { 96,  { 0x58, 0x78 } },
 777         { 104, { 0x38, 0x48 } },
 778         { 75,  { 0xfe, 0x80 } },
 779         { 86,  { 0xfe, 0x80 } },
 780         { 88,  { 0xfe, 0x80 } },
 781         { 35,  { 0x60, 0x60 } },
 782         { 97,  { 0x58, 0x58 } },
 783         { 98,  { 0x58, 0x58 } },
 784 };
 785
 786 static const struct antenna_sel antenna_sel_bg[] = {
 787         { 96,  { 0x48, 0x68 } },
 788         { 104, { 0x2c, 0x3c } },
 789         { 75,  { 0xfe, 0x80 } },
 790         { 86,  { 0xfe, 0x80 } },
 791         { 88,  { 0xfe, 0x80 } },
 792         { 35,  { 0x50, 0x50 } },
 793         { 97,  { 0x48, 0x48 } },
 794         { 98,  { 0x48, 0x48 } },
 795 };
 796
 797 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
 798                                struct antenna_setup *ant)
 799 {
 800         const struct antenna_sel *sel;
 801         unsigned int lna;
 802         unsigned int i;
 803         u32 reg;
 804
 805         /*
 806          * We should never come here because rt2x00lib is supposed
 807          * to catch this and send us the correct antenna explicitely.
 808          */
 809         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 810                ant->tx == ANTENNA_SW_DIVERSITY);
 811
 812         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 813                 sel = antenna_sel_a;
 814                 lna = test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
 815         } else {
 816                 sel = antenna_sel_bg;
 817                 lna = test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
 818         }
 819
 820         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 821                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 822
 823         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
 824
 825         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 826                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 827         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 828                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 829
 830         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
 831
 832         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
 833                 rt61pci_config_antenna_5x(rt2x00dev, ant);
 834         else if (rt2x00_rf(rt2x00dev, RF2527))
 835                 rt61pci_config_antenna_2x(rt2x00dev, ant);
 836         else if (rt2x00_rf(rt2x00dev, RF2529)) {
 837                 if (test_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags))
 838                         rt61pci_config_antenna_2x(rt2x00dev, ant);
 839                 else
 840                         rt61pci_config_antenna_2529(rt2x00dev, ant);
 841         }
 842 }
 843
 844 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 845                                     struct rt2x00lib_conf *libconf)
 846 {
 847         u16 eeprom;
 848         short lna_gain = 0;
 849
 850         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
 851                 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
 852                         lna_gain += 14;
 853
 854                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 855                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 856         } else {
 857                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
 858                         lna_gain += 14;
 859
 860                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 861                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 862         }
 863
 864         rt2x00dev->lna_gain = lna_gain;
 865 }
 866
 867 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
 868                                    struct rf_channel *rf, const int txpower)
 869 {
 870         u8 r3;
 871         u8 r94;
 872         u8 smart;
 873
 874         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 875         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 876
 877         smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
 878
 879         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 880         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 881         rt61pci_bbp_write(rt2x00dev, 3, r3);
 882
 883         r94 = 6;
 884         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 885                 r94 += txpower - MAX_TXPOWER;
 886         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 887                 r94 += txpower;
 888         rt61pci_bbp_write(rt2x00dev, 94, r94);
 889
 890         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 891         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 892         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 893         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 894
 895         udelay(200);
 896
 897         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 898         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 899         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 900         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 901
 902         udelay(200);
 903
 904         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 905         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 906         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 907         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 908
 909         msleep(1);
 910 }
 911
 912 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 913                                    const int txpower)
 914 {
 915         struct rf_channel rf;
 916
 917         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 918         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 919         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 920         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 921
 922         rt61pci_config_channel(rt2x00dev, &rf, txpower);
 923 }
 924
 925 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 926                                     struct rt2x00lib_conf *libconf)
 927 {
 928         u32 reg;
 929
 930         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 931         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
 932         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
 933         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
 934         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
 935                            libconf->conf->long_frame_max_tx_count);
 936         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
 937                            libconf->conf->short_frame_max_tx_count);
 938         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 939 }
 940
 941 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
 942                                 struct rt2x00lib_conf *libconf)
 943 {
 944         enum dev_state state =
 945             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 946                 STATE_SLEEP : STATE_AWAKE;
 947         u32 reg;
 948
 949         if (state == STATE_SLEEP) {
 950                 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
 951                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
 952                                    rt2x00dev->beacon_int - 10);
 953                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
 954                                    libconf->conf->listen_interval - 1);
 955                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
 956
 957                 /* We must first disable autowake before it can be enabled */
 958                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 959                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 960
 961                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
 962                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 963
 964                 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
 965                 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
 966                 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
 967
 968                 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
 969         } else {
 970                 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
 971                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
 972                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
 973                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 974                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
 975                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 976
 977                 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
 978                 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
 979                 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
 980
 981                 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
 982         }
 983 }
 984
 985 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
 986                            struct rt2x00lib_conf *libconf,
 987                            const unsigned int flags)
 988 {
 989         /* Always recalculate LNA gain before changing configuration */
 990         rt61pci_config_lna_gain(rt2x00dev, libconf);
 991
 992         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 993                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
 994                                        libconf->conf->power_level);
 995         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
 996             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
 997                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
 998         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 999                 rt61pci_config_retry_limit(rt2x00dev, libconf);
1000         if (flags & IEEE80211_CONF_CHANGE_PS)
1001                 rt61pci_config_ps(rt2x00dev, libconf);
1002 }
1003
1004 /*
1005  * Link tuning
1006  */
1007 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1008                                struct link_qual *qual)
1009 {
1010         u32 reg;
1011
1012         /*
1013          * Update FCS error count from register.
1014          */
1015         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1016         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1017
1018         /*
1019          * Update False CCA count from register.
1020          */
1021         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1022         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1023 }
1024
1025 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1026                                    struct link_qual *qual, u8 vgc_level)
1027 {
1028         if (qual->vgc_level != vgc_level) {
1029                 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
1030                 qual->vgc_level = vgc_level;
1031                 qual->vgc_level_reg = vgc_level;
1032         }
1033 }
1034
1035 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1036                                 struct link_qual *qual)
1037 {
1038         rt61pci_set_vgc(rt2x00dev, qual, 0x20);
1039 }
1040
1041 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1042                                struct link_qual *qual, const u32 count)
1043 {
1044         u8 up_bound;
1045         u8 low_bound;
1046
1047         /*
1048          * Determine r17 bounds.
1049          */
1050         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1051                 low_bound = 0x28;
1052                 up_bound = 0x48;
1053                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) {
1054                         low_bound += 0x10;
1055                         up_bound += 0x10;
1056                 }
1057         } else {
1058                 low_bound = 0x20;
1059                 up_bound = 0x40;
1060                 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags)) {
1061                         low_bound += 0x10;
1062                         up_bound += 0x10;
1063                 }
1064         }
1065
1066         /*
1067          * If we are not associated, we should go straight to the
1068          * dynamic CCA tuning.
1069          */
1070         if (!rt2x00dev->intf_associated)
1071                 goto dynamic_cca_tune;
1072
1073         /*
1074          * Special big-R17 for very short distance
1075          */
1076         if (qual->rssi >= -35) {
1077                 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
1078                 return;
1079         }
1080
1081         /*
1082          * Special big-R17 for short distance
1083          */
1084         if (qual->rssi >= -58) {
1085                 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1086                 return;
1087         }
1088
1089         /*
1090          * Special big-R17 for middle-short distance
1091          */
1092         if (qual->rssi >= -66) {
1093                 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1094                 return;
1095         }
1096
1097         /*
1098          * Special mid-R17 for middle distance
1099          */
1100         if (qual->rssi >= -74) {
1101                 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1102                 return;
1103         }
1104
1105         /*
1106          * Special case: Change up_bound based on the rssi.
1107          * Lower up_bound when rssi is weaker then -74 dBm.
1108          */
1109         up_bound -= 2 * (-74 - qual->rssi);
1110         if (low_bound > up_bound)
1111                 up_bound = low_bound;
1112
1113         if (qual->vgc_level > up_bound) {
1114                 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1115                 return;
1116         }
1117
1118 dynamic_cca_tune:
1119
1120         /*
1121          * r17 does not yet exceed upper limit, continue and base
1122          * the r17 tuning on the false CCA count.
1123          */
1124         if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1125                 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1126         else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1127                 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
1128 }
1129
1130 /*
1131  * Queue handlers.
1132  */
1133 static void rt61pci_start_queue(struct data_queue *queue)
1134 {
1135         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1136         u32 reg;
1137
1138         switch (queue->qid) {
1139         case QID_RX:
1140                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1141                 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1142                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1143                 break;
1144         case QID_BEACON:
1145                 /*
1146                  * Allow the tbtt tasklet to be scheduled.
1147                  */
1148                 tasklet_enable(&rt2x00dev->tbtt_tasklet);
1149
1150                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1151                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1152                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1153                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1154                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1155                 break;
1156         default:
1157                 break;
1158         }
1159 }
1160
1161 static void rt61pci_kick_queue(struct data_queue *queue)
1162 {
1163         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1164         u32 reg;
1165
1166         switch (queue->qid) {
1167         case QID_AC_VO:
1168                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1169                 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1170                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1171                 break;
1172         case QID_AC_VI:
1173                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1174                 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1175                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1176                 break;
1177         case QID_AC_BE:
1178                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1179                 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1180                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1181                 break;
1182         case QID_AC_BK:
1183                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1184                 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1185                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1186                 break;
1187         default:
1188                 break;
1189         }
1190 }
1191
1192 static void rt61pci_stop_queue(struct data_queue *queue)
1193 {
1194         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1195         u32 reg;
1196
1197         switch (queue->qid) {
1198         case QID_AC_VO:
1199                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1200                 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1201                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1202                 break;
1203         case QID_AC_VI:
1204                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1205                 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1206                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1207                 break;
1208         case QID_AC_BE:
1209                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1210                 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1211                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1212                 break;
1213         case QID_AC_BK:
1214                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1215                 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1216                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1217                 break;
1218         case QID_RX:
1219                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1220                 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1221                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1222                 break;
1223         case QID_BEACON:
1224                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1225                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1226                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1227                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1228                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1229
1230                 /*
1231                  * Wait for possibly running tbtt tasklets.
1232                  */
1233                 tasklet_disable(&rt2x00dev->tbtt_tasklet);
1234                 break;
1235         default:
1236                 break;
1237         }
1238 }
1239
1240 /*
1241  * Firmware functions
1242  */
1243 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1244 {
1245         u16 chip;
1246         char *fw_name;
1247
1248         pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1249         switch (chip) {
1250         case RT2561_PCI_ID:
1251                 fw_name = FIRMWARE_RT2561;
1252                 break;
1253         case RT2561s_PCI_ID:
1254                 fw_name = FIRMWARE_RT2561s;
1255                 break;
1256         case RT2661_PCI_ID:
1257                 fw_name = FIRMWARE_RT2661;
1258                 break;
1259         default:
1260                 fw_name = NULL;
1261                 break;
1262         }
1263
1264         return fw_name;
1265 }
1266
1267 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1268                                   const u8 *data, const size_t len)
1269 {
1270         u16 fw_crc;
1271         u16 crc;
1272
1273         /*
1274          * Only support 8kb firmware files.
1275          */
1276         if (len != 8192)
1277                 return FW_BAD_LENGTH;
1278
1279         /*
1280          * The last 2 bytes in the firmware array are the crc checksum itself.
1281          * This means that we should never pass those 2 bytes to the crc
1282          * algorithm.
1283          */
1284         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1285
1286         /*
1287          * Use the crc itu-t algorithm.
1288          */
1289         crc = crc_itu_t(0, data, len - 2);
1290         crc = crc_itu_t_byte(crc, 0);
1291         crc = crc_itu_t_byte(crc, 0);
1292
1293         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1294 }
1295
1296 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1297                                  const u8 *data, const size_t len)
1298 {
1299         int i;
1300         u32 reg;
1301
1302         /*
1303          * Wait for stable hardware.
1304          */
1305         for (i = 0; i < 100; i++) {
1306                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1307                 if (reg)
1308                         break;
1309                 msleep(1);
1310         }
1311
1312         if (!reg) {
1313                 ERROR(rt2x00dev, "Unstable hardware.\n");
1314                 return -EBUSY;
1315         }
1316
1317         /*
1318          * Prepare MCU and mailbox for firmware loading.
1319          */
1320         reg = 0;
1321         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1322         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1323         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1324         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1325         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1326
1327         /*
1328          * Write firmware to device.
1329          */
1330         reg = 0;
1331         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1332         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1333         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1334
1335         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1336                                       data, len);
1337
1338         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1339         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1340
1341         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1342         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1343
1344         for (i = 0; i < 100; i++) {
1345                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1346                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1347                         break;
1348                 msleep(1);
1349         }
1350
1351         if (i == 100) {
1352                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1353                 return -EBUSY;
1354         }
1355
1356         /*
1357          * Hardware needs another millisecond before it is ready.
1358          */
1359         msleep(1);
1360
1361         /*
1362          * Reset MAC and BBP registers.
1363          */
1364         reg = 0;
1365         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1366         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1367         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1368
1369         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1370         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1371         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1372         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1373
1374         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1375         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1376         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1377
1378         return 0;
1379 }
1380
1381 /*
1382  * Initialization functions.
1383  */
1384 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1385 {
1386         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1387         u32 word;
1388
1389         if (entry->queue->qid == QID_RX) {
1390                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1391
1392                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1393         } else {
1394                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1395
1396                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1397                         rt2x00_get_field32(word, TXD_W0_VALID));
1398         }
1399 }
1400
1401 static void rt61pci_clear_entry(struct queue_entry *entry)
1402 {
1403         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1404         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1405         u32 word;
1406
1407         if (entry->queue->qid == QID_RX) {
1408                 rt2x00_desc_read(entry_priv->desc, 5, &word);
1409                 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1410                                    skbdesc->skb_dma);
1411                 rt2x00_desc_write(entry_priv->desc, 5, word);
1412
1413                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1414                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1415                 rt2x00_desc_write(entry_priv->desc, 0, word);
1416         } else {
1417                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1418                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1419                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1420                 rt2x00_desc_write(entry_priv->desc, 0, word);
1421         }
1422 }
1423
1424 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1425 {
1426         struct queue_entry_priv_pci *entry_priv;
1427         u32 reg;
1428
1429         /*
1430          * Initialize registers.
1431          */
1432         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1433         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1434                            rt2x00dev->tx[0].limit);
1435         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1436                            rt2x00dev->tx[1].limit);
1437         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1438                            rt2x00dev->tx[2].limit);
1439         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1440                            rt2x00dev->tx[3].limit);
1441         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1442
1443         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1444         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1445                            rt2x00dev->tx[0].desc_size / 4);
1446         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1447
1448         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1449         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1450         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1451                            entry_priv->desc_dma);
1452         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1453
1454         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1455         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1456         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1457                            entry_priv->desc_dma);
1458         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1459
1460         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1461         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1462         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1463                            entry_priv->desc_dma);
1464         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1465
1466         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1467         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1468         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1469                            entry_priv->desc_dma);
1470         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1471
1472         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1473         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1474         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1475                            rt2x00dev->rx->desc_size / 4);
1476         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1477         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1478
1479         entry_priv = rt2x00dev->rx->entries[0].priv_data;
1480         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1481         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1482                            entry_priv->desc_dma);
1483         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1484
1485         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1486         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1487         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1488         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1489         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1490         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1491
1492         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1493         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1494         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1495         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1496         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1497         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1498
1499         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1500         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1501         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1502
1503         return 0;
1504 }
1505
1506 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1507 {
1508         u32 reg;
1509
1510         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1511         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1512         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1513         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1514         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1515
1516         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1517         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1518         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1519         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1520         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1521         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1522         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1523         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1524         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1525         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1526
1527         /*
1528          * CCK TXD BBP registers
1529          */
1530         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1531         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1532         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1533         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1534         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1535         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1536         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1537         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1538         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1539         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1540
1541         /*
1542          * OFDM TXD BBP registers
1543          */
1544         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1545         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1546         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1547         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1548         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1549         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1550         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1551         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1552
1553         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1554         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1555         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1556         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1557         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1558         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1559
1560         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1561         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1562         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1563         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1564         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1565         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1566
1567         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1568         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1569         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1570         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1571         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1572         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1573         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1574         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1575
1576         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1577
1578         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1579
1580         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1581         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1582         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1583
1584         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1585
1586         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1587                 return -EBUSY;
1588
1589         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1590
1591         /*
1592          * Invalidate all Shared Keys (SEC_CSR0),
1593          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1594          */
1595         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1596         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1597         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1598
1599         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1600         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1601         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1602         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1603
1604         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1605
1606         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1607
1608         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1609
1610         /*
1611          * Clear all beacons
1612          * For the Beacon base registers we only need to clear
1613          * the first byte since that byte contains the VALID and OWNER
1614          * bits which (when set to 0) will invalidate the entire beacon.
1615          */
1616         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1617         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1618         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1619         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1620
1621         /*
1622          * We must clear the error counters.
1623          * These registers are cleared on read,
1624          * so we may pass a useless variable to store the value.
1625          */
1626         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1627         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1628         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1629
1630         /*
1631          * Reset MAC and BBP registers.
1632          */
1633         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1634         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1635         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1636         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1637
1638         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1639         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1640         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1641         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1642
1643         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1644         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1645         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1646
1647         return 0;
1648 }
1649
1650 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1651 {
1652         unsigned int i;
1653         u8 value;
1654
1655         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1656                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1657                 if ((value != 0xff) && (value != 0x00))
1658                         return 0;
1659                 udelay(REGISTER_BUSY_DELAY);
1660         }
1661
1662         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1663         return -EACCES;
1664 }
1665
1666 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1667 {
1668         unsigned int i;
1669         u16 eeprom;
1670         u8 reg_id;
1671         u8 value;
1672
1673         if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1674                 return -EACCES;
1675
1676         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1677         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1678         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1679         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1680         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1681         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1682         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1683         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1684         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1685         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1686         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1687         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1688         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1689         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1690         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1691         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1692         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1693         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1694         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1695         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1696         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1697         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1698         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1699         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1700
1701         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1702                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1703
1704                 if (eeprom != 0xffff && eeprom != 0x0000) {
1705                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1706                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1707                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1708                 }
1709         }
1710
1711         return 0;
1712 }
1713
1714 /*
1715  * Device state switch handlers.
1716  */
1717 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1718                                enum dev_state state)
1719 {
1720         int mask = (state == STATE_RADIO_IRQ_OFF);
1721         u32 reg;
1722         unsigned long flags;
1723
1724         /*
1725          * When interrupts are being enabled, the interrupt registers
1726          * should clear the register to assure a clean state.
1727          */
1728         if (state == STATE_RADIO_IRQ_ON) {
1729                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1730                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1731
1732                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1733                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1734
1735                 /*
1736                  * Enable tasklets.
1737                  */
1738                 tasklet_enable(&rt2x00dev->txstatus_tasklet);
1739                 tasklet_enable(&rt2x00dev->rxdone_tasklet);
1740                 tasklet_enable(&rt2x00dev->autowake_tasklet);
1741         }
1742
1743         /*
1744          * Only toggle the interrupts bits we are going to use.
1745          * Non-checked interrupt bits are disabled by default.
1746          */
1747         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1748
1749         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1750         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1751         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1752         rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask);
1753         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1754         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1755         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1756
1757         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1758         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1759         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1760         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1761         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1762         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1763         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1764         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1765         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1766         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask);
1767         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1768
1769         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1770
1771         if (state == STATE_RADIO_IRQ_OFF) {
1772                 /*
1773                  * Ensure that all tasklets are finished.
1774                  */
1775                 tasklet_disable(&rt2x00dev->txstatus_tasklet);
1776                 tasklet_disable(&rt2x00dev->rxdone_tasklet);
1777                 tasklet_disable(&rt2x00dev->autowake_tasklet);
1778         }
1779 }
1780
1781 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1782 {
1783         u32 reg;
1784
1785         /*
1786          * Initialize all registers.
1787          */
1788         if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1789                      rt61pci_init_registers(rt2x00dev) ||
1790                      rt61pci_init_bbp(rt2x00dev)))
1791                 return -EIO;
1792
1793         /*
1794          * Enable RX.
1795          */
1796         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1797         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1798         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1799
1800         return 0;
1801 }
1802
1803 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1804 {
1805         /*
1806          * Disable power
1807          */
1808         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1809 }
1810
1811 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1812 {
1813         u32 reg, reg2;
1814         unsigned int i;
1815         char put_to_sleep;
1816
1817         put_to_sleep = (state != STATE_AWAKE);
1818
1819         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1820         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1821         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1822         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1823
1824         /*
1825          * Device is not guaranteed to be in the requested state yet.
1826          * We must wait until the register indicates that the
1827          * device has entered the correct state.
1828          */
1829         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1830                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg2);
1831                 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1832                 if (state == !put_to_sleep)
1833                         return 0;
1834                 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1835                 msleep(10);
1836         }
1837
1838         return -EBUSY;
1839 }
1840
1841 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1842                                     enum dev_state state)
1843 {
1844         int retval = 0;
1845
1846         switch (state) {
1847         case STATE_RADIO_ON:
1848                 retval = rt61pci_enable_radio(rt2x00dev);
1849                 break;
1850         case STATE_RADIO_OFF:
1851                 rt61pci_disable_radio(rt2x00dev);
1852                 break;
1853         case STATE_RADIO_IRQ_ON:
1854         case STATE_RADIO_IRQ_OFF:
1855                 rt61pci_toggle_irq(rt2x00dev, state);
1856                 break;
1857         case STATE_DEEP_SLEEP:
1858         case STATE_SLEEP:
1859         case STATE_STANDBY:
1860         case STATE_AWAKE:
1861                 retval = rt61pci_set_state(rt2x00dev, state);
1862                 break;
1863         default:
1864                 retval = -ENOTSUPP;
1865                 break;
1866         }
1867
1868         if (unlikely(retval))
1869                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1870                       state, retval);
1871
1872         return retval;
1873 }
1874
1875 /*
1876  * TX descriptor initialization
1877  */
1878 static void rt61pci_write_tx_desc(struct queue_entry *entry,
1879                                   struct txentry_desc *txdesc)
1880 {
1881         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1882         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1883         __le32 *txd = entry_priv->desc;
1884         u32 word;
1885
1886         /*
1887          * Start writing the descriptor words.
1888          */
1889         rt2x00_desc_read(txd, 1, &word);
1890         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1891         rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1892         rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1893         rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1894         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1895         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1896                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1897         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1898         rt2x00_desc_write(txd, 1, word);
1899
1900         rt2x00_desc_read(txd, 2, &word);
1901         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1902         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1903         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1904                            txdesc->u.plcp.length_low);
1905         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1906                            txdesc->u.plcp.length_high);
1907         rt2x00_desc_write(txd, 2, word);
1908
1909         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1910                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1911                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1912         }
1913
1914         rt2x00_desc_read(txd, 5, &word);
1915         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1916         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1917                            skbdesc->entry->entry_idx);
1918         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1919                            TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1920         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1921         rt2x00_desc_write(txd, 5, word);
1922
1923         if (entry->queue->qid != QID_BEACON) {
1924                 rt2x00_desc_read(txd, 6, &word);
1925                 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1926                                    skbdesc->skb_dma);
1927                 rt2x00_desc_write(txd, 6, word);
1928
1929                 rt2x00_desc_read(txd, 11, &word);
1930                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1931                                    txdesc->length);
1932                 rt2x00_desc_write(txd, 11, word);
1933         }
1934
1935         /*
1936          * Writing TXD word 0 must the last to prevent a race condition with
1937          * the device, whereby the device may take hold of the TXD before we
1938          * finished updating it.
1939          */
1940         rt2x00_desc_read(txd, 0, &word);
1941         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1942         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1943         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1944                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1945         rt2x00_set_field32(&word, TXD_W0_ACK,
1946                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1947         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1948                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1949         rt2x00_set_field32(&word, TXD_W0_OFDM,
1950                            (txdesc->rate_mode == RATE_MODE_OFDM));
1951         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1952         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1953                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1954         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1955                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1956         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1957                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1958         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1959         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1960         rt2x00_set_field32(&word, TXD_W0_BURST,
1961                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1962         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1963         rt2x00_desc_write(txd, 0, word);
1964
1965         /*
1966          * Register descriptor details in skb frame descriptor.
1967          */
1968         skbdesc->desc = txd;
1969         skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE :
1970                             TXD_DESC_SIZE;
1971 }
1972
1973 /*
1974  * TX data initialization
1975  */
1976 static void rt61pci_write_beacon(struct queue_entry *entry,
1977                                  struct txentry_desc *txdesc)
1978 {
1979         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1980         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1981         unsigned int beacon_base;
1982         unsigned int padding_len;
1983         u32 orig_reg, reg;
1984
1985         /*
1986          * Disable beaconing while we are reloading the beacon data,
1987          * otherwise we might be sending out invalid data.
1988          */
1989         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1990         orig_reg = reg;
1991         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1992         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1993
1994         /*
1995          * Write the TX descriptor for the beacon.
1996          */
1997         rt61pci_write_tx_desc(entry, txdesc);
1998
1999         /*
2000          * Dump beacon to userspace through debugfs.
2001          */
2002         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
2003
2004         /*
2005          * Write entire beacon with descriptor and padding to register.
2006          */
2007         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
2008         if (padding_len && skb_pad(entry->skb, padding_len)) {
2009                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
2010                 /* skb freed by skb_pad() on failure */
2011                 entry->skb = NULL;
2012                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
2013                 return;
2014         }
2015
2016         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2017         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2018                                       entry_priv->desc, TXINFO_SIZE);
2019         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
2020                                       entry->skb->data,
2021                                       entry->skb->len + padding_len);
2022
2023         /*
2024          * Enable beaconing again.
2025          *
2026          * For Wi-Fi faily generated beacons between participating
2027          * stations. Set TBTT phase adaptive adjustment step to 8us.
2028          */
2029         rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
2030
2031         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2032         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2033
2034         /*
2035          * Clean up beacon skb.
2036          */
2037         dev_kfree_skb_any(entry->skb);
2038         entry->skb = NULL;
2039 }
2040
2041 static void rt61pci_clear_beacon(struct queue_entry *entry)
2042 {
2043         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2044         u32 reg;
2045
2046         /*
2047          * Disable beaconing while we are reloading the beacon data,
2048          * otherwise we might be sending out invalid data.
2049          */
2050         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2051         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2052         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2053
2054         /*
2055          * Clear beacon.
2056          */
2057         rt2x00pci_register_write(rt2x00dev,
2058                                  HW_BEACON_OFFSET(entry->entry_idx), 0);
2059
2060         /*
2061          * Enable beaconing again.
2062          */
2063         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2064         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2065 }
2066
2067 /*
2068  * RX control handlers
2069  */
2070 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
2071 {
2072         u8 offset = rt2x00dev->lna_gain;
2073         u8 lna;
2074
2075         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
2076         switch (lna) {
2077         case 3:
2078                 offset += 90;
2079                 break;
2080         case 2:
2081                 offset += 74;
2082                 break;
2083         case 1:
2084                 offset += 64;
2085                 break;
2086         default:
2087                 return 0;
2088         }
2089
2090         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
2091                 if (lna == 3 || lna == 2)
2092                         offset += 10;
2093         }
2094
2095         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
2096 }
2097
2098 static void rt61pci_fill_rxdone(struct queue_entry *entry,
2099                                 struct rxdone_entry_desc *rxdesc)
2100 {
2101         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2102         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
2103         u32 word0;
2104         u32 word1;
2105
2106         rt2x00_desc_read(entry_priv->desc, 0, &word0);
2107         rt2x00_desc_read(entry_priv->desc, 1, &word1);
2108
2109         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
2110                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2111
2112         rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
2113         rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
2114
2115         if (rxdesc->cipher != CIPHER_NONE) {
2116                 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
2117                 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
2118                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
2119
2120                 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
2121                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
2122
2123                 /*
2124                  * Hardware has stripped IV/EIV data from 802.11 frame during
2125                  * decryption. It has provided the data separately but rt2x00lib
2126                  * should decide if it should be reinserted.
2127                  */
2128                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2129
2130                 /*
2131                  * The hardware has already checked the Michael Mic and has
2132                  * stripped it from the frame. Signal this to mac80211.
2133                  */
2134                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2135
2136                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2137                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2138                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2139                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2140         }
2141
2142         /*
2143          * Obtain the status about this packet.
2144          * When frame was received with an OFDM bitrate,
2145          * the signal is the PLCP value. If it was received with
2146          * a CCK bitrate the signal is the rate in 100kbit/s.
2147          */
2148         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
2149         rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2150         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2151
2152         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2153                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2154         else
2155                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2156         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2157                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2158 }
2159
2160 /*
2161  * Interrupt functions.
2162  */
2163 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2164 {
2165         struct data_queue *queue;
2166         struct queue_entry *entry;
2167         struct queue_entry *entry_done;
2168         struct queue_entry_priv_pci *entry_priv;
2169         struct txdone_entry_desc txdesc;
2170         u32 word;
2171         u32 reg;
2172         int type;
2173         int index;
2174         int i;
2175
2176         /*
2177          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2178          * at most X times and also stop processing once the TX_STA_FIFO_VALID
2179          * flag is not set anymore.
2180          *
2181          * The legacy drivers use X=TX_RING_SIZE but state in a comment
2182          * that the TX_STA_FIFO stack has a size of 16. We stick to our
2183          * tx ring size for now.
2184          */
2185         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
2186                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2187                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2188                         break;
2189
2190                 /*
2191                  * Skip this entry when it contains an invalid
2192                  * queue identication number.
2193                  */
2194                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2195                 queue = rt2x00queue_get_tx_queue(rt2x00dev, type);
2196                 if (unlikely(!queue))
2197                         continue;
2198
2199                 /*
2200                  * Skip this entry when it contains an invalid
2201                  * index number.
2202                  */
2203                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2204                 if (unlikely(index >= queue->limit))
2205                         continue;
2206
2207                 entry = &queue->entries[index];
2208                 entry_priv = entry->priv_data;
2209                 rt2x00_desc_read(entry_priv->desc, 0, &word);
2210
2211                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2212                     !rt2x00_get_field32(word, TXD_W0_VALID))
2213                         return;
2214
2215                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2216                 while (entry != entry_done) {
2217                         /* Catch up.
2218                          * Just report any entries we missed as failed.
2219                          */
2220                         WARNING(rt2x00dev,
2221                                 "TX status report missed for entry %d\n",
2222                                 entry_done->entry_idx);
2223
2224                         rt2x00lib_txdone_noinfo(entry_done, TXDONE_UNKNOWN);
2225                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2226                 }
2227
2228                 /*
2229                  * Obtain the status about this packet.
2230                  */
2231                 txdesc.flags = 0;
2232                 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2233                 case 0: /* Success, maybe with retry */
2234                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2235                         break;
2236                 case 6: /* Failure, excessive retries */
2237                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2238                         /* Don't break, this is a failed frame! */
2239                 default: /* Failure */
2240                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
2241                 }
2242                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2243
2244                 /*
2245                  * the frame was retried at least once
2246                  * -> hw used fallback rates
2247                  */
2248                 if (txdesc.retry)
2249                         __set_bit(TXDONE_FALLBACK, &txdesc.flags);
2250
2251                 rt2x00lib_txdone(entry, &txdesc);
2252         }
2253 }
2254
2255 static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2256 {
2257         struct ieee80211_conf conf = { .flags = 0 };
2258         struct rt2x00lib_conf libconf = { .conf = &conf };
2259
2260         rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2261 }
2262
2263 static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
2264                                             struct rt2x00_field32 irq_field)
2265 {
2266         u32 reg;
2267
2268         /*
2269          * Enable a single interrupt. The interrupt mask register
2270          * access needs locking.
2271          */
2272         spin_lock_irq(&rt2x00dev->irqmask_lock);
2273
2274         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2275         rt2x00_set_field32(&reg, irq_field, 0);
2276         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
2277
2278         spin_unlock_irq(&rt2x00dev->irqmask_lock);
2279 }
2280
2281 static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev,
2282                                          struct rt2x00_field32 irq_field)
2283 {
2284         u32 reg;
2285
2286         /*
2287          * Enable a single MCU interrupt. The interrupt mask register
2288          * access needs locking.
2289          */
2290         spin_lock_irq(&rt2x00dev->irqmask_lock);
2291
2292         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2293         rt2x00_set_field32(&reg, irq_field, 0);
2294         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2295
2296         spin_unlock_irq(&rt2x00dev->irqmask_lock);
2297 }
2298
2299 static void rt61pci_txstatus_tasklet(unsigned long data)
2300 {
2301         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2302         rt61pci_txdone(rt2x00dev);
2303         rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE);
2304 }
2305
2306 static void rt61pci_tbtt_tasklet(unsigned long data)
2307 {
2308         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2309         rt2x00lib_beacondone(rt2x00dev);
2310         rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE);
2311 }
2312
2313 static void rt61pci_rxdone_tasklet(unsigned long data)
2314 {
2315         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2316         if (rt2x00pci_rxdone(rt2x00dev))
2317                 rt2x00pci_rxdone(rt2x00dev);
2318         else
2319                 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE);
2320 }
2321
2322 static void rt61pci_autowake_tasklet(unsigned long data)
2323 {
2324         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2325         rt61pci_wakeup(rt2x00dev);
2326         rt2x00pci_register_write(rt2x00dev,
2327                                  M2H_CMD_DONE_CSR, 0xffffffff);
2328         rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP);
2329 }
2330
2331 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2332 {
2333         struct rt2x00_dev *rt2x00dev = dev_instance;
2334         u32 reg_mcu, mask_mcu;
2335         u32 reg, mask;
2336
2337         /*
2338          * Get the interrupt sources & saved to local variable.
2339          * Write register value back to clear pending interrupts.
2340          */
2341         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2342         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2343
2344         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2345         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2346
2347         if (!reg && !reg_mcu)
2348                 return IRQ_NONE;
2349
2350         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2351                 return IRQ_HANDLED;
2352
2353         /*
2354          * Schedule tasklets for interrupt handling.
2355          */
2356         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2357                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2358
2359         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2360                 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
2361
2362         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2363                 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
2364
2365         if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2366                 tasklet_schedule(&rt2x00dev->autowake_tasklet);
2367
2368         /*
2369          * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
2370          * for interrupts and interrupt masks we can just use the value of
2371          * INT_SOURCE_CSR to create the interrupt mask.
2372          */
2373         mask = reg;
2374         mask_mcu = reg_mcu;
2375
2376         /*
2377          * Disable all interrupts for which a tasklet was scheduled right now,
2378          * the tasklet will reenable the appropriate interrupts.
2379          */
2380         spin_lock(&rt2x00dev->irqmask_lock);
2381
2382         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2383         reg |= mask;
2384         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
2385
2386         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2387         reg |= mask_mcu;
2388         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2389
2390         spin_unlock(&rt2x00dev->irqmask_lock);
2391
2392         return IRQ_HANDLED;
2393 }
2394
2395 /*
2396  * Device probe functions.
2397  */
2398 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2399 {
2400         struct eeprom_93cx6 eeprom;
2401         u32 reg;
2402         u16 word;
2403         u8 *mac;
2404         s8 value;
2405
2406         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2407
2408         eeprom.data = rt2x00dev;
2409         eeprom.register_read = rt61pci_eepromregister_read;
2410         eeprom.register_write = rt61pci_eepromregister_write;
2411         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2412             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2413         eeprom.reg_data_in = 0;
2414         eeprom.reg_data_out = 0;
2415         eeprom.reg_data_clock = 0;
2416         eeprom.reg_chip_select = 0;
2417
2418         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2419                                EEPROM_SIZE / sizeof(u16));
2420
2421         /*
2422          * Start validation of the data that has been read.
2423          */
2424         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2425         if (!is_valid_ether_addr(mac)) {
2426                 random_ether_addr(mac);
2427                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2428         }
2429
2430         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2431         if (word == 0xffff) {
2432                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2433                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2434                                    ANTENNA_B);
2435                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2436                                    ANTENNA_B);
2437                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2438                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2439                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2440                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2441                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2442                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2443         }
2444
2445         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2446         if (word == 0xffff) {
2447                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2448                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2449                 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2450                 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
2451                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2452                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2453                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2454                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2455                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2456         }
2457
2458         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2459         if (word == 0xffff) {
2460                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2461                                    LED_MODE_DEFAULT);
2462                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2463                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2464         }
2465
2466         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2467         if (word == 0xffff) {
2468                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2469                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2470                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2471                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2472         }
2473
2474         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2475         if (word == 0xffff) {
2476                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2477                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2478                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2479                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2480         } else {
2481                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2482                 if (value < -10 || value > 10)
2483                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2484                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2485                 if (value < -10 || value > 10)
2486                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2487                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2488         }
2489
2490         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2491         if (word == 0xffff) {
2492                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2493                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2494                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2495                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2496         } else {
2497                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2498                 if (value < -10 || value > 10)
2499                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2500                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2501                 if (value < -10 || value > 10)
2502                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2503                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2504         }
2505
2506         return 0;
2507 }
2508
2509 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2510 {
2511         u32 reg;
2512         u16 value;
2513         u16 eeprom;
2514
2515         /*
2516          * Read EEPROM word for configuration.
2517          */
2518         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2519
2520         /*
2521          * Identify RF chipset.
2522          */
2523         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2524         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2525         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2526                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2527
2528         if (!rt2x00_rf(rt2x00dev, RF5225) &&
2529             !rt2x00_rf(rt2x00dev, RF5325) &&
2530             !rt2x00_rf(rt2x00dev, RF2527) &&
2531             !rt2x00_rf(rt2x00dev, RF2529)) {
2532                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2533                 return -ENODEV;
2534         }
2535
2536         /*
2537          * Determine number of antennas.
2538          */
2539         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2540                 __set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags);
2541
2542         /*
2543          * Identify default antenna configuration.
2544          */
2545         rt2x00dev->default_ant.tx =
2546             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2547         rt2x00dev->default_ant.rx =
2548             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2549
2550         /*
2551          * Read the Frame type.
2552          */
2553         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2554                 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags);
2555
2556         /*
2557          * Detect if this device has a hardware controlled radio.
2558          */
2559         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2560                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
2561
2562         /*
2563          * Read frequency offset and RF programming sequence.
2564          */
2565         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2566         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2567                 __set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags);
2568
2569         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2570
2571         /*
2572          * Read external LNA informations.
2573          */
2574         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2575
2576         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2577                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
2578         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2579                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
2580
2581         /*
2582          * When working with a RF2529 chip without double antenna,
2583          * the antenna settings should be gathered from the NIC
2584          * eeprom word.
2585          */
2586         if (rt2x00_rf(rt2x00dev, RF2529) &&
2587             !test_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags)) {
2588                 rt2x00dev->default_ant.rx =
2589                     ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2590                 rt2x00dev->default_ant.tx =
2591                     ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
2592
2593                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2594                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2595                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2596                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2597         }
2598
2599         /*
2600          * Store led settings, for correct led behaviour.
2601          * If the eeprom value is invalid,
2602          * switch to default led mode.
2603          */
2604 #ifdef CONFIG_RT2X00_LIB_LEDS
2605         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2606         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2607
2608         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2609         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2610         if (value == LED_MODE_SIGNAL_STRENGTH)
2611                 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2612                                  LED_TYPE_QUALITY);
2613
2614         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2615         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2616                            rt2x00_get_field16(eeprom,
2617                                               EEPROM_LED_POLARITY_GPIO_0));
2618         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2619                            rt2x00_get_field16(eeprom,
2620                                               EEPROM_LED_POLARITY_GPIO_1));
2621         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2622                            rt2x00_get_field16(eeprom,
2623                                               EEPROM_LED_POLARITY_GPIO_2));
2624         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2625                            rt2x00_get_field16(eeprom,
2626                                               EEPROM_LED_POLARITY_GPIO_3));
2627         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2628                            rt2x00_get_field16(eeprom,
2629                                               EEPROM_LED_POLARITY_GPIO_4));
2630         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2631                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2632         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2633                            rt2x00_get_field16(eeprom,
2634                                               EEPROM_LED_POLARITY_RDY_G));
2635         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2636                            rt2x00_get_field16(eeprom,
2637                                               EEPROM_LED_POLARITY_RDY_A));
2638 #endif /* CONFIG_RT2X00_LIB_LEDS */
2639
2640         return 0;
2641 }
2642
2643 /*
2644  * RF value list for RF5225 & RF5325
2645  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2646  */
2647 static const struct rf_channel rf_vals_noseq[] = {
2648         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2649         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2650         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2651         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2652         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2653         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2654         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2655         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2656         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2657         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2658         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2659         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2660         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2661         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2662
2663         /* 802.11 UNI / HyperLan 2 */
2664         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2665         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2666         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2667         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2668         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2669         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2670         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2671         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2672
2673         /* 802.11 HyperLan 2 */
2674         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2675         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2676         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2677         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2678         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2679         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2680         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2681         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2682         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2683         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2684
2685         /* 802.11 UNII */
2686         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2687         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2688         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2689         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2690         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2691         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2692
2693         /* MMAC(Japan)J52 ch 34,38,42,46 */
2694         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2695         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2696         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2697         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2698 };
2699
2700 /*
2701  * RF value list for RF5225 & RF5325
2702  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2703  */
2704 static const struct rf_channel rf_vals_seq[] = {
2705         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2706         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2707         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2708         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2709         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2710         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2711         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2712         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2713         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2714         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2715         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2716         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2717         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2718         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2719
2720         /* 802.11 UNI / HyperLan 2 */
2721         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2722         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2723         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2724         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2725         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2726         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2727         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2728         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2729
2730         /* 802.11 HyperLan 2 */
2731         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2732         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2733         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2734         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2735         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2736         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2737         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2738         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2739         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2740         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2741
2742         /* 802.11 UNII */
2743         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2744         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2745         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2746         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2747         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2748         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2749
2750         /* MMAC(Japan)J52 ch 34,38,42,46 */
2751         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2752         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2753         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2754         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2755 };
2756
2757 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2758 {
2759         struct hw_mode_spec *spec = &rt2x00dev->spec;
2760         struct channel_info *info;
2761         char *tx_power;
2762         unsigned int i;
2763
2764         /*
2765          * Disable powersaving as default.
2766          */
2767         rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2768
2769         /*
2770          * Initialize all hw fields.
2771          */
2772         rt2x00dev->hw->flags =
2773             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2774             IEEE80211_HW_SIGNAL_DBM |
2775             IEEE80211_HW_SUPPORTS_PS |
2776             IEEE80211_HW_PS_NULLFUNC_STACK;
2777
2778         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2779         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2780                                 rt2x00_eeprom_addr(rt2x00dev,
2781                                                    EEPROM_MAC_ADDR_0));
2782
2783         /*
2784          * As rt61 has a global fallback table we cannot specify
2785          * more then one tx rate per frame but since the hw will
2786          * try several rates (based on the fallback table) we should
2787          * initialize max_report_rates to the maximum number of rates
2788          * we are going to try. Otherwise mac80211 will truncate our
2789          * reported tx rates and the rc algortihm will end up with
2790          * incorrect data.
2791          */
2792         rt2x00dev->hw->max_rates = 1;
2793         rt2x00dev->hw->max_report_rates = 7;
2794         rt2x00dev->hw->max_rate_tries = 1;
2795
2796         /*
2797          * Initialize hw_mode information.
2798          */
2799         spec->supported_bands = SUPPORT_BAND_2GHZ;
2800         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2801
2802         if (!test_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags)) {
2803                 spec->num_channels = 14;
2804                 spec->channels = rf_vals_noseq;
2805         } else {
2806                 spec->num_channels = 14;
2807                 spec->channels = rf_vals_seq;
2808         }
2809
2810         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
2811                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2812                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2813         }
2814
2815         /*
2816          * Create channel information array
2817          */
2818         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2819         if (!info)
2820                 return -ENOMEM;
2821
2822         spec->channels_info = info;
2823
2824         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2825         for (i = 0; i < 14; i++) {
2826                 info[i].max_power = MAX_TXPOWER;
2827                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2828         }
2829
2830         if (spec->num_channels > 14) {
2831                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2832                 for (i = 14; i < spec->num_channels; i++) {
2833                         info[i].max_power = MAX_TXPOWER;
2834                         info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2835                 }
2836         }
2837
2838         return 0;
2839 }
2840
2841 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2842 {
2843         int retval;
2844
2845         /*
2846          * Disable power saving.
2847          */
2848         rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2849
2850         /*
2851          * Allocate eeprom data.
2852          */
2853         retval = rt61pci_validate_eeprom(rt2x00dev);
2854         if (retval)
2855                 return retval;
2856
2857         retval = rt61pci_init_eeprom(rt2x00dev);
2858         if (retval)
2859                 return retval;
2860
2861         /*
2862          * Initialize hw specifications.
2863          */
2864         retval = rt61pci_probe_hw_mode(rt2x00dev);
2865         if (retval)
2866                 return retval;
2867
2868         /*
2869          * This device has multiple filters for control frames,
2870          * but has no a separate filter for PS Poll frames.
2871          */
2872         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
2873
2874         /*
2875          * This device requires firmware and DMA mapped skbs.
2876          */
2877         __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
2878         __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
2879         if (!modparam_nohwcrypt)
2880                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
2881         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
2882
2883         /*
2884          * Set the rssi offset.
2885          */
2886         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2887
2888         return 0;
2889 }
2890
2891 /*
2892  * IEEE80211 stack callback functions.
2893  */
2894 static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2895                            const struct ieee80211_tx_queue_params *params)
2896 {
2897         struct rt2x00_dev *rt2x00dev = hw->priv;
2898         struct data_queue *queue;
2899         struct rt2x00_field32 field;
2900         int retval;
2901         u32 reg;
2902         u32 offset;
2903
2904         /*
2905          * First pass the configuration through rt2x00lib, that will
2906          * update the queue settings and validate the input. After that
2907          * we are free to update the registers based on the value
2908          * in the queue parameter.
2909          */
2910         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2911         if (retval)
2912                 return retval;
2913
2914         /*
2915          * We only need to perform additional register initialization
2916          * for WMM queues.
2917          */
2918         if (queue_idx >= 4)
2919                 return 0;
2920
2921         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2922
2923         /* Update WMM TXOP register */
2924         offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2925         field.bit_offset = (queue_idx & 1) * 16;
2926         field.bit_mask = 0xffff << field.bit_offset;
2927
2928         rt2x00pci_register_read(rt2x00dev, offset, &reg);
2929         rt2x00_set_field32(&reg, field, queue->txop);
2930         rt2x00pci_register_write(rt2x00dev, offset, reg);
2931
2932         /* Update WMM registers */
2933         field.bit_offset = queue_idx * 4;
2934         field.bit_mask = 0xf << field.bit_offset;
2935
2936         rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2937         rt2x00_set_field32(&reg, field, queue->aifs);
2938         rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2939
2940         rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2941         rt2x00_set_field32(&reg, field, queue->cw_min);
2942         rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2943
2944         rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2945         rt2x00_set_field32(&reg, field, queue->cw_max);
2946         rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2947
2948         return 0;
2949 }
2950
2951 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2952 {
2953         struct rt2x00_dev *rt2x00dev = hw->priv;
2954         u64 tsf;
2955         u32 reg;
2956
2957         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2958         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2959         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2960         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2961
2962         return tsf;
2963 }
2964
2965 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2966         .tx                     = rt2x00mac_tx,
2967         .start                  = rt2x00mac_start,
2968         .stop                   = rt2x00mac_stop,
2969         .add_interface          = rt2x00mac_add_interface,
2970         .remove_interface       = rt2x00mac_remove_interface,
2971         .config                 = rt2x00mac_config,
2972         .configure_filter       = rt2x00mac_configure_filter,
2973         .set_key                = rt2x00mac_set_key,
2974         .sw_scan_start          = rt2x00mac_sw_scan_start,
2975         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
2976         .get_stats              = rt2x00mac_get_stats,
2977         .bss_info_changed       = rt2x00mac_bss_info_changed,
2978         .conf_tx                = rt61pci_conf_tx,
2979         .get_tsf                = rt61pci_get_tsf,
2980         .rfkill_poll            = rt2x00mac_rfkill_poll,
2981         .flush                  = rt2x00mac_flush,
2982         .set_antenna            = rt2x00mac_set_antenna,
2983         .get_antenna            = rt2x00mac_get_antenna,
2984         .get_ringparam          = rt2x00mac_get_ringparam,
2985 };
2986
2987 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2988         .irq_handler            = rt61pci_interrupt,
2989         .txstatus_tasklet       = rt61pci_txstatus_tasklet,
2990         .tbtt_tasklet           = rt61pci_tbtt_tasklet,
2991         .rxdone_tasklet         = rt61pci_rxdone_tasklet,
2992         .autowake_tasklet       = rt61pci_autowake_tasklet,
2993         .probe_hw               = rt61pci_probe_hw,
2994         .get_firmware_name      = rt61pci_get_firmware_name,
2995         .check_firmware         = rt61pci_check_firmware,
2996         .load_firmware          = rt61pci_load_firmware,
2997         .initialize             = rt2x00pci_initialize,
2998         .uninitialize           = rt2x00pci_uninitialize,
2999         .get_entry_state        = rt61pci_get_entry_state,
3000         .clear_entry            = rt61pci_clear_entry,
3001         .set_device_state       = rt61pci_set_device_state,
3002         .rfkill_poll            = rt61pci_rfkill_poll,
3003         .link_stats             = rt61pci_link_stats,
3004         .reset_tuner            = rt61pci_reset_tuner,
3005         .link_tuner             = rt61pci_link_tuner,
3006         .start_queue            = rt61pci_start_queue,
3007         .kick_queue             = rt61pci_kick_queue,
3008         .stop_queue             = rt61pci_stop_queue,
3009         .flush_queue            = rt2x00pci_flush_queue,
3010         .write_tx_desc          = rt61pci_write_tx_desc,
3011         .write_beacon           = rt61pci_write_beacon,
3012         .clear_beacon           = rt61pci_clear_beacon,
3013         .fill_rxdone            = rt61pci_fill_rxdone,
3014         .config_shared_key      = rt61pci_config_shared_key,
3015         .config_pairwise_key    = rt61pci_config_pairwise_key,
3016         .config_filter          = rt61pci_config_filter,
3017         .config_intf            = rt61pci_config_intf,
3018         .config_erp             = rt61pci_config_erp,
3019         .config_ant             = rt61pci_config_ant,
3020         .config                 = rt61pci_config,
3021 };
3022
3023 static const struct data_queue_desc rt61pci_queue_rx = {
3024         .entry_num              = 32,
3025         .data_size              = DATA_FRAME_SIZE,
3026         .desc_size              = RXD_DESC_SIZE,
3027         .priv_size              = sizeof(struct queue_entry_priv_pci),
3028 };
3029
3030 static const struct data_queue_desc rt61pci_queue_tx = {
3031         .entry_num              = 32,
3032         .data_size              = DATA_FRAME_SIZE,
3033         .desc_size              = TXD_DESC_SIZE,
3034         .priv_size              = sizeof(struct queue_entry_priv_pci),
3035 };
3036
3037 static const struct data_queue_desc rt61pci_queue_bcn = {
3038         .entry_num              = 4,
3039         .data_size              = 0, /* No DMA required for beacons */
3040         .desc_size              = TXINFO_SIZE,
3041         .priv_size              = sizeof(struct queue_entry_priv_pci),
3042 };
3043
3044 static const struct rt2x00_ops rt61pci_ops = {
3045         .name                   = KBUILD_MODNAME,
3046         .max_sta_intf           = 1,
3047         .max_ap_intf            = 4,
3048         .eeprom_size            = EEPROM_SIZE,
3049         .rf_size                = RF_SIZE,
3050         .tx_queues              = NUM_TX_QUEUES,
3051         .extra_tx_headroom      = 0,
3052         .rx                     = &rt61pci_queue_rx,
3053         .tx                     = &rt61pci_queue_tx,
3054         .bcn                    = &rt61pci_queue_bcn,
3055         .lib                    = &rt61pci_rt2x00_ops,
3056         .hw                     = &rt61pci_mac80211_ops,
3057 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
3058         .debugfs                = &rt61pci_rt2x00debug,
3059 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3060 };
3061
3062 /*
3063  * RT61pci module information.
3064  */
3065 static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
3066         /* RT2561s */
3067         { PCI_DEVICE(0x1814, 0x0301) },
3068         /* RT2561 v2 */
3069         { PCI_DEVICE(0x1814, 0x0302) },
3070         /* RT2661 */
3071         { PCI_DEVICE(0x1814, 0x0401) },
3072         { 0, }
3073 };
3074
3075 MODULE_AUTHOR(DRV_PROJECT);
3076 MODULE_VERSION(DRV_VERSION);
3077 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
3078 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
3079                         "PCI & PCMCIA chipset based cards");
3080 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
3081 MODULE_FIRMWARE(FIRMWARE_RT2561);
3082 MODULE_FIRMWARE(FIRMWARE_RT2561s);
3083 MODULE_FIRMWARE(FIRMWARE_RT2661);
3084 MODULE_LICENSE("GPL");
3085
3086 static int rt61pci_probe(struct pci_dev *pci_dev,
3087                          const struct pci_device_id *id)
3088 {
3089         return rt2x00pci_probe(pci_dev, &rt61pci_ops);
3090 }
3091
3092 static struct pci_driver rt61pci_driver = {
3093         .name           = KBUILD_MODNAME,
3094         .id_table       = rt61pci_device_table,
3095         .probe          = rt61pci_probe,
3096         .remove         = __devexit_p(rt2x00pci_remove),
3097         .suspend        = rt2x00pci_suspend,
3098         .resume         = rt2x00pci_resume,
3099 };
3100
3101 static int __init rt61pci_init(void)
3102 {
3103         return pci_register_driver(&rt61pci_driver);
3104 }
3105
3106 static void __exit rt61pci_exit(void)
3107 {
3108         pci_unregister_driver(&rt61pci_driver);
3109 }
3110
3111 module_init(rt61pci_init);
3112 module_exit(rt61pci_exit);