rt2x00: Fix MCS register intialization
[pandora-kernel.git] / drivers / net / wireless / rt2x00 / rt2800usb.c
1 /*
2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt2800usb
23         Abstract: rt2800usb device specific routines.
24         Supported chipsets: RT2800U.
25  */
26
27 #include <linux/crc-ccitt.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/usb.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00usb.h"
37 #include "rt2800usb.h"
38
39 /*
40  * Allow hardware encryption to be disabled.
41  */
42 static int modparam_nohwcrypt = 1;
43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
46 /*
47  * Register access.
48  * All access to the CSR registers will go through the methods
49  * rt2x00usb_register_read and rt2x00usb_register_write.
50  * BBP and RF register require indirect register access,
51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
52  * These indirect registers work with busy bits,
53  * and we will try maximal REGISTER_BUSY_COUNT times to access
54  * the register while taking a REGISTER_BUSY_DELAY us delay
55  * between each attampt. When the busy bit is still set at that time,
56  * the access attempt is considered to have failed,
57  * and we will print an error.
58  * The _lock versions must be used if you already hold the csr_mutex
59  */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61         rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63         rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65         rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67         rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68                                H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
71                                 const unsigned int word, const u8 value)
72 {
73         u32 reg;
74
75         mutex_lock(&rt2x00dev->csr_mutex);
76
77         /*
78          * Wait until the BBP becomes available, afterwards we
79          * can safely write the new data into the register.
80          */
81         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
82                 reg = 0;
83                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
84                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
85                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
86                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
87
88                 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
89         }
90
91         mutex_unlock(&rt2x00dev->csr_mutex);
92 }
93
94 static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95                                const unsigned int word, u8 *value)
96 {
97         u32 reg;
98
99         mutex_lock(&rt2x00dev->csr_mutex);
100
101         /*
102          * Wait until the BBP becomes available, afterwards we
103          * can safely write the read request into the register.
104          * After the data has been written, we wait until hardware
105          * returns the correct value, if at any time the register
106          * doesn't become available in time, reg will be 0xffffffff
107          * which means we return 0xff to the caller.
108          */
109         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
110                 reg = 0;
111                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
112                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
113                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
114
115                 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
116
117                 WAIT_FOR_BBP(rt2x00dev, &reg);
118         }
119
120         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
121
122         mutex_unlock(&rt2x00dev->csr_mutex);
123 }
124
125 static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
126                                   const unsigned int word, const u8 value)
127 {
128         u32 reg;
129
130         mutex_lock(&rt2x00dev->csr_mutex);
131
132         /*
133          * Wait until the RFCSR becomes available, afterwards we
134          * can safely write the new data into the register.
135          */
136         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
137                 reg = 0;
138                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
139                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
140                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
141                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
142
143                 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
144         }
145
146         mutex_unlock(&rt2x00dev->csr_mutex);
147 }
148
149 static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
150                                  const unsigned int word, u8 *value)
151 {
152         u32 reg;
153
154         mutex_lock(&rt2x00dev->csr_mutex);
155
156         /*
157          * Wait until the RFCSR becomes available, afterwards we
158          * can safely write the read request into the register.
159          * After the data has been written, we wait until hardware
160          * returns the correct value, if at any time the register
161          * doesn't become available in time, reg will be 0xffffffff
162          * which means we return 0xff to the caller.
163          */
164         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
165                 reg = 0;
166                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
167                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
168                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
169
170                 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
171
172                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
173         }
174
175         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
176
177         mutex_unlock(&rt2x00dev->csr_mutex);
178 }
179
180 static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
181                                const unsigned int word, const u32 value)
182 {
183         u32 reg;
184
185         mutex_lock(&rt2x00dev->csr_mutex);
186
187         /*
188          * Wait until the RF becomes available, afterwards we
189          * can safely write the new data into the register.
190          */
191         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
192                 reg = 0;
193                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
194                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
195                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
196                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
197
198                 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
199                 rt2x00_rf_write(rt2x00dev, word, value);
200         }
201
202         mutex_unlock(&rt2x00dev->csr_mutex);
203 }
204
205 static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
206                                   const u8 command, const u8 token,
207                                   const u8 arg0, const u8 arg1)
208 {
209         u32 reg;
210
211         mutex_lock(&rt2x00dev->csr_mutex);
212
213         /*
214          * Wait until the MCU becomes available, afterwards we
215          * can safely write the new data into the register.
216          */
217         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
218                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
219                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
220                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
221                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
222                 rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
223
224                 reg = 0;
225                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
226                 rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
227         }
228
229         mutex_unlock(&rt2x00dev->csr_mutex);
230 }
231
232 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
233 static const struct rt2x00debug rt2800usb_rt2x00debug = {
234         .owner  = THIS_MODULE,
235         .csr    = {
236                 .read           = rt2x00usb_register_read,
237                 .write          = rt2x00usb_register_write,
238                 .flags          = RT2X00DEBUGFS_OFFSET,
239                 .word_base      = CSR_REG_BASE,
240                 .word_size      = sizeof(u32),
241                 .word_count     = CSR_REG_SIZE / sizeof(u32),
242         },
243         .eeprom = {
244                 .read           = rt2x00_eeprom_read,
245                 .write          = rt2x00_eeprom_write,
246                 .word_base      = EEPROM_BASE,
247                 .word_size      = sizeof(u16),
248                 .word_count     = EEPROM_SIZE / sizeof(u16),
249         },
250         .bbp    = {
251                 .read           = rt2800usb_bbp_read,
252                 .write          = rt2800usb_bbp_write,
253                 .word_base      = BBP_BASE,
254                 .word_size      = sizeof(u8),
255                 .word_count     = BBP_SIZE / sizeof(u8),
256         },
257         .rf     = {
258                 .read           = rt2x00_rf_read,
259                 .write          = rt2800usb_rf_write,
260                 .word_base      = RF_BASE,
261                 .word_size      = sizeof(u32),
262                 .word_count     = RF_SIZE / sizeof(u32),
263         },
264 };
265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
266
267 static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
268 {
269         u32 reg;
270
271         rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
272         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
273 }
274
275 #ifdef CONFIG_RT2X00_LIB_LEDS
276 static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
277                                      enum led_brightness brightness)
278 {
279         struct rt2x00_led *led =
280             container_of(led_cdev, struct rt2x00_led, led_dev);
281         unsigned int enabled = brightness != LED_OFF;
282         unsigned int bg_mode =
283             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
284         unsigned int polarity =
285                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
286                                    EEPROM_FREQ_LED_POLARITY);
287         unsigned int ledmode =
288                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
289                                    EEPROM_FREQ_LED_MODE);
290
291         if (led->type == LED_TYPE_RADIO) {
292                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
293                                       enabled ? 0x20 : 0);
294         } else if (led->type == LED_TYPE_ASSOC) {
295                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
296                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
297         } else if (led->type == LED_TYPE_QUALITY) {
298                 /*
299                  * The brightness is divided into 6 levels (0 - 5),
300                  * The specs tell us the following levels:
301                  *      0, 1 ,3, 7, 15, 31
302                  * to determine the level in a simple way we can simply
303                  * work with bitshifting:
304                  *      (1 << level) - 1
305                  */
306                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
307                                       (1 << brightness / (LED_FULL / 6)) - 1,
308                                       polarity);
309         }
310 }
311
312 static int rt2800usb_blink_set(struct led_classdev *led_cdev,
313                                unsigned long *delay_on,
314                                unsigned long *delay_off)
315 {
316         struct rt2x00_led *led =
317             container_of(led_cdev, struct rt2x00_led, led_dev);
318         u32 reg;
319
320         rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
321         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
322         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
323         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
324         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
325         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
326         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
327         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
328         rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
329
330         return 0;
331 }
332
333 static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
334                                struct rt2x00_led *led,
335                                enum led_type type)
336 {
337         led->rt2x00dev = rt2x00dev;
338         led->type = type;
339         led->led_dev.brightness_set = rt2800usb_brightness_set;
340         led->led_dev.blink_set = rt2800usb_blink_set;
341         led->flags = LED_INITIALIZED;
342 }
343 #endif /* CONFIG_RT2X00_LIB_LEDS */
344
345 /*
346  * Configuration handlers.
347  */
348 static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
349                                        struct rt2x00lib_crypto *crypto,
350                                        struct ieee80211_key_conf *key)
351 {
352         struct mac_wcid_entry wcid_entry;
353         struct mac_iveiv_entry iveiv_entry;
354         u32 offset;
355         u32 reg;
356
357         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
358
359         rt2x00usb_register_read(rt2x00dev, offset, &reg);
360         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
361                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
362         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
363                            (crypto->cmd == SET_KEY) * crypto->cipher);
364         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
365                            (crypto->cmd == SET_KEY) * crypto->bssidx);
366         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
367         rt2x00usb_register_write(rt2x00dev, offset, reg);
368
369         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
370
371         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
372         if ((crypto->cipher == CIPHER_TKIP) ||
373             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
374             (crypto->cipher == CIPHER_AES))
375                 iveiv_entry.iv[3] |= 0x20;
376         iveiv_entry.iv[3] |= key->keyidx << 6;
377         rt2x00usb_register_multiwrite(rt2x00dev, offset,
378                                       &iveiv_entry, sizeof(iveiv_entry));
379
380         offset = MAC_WCID_ENTRY(key->hw_key_idx);
381
382         memset(&wcid_entry, 0, sizeof(wcid_entry));
383         if (crypto->cmd == SET_KEY)
384                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
385         rt2x00usb_register_multiwrite(rt2x00dev, offset,
386                                       &wcid_entry, sizeof(wcid_entry));
387 }
388
389 static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
390                                        struct rt2x00lib_crypto *crypto,
391                                        struct ieee80211_key_conf *key)
392 {
393         struct hw_key_entry key_entry;
394         struct rt2x00_field32 field;
395         int timeout;
396         u32 offset;
397         u32 reg;
398
399         if (crypto->cmd == SET_KEY) {
400                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
401
402                 memcpy(key_entry.key, crypto->key,
403                        sizeof(key_entry.key));
404                 memcpy(key_entry.tx_mic, crypto->tx_mic,
405                        sizeof(key_entry.tx_mic));
406                 memcpy(key_entry.rx_mic, crypto->rx_mic,
407                        sizeof(key_entry.rx_mic));
408
409                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
410                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
411                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
412                                                     USB_VENDOR_REQUEST_OUT,
413                                                     offset, &key_entry,
414                                                     sizeof(key_entry),
415                                                     timeout);
416         }
417
418         /*
419          * The cipher types are stored over multiple registers
420          * starting with SHARED_KEY_MODE_BASE each word will have
421          * 32 bits and contains the cipher types for 2 bssidx each.
422          * Using the correct defines correctly will cause overhead,
423          * so just calculate the correct offset.
424          */
425         field.bit_offset = 4 * (key->hw_key_idx % 8);
426         field.bit_mask = 0x7 << field.bit_offset;
427
428         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
429
430         rt2x00usb_register_read(rt2x00dev, offset, &reg);
431         rt2x00_set_field32(&reg, field,
432                            (crypto->cmd == SET_KEY) * crypto->cipher);
433         rt2x00usb_register_write(rt2x00dev, offset, reg);
434
435         /*
436          * Update WCID information
437          */
438         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
439
440         return 0;
441 }
442
443 static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
444                                          struct rt2x00lib_crypto *crypto,
445                                          struct ieee80211_key_conf *key)
446 {
447         struct hw_key_entry key_entry;
448         int timeout;
449         u32 offset;
450
451         if (crypto->cmd == SET_KEY) {
452                 /*
453                  * 1 pairwise key is possible per AID, this means that the AID
454                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
455                  * last possible shared key entry.
456                  */
457                 if (crypto->aid > (256 - 32))
458                         return -ENOSPC;
459
460                 key->hw_key_idx = 32 + crypto->aid;
461
462                 memcpy(key_entry.key, crypto->key,
463                        sizeof(key_entry.key));
464                 memcpy(key_entry.tx_mic, crypto->tx_mic,
465                        sizeof(key_entry.tx_mic));
466                 memcpy(key_entry.rx_mic, crypto->rx_mic,
467                        sizeof(key_entry.rx_mic));
468
469                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
470                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
471                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
472                                                     USB_VENDOR_REQUEST_OUT,
473                                                     offset, &key_entry,
474                                                     sizeof(key_entry),
475                                                     timeout);
476         }
477
478         /*
479          * Update WCID information
480          */
481         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
482
483         return 0;
484 }
485
486 static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
487                                     const unsigned int filter_flags)
488 {
489         u32 reg;
490
491         /*
492          * Start configuration steps.
493          * Note that the version error will always be dropped
494          * and broadcast frames will always be accepted since
495          * there is no filter for it at this time.
496          */
497         rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
498         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
499                            !(filter_flags & FIF_FCSFAIL));
500         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
501                            !(filter_flags & FIF_PLCPFAIL));
502         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
503                            !(filter_flags & FIF_PROMISC_IN_BSS));
504         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
505         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
506         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
507                            !(filter_flags & FIF_ALLMULTI));
508         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
509         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
510         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
511                            !(filter_flags & FIF_CONTROL));
512         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
513                            !(filter_flags & FIF_CONTROL));
514         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
515                            !(filter_flags & FIF_CONTROL));
516         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
517                            !(filter_flags & FIF_CONTROL));
518         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
519                            !(filter_flags & FIF_CONTROL));
520         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
521                            !(filter_flags & FIF_PSPOLL));
522         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
523         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
524         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
525                            !(filter_flags & FIF_CONTROL));
526         rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
527 }
528
529 static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
530                                   struct rt2x00_intf *intf,
531                                   struct rt2x00intf_conf *conf,
532                                   const unsigned int flags)
533 {
534         unsigned int beacon_base;
535         u32 reg;
536
537         if (flags & CONFIG_UPDATE_TYPE) {
538                 /*
539                  * Clear current synchronisation setup.
540                  * For the Beacon base registers we only need to clear
541                  * the first byte since that byte contains the VALID and OWNER
542                  * bits which (when set to 0) will invalidate the entire beacon.
543                  */
544                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
545                 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
546
547                 /*
548                  * Enable synchronisation.
549                  */
550                 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
551                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
552                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
553                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
554                 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
555         }
556
557         if (flags & CONFIG_UPDATE_MAC) {
558                 reg = le32_to_cpu(conf->mac[1]);
559                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
560                 conf->mac[1] = cpu_to_le32(reg);
561
562                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
563                                               conf->mac, sizeof(conf->mac));
564         }
565
566         if (flags & CONFIG_UPDATE_BSSID) {
567                 reg = le32_to_cpu(conf->bssid[1]);
568                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
569                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
570                 conf->bssid[1] = cpu_to_le32(reg);
571
572                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
573                                               conf->bssid, sizeof(conf->bssid));
574         }
575 }
576
577 static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
578                                  struct rt2x00lib_erp *erp)
579 {
580         u32 reg;
581
582         rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
583         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
584                            DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
585         rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
586
587         rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
588         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
589                            !!erp->short_preamble);
590         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
591                            !!erp->short_preamble);
592         rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
593
594         rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
595         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
596                            erp->cts_protection ? 2 : 0);
597         rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
598
599         rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
600                                  erp->basic_rates);
601         rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
602
603         rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
604         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
605         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
606         rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
607
608         rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
609         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
610         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
611         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
612         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
613         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
614         rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
615
616         rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
617         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
618                            erp->beacon_int * 16);
619         rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
620 }
621
622 static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
623                                  struct antenna_setup *ant)
624 {
625         u8 r1;
626         u8 r3;
627
628         rt2800usb_bbp_read(rt2x00dev, 1, &r1);
629         rt2800usb_bbp_read(rt2x00dev, 3, &r3);
630
631         /*
632          * Configure the TX antenna.
633          */
634         switch ((int)ant->tx) {
635         case 1:
636                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
637                 break;
638         case 2:
639                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
640                 break;
641         case 3:
642                 /* Do nothing */
643                 break;
644         }
645
646         /*
647          * Configure the RX antenna.
648          */
649         switch ((int)ant->rx) {
650         case 1:
651                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
652                 break;
653         case 2:
654                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
655                 break;
656         case 3:
657                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
658                 break;
659         }
660
661         rt2800usb_bbp_write(rt2x00dev, 3, r3);
662         rt2800usb_bbp_write(rt2x00dev, 1, r1);
663 }
664
665 static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
666                                       struct rt2x00lib_conf *libconf)
667 {
668         u16 eeprom;
669         short lna_gain;
670
671         if (libconf->rf.channel <= 14) {
672                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
673                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
674         } else if (libconf->rf.channel <= 64) {
675                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
676                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
677         } else if (libconf->rf.channel <= 128) {
678                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
679                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
680         } else {
681                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
682                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
683         }
684
685         rt2x00dev->lna_gain = lna_gain;
686 }
687
688 static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
689                                           struct ieee80211_conf *conf,
690                                           struct rf_channel *rf,
691                                           struct channel_info *info)
692 {
693         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
694
695         if (rt2x00dev->default_ant.tx == 1)
696                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
697
698         if (rt2x00dev->default_ant.rx == 1) {
699                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
700                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
701         } else if (rt2x00dev->default_ant.rx == 2)
702                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
703
704         if (rf->channel > 14) {
705                 /*
706                  * When TX power is below 0, we should increase it by 7 to
707                  * make it a positive value (Minumum value is -7).
708                  * However this means that values between 0 and 7 have
709                  * double meaning, and we should set a 7DBm boost flag.
710                  */
711                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
712                                    (info->tx_power1 >= 0));
713
714                 if (info->tx_power1 < 0)
715                         info->tx_power1 += 7;
716
717                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
718                                    TXPOWER_A_TO_DEV(info->tx_power1));
719
720                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
721                                    (info->tx_power2 >= 0));
722
723                 if (info->tx_power2 < 0)
724                         info->tx_power2 += 7;
725
726                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
727                                    TXPOWER_A_TO_DEV(info->tx_power2));
728         } else {
729                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
730                                    TXPOWER_G_TO_DEV(info->tx_power1));
731                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
732                                    TXPOWER_G_TO_DEV(info->tx_power2));
733         }
734
735         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
736
737         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
738         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
739         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
740         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
741
742         udelay(200);
743
744         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
745         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
746         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
747         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
748
749         udelay(200);
750
751         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
752         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
753         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
754         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
755 }
756
757 static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
758                                           struct ieee80211_conf *conf,
759                                           struct rf_channel *rf,
760                                           struct channel_info *info)
761 {
762         u8 rfcsr;
763
764         rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
765         rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
766
767         rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
768         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
769         rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
770
771         rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
772         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
773                           TXPOWER_G_TO_DEV(info->tx_power1));
774         rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
775
776         rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
777         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
778         rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
779
780         rt2800usb_rfcsr_write(rt2x00dev, 24,
781                               rt2x00dev->calibration[conf_is_ht40(conf)]);
782
783         rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
784         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
785         rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
786 }
787
788 static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
789                                      struct ieee80211_conf *conf,
790                                      struct rf_channel *rf,
791                                      struct channel_info *info)
792 {
793         u32 reg;
794         unsigned int tx_pin;
795         u8 bbp;
796
797         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
798                 rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
799         else
800                 rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
801
802         /*
803          * Change BBP settings
804          */
805         rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
806         rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
807         rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
808         rt2800usb_bbp_write(rt2x00dev, 86, 0);
809
810         if (rf->channel <= 14) {
811                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
812                         rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
813                         rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
814                 } else {
815                         rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
816                         rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
817                 }
818         } else {
819                 rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
820
821                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
822                         rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
823                 else
824                         rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
825         }
826
827         rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
828         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
829         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
830         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
831         rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
832
833         tx_pin = 0;
834
835         /* Turn on unused PA or LNA when not using 1T or 1R */
836         if (rt2x00dev->default_ant.tx != 1) {
837                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
838                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
839         }
840
841         /* Turn on unused PA or LNA when not using 1T or 1R */
842         if (rt2x00dev->default_ant.rx != 1) {
843                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
844                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
845         }
846
847         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
848         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
849         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
850         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
851         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
852         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
853
854         rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
855
856         rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
857         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
858         rt2800usb_bbp_write(rt2x00dev, 4, bbp);
859
860         rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
861         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
862         rt2800usb_bbp_write(rt2x00dev, 3, bbp);
863
864         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
865                 if (conf_is_ht40(conf)) {
866                         rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
867                         rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
868                         rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
869                 } else {
870                         rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
871                         rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
872                         rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
873                 }
874         }
875
876         msleep(1);
877 }
878
879 static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
880                                      const int txpower)
881 {
882         u32 reg;
883         u32 value = TXPOWER_G_TO_DEV(txpower);
884         u8 r1;
885
886         rt2800usb_bbp_read(rt2x00dev, 1, &r1);
887         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
888         rt2800usb_bbp_write(rt2x00dev, 1, r1);
889
890         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
891         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
892         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
893         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
894         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
895         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
896         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
897         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
898         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
899         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
900
901         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
902         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
903         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
904         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
905         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
906         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
907         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
908         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
909         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
910         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
911
912         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
913         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
914         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
915         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
916         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
917         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
918         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
919         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
920         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
921         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
922
923         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
924         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
925         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
926         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
927         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
928         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
929         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
930         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
931         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
932         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
933
934         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
935         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
936         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
937         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
938         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
939         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
940 }
941
942 static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
943                                          struct rt2x00lib_conf *libconf)
944 {
945         u32 reg;
946
947         rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
948         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
949                            libconf->conf->short_frame_max_tx_count);
950         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
951                            libconf->conf->long_frame_max_tx_count);
952         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
953         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
954         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
955         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
956         rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
957 }
958
959 static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
960                                 struct rt2x00lib_conf *libconf)
961 {
962         enum dev_state state =
963             (libconf->conf->flags & IEEE80211_CONF_PS) ?
964                 STATE_SLEEP : STATE_AWAKE;
965         u32 reg;
966
967         if (state == STATE_SLEEP) {
968                 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
969
970                 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
971                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
972                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
973                                    libconf->conf->listen_interval - 1);
974                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
975                 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
976
977                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
978         } else {
979                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
980
981                 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
982                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
983                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
984                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
985                 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
986         }
987 }
988
989 static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
990                              struct rt2x00lib_conf *libconf,
991                              const unsigned int flags)
992 {
993         /* Always recalculate LNA gain before changing configuration */
994         rt2800usb_config_lna_gain(rt2x00dev, libconf);
995
996         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
997                 rt2800usb_config_channel(rt2x00dev, libconf->conf,
998                                          &libconf->rf, &libconf->channel);
999         if (flags & IEEE80211_CONF_CHANGE_POWER)
1000                 rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1001         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1002                 rt2800usb_config_retry_limit(rt2x00dev, libconf);
1003         if (flags & IEEE80211_CONF_CHANGE_PS)
1004                 rt2800usb_config_ps(rt2x00dev, libconf);
1005 }
1006
1007 /*
1008  * Link tuning
1009  */
1010 static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1011                                  struct link_qual *qual)
1012 {
1013         u32 reg;
1014
1015         /*
1016          * Update FCS error count from register.
1017          */
1018         rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1019         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1020 }
1021
1022 static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1023 {
1024         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1025                 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1026                         return 0x1c + (2 * rt2x00dev->lna_gain);
1027                 else
1028                         return 0x2e + rt2x00dev->lna_gain;
1029         }
1030
1031         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1032                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1033         else
1034                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1035 }
1036
1037 static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1038                                      struct link_qual *qual, u8 vgc_level)
1039 {
1040         if (qual->vgc_level != vgc_level) {
1041                 rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1042                 qual->vgc_level = vgc_level;
1043                 qual->vgc_level_reg = vgc_level;
1044         }
1045 }
1046
1047 static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1048                                   struct link_qual *qual)
1049 {
1050         rt2800usb_set_vgc(rt2x00dev, qual,
1051                           rt2800usb_get_default_vgc(rt2x00dev));
1052 }
1053
1054 static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1055                                  struct link_qual *qual, const u32 count)
1056 {
1057         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1058                 return;
1059
1060         /*
1061          * When RSSI is better then -80 increase VGC level with 0x10
1062          */
1063         rt2800usb_set_vgc(rt2x00dev, qual,
1064                           rt2800usb_get_default_vgc(rt2x00dev) +
1065                           ((qual->rssi > -80) * 0x10));
1066 }
1067
1068 /*
1069  * Firmware functions
1070  */
1071 static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1072 {
1073         return FIRMWARE_RT2870;
1074 }
1075
1076 static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1077 {
1078         u16 fw_crc;
1079         u16 crc;
1080
1081         /*
1082          * The last 2 bytes in the firmware array are the crc checksum itself,
1083          * this means that we should never pass those 2 bytes to the crc
1084          * algorithm.
1085          */
1086         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1087
1088         /*
1089          * Use the crc ccitt algorithm.
1090          * This will return the same value as the legacy driver which
1091          * used bit ordering reversion on the both the firmware bytes
1092          * before input input as well as on the final output.
1093          * Obviously using crc ccitt directly is much more efficient.
1094          */
1095         crc = crc_ccitt(~0, data, len - 2);
1096
1097         /*
1098          * There is a small difference between the crc-itu-t + bitrev and
1099          * the crc-ccitt crc calculation. In the latter method the 2 bytes
1100          * will be swapped, use swab16 to convert the crc to the correct
1101          * value.
1102          */
1103         crc = swab16(crc);
1104
1105         return fw_crc == crc;
1106 }
1107
1108 static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1109                                     const u8 *data, const size_t len)
1110 {
1111         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1112         size_t offset = 0;
1113
1114         /*
1115          * Firmware files:
1116          * There are 2 variations of the rt2870 firmware.
1117          * a) size: 4kb
1118          * b) size: 8kb
1119          * Note that (b) contains 2 seperate firmware blobs of 4k
1120          * within the file. The first blob is the same firmware as (a),
1121          * but the second blob is for the additional chipsets.
1122          */
1123         if (len != 4096 && len != 8192)
1124                 return FW_BAD_LENGTH;
1125
1126         /*
1127          * Check if we need the upper 4kb firmware data or not.
1128          */
1129         if ((len == 4096) &&
1130             (chipset != 0x2860) &&
1131             (chipset != 0x2872) &&
1132             (chipset != 0x3070))
1133                 return FW_BAD_VERSION;
1134
1135         /*
1136          * 8kb firmware files must be checked as if it were
1137          * 2 seperate firmware files.
1138          */
1139         while (offset < len) {
1140                 if (!rt2800usb_check_crc(data + offset, 4096))
1141                         return FW_BAD_CRC;
1142
1143                 offset += 4096;
1144         }
1145
1146         return FW_OK;
1147 }
1148
1149 static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1150                                    const u8 *data, const size_t len)
1151 {
1152         unsigned int i;
1153         int status;
1154         u32 reg;
1155         u32 offset;
1156         u32 length;
1157         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1158
1159         /*
1160          * Check which section of the firmware we need.
1161          */
1162         if ((chipset == 0x2860) ||
1163             (chipset == 0x2872) ||
1164             (chipset == 0x3070)) {
1165                 offset = 0;
1166                 length = 4096;
1167         } else {
1168                 offset = 4096;
1169                 length = 4096;
1170         }
1171
1172         /*
1173          * Wait for stable hardware.
1174          */
1175         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1176                 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1177                 if (reg && reg != ~0)
1178                         break;
1179                 msleep(1);
1180         }
1181
1182         if (i == REGISTER_BUSY_COUNT) {
1183                 ERROR(rt2x00dev, "Unstable hardware.\n");
1184                 return -EBUSY;
1185         }
1186
1187         /*
1188          * Write firmware to device.
1189          */
1190         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1191                                             USB_VENDOR_REQUEST_OUT,
1192                                             FIRMWARE_IMAGE_BASE,
1193                                             data + offset, length,
1194                                             REGISTER_TIMEOUT32(length));
1195
1196         rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1197         rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1198
1199         /*
1200          * Send firmware request to device to load firmware,
1201          * we need to specify a long timeout time.
1202          */
1203         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1204                                              0, USB_MODE_FIRMWARE,
1205                                              REGISTER_TIMEOUT_FIRMWARE);
1206         if (status < 0) {
1207                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1208                 return status;
1209         }
1210
1211         msleep(10);
1212         rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1213
1214         /*
1215          * Send signal to firmware during boot time.
1216          */
1217         rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1218
1219         if ((chipset == 0x3070) ||
1220             (chipset == 0x3071) ||
1221             (chipset == 0x3572)) {
1222                 udelay(200);
1223                 rt2800usb_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
1224                 udelay(10);
1225         }
1226
1227         /*
1228          * Wait for device to stabilize.
1229          */
1230         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1231                 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1232                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1233                         break;
1234                 msleep(1);
1235         }
1236
1237         if (i == REGISTER_BUSY_COUNT) {
1238                 ERROR(rt2x00dev, "PBF system register not ready.\n");
1239                 return -EBUSY;
1240         }
1241
1242         /*
1243          * Initialize firmware.
1244          */
1245         rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1246         rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1247         msleep(1);
1248
1249         return 0;
1250 }
1251
1252 /*
1253  * Initialization functions.
1254  */
1255 static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1256 {
1257         u32 reg;
1258         unsigned int i;
1259
1260         /*
1261          * Wait untill BBP and RF are ready.
1262          */
1263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1264                 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1265                 if (reg && reg != ~0)
1266                         break;
1267                 msleep(1);
1268         }
1269
1270         if (i == REGISTER_BUSY_COUNT) {
1271                 ERROR(rt2x00dev, "Unstable hardware.\n");
1272                 return -EBUSY;
1273         }
1274
1275         rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1276         rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1277
1278         rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1279         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1280         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1281         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1282
1283         rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1284
1285         rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1286                                     USB_MODE_RESET, REGISTER_TIMEOUT);
1287
1288         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1289
1290         rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1291         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1292         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1293         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1294         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1295         rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1296
1297         rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1298         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1299         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1300         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1301         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1302         rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1303
1304         rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1305         rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1306
1307         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1308
1309         rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1310         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1311         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1312         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1313         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1314         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1315         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1316         rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1317
1318         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1319                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1320                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1321                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1322         } else {
1323                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1324                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1325         }
1326
1327         rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1328         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1329         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1330         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1331         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1332         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1333         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1334         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1335         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1336         rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1337
1338         rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1339         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1340         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1341         rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1342
1343         rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1344         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1345         if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1346             rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1347                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1348         else
1349                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1350         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1351         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1352         rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1353
1354         rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1355
1356         rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1357         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1358         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1359         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1360         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1361         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1362         rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1363
1364         rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1365         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1366         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1367         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1368         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1369         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1370         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1371         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1372         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1373         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1374         rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1375
1376         rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1377         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1378         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1379         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1380         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1381         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1382         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1383         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1384         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1385         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1386         rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1387
1388         rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1389         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1390         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1391         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1392         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1393         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1394         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1395         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1396         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1397         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1398         rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1399
1400         rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1401         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1402         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1403         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1404         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1405         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1406         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1407         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1408         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1409         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1410         rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1411
1412         rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1413         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1414         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1415         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1416         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1417         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1418         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1419         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1420         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1421         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1422         rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1423
1424         rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1425         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1426         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1427         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1428         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1429         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1430         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1431         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1432         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1433         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1434         rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1435
1436         rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1437
1438         rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1439         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1440         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1441         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1442         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1443         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1444         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1445         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1446         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1447         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1448         rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1449
1450         rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1451         rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1452
1453         rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1454         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1455         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1456                            IEEE80211_MAX_RTS_THRESHOLD);
1457         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1458         rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1459
1460         rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1461         rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1462
1463         /*
1464          * ASIC will keep garbage value after boot, clear encryption keys.
1465          */
1466         for (i = 0; i < 4; i++)
1467                 rt2x00usb_register_write(rt2x00dev,
1468                                          SHARED_KEY_MODE_ENTRY(i), 0);
1469
1470         for (i = 0; i < 256; i++) {
1471                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1472                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1473                                               wcid, sizeof(wcid));
1474
1475                 rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1476                 rt2x00usb_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1477         }
1478
1479         /*
1480          * Clear all beacons
1481          * For the Beacon base registers we only need to clear
1482          * the first byte since that byte contains the VALID and OWNER
1483          * bits which (when set to 0) will invalidate the entire beacon.
1484          */
1485         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1486         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1487         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1488         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1489         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1490         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1491         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1492         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1493
1494         rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1495         rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1496         rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1497
1498         rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1499         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1500         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1501         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1502         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1503         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1504         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1505         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1506         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1507         rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1508
1509         rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1510         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1511         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1512         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1513         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1514         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1515         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1516         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1517         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1518         rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1519
1520         rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1521         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1522         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1523         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1524         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1525         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1526         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1527         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1528         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1529         rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1530
1531         rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1532         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1533         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1534         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1535         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1536         rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1537
1538         /*
1539          * We must clear the error counters.
1540          * These registers are cleared on read,
1541          * so we may pass a useless variable to store the value.
1542          */
1543         rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1544         rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1545         rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1546         rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1547         rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1548         rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1549
1550         return 0;
1551 }
1552
1553 static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1554 {
1555         unsigned int i;
1556         u32 reg;
1557
1558         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1559                 rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1560                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1561                         return 0;
1562
1563                 udelay(REGISTER_BUSY_DELAY);
1564         }
1565
1566         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1567         return -EACCES;
1568 }
1569
1570 static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1571 {
1572         unsigned int i;
1573         u8 value;
1574
1575         /*
1576          * BBP was enabled after firmware was loaded,
1577          * but we need to reactivate it now.
1578          */
1579         rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1580         rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1581         msleep(1);
1582
1583         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1584                 rt2800usb_bbp_read(rt2x00dev, 0, &value);
1585                 if ((value != 0xff) && (value != 0x00))
1586                         return 0;
1587                 udelay(REGISTER_BUSY_DELAY);
1588         }
1589
1590         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1591         return -EACCES;
1592 }
1593
1594 static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1595 {
1596         unsigned int i;
1597         u16 eeprom;
1598         u8 reg_id;
1599         u8 value;
1600
1601         if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1602                      rt2800usb_wait_bbp_ready(rt2x00dev)))
1603                 return -EACCES;
1604
1605         rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1606         rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1607         rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1608         rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1609         rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1610         rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1611         rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1612         rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1613         rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1614         rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1615         rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1616         rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1617         rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1618         rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1619
1620         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1621                 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1622                 rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1623         }
1624
1625         if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1626                 rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1627         }
1628
1629         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1630                 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1631                 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1632                 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1633         }
1634
1635         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1636                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1637
1638                 if (eeprom != 0xffff && eeprom != 0x0000) {
1639                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1640                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1641                         rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1642                 }
1643         }
1644
1645         return 0;
1646 }
1647
1648 static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1649                                    bool bw40, u8 rfcsr24, u8 filter_target)
1650 {
1651         unsigned int i;
1652         u8 bbp;
1653         u8 rfcsr;
1654         u8 passband;
1655         u8 stopband;
1656         u8 overtuned = 0;
1657
1658         rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1659
1660         rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1661         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1662         rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1663
1664         rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1665         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1666         rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1667
1668         /*
1669          * Set power & frequency of passband test tone
1670          */
1671         rt2800usb_bbp_write(rt2x00dev, 24, 0);
1672
1673         for (i = 0; i < 100; i++) {
1674                 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1675                 msleep(1);
1676
1677                 rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1678                 if (passband)
1679                         break;
1680         }
1681
1682         /*
1683          * Set power & frequency of stopband test tone
1684          */
1685         rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1686
1687         for (i = 0; i < 100; i++) {
1688                 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1689                 msleep(1);
1690
1691                 rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1692
1693                 if ((passband - stopband) <= filter_target) {
1694                         rfcsr24++;
1695                         overtuned += ((passband - stopband) == filter_target);
1696                 } else
1697                         break;
1698
1699                 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1700         }
1701
1702         rfcsr24 -= !!overtuned;
1703
1704         rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1705         return rfcsr24;
1706 }
1707
1708 static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1709 {
1710         u8 rfcsr;
1711         u8 bbp;
1712
1713         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1714                 return 0;
1715
1716         /*
1717          * Init RF calibration.
1718          */
1719         rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1720         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1721         rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1722         msleep(1);
1723         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1724         rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1725
1726         rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1727         rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1728         rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1729         rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1730         rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1731         rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1732         rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1733         rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1734         rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1735         rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1736         rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1737         rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1738         rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1739         rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1740         rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1741         rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1742         rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1743         rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1744         rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1745         rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1746
1747         /*
1748          * Set RX Filter calibration for 20MHz and 40MHz
1749          */
1750         rt2x00dev->calibration[0] =
1751             rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1752         rt2x00dev->calibration[1] =
1753             rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1754
1755         /*
1756          * Set back to initial state
1757          */
1758         rt2800usb_bbp_write(rt2x00dev, 24, 0);
1759
1760         rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1761         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1762         rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1763
1764         /*
1765          * set BBP back to BW20
1766          */
1767         rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1768         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1769         rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1770
1771         return 0;
1772 }
1773
1774 /*
1775  * Device state switch handlers.
1776  */
1777 static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1778                                 enum dev_state state)
1779 {
1780         u32 reg;
1781
1782         rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1783         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1784                            (state == STATE_RADIO_RX_ON) ||
1785                            (state == STATE_RADIO_RX_ON_LINK));
1786         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1787 }
1788
1789 static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1790 {
1791         unsigned int i;
1792         u32 reg;
1793
1794         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1795                 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1796                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1797                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1798                         return 0;
1799
1800                 msleep(1);
1801         }
1802
1803         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1804         return -EACCES;
1805 }
1806
1807 static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1808 {
1809         u32 reg;
1810         u16 word;
1811
1812         /*
1813          * Initialize all registers.
1814          */
1815         if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1816                      rt2800usb_init_registers(rt2x00dev) ||
1817                      rt2800usb_init_bbp(rt2x00dev) ||
1818                      rt2800usb_init_rfcsr(rt2x00dev)))
1819                 return -EIO;
1820
1821         rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1822         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1823         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1824
1825         udelay(50);
1826
1827         rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1828         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1829         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1830         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1831         rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1832
1833
1834         rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1835         rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1836         /* Don't use bulk in aggregation when working with USB 1.1 */
1837         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1838                            (rt2x00dev->rx->usb_maxpacket == 512));
1839         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1840         /*
1841          * Total room for RX frames in kilobytes, PBF might still exceed
1842          * this limit so reduce the number to prevent errors.
1843          */
1844         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT,
1845                            ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3);
1846         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1847         rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1848         rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
1849
1850         rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1851         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1852         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1853         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1854
1855         /*
1856          * Initialize LED control
1857          */
1858         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1859         rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1860                               word & 0xff, (word >> 8) & 0xff);
1861
1862         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1863         rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1864                               word & 0xff, (word >> 8) & 0xff);
1865
1866         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1867         rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1868                               word & 0xff, (word >> 8) & 0xff);
1869
1870         return 0;
1871 }
1872
1873 static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1874 {
1875         u32 reg;
1876
1877         rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1878         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1879         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1880         rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1881
1882         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1883         rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1884         rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
1885
1886         /* Wait for DMA, ignore error */
1887         rt2800usb_wait_wpdma_ready(rt2x00dev);
1888
1889         rt2x00usb_disable_radio(rt2x00dev);
1890 }
1891
1892 static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1893                                enum dev_state state)
1894 {
1895         if (state == STATE_AWAKE)
1896                 rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1897         else
1898                 rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1899
1900         return 0;
1901 }
1902
1903 static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1904                                       enum dev_state state)
1905 {
1906         int retval = 0;
1907
1908         switch (state) {
1909         case STATE_RADIO_ON:
1910                 /*
1911                  * Before the radio can be enabled, the device first has
1912                  * to be woken up. After that it needs a bit of time
1913                  * to be fully awake and then the radio can be enabled.
1914                  */
1915                 rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1916                 msleep(1);
1917                 retval = rt2800usb_enable_radio(rt2x00dev);
1918                 break;
1919         case STATE_RADIO_OFF:
1920                 /*
1921                  * After the radio has been disabled, the device should
1922                  * be put to sleep for powersaving.
1923                  */
1924                 rt2800usb_disable_radio(rt2x00dev);
1925                 rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1926                 break;
1927         case STATE_RADIO_RX_ON:
1928         case STATE_RADIO_RX_ON_LINK:
1929         case STATE_RADIO_RX_OFF:
1930         case STATE_RADIO_RX_OFF_LINK:
1931                 rt2800usb_toggle_rx(rt2x00dev, state);
1932                 break;
1933         case STATE_RADIO_IRQ_ON:
1934         case STATE_RADIO_IRQ_OFF:
1935                 /* No support, but no error either */
1936                 break;
1937         case STATE_DEEP_SLEEP:
1938         case STATE_SLEEP:
1939         case STATE_STANDBY:
1940         case STATE_AWAKE:
1941                 retval = rt2800usb_set_state(rt2x00dev, state);
1942                 break;
1943         default:
1944                 retval = -ENOTSUPP;
1945                 break;
1946         }
1947
1948         if (unlikely(retval))
1949                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1950                       state, retval);
1951
1952         return retval;
1953 }
1954
1955 /*
1956  * TX descriptor initialization
1957  */
1958 static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1959                                     struct sk_buff *skb,
1960                                     struct txentry_desc *txdesc)
1961 {
1962         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1963         __le32 *txi = skbdesc->desc;
1964         __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
1965         u32 word;
1966
1967         /*
1968          * Initialize TX Info descriptor
1969          */
1970         rt2x00_desc_read(txwi, 0, &word);
1971         rt2x00_set_field32(&word, TXWI_W0_FRAG,
1972                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1973         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1974         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1975         rt2x00_set_field32(&word, TXWI_W0_TS,
1976                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1977         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1978                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1979         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1980         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1981         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1982         rt2x00_set_field32(&word, TXWI_W0_BW,
1983                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1984         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1985                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1986         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1987         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1988         rt2x00_desc_write(txwi, 0, word);
1989
1990         rt2x00_desc_read(txwi, 1, &word);
1991         rt2x00_set_field32(&word, TXWI_W1_ACK,
1992                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1993         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1994                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1995         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1996         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
1997                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
1998                                (skbdesc->entry->entry_idx + 1) : 0xff);
1999         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2000                            skb->len - txdesc->l2pad);
2001         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2002                            skbdesc->entry->queue->qid + 1);
2003         rt2x00_desc_write(txwi, 1, word);
2004
2005         /*
2006          * Always write 0 to IV/EIV fields, hardware will insert the IV
2007          * from the IVEIV register when TXINFO_W0_WIV is set to 0.
2008          * When TXINFO_W0_WIV is set to 1 it will use the IV data
2009          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2010          * crypto entry in the registers should be used to encrypt the frame.
2011          */
2012         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2013         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2014
2015         /*
2016          * Initialize TX descriptor
2017          */
2018         rt2x00_desc_read(txi, 0, &word);
2019         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2020                            skb->len + TXWI_DESC_SIZE);
2021         rt2x00_set_field32(&word, TXINFO_W0_WIV,
2022                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2023         rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2024         rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2025         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2026         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2027                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2028         rt2x00_desc_write(txi, 0, word);
2029 }
2030
2031 /*
2032  * TX data initialization
2033  */
2034 static void rt2800usb_write_beacon(struct queue_entry *entry)
2035 {
2036         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2037         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2038         unsigned int beacon_base;
2039         u32 reg;
2040
2041         /*
2042          * Add the descriptor in front of the skb.
2043          */
2044         skb_push(entry->skb, entry->queue->desc_size);
2045         memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2046         skbdesc->desc = entry->skb->data;
2047
2048         /*
2049          * Disable beaconing while we are reloading the beacon data,
2050          * otherwise we might be sending out invalid data.
2051          */
2052         rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2053         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2054         rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2055
2056         /*
2057          * Write entire beacon with descriptor to register.
2058          */
2059         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2060         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2061                                             USB_VENDOR_REQUEST_OUT, beacon_base,
2062                                             entry->skb->data, entry->skb->len,
2063                                             REGISTER_TIMEOUT32(entry->skb->len));
2064
2065         /*
2066          * Clean up the beacon skb.
2067          */
2068         dev_kfree_skb(entry->skb);
2069         entry->skb = NULL;
2070 }
2071
2072 static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2073 {
2074         int length;
2075
2076         /*
2077          * The length _must_ include 4 bytes padding,
2078          * it should always be multiple of 4,
2079          * but it must _not_ be a multiple of the USB packet size.
2080          */
2081         length = roundup(entry->skb->len + 4, 4);
2082         length += (4 * !(length % entry->queue->usb_maxpacket));
2083
2084         return length;
2085 }
2086
2087 static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2088                                     const enum data_queue_qid queue)
2089 {
2090         u32 reg;
2091
2092         if (queue != QID_BEACON) {
2093                 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2094                 return;
2095         }
2096
2097         rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2098         if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2099                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2100                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2101                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2102                 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2103         }
2104 }
2105
2106 /*
2107  * RX control handlers
2108  */
2109 static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2110                                   struct rxdone_entry_desc *rxdesc)
2111 {
2112         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2113         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2114         __le32 *rxd = (__le32 *)entry->skb->data;
2115         __le32 *rxwi;
2116         u32 rxd0;
2117         u32 rxwi0;
2118         u32 rxwi1;
2119         u32 rxwi2;
2120         u32 rxwi3;
2121
2122         /*
2123          * Copy descriptor to the skbdesc->desc buffer, making it safe from
2124          * moving of frame data in rt2x00usb.
2125          */
2126         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2127         rxd = (__le32 *)skbdesc->desc;
2128         rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2129
2130         /*
2131          * It is now safe to read the descriptor on all architectures.
2132          */
2133         rt2x00_desc_read(rxd, 0, &rxd0);
2134         rt2x00_desc_read(rxwi, 0, &rxwi0);
2135         rt2x00_desc_read(rxwi, 1, &rxwi1);
2136         rt2x00_desc_read(rxwi, 2, &rxwi2);
2137         rt2x00_desc_read(rxwi, 3, &rxwi3);
2138
2139         if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2140                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2141
2142         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2143                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2144                 rxdesc->cipher_status =
2145                     rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2146         }
2147
2148         if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2149                 /*
2150                  * Hardware has stripped IV/EIV data from 802.11 frame during
2151                  * decryption. Unfortunately the descriptor doesn't contain
2152                  * any fields with the EIV/IV data either, so they can't
2153                  * be restored by rt2x00lib.
2154                  */
2155                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2156
2157                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2158                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2159                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2160                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2161         }
2162
2163         if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2164                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2165
2166         if (rt2x00_get_field32(rxd0, RXD_W0_L2PAD)) {
2167                 rxdesc->dev_flags |= RXDONE_L2PAD;
2168                 skbdesc->flags |= SKBDESC_L2_PADDED;
2169         }
2170
2171         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2172                 rxdesc->flags |= RX_FLAG_SHORT_GI;
2173
2174         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2175                 rxdesc->flags |= RX_FLAG_40MHZ;
2176
2177         /*
2178          * Detect RX rate, always use MCS as signal type.
2179          */
2180         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2181         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2182         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2183
2184         /*
2185          * Mask of 0x8 bit to remove the short preamble flag.
2186          */
2187         if (rxdesc->rate_mode == RATE_MODE_CCK)
2188                 rxdesc->signal &= ~0x8;
2189
2190         rxdesc->rssi =
2191             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2192              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2193
2194         rxdesc->noise =
2195             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2196              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2197
2198         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2199
2200         /*
2201          * Remove RXWI descriptor from start of buffer.
2202          */
2203         skb_pull(entry->skb, skbdesc->desc_len);
2204         skb_trim(entry->skb, rxdesc->size);
2205 }
2206
2207 /*
2208  * Device probe functions.
2209  */
2210 static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2211 {
2212         u16 word;
2213         u8 *mac;
2214         u8 default_lna_gain;
2215
2216         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2217
2218         /*
2219          * Start validation of the data that has been read.
2220          */
2221         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2222         if (!is_valid_ether_addr(mac)) {
2223                 random_ether_addr(mac);
2224                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2225         }
2226
2227         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2228         if (word == 0xffff) {
2229                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2230                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2231                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2232                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2233                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2234         } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2235                 /*
2236                  * There is a max of 2 RX streams for RT2870 series
2237                  */
2238                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2239                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2240                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2241         }
2242
2243         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2244         if (word == 0xffff) {
2245                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2246                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2247                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2248                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2249                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2250                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2251                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2252                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2253                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2254                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2255                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2256                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2257         }
2258
2259         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2260         if ((word & 0x00ff) == 0x00ff) {
2261                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2262                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2263                                    LED_MODE_TXRX_ACTIVITY);
2264                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2265                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2266                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2267                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2268                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2269                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2270         }
2271
2272         /*
2273          * During the LNA validation we are going to use
2274          * lna0 as correct value. Note that EEPROM_LNA
2275          * is never validated.
2276          */
2277         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2278         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2279
2280         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2281         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2282                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2283         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2284                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2285         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2286
2287         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2288         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2289                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2290         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2291             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2292                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2293                                    default_lna_gain);
2294         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2295
2296         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2297         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2298                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2299         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2300                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2301         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2302
2303         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2304         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2305                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2306         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2307             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2308                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2309                                    default_lna_gain);
2310         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2311
2312         return 0;
2313 }
2314
2315 static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2316 {
2317         u32 reg;
2318         u16 value;
2319         u16 eeprom;
2320
2321         /*
2322          * Read EEPROM word for configuration.
2323          */
2324         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2325
2326         /*
2327          * Identify RF chipset.
2328          */
2329         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2330         rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
2331         rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2332
2333         /*
2334          * The check for rt2860 is not a typo, some rt2870 hardware
2335          * identifies itself as rt2860 in the CSR register.
2336          */
2337         if (!rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28600000) &&
2338             !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28700000) &&
2339             !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28800000) &&
2340             !rt2x00_check_rev(&rt2x00dev->chip, 0xffff0000, 0x30700000)) {
2341                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2342                 return -ENODEV;
2343         }
2344
2345         if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2346             !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2347             !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2348             !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2349             !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2350             !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2351                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2352                 return -ENODEV;
2353         }
2354
2355         /*
2356          * Identify default antenna configuration.
2357          */
2358         rt2x00dev->default_ant.tx =
2359             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2360         rt2x00dev->default_ant.rx =
2361             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2362
2363         /*
2364          * Read frequency offset and RF programming sequence.
2365          */
2366         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2367         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2368
2369         /*
2370          * Read external LNA informations.
2371          */
2372         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2373
2374         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2375                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2376         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2377                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2378
2379         /*
2380          * Detect if this device has an hardware controlled radio.
2381          */
2382         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2383                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2384
2385         /*
2386          * Store led settings, for correct led behaviour.
2387          */
2388 #ifdef CONFIG_RT2X00_LIB_LEDS
2389         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2390         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2391         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2392
2393         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2394                            &rt2x00dev->led_mcu_reg);
2395 #endif /* CONFIG_RT2X00_LIB_LEDS */
2396
2397         return 0;
2398 }
2399
2400 /*
2401  * RF value list for rt2870
2402  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2403  */
2404 static const struct rf_channel rf_vals[] = {
2405         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2406         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2407         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2408         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2409         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2410         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2411         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2412         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2413         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2414         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2415         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2416         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2417         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2418         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2419
2420         /* 802.11 UNI / HyperLan 2 */
2421         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2422         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2423         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2424         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2425         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2426         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2427         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2428         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2429         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2430         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2431         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2432         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2433
2434         /* 802.11 HyperLan 2 */
2435         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2436         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2437         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2438         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2439         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2440         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2441         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2442         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2443         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2444         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2445         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2446         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2447         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2448         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2449         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2450         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2451
2452         /* 802.11 UNII */
2453         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2454         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2455         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2456         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2457         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2458         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2459         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2460         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2461         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2462         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2463         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2464
2465         /* 802.11 Japan */
2466         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2467         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2468         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2469         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2470         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2471         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2472         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2473 };
2474
2475 /*
2476  * RF value list for rt3070
2477  * Supports: 2.4 GHz
2478  */
2479 static const struct rf_channel rf_vals_3070[] = {
2480         {1,  241, 2, 2 },
2481         {2,  241, 2, 7 },
2482         {3,  242, 2, 2 },
2483         {4,  242, 2, 7 },
2484         {5,  243, 2, 2 },
2485         {6,  243, 2, 7 },
2486         {7,  244, 2, 2 },
2487         {8,  244, 2, 7 },
2488         {9,  245, 2, 2 },
2489         {10, 245, 2, 7 },
2490         {11, 246, 2, 2 },
2491         {12, 246, 2, 7 },
2492         {13, 247, 2, 2 },
2493         {14, 248, 2, 4 },
2494 };
2495
2496 static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2497 {
2498         struct hw_mode_spec *spec = &rt2x00dev->spec;
2499         struct channel_info *info;
2500         char *tx_power1;
2501         char *tx_power2;
2502         unsigned int i;
2503         u16 eeprom;
2504
2505         /*
2506          * Initialize all hw fields.
2507          */
2508         rt2x00dev->hw->flags =
2509             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2510             IEEE80211_HW_SIGNAL_DBM |
2511             IEEE80211_HW_SUPPORTS_PS |
2512             IEEE80211_HW_PS_NULLFUNC_STACK;
2513         rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2514
2515         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2516         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2517                                 rt2x00_eeprom_addr(rt2x00dev,
2518                                                    EEPROM_MAC_ADDR_0));
2519
2520         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2521
2522         /*
2523          * Initialize HT information.
2524          */
2525         spec->ht.ht_supported = true;
2526         spec->ht.cap =
2527             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2528             IEEE80211_HT_CAP_GRN_FLD |
2529             IEEE80211_HT_CAP_SGI_20 |
2530             IEEE80211_HT_CAP_SGI_40 |
2531             IEEE80211_HT_CAP_TX_STBC |
2532             IEEE80211_HT_CAP_RX_STBC |
2533             IEEE80211_HT_CAP_PSMP_SUPPORT;
2534         spec->ht.ampdu_factor = 3;
2535         spec->ht.ampdu_density = 4;
2536         spec->ht.mcs.tx_params =
2537             IEEE80211_HT_MCS_TX_DEFINED |
2538             IEEE80211_HT_MCS_TX_RX_DIFF |
2539             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2540                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2541
2542         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2543         case 3:
2544                 spec->ht.mcs.rx_mask[2] = 0xff;
2545         case 2:
2546                 spec->ht.mcs.rx_mask[1] = 0xff;
2547         case 1:
2548                 spec->ht.mcs.rx_mask[0] = 0xff;
2549                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2550                 break;
2551         }
2552
2553         /*
2554          * Initialize hw_mode information.
2555          */
2556         spec->supported_bands = SUPPORT_BAND_2GHZ;
2557         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2558
2559         if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2560             rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2561                 spec->num_channels = 14;
2562                 spec->channels = rf_vals;
2563         } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2564                    rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2565                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2566                 spec->num_channels = ARRAY_SIZE(rf_vals);
2567                 spec->channels = rf_vals;
2568         } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2569                    rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2570                 spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2571                 spec->channels = rf_vals_3070;
2572         }
2573
2574         /*
2575          * Create channel information array
2576          */
2577         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2578         if (!info)
2579                 return -ENOMEM;
2580
2581         spec->channels_info = info;
2582
2583         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2584         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2585
2586         for (i = 0; i < 14; i++) {
2587                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2588                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2589         }
2590
2591         if (spec->num_channels > 14) {
2592                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2593                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2594
2595                 for (i = 14; i < spec->num_channels; i++) {
2596                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2597                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2598                 }
2599         }
2600
2601         return 0;
2602 }
2603
2604 static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2605 {
2606         int retval;
2607
2608         /*
2609          * Allocate eeprom data.
2610          */
2611         retval = rt2800usb_validate_eeprom(rt2x00dev);
2612         if (retval)
2613                 return retval;
2614
2615         retval = rt2800usb_init_eeprom(rt2x00dev);
2616         if (retval)
2617                 return retval;
2618
2619         /*
2620          * Initialize hw specifications.
2621          */
2622         retval = rt2800usb_probe_hw_mode(rt2x00dev);
2623         if (retval)
2624                 return retval;
2625
2626         /*
2627          * This device has multiple filters for control frames
2628          * and has a separate filter for PS Poll frames.
2629          */
2630         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2631         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
2632
2633         /*
2634          * This device requires firmware.
2635          */
2636         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2637         __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2638         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2639         if (!modparam_nohwcrypt)
2640                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2641
2642         /*
2643          * Set the rssi offset.
2644          */
2645         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2646
2647         return 0;
2648 }
2649
2650 /*
2651  * IEEE80211 stack callback functions.
2652  */
2653 static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2654                                    u32 *iv32, u16 *iv16)
2655 {
2656         struct rt2x00_dev *rt2x00dev = hw->priv;
2657         struct mac_iveiv_entry iveiv_entry;
2658         u32 offset;
2659
2660         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2661         rt2x00usb_register_multiread(rt2x00dev, offset,
2662                                       &iveiv_entry, sizeof(iveiv_entry));
2663
2664         memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2665         memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2666 }
2667
2668 static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2669 {
2670         struct rt2x00_dev *rt2x00dev = hw->priv;
2671         u32 reg;
2672         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2673
2674         rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2675         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2676         rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2677
2678         rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2679         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2680         rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2681
2682         rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2683         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2684         rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2685
2686         rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2687         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2688         rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2689
2690         rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2691         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2692         rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2693
2694         rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2695         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2696         rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2697
2698         rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2699         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2700         rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2701
2702         return 0;
2703 }
2704
2705 static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2706                              const struct ieee80211_tx_queue_params *params)
2707 {
2708         struct rt2x00_dev *rt2x00dev = hw->priv;
2709         struct data_queue *queue;
2710         struct rt2x00_field32 field;
2711         int retval;
2712         u32 reg;
2713         u32 offset;
2714
2715         /*
2716          * First pass the configuration through rt2x00lib, that will
2717          * update the queue settings and validate the input. After that
2718          * we are free to update the registers based on the value
2719          * in the queue parameter.
2720          */
2721         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2722         if (retval)
2723                 return retval;
2724
2725         /*
2726          * We only need to perform additional register initialization
2727          * for WMM queues/
2728          */
2729         if (queue_idx >= 4)
2730                 return 0;
2731
2732         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2733
2734         /* Update WMM TXOP register */
2735         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2736         field.bit_offset = (queue_idx & 1) * 16;
2737         field.bit_mask = 0xffff << field.bit_offset;
2738
2739         rt2x00usb_register_read(rt2x00dev, offset, &reg);
2740         rt2x00_set_field32(&reg, field, queue->txop);
2741         rt2x00usb_register_write(rt2x00dev, offset, reg);
2742
2743         /* Update WMM registers */
2744         field.bit_offset = queue_idx * 4;
2745         field.bit_mask = 0xf << field.bit_offset;
2746
2747         rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2748         rt2x00_set_field32(&reg, field, queue->aifs);
2749         rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2750
2751         rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2752         rt2x00_set_field32(&reg, field, queue->cw_min);
2753         rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2754
2755         rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2756         rt2x00_set_field32(&reg, field, queue->cw_max);
2757         rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2758
2759         /* Update EDCA registers */
2760         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2761
2762         rt2x00usb_register_read(rt2x00dev, offset, &reg);
2763         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2764         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2765         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2766         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2767         rt2x00usb_register_write(rt2x00dev, offset, reg);
2768
2769         return 0;
2770 }
2771
2772 static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2773 {
2774         struct rt2x00_dev *rt2x00dev = hw->priv;
2775         u64 tsf;
2776         u32 reg;
2777
2778         rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2779         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2780         rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2781         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2782
2783         return tsf;
2784 }
2785
2786 static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2787         .tx                     = rt2x00mac_tx,
2788         .start                  = rt2x00mac_start,
2789         .stop                   = rt2x00mac_stop,
2790         .add_interface          = rt2x00mac_add_interface,
2791         .remove_interface       = rt2x00mac_remove_interface,
2792         .config                 = rt2x00mac_config,
2793         .configure_filter       = rt2x00mac_configure_filter,
2794         .set_tim                = rt2x00mac_set_tim,
2795         .set_key                = rt2x00mac_set_key,
2796         .get_stats              = rt2x00mac_get_stats,
2797         .get_tkip_seq           = rt2800usb_get_tkip_seq,
2798         .set_rts_threshold      = rt2800usb_set_rts_threshold,
2799         .bss_info_changed       = rt2x00mac_bss_info_changed,
2800         .conf_tx                = rt2800usb_conf_tx,
2801         .get_tx_stats           = rt2x00mac_get_tx_stats,
2802         .get_tsf                = rt2800usb_get_tsf,
2803         .rfkill_poll            = rt2x00mac_rfkill_poll,
2804 };
2805
2806 static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2807         .probe_hw               = rt2800usb_probe_hw,
2808         .get_firmware_name      = rt2800usb_get_firmware_name,
2809         .check_firmware         = rt2800usb_check_firmware,
2810         .load_firmware          = rt2800usb_load_firmware,
2811         .initialize             = rt2x00usb_initialize,
2812         .uninitialize           = rt2x00usb_uninitialize,
2813         .clear_entry            = rt2x00usb_clear_entry,
2814         .set_device_state       = rt2800usb_set_device_state,
2815         .rfkill_poll            = rt2800usb_rfkill_poll,
2816         .link_stats             = rt2800usb_link_stats,
2817         .reset_tuner            = rt2800usb_reset_tuner,
2818         .link_tuner             = rt2800usb_link_tuner,
2819         .write_tx_desc          = rt2800usb_write_tx_desc,
2820         .write_tx_data          = rt2x00usb_write_tx_data,
2821         .write_beacon           = rt2800usb_write_beacon,
2822         .get_tx_data_len        = rt2800usb_get_tx_data_len,
2823         .kick_tx_queue          = rt2800usb_kick_tx_queue,
2824         .kill_tx_queue          = rt2x00usb_kill_tx_queue,
2825         .fill_rxdone            = rt2800usb_fill_rxdone,
2826         .config_shared_key      = rt2800usb_config_shared_key,
2827         .config_pairwise_key    = rt2800usb_config_pairwise_key,
2828         .config_filter          = rt2800usb_config_filter,
2829         .config_intf            = rt2800usb_config_intf,
2830         .config_erp             = rt2800usb_config_erp,
2831         .config_ant             = rt2800usb_config_ant,
2832         .config                 = rt2800usb_config,
2833 };
2834
2835 static const struct data_queue_desc rt2800usb_queue_rx = {
2836         .entry_num              = RX_ENTRIES,
2837         .data_size              = AGGREGATION_SIZE,
2838         .desc_size              = RXD_DESC_SIZE + RXWI_DESC_SIZE,
2839         .priv_size              = sizeof(struct queue_entry_priv_usb),
2840 };
2841
2842 static const struct data_queue_desc rt2800usb_queue_tx = {
2843         .entry_num              = TX_ENTRIES,
2844         .data_size              = AGGREGATION_SIZE,
2845         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2846         .priv_size              = sizeof(struct queue_entry_priv_usb),
2847 };
2848
2849 static const struct data_queue_desc rt2800usb_queue_bcn = {
2850         .entry_num              = 8 * BEACON_ENTRIES,
2851         .data_size              = MGMT_FRAME_SIZE,
2852         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2853         .priv_size              = sizeof(struct queue_entry_priv_usb),
2854 };
2855
2856 static const struct rt2x00_ops rt2800usb_ops = {
2857         .name           = KBUILD_MODNAME,
2858         .max_sta_intf   = 1,
2859         .max_ap_intf    = 8,
2860         .eeprom_size    = EEPROM_SIZE,
2861         .rf_size        = RF_SIZE,
2862         .tx_queues      = NUM_TX_QUEUES,
2863         .rx             = &rt2800usb_queue_rx,
2864         .tx             = &rt2800usb_queue_tx,
2865         .bcn            = &rt2800usb_queue_bcn,
2866         .lib            = &rt2800usb_rt2x00_ops,
2867         .hw             = &rt2800usb_mac80211_ops,
2868 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2869         .debugfs        = &rt2800usb_rt2x00debug,
2870 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2871 };
2872
2873 /*
2874  * rt2800usb module information.
2875  */
2876 static struct usb_device_id rt2800usb_device_table[] = {
2877         /* Abocom */
2878         { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2879         { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2880         { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2881         { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2882         { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2883         { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2884         /* AirTies */
2885         { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2886         /* Amigo */
2887         { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2888         { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2889         /* Amit */
2890         { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2891         /* ASUS */
2892         { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2893         { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2894         { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2895         { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2896         { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2897         /* AzureWave */
2898         { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2899         { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2900         { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2901         { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
2902         /* Belkin */
2903         { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2904         { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2905         { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2906         { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) },
2907         /* Buffalo */
2908         { USB_DEVICE(0x0411, 0x00e8), USB_DEVICE_DATA(&rt2800usb_ops) },
2909         { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2910         /* Conceptronic */
2911         { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2912         { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2913         { USB_DEVICE(0x14b2, 0x3c08), USB_DEVICE_DATA(&rt2800usb_ops) },
2914         { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2915         { USB_DEVICE(0x14b2, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2916         { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2917         { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2918         { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2919         { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2920         { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2921         /* Corega */
2922         { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2923         { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2924         { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2925         { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2926         { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2927         /* D-Link */
2928         { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2929         { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2930         { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
2931         { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
2932         { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
2933         { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
2934         { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2935         { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2936         /* Edimax */
2937         { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2938         { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2939         { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2940         /* Encore */
2941         { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
2942         /* EnGenius */
2943         { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2944         { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2945         { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2946         { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
2947         { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
2948         { USB_DEVICE(0x1740, 0x9801), USB_DEVICE_DATA(&rt2800usb_ops) },
2949         /* Gemtek */
2950         { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2951         /* Gigabyte */
2952         { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2953         { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2954         { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2955         /* Hawking */
2956         { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2957         { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2958         { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2959         { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2960         /* I-O DATA */
2961         { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
2962         /* LevelOne */
2963         { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
2964         { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
2965         /* Linksys */
2966         { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) },
2967         { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2968         { USB_DEVICE(0x1737, 0x0077), USB_DEVICE_DATA(&rt2800usb_ops) },
2969         /* Logitec */
2970         { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2971         { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2972         { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2973         /* Motorola */
2974         { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2975         { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) },
2976         /* Ovislink */
2977         { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2978         /* Pegatron */
2979         { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
2980         { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
2981         { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
2982         /* Philips */
2983         { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2984         /* Pla