drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 225                         const u8 command, const u8 token,
 226                         const u8 arg0, const u8 arg1)
 227 {
 228         u32 reg;
 229
 230         /*
 231          * SOC devices don't support MCU requests.
 232          */
 233         if (rt2x00_is_soc(rt2x00dev))
 234                 return;
 235
 236         mutex_lock(&rt2x00dev->csr_mutex);
 237
 238         /*
 239          * Wait until the MCU becomes available, afterwards we
 240          * can safely write the new data into the register.
 241          */
 242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 248
 249                 reg = 0;
 250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 252         }
 253
 254         mutex_unlock(&rt2x00dev->csr_mutex);
 255 }
 256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 257
 258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 259 {
 260         unsigned int i = 0;
 261         u32 reg;
 262
 263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 265                 if (reg && reg != ~0)
 266                         return 0;
 267                 msleep(1);
 268         }
 269
 270         ERROR(rt2x00dev, "Unstable hardware.\n");
 271         return -EBUSY;
 272 }
 273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 274
 275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 276 {
 277         unsigned int i;
 278         u32 reg;
 279
 280         /*
 281          * Some devices are really slow to respond here. Wait a whole second
 282          * before timing out.
 283          */
 284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 288                         return 0;
 289
 290                 msleep(10);
 291         }
 292
 293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 294         return -EACCES;
 295 }
 296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 297
 298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 299 {
 300         u16 fw_crc;
 301         u16 crc;
 302
 303         /*
 304          * The last 2 bytes in the firmware array are the crc checksum itself,
 305          * this means that we should never pass those 2 bytes to the crc
 306          * algorithm.
 307          */
 308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 309
 310         /*
 311          * Use the crc ccitt algorithm.
 312          * This will return the same value as the legacy driver which
 313          * used bit ordering reversion on the both the firmware bytes
 314          * before input input as well as on the final output.
 315          * Obviously using crc ccitt directly is much more efficient.
 316          */
 317         crc = crc_ccitt(~0, data, len - 2);
 318
 319         /*
 320          * There is a small difference between the crc-itu-t + bitrev and
 321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 322          * will be swapped, use swab16 to convert the crc to the correct
 323          * value.
 324          */
 325         crc = swab16(crc);
 326
 327         return fw_crc == crc;
 328 }
 329
 330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 331                           const u8 *data, const size_t len)
 332 {
 333         size_t offset = 0;
 334         size_t fw_len;
 335         bool multiple;
 336
 337         /*
 338          * PCI(e) & SOC devices require firmware with a length
 339          * of 8kb. USB devices require firmware files with a length
 340          * of 4kb. Certain USB chipsets however require different firmware,
 341          * which Ralink only provides attached to the original firmware
 342          * file. Thus for USB devices, firmware files have a length
 343          * which is a multiple of 4kb.
 344          */
 345         if (rt2x00_is_usb(rt2x00dev)) {
 346                 fw_len = 4096;
 347                 multiple = true;
 348         } else {
 349                 fw_len = 8192;
 350                 multiple = true;
 351         }
 352
 353         /*
 354          * Validate the firmware length
 355          */
 356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 357                 return FW_BAD_LENGTH;
 358
 359         /*
 360          * Check if the chipset requires one of the upper parts
 361          * of the firmware.
 362          */
 363         if (rt2x00_is_usb(rt2x00dev) &&
 364             !rt2x00_rt(rt2x00dev, RT2860) &&
 365             !rt2x00_rt(rt2x00dev, RT2872) &&
 366             !rt2x00_rt(rt2x00dev, RT3070) &&
 367             ((len / fw_len) == 1))
 368                 return FW_BAD_VERSION;
 369
 370         /*
 371          * 8kb firmware files must be checked as if it were
 372          * 2 separate firmware files.
 373          */
 374         while (offset < len) {
 375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 376                         return FW_BAD_CRC;
 377
 378                 offset += fw_len;
 379         }
 380
 381         return FW_OK;
 382 }
 383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 384
 385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 386                          const u8 *data, const size_t len)
 387 {
 388         unsigned int i;
 389         u32 reg;
 390
 391         /*
 392          * If driver doesn't wake up firmware here,
 393          * rt2800_load_firmware will hang forever when interface is up again.
 394          */
 395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 396
 397         /*
 398          * Wait for stable hardware.
 399          */
 400         if (rt2800_wait_csr_ready(rt2x00dev))
 401                 return -EBUSY;
 402
 403         if (rt2x00_is_pci(rt2x00dev)) {
 404                 if (rt2x00_rt(rt2x00dev, RT3572) ||
 405                     rt2x00_rt(rt2x00dev, RT5390)) {
 406                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 407                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 408                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 409                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 410                 }
 411                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 412         }
 413
 414         /*
 415          * Disable DMA, will be reenabled later when enabling
 416          * the radio.
 417          */
 418         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 419         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 420         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 421         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 422         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 423         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 424         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 425
 426         /*
 427          * Write firmware to the device.
 428          */
 429         rt2800_drv_write_firmware(rt2x00dev, data, len);
 430
 431         /*
 432          * Wait for device to stabilize.
 433          */
 434         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 435                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 436                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 437                         break;
 438                 msleep(1);
 439         }
 440
 441         if (i == REGISTER_BUSY_COUNT) {
 442                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 443                 return -EBUSY;
 444         }
 445
 446         /*
 447          * Initialize firmware.
 448          */
 449         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 450         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 451         msleep(1);
 452
 453         return 0;
 454 }
 455 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 456
 457 void rt2800_write_tx_data(struct queue_entry *entry,
 458                           struct txentry_desc *txdesc)
 459 {
 460         __le32 *txwi = rt2800_drv_get_txwi(entry);
 461         u32 word;
 462
 463         /*
 464          * Initialize TX Info descriptor
 465          */
 466         rt2x00_desc_read(txwi, 0, &word);
 467         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 468                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 469         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 470                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 471         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 472         rt2x00_set_field32(&word, TXWI_W0_TS,
 473                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 474         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 475                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 476         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 477                            txdesc->u.ht.mpdu_density);
 478         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 479         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 480         rt2x00_set_field32(&word, TXWI_W0_BW,
 481                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 482         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 483                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 484         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 485         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 486         rt2x00_desc_write(txwi, 0, word);
 487
 488         rt2x00_desc_read(txwi, 1, &word);
 489         rt2x00_set_field32(&word, TXWI_W1_ACK,
 490                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 491         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 492                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 493         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 494         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 495                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 496                            txdesc->key_idx : 0xff);
 497         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 498                            txdesc->length);
 499         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 500         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 501         rt2x00_desc_write(txwi, 1, word);
 502
 503         /*
 504          * Always write 0 to IV/EIV fields, hardware will insert the IV
 505          * from the IVEIV register when TXD_W3_WIV is set to 0.
 506          * When TXD_W3_WIV is set to 1 it will use the IV data
 507          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 508          * crypto entry in the registers should be used to encrypt the frame.
 509          */
 510         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 511         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 512 }
 513 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 514
 515 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 516 {
 517         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 518         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 519         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 520         u16 eeprom;
 521         u8 offset0;
 522         u8 offset1;
 523         u8 offset2;
 524
 525         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 526                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 527                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 528                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 529                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 530                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 531         } else {
 532                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 533                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 534                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 535                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 536                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 537         }
 538
 539         /*
 540          * Convert the value from the descriptor into the RSSI value
 541          * If the value in the descriptor is 0, it is considered invalid
 542          * and the default (extremely low) rssi value is assumed
 543          */
 544         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 545         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 546         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 547
 548         /*
 549          * mac80211 only accepts a single RSSI value. Calculating the
 550          * average doesn't deliver a fair answer either since -60:-60 would
 551          * be considered equally good as -50:-70 while the second is the one
 552          * which gives less energy...
 553          */
 554         rssi0 = max(rssi0, rssi1);
 555         return max(rssi0, rssi2);
 556 }
 557
 558 void rt2800_process_rxwi(struct queue_entry *entry,
 559                          struct rxdone_entry_desc *rxdesc)
 560 {
 561         __le32 *rxwi = (__le32 *) entry->skb->data;
 562         u32 word;
 563
 564         rt2x00_desc_read(rxwi, 0, &word);
 565
 566         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 567         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 568
 569         rt2x00_desc_read(rxwi, 1, &word);
 570
 571         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 572                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 573
 574         if (rt2x00_get_field32(word, RXWI_W1_BW))
 575                 rxdesc->flags |= RX_FLAG_40MHZ;
 576
 577         /*
 578          * Detect RX rate, always use MCS as signal type.
 579          */
 580         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 581         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 582         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 583
 584         /*
 585          * Mask of 0x8 bit to remove the short preamble flag.
 586          */
 587         if (rxdesc->rate_mode == RATE_MODE_CCK)
 588                 rxdesc->signal &= ~0x8;
 589
 590         rt2x00_desc_read(rxwi, 2, &word);
 591
 592         /*
 593          * Convert descriptor AGC value to RSSI value.
 594          */
 595         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 596
 597         /*
 598          * Remove RXWI descriptor from start of buffer.
 599          */
 600         skb_pull(entry->skb, RXWI_DESC_SIZE);
 601 }
 602 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 603
 604 void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
 605 {
 606         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 607         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 608         struct txdone_entry_desc txdesc;
 609         u32 word;
 610         u16 mcs, real_mcs;
 611         int aggr, ampdu;
 612         __le32 *txwi;
 613
 614         /*
 615          * Obtain the status about this packet.
 616          */
 617         txdesc.flags = 0;
 618         txwi = rt2800_drv_get_txwi(entry);
 619         rt2x00_desc_read(txwi, 0, &word);
 620
 621         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 622         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 623
 624         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 625         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 626
 627         /*
 628          * If a frame was meant to be sent as a single non-aggregated MPDU
 629          * but ended up in an aggregate the used tx rate doesn't correlate
 630          * with the one specified in the TXWI as the whole aggregate is sent
 631          * with the same rate.
 632          *
 633          * For example: two frames are sent to rt2x00, the first one sets
 634          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 635          * and requests MCS15. If the hw aggregates both frames into one
 636          * AMDPU the tx status for both frames will contain MCS7 although
 637          * the frame was sent successfully.
 638          *
 639          * Hence, replace the requested rate with the real tx rate to not
 640          * confuse the rate control algortihm by providing clearly wrong
 641          * data.
 642          */
 643         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 644                 skbdesc->tx_rate_idx = real_mcs;
 645                 mcs = real_mcs;
 646         }
 647
 648         if (aggr == 1 || ampdu == 1)
 649                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 650
 651         /*
 652          * Ralink has a retry mechanism using a global fallback
 653          * table. We setup this fallback table to try the immediate
 654          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 655          * always contains the MCS used for the last transmission, be
 656          * it successful or not.
 657          */
 658         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 659                 /*
 660                  * Transmission succeeded. The number of retries is
 661                  * mcs - real_mcs
 662                  */
 663                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 664                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 665         } else {
 666                 /*
 667                  * Transmission failed. The number of retries is
 668                  * always 7 in this case (for a total number of 8
 669                  * frames sent).
 670                  */
 671                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 672                 txdesc.retry = rt2x00dev->long_retry;
 673         }
 674
 675         /*
 676          * the frame was retried at least once
 677          * -> hw used fallback rates
 678          */
 679         if (txdesc.retry)
 680                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 681
 682         rt2x00lib_txdone(entry, &txdesc);
 683 }
 684 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 685
 686 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 687 {
 688         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 689         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 690         unsigned int beacon_base;
 691         unsigned int padding_len;
 692         u32 orig_reg, reg;
 693
 694         /*
 695          * Disable beaconing while we are reloading the beacon data,
 696          * otherwise we might be sending out invalid data.
 697          */
 698         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 699         orig_reg = reg;
 700         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 701         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 702
 703         /*
 704          * Add space for the TXWI in front of the skb.
 705          */
 706         memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
 707
 708         /*
 709          * Register descriptor details in skb frame descriptor.
 710          */
 711         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 712         skbdesc->desc = entry->skb->data;
 713         skbdesc->desc_len = TXWI_DESC_SIZE;
 714
 715         /*
 716          * Add the TXWI for the beacon to the skb.
 717          */
 718         rt2800_write_tx_data(entry, txdesc);
 719
 720         /*
 721          * Dump beacon to userspace through debugfs.
 722          */
 723         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 724
 725         /*
 726          * Write entire beacon with TXWI and padding to register.
 727          */
 728         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 729         if (padding_len && skb_pad(entry->skb, padding_len)) {
 730                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
 731                 /* skb freed by skb_pad() on failure */
 732                 entry->skb = NULL;
 733                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 734                 return;
 735         }
 736
 737         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 738         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 739                                    entry->skb->len + padding_len);
 740
 741         /*
 742          * Enable beaconing again.
 743          */
 744         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 745         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 746
 747         /*
 748          * Clean up beacon skb.
 749          */
 750         dev_kfree_skb_any(entry->skb);
 751         entry->skb = NULL;
 752 }
 753 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 754
 755 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 756                                                 unsigned int beacon_base)
 757 {
 758         int i;
 759
 760         /*
 761          * For the Beacon base registers we only need to clear
 762          * the whole TXWI which (when set to 0) will invalidate
 763          * the entire beacon.
 764          */
 765         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 766                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 767 }
 768
 769 void rt2800_clear_beacon(struct queue_entry *entry)
 770 {
 771         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 772         u32 reg;
 773
 774         /*
 775          * Disable beaconing while we are reloading the beacon data,
 776          * otherwise we might be sending out invalid data.
 777          */
 778         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 779         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 780         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 781
 782         /*
 783          * Clear beacon.
 784          */
 785         rt2800_clear_beacon_register(rt2x00dev,
 786                                      HW_BEACON_OFFSET(entry->entry_idx));
 787
 788         /*
 789          * Enabled beaconing again.
 790          */
 791         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 792         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 793 }
 794 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 795
 796 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 797 const struct rt2x00debug rt2800_rt2x00debug = {
 798         .owner  = THIS_MODULE,
 799         .csr    = {
 800                 .read           = rt2800_register_read,
 801                 .write          = rt2800_register_write,
 802                 .flags          = RT2X00DEBUGFS_OFFSET,
 803                 .word_base      = CSR_REG_BASE,
 804                 .word_size      = sizeof(u32),
 805                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 806         },
 807         .eeprom = {
 808                 .read           = rt2x00_eeprom_read,
 809                 .write          = rt2x00_eeprom_write,
 810                 .word_base      = EEPROM_BASE,
 811                 .word_size      = sizeof(u16),
 812                 .word_count     = EEPROM_SIZE / sizeof(u16),
 813         },
 814         .bbp    = {
 815                 .read           = rt2800_bbp_read,
 816                 .write          = rt2800_bbp_write,
 817                 .word_base      = BBP_BASE,
 818                 .word_size      = sizeof(u8),
 819                 .word_count     = BBP_SIZE / sizeof(u8),
 820         },
 821         .rf     = {
 822                 .read           = rt2x00_rf_read,
 823                 .write          = rt2800_rf_write,
 824                 .word_base      = RF_BASE,
 825                 .word_size      = sizeof(u32),
 826                 .word_count     = RF_SIZE / sizeof(u32),
 827         },
 828 };
 829 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 830 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 831
 832 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 833 {
 834         u32 reg;
 835
 836         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 837         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 838 }
 839 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 840
 841 #ifdef CONFIG_RT2X00_LIB_LEDS
 842 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 843                                   enum led_brightness brightness)
 844 {
 845         struct rt2x00_led *led =
 846             container_of(led_cdev, struct rt2x00_led, led_dev);
 847         unsigned int enabled = brightness != LED_OFF;
 848         unsigned int bg_mode =
 849             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 850         unsigned int polarity =
 851                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 852                                    EEPROM_FREQ_LED_POLARITY);
 853         unsigned int ledmode =
 854                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 855                                    EEPROM_FREQ_LED_MODE);
 856         u32 reg;
 857
 858         /* Check for SoC (SOC devices don't support MCU requests) */
 859         if (rt2x00_is_soc(led->rt2x00dev)) {
 860                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 861
 862                 /* Set LED Polarity */
 863                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 864
 865                 /* Set LED Mode */
 866                 if (led->type == LED_TYPE_RADIO) {
 867                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 868                                            enabled ? 3 : 0);
 869                 } else if (led->type == LED_TYPE_ASSOC) {
 870                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 871                                            enabled ? 3 : 0);
 872                 } else if (led->type == LED_TYPE_QUALITY) {
 873                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 874                                            enabled ? 3 : 0);
 875                 }
 876
 877                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 878
 879         } else {
 880                 if (led->type == LED_TYPE_RADIO) {
 881                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 882                                               enabled ? 0x20 : 0);
 883                 } else if (led->type == LED_TYPE_ASSOC) {
 884                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 885                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 886                 } else if (led->type == LED_TYPE_QUALITY) {
 887                         /*
 888                          * The brightness is divided into 6 levels (0 - 5),
 889                          * The specs tell us the following levels:
 890                          *      0, 1 ,3, 7, 15, 31
 891                          * to determine the level in a simple way we can simply
 892                          * work with bitshifting:
 893                          *      (1 << level) - 1
 894                          */
 895                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 896                                               (1 << brightness / (LED_FULL / 6)) - 1,
 897                                               polarity);
 898                 }
 899         }
 900 }
 901
 902 static int rt2800_blink_set(struct led_classdev *led_cdev,
 903                             unsigned long *delay_on, unsigned long *delay_off)
 904 {
 905         struct rt2x00_led *led =
 906             container_of(led_cdev, struct rt2x00_led, led_dev);
 907         u32 reg;
 908
 909         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 910         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 911         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 912         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 913
 914         return 0;
 915 }
 916
 917 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 918                      struct rt2x00_led *led, enum led_type type)
 919 {
 920         led->rt2x00dev = rt2x00dev;
 921         led->type = type;
 922         led->led_dev.brightness_set = rt2800_brightness_set;
 923         led->led_dev.blink_set = rt2800_blink_set;
 924         led->flags = LED_INITIALIZED;
 925 }
 926 #endif /* CONFIG_RT2X00_LIB_LEDS */
 927
 928 /*
 929  * Configuration handlers.
 930  */
 931 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 932                                     struct rt2x00lib_crypto *crypto,
 933                                     struct ieee80211_key_conf *key)
 934 {
 935         struct mac_wcid_entry wcid_entry;
 936         struct mac_iveiv_entry iveiv_entry;
 937         u32 offset;
 938         u32 reg;
 939
 940         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 941
 942         if (crypto->cmd == SET_KEY) {
 943                 rt2800_register_read(rt2x00dev, offset, &reg);
 944                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 945                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 946                 /*
 947                  * Both the cipher as the BSS Idx numbers are split in a main
 948                  * value of 3 bits, and a extended field for adding one additional
 949                  * bit to the value.
 950                  */
 951                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 952                                    (crypto->cipher & 0x7));
 953                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
 954                                    (crypto->cipher & 0x8) >> 3);
 955                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 956                                    (crypto->bssidx & 0x7));
 957                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
 958                                    (crypto->bssidx & 0x8) >> 3);
 959                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 960                 rt2800_register_write(rt2x00dev, offset, reg);
 961         } else {
 962                 rt2800_register_write(rt2x00dev, offset, 0);
 963         }
 964
 965         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 966
 967         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 968         if ((crypto->cipher == CIPHER_TKIP) ||
 969             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 970             (crypto->cipher == CIPHER_AES))
 971                 iveiv_entry.iv[3] |= 0x20;
 972         iveiv_entry.iv[3] |= key->keyidx << 6;
 973         rt2800_register_multiwrite(rt2x00dev, offset,
 974                                       &iveiv_entry, sizeof(iveiv_entry));
 975
 976         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 977
 978         memset(&wcid_entry, 0, sizeof(wcid_entry));
 979         if (crypto->cmd == SET_KEY)
 980                 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
 981         rt2800_register_multiwrite(rt2x00dev, offset,
 982                                       &wcid_entry, sizeof(wcid_entry));
 983 }
 984
 985 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 986                              struct rt2x00lib_crypto *crypto,
 987                              struct ieee80211_key_conf *key)
 988 {
 989         struct hw_key_entry key_entry;
 990         struct rt2x00_field32 field;
 991         u32 offset;
 992         u32 reg;
 993
 994         if (crypto->cmd == SET_KEY) {
 995                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 996
 997                 memcpy(key_entry.key, crypto->key,
 998                        sizeof(key_entry.key));
 999                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1000                        sizeof(key_entry.tx_mic));
1001                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1002                        sizeof(key_entry.rx_mic));
1003
1004                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1005                 rt2800_register_multiwrite(rt2x00dev, offset,
1006                                               &key_entry, sizeof(key_entry));
1007         }
1008
1009         /*
1010          * The cipher types are stored over multiple registers
1011          * starting with SHARED_KEY_MODE_BASE each word will have
1012          * 32 bits and contains the cipher types for 2 bssidx each.
1013          * Using the correct defines correctly will cause overhead,
1014          * so just calculate the correct offset.
1015          */
1016         field.bit_offset = 4 * (key->hw_key_idx % 8);
1017         field.bit_mask = 0x7 << field.bit_offset;
1018
1019         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1020
1021         rt2800_register_read(rt2x00dev, offset, &reg);
1022         rt2x00_set_field32(&reg, field,
1023                            (crypto->cmd == SET_KEY) * crypto->cipher);
1024         rt2800_register_write(rt2x00dev, offset, reg);
1025
1026         /*
1027          * Update WCID information
1028          */
1029         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1030
1031         return 0;
1032 }
1033 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1034
1035 static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev *rt2x00dev)
1036 {
1037         int idx;
1038         u32 offset, reg;
1039
1040         /*
1041          * Search for the first free pairwise key entry and return the
1042          * corresponding index.
1043          *
1044          * Make sure the WCID starts _after_ the last possible shared key
1045          * entry (>32).
1046          *
1047          * Since parts of the pairwise key table might be shared with
1048          * the beacon frame buffers 6 & 7 we should only write into the
1049          * first 222 entries.
1050          */
1051         for (idx = 33; idx <= 222; idx++) {
1052                 offset = MAC_WCID_ATTR_ENTRY(idx);
1053                 rt2800_register_read(rt2x00dev, offset, &reg);
1054                 if (!reg)
1055                         return idx;
1056         }
1057         return -1;
1058 }
1059
1060 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1061                                struct rt2x00lib_crypto *crypto,
1062                                struct ieee80211_key_conf *key)
1063 {
1064         struct hw_key_entry key_entry;
1065         u32 offset;
1066         int idx;
1067
1068         if (crypto->cmd == SET_KEY) {
1069                 idx = rt2800_find_pairwise_keyslot(rt2x00dev);
1070                 if (idx < 0)
1071                         return -ENOSPC;
1072                 key->hw_key_idx = idx;
1073
1074                 memcpy(key_entry.key, crypto->key,
1075                        sizeof(key_entry.key));
1076                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1077                        sizeof(key_entry.tx_mic));
1078                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1079                        sizeof(key_entry.rx_mic));
1080
1081                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1082                 rt2800_register_multiwrite(rt2x00dev, offset,
1083                                               &key_entry, sizeof(key_entry));
1084         }
1085
1086         /*
1087          * Update WCID information
1088          */
1089         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1090
1091         return 0;
1092 }
1093 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1094
1095 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1096                           const unsigned int filter_flags)
1097 {
1098         u32 reg;
1099
1100         /*
1101          * Start configuration steps.
1102          * Note that the version error will always be dropped
1103          * and broadcast frames will always be accepted since
1104          * there is no filter for it at this time.
1105          */
1106         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1107         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1108                            !(filter_flags & FIF_FCSFAIL));
1109         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1110                            !(filter_flags & FIF_PLCPFAIL));
1111         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1112                            !(filter_flags & FIF_PROMISC_IN_BSS));
1113         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1114         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1115         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1116                            !(filter_flags & FIF_ALLMULTI));
1117         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1118         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1119         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1120                            !(filter_flags & FIF_CONTROL));
1121         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1122                            !(filter_flags & FIF_CONTROL));
1123         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1124                            !(filter_flags & FIF_CONTROL));
1125         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1126                            !(filter_flags & FIF_CONTROL));
1127         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1128                            !(filter_flags & FIF_CONTROL));
1129         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1130                            !(filter_flags & FIF_PSPOLL));
1131         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1132         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1133         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1134                            !(filter_flags & FIF_CONTROL));
1135         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1136 }
1137 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1138
1139 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1140                         struct rt2x00intf_conf *conf, const unsigned int flags)
1141 {
1142         u32 reg;
1143         bool update_bssid = false;
1144
1145         if (flags & CONFIG_UPDATE_TYPE) {
1146                 /*
1147                  * Enable synchronisation.
1148                  */
1149                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1150                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1151                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1152
1153                 if (conf->sync == TSF_SYNC_AP_NONE) {
1154                         /*
1155                          * Tune beacon queue transmit parameters for AP mode
1156                          */
1157                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1158                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1159                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1160                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1161                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1162                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1163                 } else {
1164                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1165                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1166                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1167                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1168                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1169                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1170                 }
1171         }
1172
1173         if (flags & CONFIG_UPDATE_MAC) {
1174                 if (flags & CONFIG_UPDATE_TYPE &&
1175                     conf->sync == TSF_SYNC_AP_NONE) {
1176                         /*
1177                          * The BSSID register has to be set to our own mac
1178                          * address in AP mode.
1179                          */
1180                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1181                         update_bssid = true;
1182                 }
1183
1184                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1185                         reg = le32_to_cpu(conf->mac[1]);
1186                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1187                         conf->mac[1] = cpu_to_le32(reg);
1188                 }
1189
1190                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1191                                               conf->mac, sizeof(conf->mac));
1192         }
1193
1194         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1195                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1196                         reg = le32_to_cpu(conf->bssid[1]);
1197                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1198                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1199                         conf->bssid[1] = cpu_to_le32(reg);
1200                 }
1201
1202                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1203                                               conf->bssid, sizeof(conf->bssid));
1204         }
1205 }
1206 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1207
1208 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1209                                     struct rt2x00lib_erp *erp)
1210 {
1211         bool any_sta_nongf = !!(erp->ht_opmode &
1212                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1213         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1214         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1215         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1216         u32 reg;
1217
1218         /* default protection rate for HT20: OFDM 24M */
1219         mm20_rate = gf20_rate = 0x4004;
1220
1221         /* default protection rate for HT40: duplicate OFDM 24M */
1222         mm40_rate = gf40_rate = 0x4084;
1223
1224         switch (protection) {
1225         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1226                 /*
1227                  * All STAs in this BSS are HT20/40 but there might be
1228                  * STAs not supporting greenfield mode.
1229                  * => Disable protection for HT transmissions.
1230                  */
1231                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1232
1233                 break;
1234         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1235                 /*
1236                  * All STAs in this BSS are HT20 or HT20/40 but there
1237                  * might be STAs not supporting greenfield mode.
1238                  * => Protect all HT40 transmissions.
1239                  */
1240                 mm20_mode = gf20_mode = 0;
1241                 mm40_mode = gf40_mode = 2;
1242
1243                 break;
1244         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1245                 /*
1246                  * Nonmember protection:
1247                  * According to 802.11n we _should_ protect all
1248                  * HT transmissions (but we don't have to).
1249                  *
1250                  * But if cts_protection is enabled we _shall_ protect
1251                  * all HT transmissions using a CCK rate.
1252                  *
1253                  * And if any station is non GF we _shall_ protect
1254                  * GF transmissions.
1255                  *
1256                  * We decide to protect everything
1257                  * -> fall through to mixed mode.
1258                  */
1259         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1260                 /*
1261                  * Legacy STAs are present
1262                  * => Protect all HT transmissions.
1263                  */
1264                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1265
1266                 /*
1267                  * If erp protection is needed we have to protect HT
1268                  * transmissions with CCK 11M long preamble.
1269                  */
1270                 if (erp->cts_protection) {
1271                         /* don't duplicate RTS/CTS in CCK mode */
1272                         mm20_rate = mm40_rate = 0x0003;
1273                         gf20_rate = gf40_rate = 0x0003;
1274                 }
1275                 break;
1276         }
1277
1278         /* check for STAs not supporting greenfield mode */
1279         if (any_sta_nongf)
1280                 gf20_mode = gf40_mode = 2;
1281
1282         /* Update HT protection config */
1283         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1284         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1285         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1286         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1287
1288         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1289         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1290         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1291         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1292
1293         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1294         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1295         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1296         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1297
1298         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1299         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1300         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1301         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1302 }
1303
1304 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1305                        u32 changed)
1306 {
1307         u32 reg;
1308
1309         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1310                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1311                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1312                                    !!erp->short_preamble);
1313                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1314                                    !!erp->short_preamble);
1315                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1316         }
1317
1318         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1319                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1320                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1321                                    erp->cts_protection ? 2 : 0);
1322                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1323         }
1324
1325         if (changed & BSS_CHANGED_BASIC_RATES) {
1326                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1327                                          erp->basic_rates);
1328                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1329         }
1330
1331         if (changed & BSS_CHANGED_ERP_SLOT) {
1332                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1333                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1334                                    erp->slot_time);
1335                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1336
1337                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1338                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1339                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1340         }
1341
1342         if (changed & BSS_CHANGED_BEACON_INT) {
1343                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1344                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1345                                    erp->beacon_int * 16);
1346                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1347         }
1348
1349         if (changed & BSS_CHANGED_HT)
1350                 rt2800_config_ht_opmode(rt2x00dev, erp);
1351 }
1352 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1353
1354 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1355 {
1356         u32 reg;
1357         u16 eeprom;
1358         u8 led_ctrl, led_g_mode, led_r_mode;
1359
1360         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1361         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1362                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1363                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1364         } else {
1365                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1366                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1367         }
1368         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1369
1370         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1371         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1372         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1373         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1374             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1375                 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1376                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1377                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1378                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1379                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1380                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1381                 } else {
1382                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1383                                            (led_g_mode << 2) | led_r_mode, 1);
1384                 }
1385         }
1386 }
1387
1388 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1389                                      enum antenna ant)
1390 {
1391         u32 reg;
1392         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1393         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1394
1395         if (rt2x00_is_pci(rt2x00dev)) {
1396                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1397                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1398                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1399         } else if (rt2x00_is_usb(rt2x00dev))
1400                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1401                                    eesk_pin, 0);
1402
1403         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1404         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1405         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1406         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1407 }
1408
1409 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1410 {
1411         u8 r1;
1412         u8 r3;
1413         u16 eeprom;
1414
1415         rt2800_bbp_read(rt2x00dev, 1, &r1);
1416         rt2800_bbp_read(rt2x00dev, 3, &r3);
1417
1418         if (rt2x00_rt(rt2x00dev, RT3572) &&
1419             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1420                 rt2800_config_3572bt_ant(rt2x00dev);
1421
1422         /*
1423          * Configure the TX antenna.
1424          */
1425         switch (ant->tx_chain_num) {
1426         case 1:
1427                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1428                 break;
1429         case 2:
1430                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1431                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1432                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1433                 else
1434                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1435                 break;
1436         case 3:
1437                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1438                 break;
1439         }
1440
1441         /*
1442          * Configure the RX antenna.
1443          */
1444         switch (ant->rx_chain_num) {
1445         case 1:
1446                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1447                     rt2x00_rt(rt2x00dev, RT3090) ||
1448                     rt2x00_rt(rt2x00dev, RT3390)) {
1449                         rt2x00_eeprom_read(rt2x00dev,
1450                                            EEPROM_NIC_CONF1, &eeprom);
1451                         if (rt2x00_get_field16(eeprom,
1452                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1453                                 rt2800_set_ant_diversity(rt2x00dev,
1454                                                 rt2x00dev->default_ant.rx);
1455                 }
1456                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1457                 break;
1458         case 2:
1459                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1460                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1461                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1462                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1463                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1464                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1465                 } else {
1466                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1467                 }
1468                 break;
1469         case 3:
1470                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1471                 break;
1472         }
1473
1474         rt2800_bbp_write(rt2x00dev, 3, r3);
1475         rt2800_bbp_write(rt2x00dev, 1, r1);
1476 }
1477 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1478
1479 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1480                                    struct rt2x00lib_conf *libconf)
1481 {
1482         u16 eeprom;
1483         short lna_gain;
1484
1485         if (libconf->rf.channel <= 14) {
1486                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1487                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1488         } else if (libconf->rf.channel <= 64) {
1489                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1490                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1491         } else if (libconf->rf.channel <= 128) {
1492                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1493                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1494         } else {
1495                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1496                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1497         }
1498
1499         rt2x00dev->lna_gain = lna_gain;
1500 }
1501
1502 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1503                                          struct ieee80211_conf *conf,
1504                                          struct rf_channel *rf,
1505                                          struct channel_info *info)
1506 {
1507         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1508
1509         if (rt2x00dev->default_ant.tx_chain_num == 1)
1510                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1511
1512         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1513                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1514                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1515         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1516                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1517
1518         if (rf->channel > 14) {
1519                 /*
1520                  * When TX power is below 0, we should increase it by 7 to
1521                  * make it a positive value (Minimum value is -7).
1522                  * However this means that values between 0 and 7 have
1523                  * double meaning, and we should set a 7DBm boost flag.
1524                  */
1525                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1526                                    (info->default_power1 >= 0));
1527
1528                 if (info->default_power1 < 0)
1529                         info->default_power1 += 7;
1530
1531                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1532
1533                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1534                                    (info->default_power2 >= 0));
1535
1536                 if (info->default_power2 < 0)
1537                         info->default_power2 += 7;
1538
1539                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1540         } else {
1541                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1542                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1543         }
1544
1545         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1546
1547         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1548         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1549         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1550         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1551
1552         udelay(200);
1553
1554         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1555         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1556         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1557         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1558
1559         udelay(200);
1560
1561         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1562         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1563         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1564         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1565 }
1566
1567 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1568                                          struct ieee80211_conf *conf,
1569                                          struct rf_channel *rf,
1570                                          struct channel_info *info)
1571 {
1572         u8 rfcsr;
1573
1574         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1575         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1576
1577         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1578         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1579         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1580
1581         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1582         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1583         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1584
1585         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1586         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1587         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1588
1589         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1590         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1591         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1592
1593         rt2800_rfcsr_write(rt2x00dev, 24,
1594                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1595
1596         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1597         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1598         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1599 }
1600
1601 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1602                                          struct ieee80211_conf *conf,
1603                                          struct rf_channel *rf,
1604                                          struct channel_info *info)
1605 {
1606         u8 rfcsr;
1607         u32 reg;
1608
1609         if (rf->channel <= 14) {
1610                 rt2800_bbp_write(rt2x00dev, 25, 0x15);
1611                 rt2800_bbp_write(rt2x00dev, 26, 0x85);
1612         } else {
1613                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1614                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1615         }
1616
1617         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1618         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1619
1620         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1621         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1622         if (rf->channel <= 14)
1623                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1624         else
1625                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1626         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1627
1628         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1629         if (rf->channel <= 14)
1630                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1631         else
1632                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1633         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1634
1635         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1636         if (rf->channel <= 14) {
1637                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1638                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1639                                 (info->default_power1 & 0x3) |
1640                                 ((info->default_power1 & 0xC) << 1));
1641         } else {
1642                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1643                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1644                                 (info->default_power1 & 0x3) |
1645                                 ((info->default_power1 & 0xC) << 1));
1646         }
1647         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1648
1649         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1650         if (rf->channel <= 14) {
1651                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1652                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1653                                 (info->default_power2 & 0x3) |
1654                                 ((info->default_power2 & 0xC) << 1));
1655         } else {
1656                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1657                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1658                                 (info->default_power2 & 0x3) |
1659                                 ((info->default_power2 & 0xC) << 1));
1660         }
1661         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1662
1663         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1664         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1665         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1666         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1667         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1668         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1669         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1670                 if (rf->channel <= 14) {
1671                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1672                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1673                 }
1674                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1675                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1676         } else {
1677                 switch (rt2x00dev->default_ant.tx_chain_num) {
1678                 case 1:
1679                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1680                 case 2:
1681                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1682                         break;
1683                 }
1684
1685                 switch (rt2x00dev->default_ant.rx_chain_num) {
1686                 case 1:
1687                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1688                 case 2:
1689                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1690                         break;
1691                 }
1692         }
1693         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1694
1695         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1696         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1697         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1698
1699         rt2800_rfcsr_write(rt2x00dev, 24,
1700                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1701         rt2800_rfcsr_write(rt2x00dev, 31,
1702                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1703
1704         if (rf->channel <= 14) {
1705                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1706                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1707                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1708                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1709                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1710                 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
1711                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1712                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1713                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1714                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1715                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1716                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1717                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1718         } else {
1719                 rt2800_rfcsr_write(rt2x00dev, 7, 0x14);
1720                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1721                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1722                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1723                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1724                 rt2800_rfcsr_write(rt2x00dev, 16, 0x7a);
1725                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1726                 if (rf->channel <= 64) {
1727                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1728                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1729                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1730                 } else if (rf->channel <= 128) {
1731                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1732                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1733                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1734                 } else {
1735                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1736                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1737                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1738                 }
1739                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1740                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1741                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1742         }
1743
1744         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1745         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1746         if (rf->channel <= 14)
1747                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1748         else
1749                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1750         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1751
1752         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1753         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1754         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1755 }
1756
1757 #define RT5390_POWER_BOUND     0x27
1758 #define RT5390_FREQ_OFFSET_BOUND       0x5f
1759
1760 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1761                                          struct ieee80211_conf *conf,
1762                                          struct rf_channel *rf,
1763                                          struct channel_info *info)
1764 {
1765         u8 rfcsr;
1766
1767         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1768         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1769         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1770         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1771         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1772
1773         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1774         if (info->default_power1 > RT5390_POWER_BOUND)
1775                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1776         else
1777                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1778         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1779
1780         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1781         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1782         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1783         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1784         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1785         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1786
1787         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1788         if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1789                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1790                                   RT5390_FREQ_OFFSET_BOUND);
1791         else
1792                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1793         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1794
1795         if (rf->channel <= 14) {
1796                 int idx = rf->channel-1;
1797
1798                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1799                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1800                                 /* r55/r59 value array of channel 1~14 */
1801                                 static const char r55_bt_rev[] = {0x83, 0x83,
1802                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1803                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1804                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
1805                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1806                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1807
1808                                 rt2800_rfcsr_write(rt2x00dev, 55,
1809                                                    r55_bt_rev[idx]);
1810                                 rt2800_rfcsr_write(rt2x00dev, 59,
1811                                                    r59_bt_rev[idx]);
1812                         } else {
1813                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1814                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1815                                         0x88, 0x88, 0x86, 0x85, 0x84};
1816
1817                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1818                         }
1819                 } else {
1820                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1821                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
1822                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1823                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1824                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
1825                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1826                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1827
1828                                 rt2800_rfcsr_write(rt2x00dev, 55,
1829                                                    r55_nonbt_rev[idx]);
1830                                 rt2800_rfcsr_write(rt2x00dev, 59,
1831                                                    r59_nonbt_rev[idx]);
1832                         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1833                                 static const char r59_non_bt[] = {0x8f, 0x8f,
1834                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1835                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1836
1837                                 rt2800_rfcsr_write(rt2x00dev, 59,
1838                                                    r59_non_bt[idx]);
1839                         }
1840                 }
1841         }
1842
1843         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1844         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1845         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1846         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1847
1848         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1849         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1850         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1851 }
1852
1853 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1854                                   struct ieee80211_conf *conf,
1855                                   struct rf_channel *rf,
1856                                   struct channel_info *info)
1857 {
1858         u32 reg;
1859         unsigned int tx_pin;
1860         u8 bbp;
1861
1862         if (rf->channel <= 14) {
1863                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1864                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1865         } else {
1866                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1867                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1868         }
1869
1870         if (rt2x00_rf(rt2x00dev, RF2020) ||
1871             rt2x00_rf(rt2x00dev, RF3020) ||
1872             rt2x00_rf(rt2x00dev, RF3021) ||
1873             rt2x00_rf(rt2x00dev, RF3022) ||
1874             rt2x00_rf(rt2x00dev, RF3320))
1875                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1876         else if (rt2x00_rf(rt2x00dev, RF3052))
1877                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
1878         else if (rt2x00_rf(rt2x00dev, RF5370) ||
1879                  rt2x00_rf(rt2x00dev, RF5390))
1880                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1881         else
1882                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1883
1884         /*
1885          * Change BBP settings
1886          */
1887         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1888         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1889         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1890         rt2800_bbp_write(rt2x00dev, 86, 0);
1891
1892         if (rf->channel <= 14) {
1893                 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1894                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
1895                                      &rt2x00dev->cap_flags)) {
1896                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1897                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1898                         } else {
1899                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1900                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1901                         }
1902                 }
1903         } else {
1904                 if (rt2x00_rt(rt2x00dev, RT3572))
1905                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
1906                 else
1907                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1908
1909                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
1910                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1911                 else
1912                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1913         }
1914
1915         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1916         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1917         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1918         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1919         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1920
1921         if (rt2x00_rt(rt2x00dev, RT3572))
1922                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
1923
1924         tx_pin = 0;
1925
1926         /* Turn on unused PA or LNA when not using 1T or 1R */
1927         if (rt2x00dev->default_ant.tx_chain_num == 2) {
1928                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
1929                                    rf->channel > 14);
1930                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
1931                                    rf->channel <= 14);
1932         }
1933
1934         /* Turn on unused PA or LNA when not using 1T or 1R */
1935         if (rt2x00dev->default_ant.rx_chain_num == 2) {
1936                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1937                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1938         }
1939
1940         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1941         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1942         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1943         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1944         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1945                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
1946         else
1947                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
1948                                    rf->channel <= 14);
1949         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1950
1951         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1952
1953         if (rt2x00_rt(rt2x00dev, RT3572))
1954                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
1955
1956         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1957         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1958         rt2800_bbp_write(rt2x00dev, 4, bbp);
1959
1960         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1961         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1962         rt2800_bbp_write(rt2x00dev, 3, bbp);
1963
1964         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1965                 if (conf_is_ht40(conf)) {
1966                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1967                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1968                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1969                 } else {
1970                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1971                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1972                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1973                 }
1974         }
1975
1976         msleep(1);
1977
1978         /*
1979          * Clear channel statistic counters
1980          */
1981         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1982         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1983         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
1984 }
1985
1986 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
1987 {
1988         u8 tssi_bounds[9];
1989         u8 current_tssi;
1990         u16 eeprom;
1991         u8 step;
1992         int i;
1993
1994         /*
1995          * Read TSSI boundaries for temperature compensation from
1996          * the EEPROM.
1997          *
1998          * Array idx               0    1    2    3    4    5    6    7    8
1999          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
2000          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2001          */
2002         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2003                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2004                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2005                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
2006                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2007                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
2008
2009                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2010                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2011                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
2012                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2013                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
2014
2015                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2016                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2017                                         EEPROM_TSSI_BOUND_BG3_REF);
2018                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2019                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
2020
2021                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2022                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2023                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
2024                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2025                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
2026
2027                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2028                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2029                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
2030
2031                 step = rt2x00_get_field16(eeprom,
2032                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2033         } else {
2034                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2035                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2036                                         EEPROM_TSSI_BOUND_A1_MINUS4);
2037                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2038                                         EEPROM_TSSI_BOUND_A1_MINUS3);
2039
2040                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2041                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2042                                         EEPROM_TSSI_BOUND_A2_MINUS2);
2043                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2044                                         EEPROM_TSSI_BOUND_A2_MINUS1);
2045
2046                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2047                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2048                                         EEPROM_TSSI_BOUND_A3_REF);
2049                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2050                                         EEPROM_TSSI_BOUND_A3_PLUS1);
2051
2052                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2053                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2054                                         EEPROM_TSSI_BOUND_A4_PLUS2);
2055                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2056                                         EEPROM_TSSI_BOUND_A4_PLUS3);
2057
2058                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2059                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2060                                         EEPROM_TSSI_BOUND_A5_PLUS4);
2061
2062                 step = rt2x00_get_field16(eeprom,
2063                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
2064         }
2065
2066         /*
2067          * Check if temperature compensation is supported.
2068          */
2069         if (tssi_bounds[4] == 0xff)
2070                 return 0;
2071
2072         /*
2073          * Read current TSSI (BBP 49).
2074          */
2075         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2076
2077         /*
2078          * Compare TSSI value (BBP49) with the compensation boundaries
2079          * from the EEPROM and increase or decrease tx power.
2080          */
2081         for (i = 0; i <= 3; i++) {
2082                 if (current_tssi > tssi_bounds[i])
2083                         break;
2084         }
2085
2086         if (i == 4) {
2087                 for (i = 8; i >= 5; i--) {
2088                         if (current_tssi < tssi_bounds[i])
2089                                 break;
2090                 }
2091         }
2092
2093         return (i - 4) * step;
2094 }
2095
2096 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2097                                       enum ieee80211_band band)
2098 {
2099         u16 eeprom;
2100         u8 comp_en;
2101         u8 comp_type;
2102         int comp_value = 0;
2103
2104         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2105
2106         /*
2107          * HT40 compensation not required.
2108          */
2109         if (eeprom == 0xffff ||
2110             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2111                 return 0;
2112
2113         if (band == IEEE80211_BAND_2GHZ) {
2114                 comp_en = rt2x00_get_field16(eeprom,
2115                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
2116                 if (comp_en) {
2117                         comp_type = rt2x00_get_field16(eeprom,
2118                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
2119                         comp_value = rt2x00_get_field16(eeprom,
2120                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
2121                         if (!comp_type)
2122                                 comp_value = -comp_value;
2123                 }
2124         } else {
2125                 comp_en = rt2x00_get_field16(eeprom,
2126                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
2127                 if (comp_en) {
2128                         comp_type = rt2x00_get_field16(eeprom,
2129                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
2130                         comp_value = rt2x00_get_field16(eeprom,
2131                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
2132                         if (!comp_type)
2133                                 comp_value = -comp_value;
2134                 }
2135         }
2136
2137         return comp_value;
2138 }
2139
2140 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2141                                    enum ieee80211_band band, int power_level,
2142                                    u8 txpower, int delta)
2143 {
2144         u32 reg;
2145         u16 eeprom;
2146         u8 criterion;
2147         u8 eirp_txpower;
2148         u8 eirp_txpower_criterion;
2149         u8 reg_limit;
2150
2151         if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2152                 return txpower;
2153
2154         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2155                 /*
2156                  * Check if eirp txpower exceed txpower_limit.
2157                  * We use OFDM 6M as criterion and its eirp txpower
2158                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2159                  * .11b data rate need add additional 4dbm
2160                  * when calculating eirp txpower.
2161                  */
2162                 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2163                 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2164
2165                 rt2x00_eeprom_read(rt2x00dev,
2166                                    EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2167
2168                 if (band == IEEE80211_BAND_2GHZ)
2169                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2170                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2171                 else
2172                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2173                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2174
2175                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2176                                (is_rate_b ? 4 : 0) + delta;
2177
2178                 reg_limit = (eirp_txpower > power_level) ?
2179                                         (eirp_txpower - power_level) : 0;
2180         } else
2181                 reg_limit = 0;
2182
2183         return txpower + delta - reg_limit;
2184 }
2185
2186 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2187                                   enum ieee80211_band band,
2188                                   int power_level)
2189 {
2190         u8 txpower;
2191         u16 eeprom;
2192         int i, is_rate_b;
2193         u32 reg;
2194         u8 r1;
2195         u32 offset;
2196         int delta;
2197
2198         /*
2199          * Calculate HT40 compensation delta
2200          */
2201         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2202
2203         /*
2204          * calculate temperature compensation delta
2205          */
2206         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2207
2208         /*
2209          * set to normal bbp tx power control mode: +/- 0dBm
2210          */
2211         rt2800_bbp_read(rt2x00dev, 1, &r1);
2212         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2213         rt2800_bbp_write(rt2x00dev, 1, r1);
2214         offset = TX_PWR_CFG_0;
2215
2216         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2217                 /* just to be safe */
2218                 if (offset > TX_PWR_CFG_4)
2219                         break;
2220
2221                 rt2800_register_read(rt2x00dev, offset, &reg);
2222
2223                 /* read the next four txpower values */
2224                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2225                                    &eeprom);
2226
2227                 is_rate_b = i ? 0 : 1;
2228                 /*
2229                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2230                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2231                  * TX_PWR_CFG_4: unknown
2232                  */
2233                 txpower = rt2x00_get_field16(eeprom,
2234                                              EEPROM_TXPOWER_BYRATE_RATE0);
2235                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2236                                              power_level, txpower, delta);
2237                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2238
2239                 /*
2240                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2241                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2242                  * TX_PWR_CFG_4: unknown
2243                  */
2244                 txpower = rt2x00_get_field16(eeprom,
2245                                              EEPROM_TXPOWER_BYRATE_RATE1);
2246                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2247                                              power_level, txpower, delta);
2248                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2249
2250                 /*
2251                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2252                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
2253                  * TX_PWR_CFG_4: unknown
2254                  */
2255                 txpower = rt2x00_get_field16(eeprom,
2256                                              EEPROM_TXPOWER_BYRATE_RATE2);
2257                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2258                                              power_level, txpower, delta);
2259                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2260
2261                 /*
2262                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2263                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
2264                  * TX_PWR_CFG_4: unknown
2265                  */
2266                 txpower = rt2x00_get_field16(eeprom,
2267                                              EEPROM_TXPOWER_BYRATE_RATE3);
2268                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2269                                              power_level, txpower, delta);
2270                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2271
2272                 /* read the next four txpower values */
2273                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2274                                    &eeprom);
2275
2276                 is_rate_b = 0;
2277                 /*
2278                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2279                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2280                  * TX_PWR_CFG_4: unknown
2281                  */
2282                 txpower = rt2x00_get_field16(eeprom,
2283                                              EEPROM_TXPOWER_BYRATE_RATE0);
2284                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2285                                              power_level, txpower, delta);
2286                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2287
2288                 /*
2289                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2290                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2291                  * TX_PWR_CFG_4: unknown
2292                  */
2293                 txpower = rt2x00_get_field16(eeprom,
2294                                              EEPROM_TXPOWER_BYRATE_RATE1);
2295                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2296                                              power_level, txpower, delta);
2297                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2298
2299                 /*
2300                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2301                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2302                  * TX_PWR_CFG_4: unknown
2303                  */
2304                 txpower = rt2x00_get_field16(eeprom,
2305                                              EEPROM_TXPOWER_BYRATE_RATE2);
2306                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2307                                              power_level, txpower, delta);
2308                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2309
2310                 /*
2311                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2312                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2313                  * TX_PWR_CFG_4: unknown
2314                  */
2315                 txpower = rt2x00_get_field16(eeprom,
2316                                              EEPROM_TXPOWER_BYRATE_RATE3);
2317                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2318                                              power_level, txpower, delta);
2319                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2320
2321                 rt2800_register_write(rt2x00dev, offset, reg);
2322
2323                 /* next TX_PWR_CFG register */
2324                 offset += 4;
2325         }
2326 }
2327
2328 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2329 {
2330         rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2331                               rt2x00dev->tx_power);
2332 }
2333 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2334
2335 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2336                                       struct rt2x00lib_conf *libconf)
2337 {
2338         u32 reg;
2339
2340         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2341         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2342                            libconf->conf->short_frame_max_tx_count);
2343         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2344                            libconf->conf->long_frame_max_tx_count);
2345         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2346 }
2347
2348 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2349                              struct rt2x00lib_conf *libconf)
2350 {
2351         enum dev_state state =
2352             (libconf->conf->flags & IEEE80211_CONF_PS) ?
2353                 STATE_SLEEP : STATE_AWAKE;
2354         u32 reg;
2355
2356         if (state == STATE_SLEEP) {
2357                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2358
2359                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2360                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2361                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2362                                    libconf->conf->listen_interval - 1);
2363                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2364                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2365
2366                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2367         } else {
2368                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2369                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2370                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2371                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2372                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2373
2374                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2375         }
2376 }
2377
2378 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2379                    struct rt2x00lib_conf *libconf,
2380                    const unsigned int flags)
2381 {
2382         /* Always recalculate LNA gain before changing configuration */
2383         rt2800_config_lna_gain(rt2x00dev, libconf);
2384
2385         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2386                 rt2800_config_channel(rt2x00dev, libconf->conf,
2387                                       &libconf->rf, &libconf->channel);
2388                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2389                                       libconf->conf->power_level);
2390         }
2391         if (flags & IEEE80211_CONF_CHANGE_POWER)
2392                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2393                                       libconf->conf->power_level);
2394         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2395                 rt2800_config_retry_limit(rt2x00dev, libconf);
2396         if (flags & IEEE80211_CONF_CHANGE_PS)
2397                 rt2800_config_ps(rt2x00dev, libconf);
2398 }
2399 EXPORT_SYMBOL_GPL(rt2800_config);
2400
2401 /*
2402  * Link tuning
2403  */
2404 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2405 {
2406         u32 reg;
2407
2408         /*
2409          * Update FCS error count from register.
2410          */
2411         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2412         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2413 }
2414 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2415
2416 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2417 {
2418         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2419                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2420                     rt2x00_rt(rt2x00dev, RT3071) ||
2421                     rt2x00_rt(rt2x00dev, RT3090) ||
2422                     rt2x00_rt(rt2x00dev, RT3390) ||
2423                     rt2x00_rt(rt2x00dev, RT5390))
2424                         return 0x1c + (2 * rt2x00dev->lna_gain);
2425                 else
2426                         return 0x2e + rt2x00dev->lna_gain;
2427         }
2428
2429         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2430                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2431         else
2432                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2433 }
2434
2435 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2436                                   struct link_qual *qual, u8 vgc_level)
2437 {
2438         if (qual->vgc_level != vgc_level) {
2439                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2440                 qual->vgc_level = vgc_level;
2441                 qual->vgc_level_reg = vgc_level;
2442         }
2443 }
2444
2445 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2446 {
2447         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2448 }
2449 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2450
2451 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2452                        const u32 count)
2453 {
2454         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2455                 return;
2456
2457         /*
2458          * When RSSI is better then -80 increase VGC level with 0x10
2459          */
2460         rt2800_set_vgc(rt2x00dev, qual,
2461                        rt2800_get_default_vgc(rt2x00dev) +
2462                        ((qual->rssi > -80) * 0x10));
2463 }
2464 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2465
2466 /*
2467  * Initialization functions.
2468  */
2469 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2470 {
2471         u32 reg;
2472         u16 eeprom;
2473         unsigned int i;
2474         int ret;
2475
2476         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2477         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2478         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2479         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2480         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2481         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2482         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2483
2484         ret = rt2800_drv_init_registers(rt2x00dev);
2485         if (ret)
2486                 return ret;
2487
2488         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2489         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2490         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2491         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2492         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2493         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2494
2495         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2496         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2497         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2498         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2499         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2500         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2501
2502         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2503         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2504
2505         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2506
2507         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2508         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2509         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2510         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2511         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2512         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2513         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2514         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2515
2516         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2517
2518         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2519         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2520         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2521         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2522
2523         if (rt2x00_rt(rt2x00dev, RT3071) ||
2524             rt2x00_rt(rt2x00dev, RT3090) ||
2525             rt2x00_rt(rt2x00dev, RT3390)) {
2526                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2527                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2528                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2529                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2530                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2531                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2532                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2533                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2534                                                       0x0000002c);
2535                         else
2536                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2537                                                       0x0000000f);
2538                 } else {
2539                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2540                 }
2541         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2542                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2543
2544                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2545                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2546                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2547                 } else {
2548                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2549                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2550                 }
2551         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2552                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2553                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2554                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
2555         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2556                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2557                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2558         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2559                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2560                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2561                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2562         } else {
2563                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2564                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2565         }
2566
2567         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2568         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2569         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2570         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2571         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2572         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2573         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2574         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2575         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2576         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2577
2578         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2579         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2580         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2581         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2582         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2583
2584         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2585         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2586         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2587             rt2x00_rt(rt2x00dev, RT2883) ||
2588             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2589                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2590         else
2591                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2592         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2593         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2594         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2595
2596         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2597         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2598         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2599         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2600         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2601         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2602         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2603         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2604         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2605
2606         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2607
2608         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2609         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2610         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2611         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2612         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2613         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2614         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2615         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2616
2617         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2618         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2619         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2620         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2621         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2622         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2623         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2624         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2625         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2626
2627         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2628         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2629         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2630         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2631         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2632         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2633         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2634         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2635         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2636         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2637         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2638         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2639
2640         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2641         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2642         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2643         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2644         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2645         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2646         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2647         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2648         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2649         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2650         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2651         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2652
2653         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2654         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2655         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2656         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2657         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2658         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2659         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2660         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2661         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2662         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2663         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2664         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2665
2666         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2667         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2668         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2669         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2670         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2671         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2672         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2673         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2674         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2675         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2676         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2677         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2678
2679         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2680         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2681         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2682         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2683         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2684         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2685         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2686         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2687         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2688         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2689         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2690         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2691
2692         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2693         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2694         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2695         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2696         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2697         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2698         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2699         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2700         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2701         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2702         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2703         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2704
2705         if (rt2x00_is_usb(rt2x00dev)) {
2706                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2707
2708                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2709                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2710                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2711                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2712                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2713                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2714                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2715                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2716                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2717                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2718                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2719         }
2720
2721         /*
2722          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2723          * although it is reserved.
2724          */
2725         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2726         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2727         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2728         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2729         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2730         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2731         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2732         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2733         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2734         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2735         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2736         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2737
2738         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2739
2740         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2741         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2742         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2743                            IEEE80211_MAX_RTS_THRESHOLD);
2744         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2745         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2746
2747         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2748
2749         /*
2750          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2751          * time should be set to 16. However, the original Ralink driver uses
2752          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2753          * connection problems with 11g + CTS protection. Hence, use the same
2754          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2755          */
2756         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2757         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2758         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2759         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2760         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2761         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2762         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2763
2764         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2765
2766         /*
2767          * ASIC will keep garbage value after boot, clear encryption keys.
2768          */
2769         for (i = 0; i < 4; i++)
2770                 rt2800_register_write(rt2x00dev,
2771                                          SHARED_KEY_MODE_ENTRY(i), 0);
2772
2773         for (i = 0; i < 256; i++) {
2774                 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2775                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2776                                               wcid, sizeof(wcid));
2777
2778                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 0);
2779                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2780         }
2781
2782         /*
2783          * Clear all beacons
2784          */
2785         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2786         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2787         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2788         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2789         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2790         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2791         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2792         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2793
2794         if (rt2x00_is_usb(rt2x00dev)) {
2795                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2796                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2797                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2798         } else if (rt2x00_is_pcie(rt2x00dev)) {
2799                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2800                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2801                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2802         }
2803
2804         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2805         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2806         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2807         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2808         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2809         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2810         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2811         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2812         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2813         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2814
2815         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2816         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2817         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2818         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2819         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2820         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2821         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2822         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2823         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2824         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2825
2826         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2827         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2828         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2829         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2830         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2831         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2832         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2833         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2834         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2835         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2836
2837         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2838         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2839         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2840         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2841         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2842         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2843
2844         /*
2845          * Do not force the BA window size, we use the TXWI to set it
2846          */
2847         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2848         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2849         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2850         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2851
2852         /*
2853          * We must clear the error counters.
2854          * These registers are cleared on read,
2855          * so we may pass a useless variable to store the value.
2856          */
2857         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2858         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2859         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2860         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2861         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2862         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2863
2864         /*
2865          * Setup leadtime for pre tbtt interrupt to 6ms
2866          */
2867         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2868         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2869         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2870
2871         /*
2872          * Set up channel statistics timer
2873          */
2874         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2875         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2876         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2877         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2878         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2879         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2880         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2881
2882         return 0;
2883 }
2884
2885 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2886 {
2887         unsigned int i;
2888         u32 reg;
2889
2890         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2891                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2892                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2893                         return 0;
2894
2895                 udelay(REGISTER_BUSY_DELAY);
2896         }
2897
2898         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2899         return -EACCES;
2900 }
2901
2902 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2903 {
2904         unsigned int i;
2905         u8 value;
2906
2907         /*
2908          * BBP was enabled after firmware was loaded,
2909          * but we need to reactivate it now.
2910          */
2911         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2912         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2913         msleep(1);
2914
2915         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2916                 rt2800_bbp_read(rt2x00dev, 0, &value);
2917                 if ((value != 0xff) && (value != 0x00))
2918                         return 0;
2919                 udelay(REGISTER_BUSY_DELAY);
2920         }
2921
2922         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2923         return -EACCES;
2924 }
2925
2926 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2927 {
2928         unsigned int i;
2929         u16 eeprom;
2930         u8 reg_id;
2931         u8 value;
2932
2933         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2934                      rt2800_wait_bbp_ready(rt2x00dev)))
2935                 return -EACCES;
2936
2937         if (rt2x00_rt(rt2x00dev, RT5390)) {
2938                 rt2800_bbp_read(rt2x00dev, 4, &value);
2939                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2940                 rt2800_bbp_write(rt2x00dev, 4, value);
2941         }
2942
2943         if (rt2800_is_305x_soc(rt2x00dev) ||
2944             rt2x00_rt(rt2x00dev, RT3572) ||
2945             rt2x00_rt(rt2x00dev, RT5390))
2946                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2947
2948         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2949         rt2800_bbp_write(rt2x00dev, 66, 0x38);
2950
2951         if (rt2x00_rt(rt2x00dev, RT5390))
2952                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2953
2954         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2955                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2956                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2957         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2958                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2959                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2960                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2961                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2962                 rt2800_bbp_write(rt2x00dev, 77, 0x59);
2963         } else {
2964                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2965                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2966         }
2967
2968         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2969
2970         if (rt2x00_rt(rt2x00dev, RT3070) ||
2971             rt2x00_rt(rt2x00dev, RT3071) ||
2972             rt2x00_rt(rt2x00dev, RT3090) ||
2973             rt2x00_rt(rt2x00dev, RT3390) ||
2974             rt2x00_rt(rt2x00dev, RT3572) ||
2975             rt2x00_rt(rt2x00dev, RT5390)) {
2976                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2977                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2978                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2979         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2980                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2981                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2982         } else {
2983                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2984         }
2985
2986         rt2800_bbp_write(rt2x00dev, 82, 0x62);
2987         if (rt2x00_rt(rt2x00dev, RT5390))
2988                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2989         else
2990                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2991
2992         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2993                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2994         else if (rt2x00_rt(rt2x00dev, RT5390))
2995                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
2996         else
2997                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2998
2999         if (rt2x00_rt(rt2x00dev, RT5390))
3000                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3001         else
3002                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3003
3004         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3005
3006         if (rt2x00_rt(rt2x00dev, RT5390))
3007                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3008         else
3009                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3010
3011         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3012             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3013             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3014             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3015             rt2x00_rt(rt2x00dev, RT3572) ||
3016             rt2x00_rt(rt2x00dev, RT5390) ||
3017             rt2800_is_305x_soc(rt2x00dev))
3018                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3019         else
3020                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3021
3022         if (rt2x00_rt(rt2x00dev, RT5390))
3023                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3024
3025         if (rt2800_is_305x_soc(rt2x00dev))
3026                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3027         else if (rt2x00_rt(rt2x00dev, RT5390))
3028                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3029         else
3030                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3031
3032         if (rt2x00_rt(rt2x00dev, RT5390))
3033                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3034         else
3035                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3036
3037         if (rt2x00_rt(rt2x00dev, RT5390))
3038                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3039
3040         if (rt2x00_rt(rt2x00dev, RT3071) ||
3041             rt2x00_rt(rt2x00dev, RT3090) ||
3042             rt2x00_rt(rt2x00dev, RT3390) ||
3043             rt2x00_rt(rt2x00dev, RT3572) ||
3044             rt2x00_rt(rt2x00dev, RT5390)) {
3045                 rt2800_bbp_read(rt2x00dev, 138, &value);
3046
3047                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3048                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3049                         value |= 0x20;
3050                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3051                         value &= ~0x02;
3052
3053                 rt2800_bbp_write(rt2x00dev, 138, value);
3054         }
3055
3056         if (rt2x00_rt(rt2x00dev, RT5390)) {
3057                 int ant, div_mode;
3058
3059                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3060                 div_mode = rt2x00_get_field16(eeprom,
3061                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
3062                 ant = (div_mode == 3) ? 1 : 0;
3063
3064                 /* check if this is a Bluetooth combo card */
3065                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3066                         u32 reg;
3067
3068                         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3069                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3070                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3071                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3072                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3073                         if (ant == 0)
3074                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3075                         else if (ant == 1)
3076                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3077                         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3078                 }
3079
3080                 rt2800_bbp_read(rt2x00dev, 152, &value);
3081                 if (ant == 0)
3082                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3083                 else
3084                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3085                 rt2800_bbp_write(rt2x00dev, 152, value);
3086
3087                 /* Init frequency calibration */
3088                 rt2800_bbp_write(rt2x00dev, 142, 1);
3089                 rt2800_bbp_write(rt2x00dev, 143, 57);
3090         }
3091
3092         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3093                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3094
3095                 if (eeprom != 0xffff && eeprom != 0x0000) {
3096                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3097                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3098                         rt2800_bbp_write(rt2x00dev, reg_id, value);
3099                 }
3100         }
3101
3102         return 0;
3103 }
3104
3105 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3106                                 bool bw40, u8 rfcsr24, u8 filter_target)
3107 {
3108         unsigned int i;
3109         u8 bbp;
3110         u8 rfcsr;
3111         u8 passband;
3112         u8 stopband;
3113         u8 overtuned = 0;
3114
3115         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3116
3117         rt2800_bbp_read(rt2x00dev, 4, &bbp);
3118         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3119         rt2800_bbp_write(rt2x00dev, 4, bbp);
3120
3121         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3122         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3123         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3124
3125         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3126         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3127         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3128
3129         /*
3130          * Set power & frequency of passband test tone
3131          */
3132         rt2800_bbp_write(rt2x00dev, 24, 0);
3133
3134         for (i = 0; i < 100; i++) {
3135                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3136                 msleep(1);
3137
3138                 rt2800_bbp_read(rt2x00dev, 55, &passband);
3139                 if (passband)
3140                         break;
3141         }
3142
3143         /*
3144          * Set power & frequency of stopband test tone
3145          */
3146         rt2800_bbp_write(rt2x00dev, 24, 0x06);
3147
3148         for (i = 0; i < 100; i++) {
3149                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3150                 msleep(1);
3151
3152                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3153
3154                 if ((passband - stopband) <= filter_target) {
3155                         rfcsr24++;
3156                         overtuned += ((passband - stopband) == filter_target);
3157                 } else
3158                         break;
3159
3160                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3161         }
3162
3163         rfcsr24 -= !!overtuned;
3164
3165         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3166         return rfcsr24;
3167 }
3168
3169 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3170 {
3171         u8 rfcsr;
3172         u8 bbp;
3173         u32 reg;
3174         u16 eeprom;
3175
3176         if (!rt2x00_rt(rt2x00dev, RT3070) &&
3177             !rt2x00_rt(rt2x00dev, RT3071) &&
3178             !rt2x00_rt(rt2x00dev, RT3090) &&
3179             !rt2x00_rt(rt2x00dev, RT3390) &&
3180             !rt2x00_rt(rt2x00dev, RT3572) &&
3181             !rt2x00_rt(rt2x00dev, RT5390) &&
3182             !rt2800_is_305x_soc(rt2x00dev))
3183                 return 0;
3184
3185         /*
3186          * Init RF calibration.
3187          */
3188         if (rt2x00_rt(rt2x00dev, RT5390)) {
3189                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3190                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3191                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3192                 msleep(1);
3193                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3194                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3195         } else {
3196                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3197                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3198                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3199                 msleep(1);
3200                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3201                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3202         }
3203
3204         if (rt2x00_rt(rt2x00dev, RT3070) ||
3205             rt2x00_rt(rt2x00dev, RT3071) ||
3206             rt2x00_rt(rt2x00dev, RT3090)) {
3207                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3208                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3209                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3210                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3211                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3212                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3213                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3214                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3215                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3216                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3217                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3218                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3219                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3220                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3221                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3222                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3223                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3224                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3225                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3226         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3227                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3228                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3229                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3230                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3231                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3232                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3233                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3234                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3235                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3236                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3237                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3238                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3239                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3240                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3241                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3242                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3243                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3244                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3245                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3246                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3247                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3248                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3249                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3250                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3251                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3252                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3253                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3254                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3255                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3256                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3257                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3258                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3259         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3260                 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3261                 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3262                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3263                 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3264                 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3265                 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3266                 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3267                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3268                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3269                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3270                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3271                 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3272                 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3273                 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3274                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3275                 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3276                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3277                 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3278                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3279                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3280                 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3281                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3282                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3283                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3284                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3285                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3286                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3287                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3288                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3289                 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3290                 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
3291         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3292                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3293                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3294                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3295                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3296                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3297                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3298                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3299                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3300                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3301                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3302                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3303                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3304                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3305                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3306                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3307                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3308                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3309                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3310                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3311                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3312                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3313                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3314                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3315                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3316                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3317                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3318                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3319                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3320                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3321                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3322                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3323                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3324                 return 0;
3325         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3326                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3327                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3328                 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3329                 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3330                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3331                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3332                 else
3333                         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3334                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3335                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3336                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3337                 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3338                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3339                 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3340                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3341                 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3342                 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3343                 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3344
3345                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3346                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3347                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3348                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3349                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3350                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3351                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3352                 else
3353                         rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3354                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3355                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3356                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3357                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3358
3359                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3360                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3361                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3362                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3363                 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3364                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3365                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3366                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3367                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3368                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3369
3370                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3371                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3372                 else
3373                         rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3374                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3375                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3376                 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3377                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3378                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3379                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3380                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3381                 else
3382                         rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3383                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3384                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3385                 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3386
3387                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3388                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3389                         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3390                 else
3391                         rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3392                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3393                 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3394                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3395                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3396                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3397                 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3398
3399                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3400                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3401                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3402                 else
3403                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3404                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3405                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3406         }
3407
3408         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3409                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3410                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3411                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3412                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3413         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3414                    rt2x00_rt(rt2x00dev, RT3090)) {
3415                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3416
3417                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3418                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3419                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3420
3421                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3422                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3423                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3424                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3425                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3426                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3427                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3428                         else
3429                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3430                 }
3431                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3432
3433                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3434                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3435                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3436         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3437                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3438                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3439                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3440         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3441                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3442                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3443                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3444
3445                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3446                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3447                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3448                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3449                 msleep(1);
3450                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3451                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3452                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3453         }
3454
3455         /*
3456          * Set RX Filter calibration for 20MHz and 40MHz
3457          */
3458         if (rt2x00_rt(rt2x00dev, RT3070)) {
3459                 rt2x00dev->calibration[0] =
3460                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3461                 rt2x00dev->calibration[1] =
3462                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3463         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3464                    rt2x00_rt(rt2x00dev, RT3090) ||
3465                    rt2x00_rt(rt2x00dev, RT3390) ||
3466                    rt2x00_rt(rt2x00dev, RT3572)) {
3467                 rt2x00dev->calibration[0] =
3468                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3469                 rt2x00dev->calibration[1] =
3470                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3471         }
3472
3473         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3474                 /*
3475                  * Set back to initial state
3476                  */
3477                 rt2800_bbp_write(rt2x00dev, 24, 0);
3478
3479                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3480                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3481                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3482
3483                 /*
3484                  * Set BBP back to BW20
3485                  */
3486                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3487                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3488                 rt2800_bbp_write(rt2x00dev, 4, bbp);
3489         }
3490
3491         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3492             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3493             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3494             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3495                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3496
3497         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3498         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3499         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3500
3501         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3502                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3503                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3504                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3505                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3506                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3507                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3508                         if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3509                                       &rt2x00dev->cap_flags))
3510                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3511                 }
3512                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3513                 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3514                         rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3515                                         rt2x00_get_field16(eeprom,
3516                                                 EEPROM_TXMIXER_GAIN_BG_VAL));
3517                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3518         }
3519
3520         if (rt2x00_rt(rt2x00dev, RT3090)) {
3521                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3522
3523                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
3524                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3525                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3526                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3527                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3528                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3529
3530                 rt2800_bbp_write(rt2x00dev, 138, bbp);
3531         }
3532
3533         if (rt2x00_rt(rt2x00dev, RT3071) ||
3534             rt2x00_rt(rt2x00dev, RT3090) ||
3535             rt2x00_rt(rt2x00dev, RT3390)) {
3536                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3537                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3538                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3539                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3540                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3541                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3542                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3543
3544                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3545                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3546                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3547
3548                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3549                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3550                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3551
3552                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3553                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3554                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3555         }
3556
3557         if (rt2x00_rt(rt2x00dev, RT3070)) {
3558                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3559                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3560                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3561                 else
3562                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3563                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3564                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3565                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3566                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3567         }
3568
3569         if (rt2x00_rt(rt2x00dev, RT5390)) {
3570                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3571                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3572                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3573
3574                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3575                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3576                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3577
3578                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3579                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3580                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3581         }
3582
3583         return 0;
3584 }
3585
3586 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3587 {
3588         u32 reg;
3589         u16 word;
3590
3591         /*
3592          * Initialize all registers.
3593          */
3594         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3595                      rt2800_init_registers(rt2x00dev) ||
3596                      rt2800_init_bbp(rt2x00dev) ||
3597                      rt2800_init_rfcsr(rt2x00dev)))
3598                 return -EIO;
3599
3600         /*
3601          * Send signal to firmware during boot time.
3602          */
3603         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3604
3605         if (rt2x00_is_usb(rt2x00dev) &&
3606             (rt2x00_rt(rt2x00dev, RT3070) ||
3607              rt2x00_rt(rt2x00dev, RT3071) ||
3608              rt2x00_rt(rt2x00dev, RT3572))) {
3609                 udelay(200);
3610                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3611                 udelay(10);
3612         }
3613
3614         /*
3615          * Enable RX.
3616          */
3617         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3618         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3619         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3620         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3621
3622         udelay(50);
3623
3624         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3625         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3626         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3627         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3628         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3629         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3630
3631         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3632         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3633         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3634         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3635
3636         /*
3637          * Initialize LED control
3638          */
3639         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3640         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3641                            word & 0xff, (word >> 8) & 0xff);
3642
3643         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3644         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3645                            word & 0xff, (word >> 8) & 0xff);
3646
3647         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3648         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3649                            word & 0xff, (word >> 8) & 0xff);
3650
3651         return 0;
3652 }
3653 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3654
3655 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3656 {
3657         u32 reg;
3658
3659         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3660         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3661         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3662         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3663
3664         /* Wait for DMA, ignore error */
3665         rt2800_wait_wpdma_ready(rt2x00dev);
3666
3667         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3668         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3669         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3670         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3671 }
3672 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
3673
3674 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3675 {
3676         u32 reg;
3677
3678         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3679
3680         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3681 }
3682 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3683
3684 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3685 {
3686         u32 reg;
3687
3688         mutex_lock(&rt2x00dev->csr_mutex);
3689
3690         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
3691         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3692         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3693         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
3694         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
3695
3696         /* Wait until the EEPROM has been loaded */
3697         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3698
3699         /* Apparently the data is read from end to start */
3700         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, &reg);
3701         /* The returned value is in CPU order, but eeprom is le */
3702         rt2x00dev->eeprom[i] = cpu_to_le32(reg);
3703         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, &reg);
3704         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
3705         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, &reg);
3706         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
3707         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, &reg);
3708         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
3709
3710         mutex_unlock(&rt2x00dev->csr_mutex);
3711 }
3712
3713 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3714 {
3715         unsigned int i;
3716
3717         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3718                 rt2800_efuse_read(rt2x00dev, i);
3719 }
3720 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3721
3722 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3723 {
3724         u16 word;
3725         u8 *mac;
3726         u8 default_lna_gain;
3727
3728         /*
3729          * Start validation of the data that has been read.
3730          */
3731         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3732         if (!is_valid_ether_addr(mac)) {
3733                 random_ether_addr(mac);
3734                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3735         }
3736
3737         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
3738         if (word == 0xffff) {
3739                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3740                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3741                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3742                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3743                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
3744         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
3745                    rt2x00_rt(rt2x00dev, RT2872)) {
3746                 /*
3747                  * There is a max of 2 RX streams for RT28x0 series
3748                  */
3749                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3750                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3751                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3752         }
3753
3754         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
3755         if (word == 0xffff) {
3756                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3757                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3758                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3759                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3760                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3761                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3762                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3763                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3764                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3765                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3766                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3767                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3768                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3769                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3770                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3771                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
3772                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3773         }
3774
3775         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3776         if ((word & 0x00ff) == 0x00ff) {
3777                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3778                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3779                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3780         }
3781         if ((word & 0xff00) == 0xff00) {
3782                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3783                                    LED_MODE_TXRX_ACTIVITY);
3784                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3785                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3786                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3787                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3788                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
3789                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
3790         }
3791
3792         /*
3793          * During the LNA validation we are going to use
3794          * lna0 as correct value. Note that EEPROM_LNA
3795          * is never validated.
3796          */
3797         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3798         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3799
3800         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3801         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3802                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3803         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3804                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3805         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3806
3807         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3808         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3809                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3810         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3811             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3812                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3813                                    default_lna_gain);
3814         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3815
3816         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3817         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3818                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3819         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3820                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3821         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3822
3823         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3824         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3825                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3826         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3827             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3828                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3829                                    default_lna_gain);
3830         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3831
3832         return 0;
3833 }
3834 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3835
3836 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3837 {
3838         u32 reg;
3839         u16 value;
3840         u16 eeprom;
3841
3842         /*
3843          * Read EEPROM word for configuration.
3844          */
3845         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3846
3847         /*
3848          * Identify RF chipset by EEPROM value
3849          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3850          * RT53xx: defined in "EEPROM_CHIP_ID" field
3851          */
3852         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3853         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3854                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3855         else
3856                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3857
3858         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3859                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3860
3861         if (!rt2x00_rt(rt2x00dev, RT2860) &&
3862             !rt2x00_rt(rt2x00dev, RT2872) &&
3863             !rt2x00_rt(rt2x00dev, RT2883) &&
3864             !rt2x00_rt(rt2x00dev, RT3070) &&
3865             !rt2x00_rt(rt2x00dev, RT3071) &&
3866             !rt2x00_rt(rt2x00dev, RT3090) &&
3867             !rt2x00_rt(rt2x00dev, RT3390) &&
3868             !rt2x00_rt(rt2x00dev, RT3572) &&
3869             !rt2x00_rt(rt2x00dev, RT5390)) {
3870                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3871                 return -ENODEV;
3872         }
3873
3874         switch (rt2x00dev->chip.rf) {
3875         case RF2820:
3876         case RF2850:
3877         case RF2720:
3878         case RF2750:
3879         case RF3020:
3880         case RF2020:
3881         case RF3021:
3882         case RF3022:
3883         case RF3052:
3884         case RF3320:
3885         case RF5370:
3886         case RF5390:
3887                 break;
3888         default:
3889                 ERROR(rt2x00dev, "Invalid RF chipset 0x%x detected.\n",
3890                       rt2x00dev->chip.rf);
3891                 return -ENODEV;
3892         }
3893
3894         /*
3895          * Identify default antenna configuration.
3896          */
3897         rt2x00dev->default_ant.tx_chain_num =
3898             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3899         rt2x00dev->default_ant.rx_chain_num =
3900             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3901
3902         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3903
3904         if (rt2x00_rt(rt2x00dev, RT3070) ||
3905             rt2x00_rt(rt2x00dev, RT3090) ||
3906             rt2x00_rt(rt2x00dev, RT3390)) {
3907                 value = rt2x00_get_field16(eeprom,
3908                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3909                 switch (value) {
3910                 case 0:
3911                 case 1:
3912                 case 2:
3913                         rt2x00dev->default_ant.tx = ANTENNA_A;
3914                         rt2x00dev->default_ant.rx = ANTENNA_A;
3915                         break;
3916                 case 3:
3917                         rt2x00dev->default_ant.tx = ANTENNA_A;
3918                         rt2x00dev->default_ant.rx = ANTENNA_B;
3919                         break;
3920                 }
3921         } else {
3922                 rt2x00dev->default_ant.tx = ANTENNA_A;
3923                 rt2x00dev->default_ant.rx = ANTENNA_A;
3924         }
3925
3926         /*
3927          * Determine external LNA informations.
3928          */
3929         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
3930                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
3931         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
3932                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
3933
3934         /*
3935          * Detect if this device has an hardware controlled radio.
3936          */
3937         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
3938                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
3939
3940         /*
3941          * Detect if this device has Bluetooth co-existence.
3942          */
3943         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
3944                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
3945
3946         /*
3947          * Read frequency offset and RF programming sequence.
3948          */
3949         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3950         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3951
3952         /*
3953          * Store led settings, for correct led behaviour.
3954          */
3955 #ifdef CONFIG_RT2X00_LIB_LEDS
3956         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3957         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3958         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3959
3960         rt2x00dev->led_mcu_reg = eeprom;
3961 #endif /* CONFIG_RT2X00_LIB_LEDS */
3962
3963         /*
3964          * Check if support EIRP tx power limit feature.
3965          */
3966         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
3967
3968         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
3969                                         EIRP_MAX_TX_POWER_LIMIT)
3970                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
3971
3972         return 0;
3973 }
3974 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3975
3976 /*
3977  * RF value list for rt28xx
3978  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3979  */
3980 static const struct rf_channel rf_vals[] = {
3981         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3982         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3983         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3984         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3985         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3986         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3987         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3988         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3989         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3990         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3991         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3992         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3993         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3994         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3995
3996         /* 802.11 UNI / HyperLan 2 */
3997         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3998         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3999         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4000         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4001         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4002         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4003         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4004         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4005         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4006         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4007         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4008         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4009
4010         /* 802.11 HyperLan 2 */
4011         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4012         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4013         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4014         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4015         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4016         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4017         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4018         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4019         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4020         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4021         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4022         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4023         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4024         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4025         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4026         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4027
4028         /* 802.11 UNII */
4029         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4030         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4031         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4032         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4033         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4034         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4035         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4036         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4037         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4038         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4039         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4040
4041         /* 802.11 Japan */
4042         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4043         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4044         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4045         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4046         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4047         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4048         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4049 };
4050
4051 /*
4052  * RF value list for rt3xxx
4053  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4054  */
4055 static const struct rf_channel rf_vals_3x[] = {
4056         {1,  241, 2, 2 },
4057         {2,  241, 2, 7 },
4058         {3,  242, 2, 2 },
4059         {4,  242, 2, 7 },
4060         {5,  243, 2, 2 },
4061         {6,  243, 2, 7 },
4062         {7,  244, 2, 2 },
4063         {8,  244, 2, 7 },
4064         {9,  245, 2, 2 },
4065         {10, 245, 2, 7 },
4066         {11, 246, 2, 2 },
4067         {12, 246, 2, 7 },
4068         {13, 247, 2, 2 },
4069         {14, 248, 2, 4 },
4070
4071         /* 802.11 UNI / HyperLan 2 */
4072         {36, 0x56, 0, 4},
4073         {38, 0x56, 0, 6},
4074         {40, 0x56, 0, 8},
4075         {44, 0x57, 0, 0},
4076         {46, 0x57, 0, 2},
4077         {48, 0x57, 0, 4},
4078         {52, 0x57, 0, 8},
4079         {54, 0x57, 0, 10},
4080         {56, 0x58, 0, 0},
4081         {60, 0x58, 0, 4},
4082         {62, 0x58, 0, 6},
4083         {64, 0x58, 0, 8},
4084
4085         /* 802.11 HyperLan 2 */
4086         {100, 0x5b, 0, 8},
4087         {102, 0x5b, 0, 10},
4088         {104, 0x5c, 0, 0},
4089         {108, 0x5c, 0, 4},
4090         {110, 0x5c, 0, 6},
4091         {112, 0x5c, 0, 8},
4092         {116, 0x5d, 0, 0},
4093         {118, 0x5d, 0, 2},
4094         {120, 0x5d, 0, 4},
4095         {124, 0x5d, 0, 8},
4096         {126, 0x5d, 0, 10},
4097         {128, 0x5e, 0, 0},
4098         {132, 0x5e, 0, 4},
4099         {134, 0x5e, 0, 6},
4100         {136, 0x5e, 0, 8},
4101         {140, 0x5f, 0, 0},
4102
4103         /* 802.11 UNII */
4104         {149, 0x5f, 0, 9},
4105         {151, 0x5f, 0, 11},
4106         {153, 0x60, 0, 1},
4107         {157, 0x60, 0, 5},
4108         {159, 0x60, 0, 7},
4109         {161, 0x60, 0, 9},
4110         {165, 0x61, 0, 1},
4111         {167, 0x61, 0, 3},
4112         {169, 0x61, 0, 5},
4113         {171, 0x61, 0, 7},
4114         {173, 0x61, 0, 9},
4115 };
4116
4117 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4118 {
4119         struct hw_mode_spec *spec = &rt2x00dev->spec;
4120         struct channel_info *info;
4121         char *default_power1;
4122         char *default_power2;
4123         unsigned int i;
4124         u16 eeprom;
4125
4126         /*
4127          * Disable powersaving as default on PCI devices.
4128          */
4129         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
4130                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4131
4132         /*
4133          * Initialize all hw fields.
4134          */
4135         rt2x00dev->hw->flags =
4136             IEEE80211_HW_SIGNAL_DBM |
4137             IEEE80211_HW_SUPPORTS_PS |
4138             IEEE80211_HW_PS_NULLFUNC_STACK |
4139             IEEE80211_HW_AMPDU_AGGREGATION;
4140         /*
4141          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4142          * unless we are capable of sending the buffered frames out after the
4143          * DTIM transmission using rt2x00lib_beacondone. This will send out
4144          * multicast and broadcast traffic immediately instead of buffering it
4145          * infinitly and thus dropping it after some time.
4146          */
4147         if (!rt2x00_is_usb(rt2x00dev))
4148                 rt2x00dev->hw->flags |=
4149                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4150
4151         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4152         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4153                                 rt2x00_eeprom_addr(rt2x00dev,
4154                                                    EEPROM_MAC_ADDR_0));
4155
4156         /*
4157          * As rt2800 has a global fallback table we cannot specify
4158          * more then one tx rate per frame but since the hw will
4159          * try several rates (based on the fallback table) we should
4160          * initialize max_report_rates to the maximum number of rates
4161          * we are going to try. Otherwise mac80211 will truncate our
4162          * reported tx rates and the rc algortihm will end up with
4163          * incorrect data.
4164          */
4165         rt2x00dev->hw->max_rates = 1;
4166         rt2x00dev->hw->max_report_rates = 7;
4167         rt2x00dev->hw->max_rate_tries = 1;
4168
4169         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4170
4171         /*
4172          * Initialize hw_mode information.
4173          */
4174         spec->supported_bands = SUPPORT_BAND_2GHZ;
4175         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4176
4177         if (rt2x00_rf(rt2x00dev, RF2820) ||
4178             rt2x00_rf(rt2x00dev, RF2720)) {
4179                 spec->num_channels = 14;
4180                 spec->channels = rf_vals;
4181         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4182                    rt2x00_rf(rt2x00dev, RF2750)) {
4183                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4184                 spec->num_channels = ARRAY_SIZE(rf_vals);
4185                 spec->channels = rf_vals;
4186         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4187                    rt2x00_rf(rt2x00dev, RF2020) ||
4188                    rt2x00_rf(rt2x00dev, RF3021) ||
4189                    rt2x00_rf(rt2x00dev, RF3022) ||
4190                    rt2x00_rf(rt2x00dev, RF3320) ||
4191                    rt2x00_rf(rt2x00dev, RF5370) ||
4192                    rt2x00_rf(rt2x00dev, RF5390)) {
4193                 spec->num_channels = 14;
4194                 spec->channels = rf_vals_3x;
4195         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4196                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4197                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4198                 spec->channels = rf_vals_3x;
4199         }
4200
4201         /*
4202          * Initialize HT information.
4203          */
4204         if (!rt2x00_rf(rt2x00dev, RF2020))
4205                 spec->ht.ht_supported = true;
4206         else
4207                 spec->ht.ht_supported = false;
4208
4209         spec->ht.cap =
4210             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4211             IEEE80211_HT_CAP_GRN_FLD |
4212             IEEE80211_HT_CAP_SGI_20 |
4213             IEEE80211_HT_CAP_SGI_40;
4214
4215         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
4216                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4217
4218         spec->ht.cap |=
4219             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
4220                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4221
4222         spec->ht.ampdu_factor = 3;
4223         spec->ht.ampdu_density = 4;
4224         spec->ht.mcs.tx_params =
4225             IEEE80211_HT_MCS_TX_DEFINED |
4226             IEEE80211_HT_MCS_TX_RX_DIFF |
4227             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4228                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4229
4230         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4231         case 3:
4232                 spec->ht.mcs.rx_mask[2] = 0xff;
4233         case 2:
4234                 spec->ht.mcs.rx_mask[1] = 0xff;
4235         case 1:
4236                 spec->ht.mcs.rx_mask[0] = 0xff;
4237                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4238                 break;
4239         }
4240
4241         /*
4242          * Create channel information array
4243          */
4244         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4245         if (!info)
4246                 return -ENOMEM;
4247
4248         spec->channels_info = info;
4249
4250         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4251         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4252
4253         for (i = 0; i < 14; i++) {
4254                 info[i].default_power1 = default_power1[i];
4255                 info[i].default_power2 = default_power2[i];
4256         }
4257
4258         if (spec->num_channels > 14) {
4259                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4260                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4261
4262                 for (i = 14; i < spec->num_channels; i++) {
4263                         info[i].default_power1 = default_power1[i];
4264                         info[i].default_power2 = default_power2[i];
4265                 }
4266         }
4267
4268         return 0;
4269 }
4270 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4271
4272 /*
4273  * IEEE80211 stack callback functions.
4274  */
4275 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4276                          u16 *iv16)
4277 {
4278         struct rt2x00_dev *rt2x00dev = hw->priv;
4279         struct mac_iveiv_entry iveiv_entry;
4280         u32 offset;
4281
4282         offset = MAC_IVEIV_ENTRY(hw_key_idx);
4283         rt2800_register_multiread(rt2x00dev, offset,
4284                                       &iveiv_entry, sizeof(iveiv_entry));
4285
4286         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4287         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
4288 }
4289 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
4290
4291 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4292 {
4293         struct rt2x00_dev *rt2x00dev = hw->priv;
4294         u32 reg;
4295         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4296
4297         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4298         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4299         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4300
4301         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4302         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4303         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4304
4305         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4306         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4307         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4308
4309         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4310         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4311         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4312
4313         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4314         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4315         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4316
4317         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4318         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4319         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4320
4321         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4322         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4323         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4324
4325         return 0;
4326 }
4327 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
4328
4329 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
4330                    const struct ieee80211_tx_queue_params *params)
4331 {
4332         struct rt2x00_dev *rt2x00dev = hw->priv;
4333         struct data_queue *queue;
4334         struct rt2x00_field32 field;
4335         int retval;
4336         u32 reg;
4337         u32 offset;
4338
4339         /*
4340          * First pass the configuration through rt2x00lib, that will
4341          * update the queue settings and validate the input. After that
4342          * we are free to update the registers based on the value
4343          * in the queue parameter.
4344          */
4345         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
4346         if (retval)
4347                 return retval;
4348
4349         /*
4350          * We only need to perform additional register initialization
4351          * for WMM queues/
4352          */
4353         if (queue_idx >= 4)
4354                 return 0;
4355
4356         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
4357
4358         /* Update WMM TXOP register */
4359         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4360         field.bit_offset = (queue_idx & 1) * 16;
4361         field.bit_mask = 0xffff << field.bit_offset;
4362
4363         rt2800_register_read(rt2x00dev, offset, &reg);
4364         rt2x00_set_field32(&reg, field, queue->txop);
4365         rt2800_register_write(rt2x00dev, offset, reg);
4366
4367         /* Update WMM registers */
4368         field.bit_offset = queue_idx * 4;
4369         field.bit_mask = 0xf << field.bit_offset;
4370
4371         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4372         rt2x00_set_field32(&reg, field, queue->aifs);
4373         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4374
4375         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4376         rt2x00_set_field32(&reg, field, queue->cw_min);
4377         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4378
4379         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4380         rt2x00_set_field32(&reg, field, queue->cw_max);
4381         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4382
4383         /* Update EDCA registers */
4384         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4385
4386         rt2800_register_read(rt2x00dev, offset, &reg);
4387         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4388         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4389         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4390         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4391         rt2800_register_write(rt2x00dev, offset, reg);
4392
4393         return 0;
4394 }
4395 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4396
4397 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
4398 {
4399         struct rt2x00_dev *rt2x00dev = hw->priv;
4400         u64 tsf;
4401         u32 reg;
4402
4403         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4404         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4405         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4406         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4407
4408         return tsf;
4409 }
4410 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4411
4412 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4413                         enum ieee80211_ampdu_mlme_action action,
4414                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4415                         u8 buf_size)
4416 {
4417         int ret = 0;
4418
4419         switch (action) {
4420         case IEEE80211_AMPDU_RX_START:
4421         case IEEE80211_AMPDU_RX_STOP:
4422                 /*
4423                  * The hw itself takes care of setting up BlockAck mechanisms.
4424                  * So, we only have to allow mac80211 to nagotiate a BlockAck
4425                  * agreement. Once that is done, the hw will BlockAck incoming
4426                  * AMPDUs without further setup.
4427                  */
4428                 break;
4429         case IEEE80211_AMPDU_TX_START:
4430                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4431                 break;
4432         case IEEE80211_AMPDU_TX_STOP:
4433                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4434                 break;
4435         case IEEE80211_AMPDU_TX_OPERATIONAL:
4436                 break;
4437         default:
4438                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4439         }
4440
4441         return ret;
4442 }
4443 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4444
4445 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4446                       struct survey_info *survey)
4447 {
4448         struct rt2x00_dev *rt2x00dev = hw->priv;
4449         struct ieee80211_conf *conf = &hw->conf;
4450         u32 idle, busy, busy_ext;
4451
4452         if (idx != 0)
4453                 return -ENOENT;
4454
4455         survey->channel = conf->channel;
4456
4457         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4458         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4459         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4460
4461         if (idle || busy) {
4462                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4463                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
4464                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4465
4466                 survey->channel_time = (idle + busy) / 1000;
4467                 survey->channel_time_busy = busy / 1000;
4468                 survey->channel_time_ext_busy = busy_ext / 1000;
4469         }
4470
4471         return 0;
4472
4473 }
4474 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4475
4476 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4477 MODULE_VERSION(DRV_VERSION);
4478 MODULE_DESCRIPTION("Ralink RT2800 library");
4479 MODULE_LICENSE("GPL");