drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2400pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 #define WAIT_FOR_BBP(__dev, __reg) \
  53         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  54 #define WAIT_FOR_RF(__dev, __reg) \
  55         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  56
  57 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  58                                 const unsigned int word, const u8 value)
  59 {
  60         u32 reg;
  61
  62         mutex_lock(&rt2x00dev->csr_mutex);
  63
  64         /*
  65          * Wait until the BBP becomes available, afterwards we
  66          * can safely write the new data into the register.
  67          */
  68         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  69                 reg = 0;
  70                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  71                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  72                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  73                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  74
  75                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  76         }
  77
  78         mutex_unlock(&rt2x00dev->csr_mutex);
  79 }
  80
  81 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  82                                const unsigned int word, u8 *value)
  83 {
  84         u32 reg;
  85
  86         mutex_lock(&rt2x00dev->csr_mutex);
  87
  88         /*
  89          * Wait until the BBP becomes available, afterwards we
  90          * can safely write the read request into the register.
  91          * After the data has been written, we wait until hardware
  92          * returns the correct value, if at any time the register
  93          * doesn't become available in time, reg will be 0xffffffff
  94          * which means we return 0xff to the caller.
  95          */
  96         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  97                 reg = 0;
  98                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  99                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 100                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 101
 102                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 103
 104                 WAIT_FOR_BBP(rt2x00dev, &reg);
 105         }
 106
 107         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
 113                                const unsigned int word, const u32 value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the RF becomes available, afterwards we
 121          * can safely write the new data into the register.
 122          */
 123         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 124                 reg = 0;
 125                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 126                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 127                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 128                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 129
 130                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 131                 rt2x00_rf_write(rt2x00dev, word, value);
 132         }
 133
 134         mutex_unlock(&rt2x00dev->csr_mutex);
 135 }
 136
 137 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 138 {
 139         struct rt2x00_dev *rt2x00dev = eeprom->data;
 140         u32 reg;
 141
 142         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 143
 144         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 145         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 146         eeprom->reg_data_clock =
 147             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 148         eeprom->reg_chip_select =
 149             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 150 }
 151
 152 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 153 {
 154         struct rt2x00_dev *rt2x00dev = eeprom->data;
 155         u32 reg = 0;
 156
 157         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 159         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 160                            !!eeprom->reg_data_clock);
 161         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 162                            !!eeprom->reg_chip_select);
 163
 164         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 165 }
 166
 167 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 168 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 169         .owner  = THIS_MODULE,
 170         .csr    = {
 171                 .read           = rt2x00pci_register_read,
 172                 .write          = rt2x00pci_register_write,
 173                 .flags          = RT2X00DEBUGFS_OFFSET,
 174                 .word_base      = CSR_REG_BASE,
 175                 .word_size      = sizeof(u32),
 176                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 177         },
 178         .eeprom = {
 179                 .read           = rt2x00_eeprom_read,
 180                 .write          = rt2x00_eeprom_write,
 181                 .word_base      = EEPROM_BASE,
 182                 .word_size      = sizeof(u16),
 183                 .word_count     = EEPROM_SIZE / sizeof(u16),
 184         },
 185         .bbp    = {
 186                 .read           = rt2400pci_bbp_read,
 187                 .write          = rt2400pci_bbp_write,
 188                 .word_base      = BBP_BASE,
 189                 .word_size      = sizeof(u8),
 190                 .word_count     = BBP_SIZE / sizeof(u8),
 191         },
 192         .rf     = {
 193                 .read           = rt2x00_rf_read,
 194                 .write          = rt2400pci_rf_write,
 195                 .word_base      = RF_BASE,
 196                 .word_size      = sizeof(u32),
 197                 .word_count     = RF_SIZE / sizeof(u32),
 198         },
 199 };
 200 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 201
 202 #ifdef CONFIG_RT2X00_LIB_RFKILL
 203 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 204 {
 205         u32 reg;
 206
 207         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 208         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 209 }
 210 #else
 211 #define rt2400pci_rfkill_poll   NULL
 212 #endif /* CONFIG_RT2X00_LIB_RFKILL */
 213
 214 #ifdef CONFIG_RT2X00_LIB_LEDS
 215 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
 216                                      enum led_brightness brightness)
 217 {
 218         struct rt2x00_led *led =
 219             container_of(led_cdev, struct rt2x00_led, led_dev);
 220         unsigned int enabled = brightness != LED_OFF;
 221         u32 reg;
 222
 223         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 224
 225         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 226                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 227         else if (led->type == LED_TYPE_ACTIVITY)
 228                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 229
 230         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 231 }
 232
 233 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
 234                                unsigned long *delay_on,
 235                                unsigned long *delay_off)
 236 {
 237         struct rt2x00_led *led =
 238             container_of(led_cdev, struct rt2x00_led, led_dev);
 239         u32 reg;
 240
 241         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 242         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 243         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 244         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 245
 246         return 0;
 247 }
 248
 249 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
 250                                struct rt2x00_led *led,
 251                                enum led_type type)
 252 {
 253         led->rt2x00dev = rt2x00dev;
 254         led->type = type;
 255         led->led_dev.brightness_set = rt2400pci_brightness_set;
 256         led->led_dev.blink_set = rt2400pci_blink_set;
 257         led->flags = LED_INITIALIZED;
 258 }
 259 #endif /* CONFIG_RT2X00_LIB_LEDS */
 260
 261 /*
 262  * Configuration handlers.
 263  */
 264 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
 265                                     const unsigned int filter_flags)
 266 {
 267         u32 reg;
 268
 269         /*
 270          * Start configuration steps.
 271          * Note that the version error will always be dropped
 272          * since there is no filter for it at this time.
 273          */
 274         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 275         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 276                            !(filter_flags & FIF_FCSFAIL));
 277         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 278                            !(filter_flags & FIF_PLCPFAIL));
 279         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 280                            !(filter_flags & FIF_CONTROL));
 281         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 282                            !(filter_flags & FIF_PROMISC_IN_BSS));
 283         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 284                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 285                            !rt2x00dev->intf_ap_count);
 286         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 287         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 288 }
 289
 290 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
 291                                   struct rt2x00_intf *intf,
 292                                   struct rt2x00intf_conf *conf,
 293                                   const unsigned int flags)
 294 {
 295         unsigned int bcn_preload;
 296         u32 reg;
 297
 298         if (flags & CONFIG_UPDATE_TYPE) {
 299                 /*
 300                  * Enable beacon config
 301                  */
 302                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
 303                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 304                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 305                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 306
 307                 /*
 308                  * Enable synchronisation.
 309                  */
 310                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 311                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 312                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 313                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 314                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 315         }
 316
 317         if (flags & CONFIG_UPDATE_MAC)
 318                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 319                                               conf->mac, sizeof(conf->mac));
 320
 321         if (flags & CONFIG_UPDATE_BSSID)
 322                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 323                                               conf->bssid, sizeof(conf->bssid));
 324 }
 325
 326 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
 327                                  struct rt2x00lib_erp *erp)
 328 {
 329         int preamble_mask;
 330         u32 reg;
 331
 332         /*
 333          * When short preamble is enabled, we should set bit 0x08
 334          */
 335         preamble_mask = erp->short_preamble << 3;
 336
 337         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 338         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, erp->ack_timeout);
 339         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 340                            erp->ack_consume_time);
 341         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 342         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 343         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 344
 345         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 346         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 347         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 348         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
 349         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 350
 351         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 352         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 353         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 354         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
 355         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 356
 357         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 358         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 359         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 360         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
 361         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 362
 363         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 364         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 365         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 366         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
 367         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 368
 369         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
 370
 371         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 372         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
 373         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 374
 375         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 376         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
 377         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
 378         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 379
 380         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 381         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
 382         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
 383         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 384
 385         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 386         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
 387         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
 388         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 389 }
 390
 391 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
 392                                  struct antenna_setup *ant)
 393 {
 394         u8 r1;
 395         u8 r4;
 396
 397         /*
 398          * We should never come here because rt2x00lib is supposed
 399          * to catch this and send us the correct antenna explicitely.
 400          */
 401         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 402                ant->tx == ANTENNA_SW_DIVERSITY);
 403
 404         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 405         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 406
 407         /*
 408          * Configure the TX antenna.
 409          */
 410         switch (ant->tx) {
 411         case ANTENNA_HW_DIVERSITY:
 412                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 413                 break;
 414         case ANTENNA_A:
 415                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 416                 break;
 417         case ANTENNA_B:
 418         default:
 419                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 420                 break;
 421         }
 422
 423         /*
 424          * Configure the RX antenna.
 425          */
 426         switch (ant->rx) {
 427         case ANTENNA_HW_DIVERSITY:
 428                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 429                 break;
 430         case ANTENNA_A:
 431                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 432                 break;
 433         case ANTENNA_B:
 434         default:
 435                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 436                 break;
 437         }
 438
 439         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 440         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 441 }
 442
 443 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 444                                      struct rf_channel *rf)
 445 {
 446         /*
 447          * Switch on tuning bits.
 448          */
 449         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 450         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 451
 452         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 453         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 454         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 455
 456         /*
 457          * RF2420 chipset don't need any additional actions.
 458          */
 459         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 460                 return;
 461
 462         /*
 463          * For the RT2421 chipsets we need to write an invalid
 464          * reference clock rate to activate auto_tune.
 465          * After that we set the value back to the correct channel.
 466          */
 467         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 468         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 469         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 470
 471         msleep(1);
 472
 473         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 474         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 475         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 476
 477         msleep(1);
 478
 479         /*
 480          * Switch off tuning bits.
 481          */
 482         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 483         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 484
 485         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 486         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 487
 488         /*
 489          * Clear false CRC during channel switch.
 490          */
 491         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 492 }
 493
 494 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 495 {
 496         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 497 }
 498
 499 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 500                                          struct rt2x00lib_conf *libconf)
 501 {
 502         u32 reg;
 503
 504         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 505         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
 506                            libconf->conf->long_frame_max_tx_count);
 507         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
 508                            libconf->conf->short_frame_max_tx_count);
 509         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 510 }
 511
 512 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
 513                                 struct rt2x00lib_conf *libconf)
 514 {
 515         enum dev_state state =
 516             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 517                 STATE_SLEEP : STATE_AWAKE;
 518         u32 reg;
 519
 520         if (state == STATE_SLEEP) {
 521                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
 522                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
 523                                    (rt2x00dev->beacon_int - 20) * 16);
 524                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
 525                                    libconf->conf->listen_interval - 1);
 526
 527                 /* We must first disable autowake before it can be enabled */
 528                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
 529                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 530
 531                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
 532                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
 533         }
 534
 535         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 536 }
 537
 538 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 539                              struct rt2x00lib_conf *libconf,
 540                              const unsigned int flags)
 541 {
 542         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 543                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
 544         if (flags & IEEE80211_CONF_CHANGE_POWER)
 545                 rt2400pci_config_txpower(rt2x00dev,
 546                                          libconf->conf->power_level);
 547         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
 548                 rt2400pci_config_retry_limit(rt2x00dev, libconf);
 549         if (flags & IEEE80211_CONF_CHANGE_PS)
 550                 rt2400pci_config_ps(rt2x00dev, libconf);
 551 }
 552
 553 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 554                                 const int cw_min, const int cw_max)
 555 {
 556         u32 reg;
 557
 558         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 559         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
 560         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
 561         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 562 }
 563
 564 /*
 565  * Link tuning
 566  */
 567 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
 568                                  struct link_qual *qual)
 569 {
 570         u32 reg;
 571         u8 bbp;
 572
 573         /*
 574          * Update FCS error count from register.
 575          */
 576         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 577         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 578
 579         /*
 580          * Update False CCA count from register.
 581          */
 582         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 583         qual->false_cca = bbp;
 584 }
 585
 586 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
 587                                      struct link_qual *qual, u8 vgc_level)
 588 {
 589         rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
 590         qual->vgc_level = vgc_level;
 591         qual->vgc_level_reg = vgc_level;
 592 }
 593
 594 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
 595                                   struct link_qual *qual)
 596 {
 597         rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
 598 }
 599
 600 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
 601                                  struct link_qual *qual, const u32 count)
 602 {
 603         /*
 604          * The link tuner should not run longer then 60 seconds,
 605          * and should run once every 2 seconds.
 606          */
 607         if (count > 60 || !(count & 1))
 608                 return;
 609
 610         /*
 611          * Base r13 link tuning on the false cca count.
 612          */
 613         if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
 614                 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
 615         else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
 616                 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
 617 }
 618
 619 /*
 620  * Initialization functions.
 621  */
 622 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
 623 {
 624         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 625         u32 word;
 626
 627         if (entry->queue->qid == QID_RX) {
 628                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 629
 630                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
 631         } else {
 632                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 633
 634                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
 635                         rt2x00_get_field32(word, TXD_W0_VALID));
 636         }
 637 }
 638
 639 static void rt2400pci_clear_entry(struct queue_entry *entry)
 640 {
 641         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 642         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 643         u32 word;
 644
 645         if (entry->queue->qid == QID_RX) {
 646                 rt2x00_desc_read(entry_priv->desc, 2, &word);
 647                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
 648                 rt2x00_desc_write(entry_priv->desc, 2, word);
 649
 650                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 651                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
 652                 rt2x00_desc_write(entry_priv->desc, 1, word);
 653
 654                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 655                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 656                 rt2x00_desc_write(entry_priv->desc, 0, word);
 657         } else {
 658                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 659                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 660                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 661                 rt2x00_desc_write(entry_priv->desc, 0, word);
 662         }
 663 }
 664
 665 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
 666 {
 667         struct queue_entry_priv_pci *entry_priv;
 668         u32 reg;
 669
 670         /*
 671          * Initialize registers.
 672          */
 673         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 674         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 675         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 676         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 677         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 678         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 679
 680         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 681         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 682         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 683                            entry_priv->desc_dma);
 684         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 685
 686         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 687         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 688         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 689                            entry_priv->desc_dma);
 690         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 691
 692         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
 693         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 694         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 695                            entry_priv->desc_dma);
 696         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 697
 698         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
 699         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 700         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 701                            entry_priv->desc_dma);
 702         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 703
 704         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 705         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 706         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 707         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 708
 709         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 710         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 711         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 712                            entry_priv->desc_dma);
 713         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 714
 715         return 0;
 716 }
 717
 718 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 719 {
 720         u32 reg;
 721
 722         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 723         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 724         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 725         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 726
 727         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 728         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 729         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 730         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 731         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 732
 733         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 734         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 735                            (rt2x00dev->rx->data_size / 128));
 736         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 737
 738         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 739         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
 740         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 741         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
 742         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
 743         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
 744         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 745         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
 746         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
 747         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 748
 749         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 750
 751         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 752         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 753         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 754         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 755         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 756         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 757
 758         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 759         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 760         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 761         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 762         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 763         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 764         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 765         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 766
 767         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 768
 769         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 770                 return -EBUSY;
 771
 772         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 773         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 774
 775         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 776         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 777         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 778
 779         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 780         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 781         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 782         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 783         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 784         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 785
 786         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 787         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 788         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 789         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 790         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 791
 792         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 793         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 794         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 795         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 796
 797         /*
 798          * We must clear the FCS and FIFO error count.
 799          * These registers are cleared on read,
 800          * so we may pass a useless variable to store the value.
 801          */
 802         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 803         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 804
 805         return 0;
 806 }
 807
 808 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 809 {
 810         unsigned int i;
 811         u8 value;
 812
 813         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 814                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 815                 if ((value != 0xff) && (value != 0x00))
 816                         return 0;
 817                 udelay(REGISTER_BUSY_DELAY);
 818         }
 819
 820         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 821         return -EACCES;
 822 }
 823
 824 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 825 {
 826         unsigned int i;
 827         u16 eeprom;
 828         u8 reg_id;
 829         u8 value;
 830
 831         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
 832                 return -EACCES;
 833
 834         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 835         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 836         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 837         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 838         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 839         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 840         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 841         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 842         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 843         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 844         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 845         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 846         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 847         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 848
 849         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 850                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 851
 852                 if (eeprom != 0xffff && eeprom != 0x0000) {
 853                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 854                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 855                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 856                 }
 857         }
 858
 859         return 0;
 860 }
 861
 862 /*
 863  * Device state switch handlers.
 864  */
 865 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 866                                 enum dev_state state)
 867 {
 868         u32 reg;
 869
 870         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 871         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 872                            (state == STATE_RADIO_RX_OFF) ||
 873                            (state == STATE_RADIO_RX_OFF_LINK));
 874         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 875 }
 876
 877 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 878                                  enum dev_state state)
 879 {
 880         int mask = (state == STATE_RADIO_IRQ_OFF);
 881         u32 reg;
 882
 883         /*
 884          * When interrupts are being enabled, the interrupt registers
 885          * should clear the register to assure a clean state.
 886          */
 887         if (state == STATE_RADIO_IRQ_ON) {
 888                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 889                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 890         }
 891
 892         /*
 893          * Only toggle the interrupts bits we are going to use.
 894          * Non-checked interrupt bits are disabled by default.
 895          */
 896         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 897         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 898         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 899         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 900         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 901         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 902         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 903 }
 904
 905 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 906 {
 907         /*
 908          * Initialize all registers.
 909          */
 910         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
 911                      rt2400pci_init_registers(rt2x00dev) ||
 912                      rt2400pci_init_bbp(rt2x00dev)))
 913                 return -EIO;
 914
 915         return 0;
 916 }
 917
 918 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 919 {
 920         /*
 921          * Disable power
 922          */
 923         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 924 }
 925
 926 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 927                                enum dev_state state)
 928 {
 929         u32 reg;
 930         unsigned int i;
 931         char put_to_sleep;
 932         char bbp_state;
 933         char rf_state;
 934
 935         put_to_sleep = (state != STATE_AWAKE);
 936
 937         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 938         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 939         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 940         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 941         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 942         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 943
 944         /*
 945          * Device is not guaranteed to be in the requested state yet.
 946          * We must wait until the register indicates that the
 947          * device has entered the correct state.
 948          */
 949         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 950                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 951                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
 952                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
 953                 if (bbp_state == state && rf_state == state)
 954                         return 0;
 955                 msleep(10);
 956         }
 957
 958         return -EBUSY;
 959 }
 960
 961 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 962                                       enum dev_state state)
 963 {
 964         int retval = 0;
 965
 966         switch (state) {
 967         case STATE_RADIO_ON:
 968                 retval = rt2400pci_enable_radio(rt2x00dev);
 969                 break;
 970         case STATE_RADIO_OFF:
 971                 rt2400pci_disable_radio(rt2x00dev);
 972                 break;
 973         case STATE_RADIO_RX_ON:
 974         case STATE_RADIO_RX_ON_LINK:
 975         case STATE_RADIO_RX_OFF:
 976         case STATE_RADIO_RX_OFF_LINK:
 977                 rt2400pci_toggle_rx(rt2x00dev, state);
 978                 break;
 979         case STATE_RADIO_IRQ_ON:
 980         case STATE_RADIO_IRQ_OFF:
 981                 rt2400pci_toggle_irq(rt2x00dev, state);
 982                 break;
 983         case STATE_DEEP_SLEEP:
 984         case STATE_SLEEP:
 985         case STATE_STANDBY:
 986         case STATE_AWAKE:
 987                 retval = rt2400pci_set_state(rt2x00dev, state);
 988                 break;
 989         default:
 990                 retval = -ENOTSUPP;
 991                 break;
 992         }
 993
 994         if (unlikely(retval))
 995                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 996                       state, retval);
 997
 998         return retval;
 999 }
1000
1001 /*
1002  * TX descriptor initialization
1003  */
1004 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1005                                     struct sk_buff *skb,
1006                                     struct txentry_desc *txdesc)
1007 {
1008         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1009         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1010         __le32 *txd = skbdesc->desc;
1011         u32 word;
1012
1013         /*
1014          * Start writing the descriptor words.
1015          */
1016         rt2x00_desc_read(entry_priv->desc, 1, &word);
1017         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1018         rt2x00_desc_write(entry_priv->desc, 1, word);
1019
1020         rt2x00_desc_read(txd, 2, &word);
1021         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1022         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1023         rt2x00_desc_write(txd, 2, word);
1024
1025         rt2x00_desc_read(txd, 3, &word);
1026         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1027         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1028         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1029         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1030         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1031         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1032         rt2x00_desc_write(txd, 3, word);
1033
1034         rt2x00_desc_read(txd, 4, &word);
1035         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1036         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1037         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1038         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1039         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1040         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1041         rt2x00_desc_write(txd, 4, word);
1042
1043         rt2x00_desc_read(txd, 0, &word);
1044         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1045         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1046         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1047                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1048         rt2x00_set_field32(&word, TXD_W0_ACK,
1049                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1050         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1051                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1052         rt2x00_set_field32(&word, TXD_W0_RTS,
1053                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1054         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1055         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1056                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1057         rt2x00_desc_write(txd, 0, word);
1058 }
1059
1060 /*
1061  * TX data initialization
1062  */
1063 static void rt2400pci_write_beacon(struct queue_entry *entry)
1064 {
1065         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1066         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1067         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1068         u32 word;
1069         u32 reg;
1070
1071         /*
1072          * Disable beaconing while we are reloading the beacon data,
1073          * otherwise we might be sending out invalid data.
1074          */
1075         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1076         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1077         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1078         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1079         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1080
1081         /*
1082          * Replace rt2x00lib allocated descriptor with the
1083          * pointer to the _real_ hardware descriptor.
1084          * After that, map the beacon to DMA and update the
1085          * descriptor.
1086          */
1087         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1088         skbdesc->desc = entry_priv->desc;
1089
1090         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1091
1092         rt2x00_desc_read(entry_priv->desc, 1, &word);
1093         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1094         rt2x00_desc_write(entry_priv->desc, 1, word);
1095 }
1096
1097 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1098                                     const enum data_queue_qid queue)
1099 {
1100         u32 reg;
1101
1102         if (queue == QID_BEACON) {
1103                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1104                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1105                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1106                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1107                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1108                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1109                 }
1110                 return;
1111         }
1112
1113         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1114         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1115         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1116         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1117         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1118 }
1119
1120 static void rt2400pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1121                                     const enum data_queue_qid qid)
1122 {
1123         u32 reg;
1124
1125         if (qid == QID_BEACON) {
1126                 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1127         } else {
1128                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1129                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1130                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1131         }
1132 }
1133
1134 /*
1135  * RX control handlers
1136  */
1137 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1138                                   struct rxdone_entry_desc *rxdesc)
1139 {
1140         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1141         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1142         u32 word0;
1143         u32 word2;
1144         u32 word3;
1145         u32 word4;
1146         u64 tsf;
1147         u32 rx_low;
1148         u32 rx_high;
1149
1150         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1151         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1152         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1153         rt2x00_desc_read(entry_priv->desc, 4, &word4);
1154
1155         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1156                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1157         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1158                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1159
1160         /*
1161          * We only get the lower 32bits from the timestamp,
1162          * to get the full 64bits we must complement it with
1163          * the timestamp from get_tsf().
1164          * Note that when a wraparound of the lower 32bits
1165          * has occurred between the frame arrival and the get_tsf()
1166          * call, we must decrease the higher 32bits with 1 to get
1167          * to correct value.
1168          */
1169         tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1170         rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1171         rx_high = upper_32_bits(tsf);
1172
1173         if ((u32)tsf <= rx_low)
1174                 rx_high--;
1175
1176         /*
1177          * Obtain the status about this packet.
1178          * The signal is the PLCP value, and needs to be stripped
1179          * of the preamble bit (0x08).
1180          */
1181         rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1182         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1183         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1184             entry->queue->rt2x00dev->rssi_offset;
1185         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1186
1187         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1188         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1189                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1190 }
1191
1192 /*
1193  * Interrupt functions.
1194  */
1195 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1196                              const enum data_queue_qid queue_idx)
1197 {
1198         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1199         struct queue_entry_priv_pci *entry_priv;
1200         struct queue_entry *entry;
1201         struct txdone_entry_desc txdesc;
1202         u32 word;
1203
1204         while (!rt2x00queue_empty(queue)) {
1205                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1206                 entry_priv = entry->priv_data;
1207                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1208
1209                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1210                     !rt2x00_get_field32(word, TXD_W0_VALID))
1211                         break;
1212
1213                 /*
1214                  * Obtain the status about this packet.
1215                  */
1216                 txdesc.flags = 0;
1217                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1218                 case 0: /* Success */
1219                 case 1: /* Success with retry */
1220                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1221                         break;
1222                 case 2: /* Failure, excessive retries */
1223                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1224                         /* Don't break, this is a failed frame! */
1225                 default: /* Failure */
1226                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1227                 }
1228                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1229
1230                 rt2x00lib_txdone(entry, &txdesc);
1231         }
1232 }
1233
1234 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1235 {
1236         struct rt2x00_dev *rt2x00dev = dev_instance;
1237         u32 reg;
1238
1239         /*
1240          * Get the interrupt sources & saved to local variable.
1241          * Write register value back to clear pending interrupts.
1242          */
1243         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1244         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1245
1246         if (!reg)
1247                 return IRQ_NONE;
1248
1249         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1250                 return IRQ_HANDLED;
1251
1252         /*
1253          * Handle interrupts, walk through all bits
1254          * and run the tasks, the bits are checked in order of
1255          * priority.
1256          */
1257
1258         /*
1259          * 1 - Beacon timer expired interrupt.
1260          */
1261         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1262                 rt2x00lib_beacondone(rt2x00dev);
1263
1264         /*
1265          * 2 - Rx ring done interrupt.
1266          */
1267         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1268                 rt2x00pci_rxdone(rt2x00dev);
1269
1270         /*
1271          * 3 - Atim ring transmit done interrupt.
1272          */
1273         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1274                 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1275
1276         /*
1277          * 4 - Priority ring transmit done interrupt.
1278          */
1279         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1280                 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1281
1282         /*
1283          * 5 - Tx ring transmit done interrupt.
1284          */
1285         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1286                 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1287
1288         return IRQ_HANDLED;
1289 }
1290
1291 /*
1292  * Device probe functions.
1293  */
1294 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1295 {
1296         struct eeprom_93cx6 eeprom;
1297         u32 reg;
1298         u16 word;
1299         u8 *mac;
1300
1301         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1302
1303         eeprom.data = rt2x00dev;
1304         eeprom.register_read = rt2400pci_eepromregister_read;
1305         eeprom.register_write = rt2400pci_eepromregister_write;
1306         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1307             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1308         eeprom.reg_data_in = 0;
1309         eeprom.reg_data_out = 0;
1310         eeprom.reg_data_clock = 0;
1311         eeprom.reg_chip_select = 0;
1312
1313         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1314                                EEPROM_SIZE / sizeof(u16));
1315
1316         /*
1317          * Start validation of the data that has been read.
1318          */
1319         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1320         if (!is_valid_ether_addr(mac)) {
1321                 random_ether_addr(mac);
1322                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1323         }
1324
1325         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1326         if (word == 0xffff) {
1327                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1328                 return -EINVAL;
1329         }
1330
1331         return 0;
1332 }
1333
1334 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1335 {
1336         u32 reg;
1337         u16 value;
1338         u16 eeprom;
1339
1340         /*
1341          * Read EEPROM word for configuration.
1342          */
1343         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1344
1345         /*
1346          * Identify RF chipset.
1347          */
1348         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1349         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1350         rt2x00_set_chip_rf(rt2x00dev, value, reg);
1351
1352         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1353             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1354                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1355                 return -ENODEV;
1356         }
1357
1358         /*
1359          * Identify default antenna configuration.
1360          */
1361         rt2x00dev->default_ant.tx =
1362             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1363         rt2x00dev->default_ant.rx =
1364             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1365
1366         /*
1367          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1368          * I am not 100% sure about this, but the legacy drivers do not
1369          * indicate antenna swapping in software is required when
1370          * diversity is enabled.
1371          */
1372         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1373                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1374         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1375                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1376
1377         /*
1378          * Store led mode, for correct led behaviour.
1379          */
1380 #ifdef CONFIG_RT2X00_LIB_LEDS
1381         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1382
1383         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1384         if (value == LED_MODE_TXRX_ACTIVITY ||
1385             value == LED_MODE_DEFAULT ||
1386             value == LED_MODE_ASUS)
1387                 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1388                                    LED_TYPE_ACTIVITY);
1389 #endif /* CONFIG_RT2X00_LIB_LEDS */
1390
1391         /*
1392          * Detect if this device has an hardware controlled radio.
1393          */
1394 #ifdef CONFIG_RT2X00_LIB_RFKILL
1395         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1396                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1397 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1398
1399         /*
1400          * Check if the BBP tuning should be enabled.
1401          */
1402         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1403                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1404
1405         return 0;
1406 }
1407
1408 /*
1409  * RF value list for RF2420 & RF2421
1410  * Supports: 2.4 GHz
1411  */
1412 static const struct rf_channel rf_vals_b[] = {
1413         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1414         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1415         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1416         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1417         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1418         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1419         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1420         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1421         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1422         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1423         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1424         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1425         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1426         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1427 };
1428
1429 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1430 {
1431         struct hw_mode_spec *spec = &rt2x00dev->spec;
1432         struct channel_info *info;
1433         char *tx_power;
1434         unsigned int i;
1435
1436         /*
1437          * Initialize all hw fields.
1438          */
1439         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1440                                IEEE80211_HW_SIGNAL_DBM |
1441                                IEEE80211_HW_SUPPORTS_PS |
1442                                IEEE80211_HW_PS_NULLFUNC_STACK;
1443         rt2x00dev->hw->extra_tx_headroom = 0;
1444
1445         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1446         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1447                                 rt2x00_eeprom_addr(rt2x00dev,
1448                                                    EEPROM_MAC_ADDR_0));
1449
1450         /*
1451          * Initialize hw_mode information.
1452          */
1453         spec->supported_bands = SUPPORT_BAND_2GHZ;
1454         spec->supported_rates = SUPPORT_RATE_CCK;
1455
1456         spec->num_channels = ARRAY_SIZE(rf_vals_b);
1457         spec->channels = rf_vals_b;
1458
1459         /*
1460          * Create channel information array
1461          */
1462         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1463         if (!info)
1464                 return -ENOMEM;
1465
1466         spec->channels_info = info;
1467
1468         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1469         for (i = 0; i < 14; i++)
1470                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1471
1472         return 0;
1473 }
1474
1475 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1476 {
1477         int retval;
1478
1479         /*
1480          * Allocate eeprom data.
1481          */
1482         retval = rt2400pci_validate_eeprom(rt2x00dev);
1483         if (retval)
1484                 return retval;
1485
1486         retval = rt2400pci_init_eeprom(rt2x00dev);
1487         if (retval)
1488                 return retval;
1489
1490         /*
1491          * Initialize hw specifications.
1492          */
1493         retval = rt2400pci_probe_hw_mode(rt2x00dev);
1494         if (retval)
1495                 return retval;
1496
1497         /*
1498          * This device requires the atim queue and DMA-mapped skbs.
1499          */
1500         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1501         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1502
1503         /*
1504          * Set the rssi offset.
1505          */
1506         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1507
1508         return 0;
1509 }
1510
1511 /*
1512  * IEEE80211 stack callback functions.
1513  */
1514 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1515                              const struct ieee80211_tx_queue_params *params)
1516 {
1517         struct rt2x00_dev *rt2x00dev = hw->priv;
1518
1519         /*
1520          * We don't support variating cw_min and cw_max variables
1521          * per queue. So by default we only configure the TX queue,
1522          * and ignore all other configurations.
1523          */
1524         if (queue != 0)
1525                 return -EINVAL;
1526
1527         if (rt2x00mac_conf_tx(hw, queue, params))
1528                 return -EINVAL;
1529
1530         /*
1531          * Write configuration to register.
1532          */
1533         rt2400pci_config_cw(rt2x00dev,
1534                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1535
1536         return 0;
1537 }
1538
1539 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1540 {
1541         struct rt2x00_dev *rt2x00dev = hw->priv;
1542         u64 tsf;
1543         u32 reg;
1544
1545         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1546         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1547         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1548         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1549
1550         return tsf;
1551 }
1552
1553 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1554 {
1555         struct rt2x00_dev *rt2x00dev = hw->priv;
1556         u32 reg;
1557
1558         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1559         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1560 }
1561
1562 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1563         .tx                     = rt2x00mac_tx,
1564         .start                  = rt2x00mac_start,
1565         .stop                   = rt2x00mac_stop,
1566         .add_interface          = rt2x00mac_add_interface,
1567         .remove_interface       = rt2x00mac_remove_interface,
1568         .config                 = rt2x00mac_config,
1569         .configure_filter       = rt2x00mac_configure_filter,
1570         .get_stats              = rt2x00mac_get_stats,
1571         .bss_info_changed       = rt2x00mac_bss_info_changed,
1572         .conf_tx                = rt2400pci_conf_tx,
1573         .get_tx_stats           = rt2x00mac_get_tx_stats,
1574         .get_tsf                = rt2400pci_get_tsf,
1575         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1576 };
1577
1578 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1579         .irq_handler            = rt2400pci_interrupt,
1580         .probe_hw               = rt2400pci_probe_hw,
1581         .initialize             = rt2x00pci_initialize,
1582         .uninitialize           = rt2x00pci_uninitialize,
1583         .get_entry_state        = rt2400pci_get_entry_state,
1584         .clear_entry            = rt2400pci_clear_entry,
1585         .set_device_state       = rt2400pci_set_device_state,
1586         .rfkill_poll            = rt2400pci_rfkill_poll,
1587         .link_stats             = rt2400pci_link_stats,
1588         .reset_tuner            = rt2400pci_reset_tuner,
1589         .link_tuner             = rt2400pci_link_tuner,
1590         .write_tx_desc          = rt2400pci_write_tx_desc,
1591         .write_tx_data          = rt2x00pci_write_tx_data,
1592         .write_beacon           = rt2400pci_write_beacon,
1593         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1594         .kill_tx_queue          = rt2400pci_kill_tx_queue,
1595         .fill_rxdone            = rt2400pci_fill_rxdone,
1596         .config_filter          = rt2400pci_config_filter,
1597         .config_intf            = rt2400pci_config_intf,
1598         .config_erp             = rt2400pci_config_erp,
1599         .config_ant             = rt2400pci_config_ant,
1600         .config                 = rt2400pci_config,
1601 };
1602
1603 static const struct data_queue_desc rt2400pci_queue_rx = {
1604         .entry_num              = RX_ENTRIES,
1605         .data_size              = DATA_FRAME_SIZE,
1606         .desc_size              = RXD_DESC_SIZE,
1607         .priv_size              = sizeof(struct queue_entry_priv_pci),
1608 };
1609
1610 static const struct data_queue_desc rt2400pci_queue_tx = {
1611         .entry_num              = TX_ENTRIES,
1612         .data_size              = DATA_FRAME_SIZE,
1613         .desc_size              = TXD_DESC_SIZE,
1614         .priv_size              = sizeof(struct queue_entry_priv_pci),
1615 };
1616
1617 static const struct data_queue_desc rt2400pci_queue_bcn = {
1618         .entry_num              = BEACON_ENTRIES,
1619         .data_size              = MGMT_FRAME_SIZE,
1620         .desc_size              = TXD_DESC_SIZE,
1621         .priv_size              = sizeof(struct queue_entry_priv_pci),
1622 };
1623
1624 static const struct data_queue_desc rt2400pci_queue_atim = {
1625         .entry_num              = ATIM_ENTRIES,
1626         .data_size              = DATA_FRAME_SIZE,
1627         .desc_size              = TXD_DESC_SIZE,
1628         .priv_size              = sizeof(struct queue_entry_priv_pci),
1629 };
1630
1631 static const struct rt2x00_ops rt2400pci_ops = {
1632         .name           = KBUILD_MODNAME,
1633         .max_sta_intf   = 1,
1634         .max_ap_intf    = 1,
1635         .eeprom_size    = EEPROM_SIZE,
1636         .rf_size        = RF_SIZE,
1637         .tx_queues      = NUM_TX_QUEUES,
1638         .rx             = &rt2400pci_queue_rx,
1639         .tx             = &rt2400pci_queue_tx,
1640         .bcn            = &rt2400pci_queue_bcn,
1641         .atim           = &rt2400pci_queue_atim,
1642         .lib            = &rt2400pci_rt2x00_ops,
1643         .hw             = &rt2400pci_mac80211_ops,
1644 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1645         .debugfs        = &rt2400pci_rt2x00debug,
1646 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1647 };
1648
1649 /*
1650  * RT2400pci module information.
1651  */
1652 static struct pci_device_id rt2400pci_device_table[] = {
1653         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1654         { 0, }
1655 };
1656
1657 MODULE_AUTHOR(DRV_PROJECT);
1658 MODULE_VERSION(DRV_VERSION);
1659 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1660 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1661 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1662 MODULE_LICENSE("GPL");
1663
1664 static struct pci_driver rt2400pci_driver = {
1665         .name           = KBUILD_MODNAME,
1666         .id_table       = rt2400pci_device_table,
1667         .probe          = rt2x00pci_probe,
1668         .remove         = __devexit_p(rt2x00pci_remove),
1669         .suspend        = rt2x00pci_suspend,
1670         .resume         = rt2x00pci_resume,
1671 };
1672
1673 static int __init rt2400pci_init(void)
1674 {
1675         return pci_register_driver(&rt2400pci_driver);
1676 }
1677
1678 static void __exit rt2400pci_exit(void)
1679 {
1680         pci_unregister_driver(&rt2400pci_driver);
1681 }
1682
1683 module_init(rt2400pci_init);
1684 module_exit(rt2400pci_exit);