30185ad28d9321ab887f08e3c757417430497b05
[pandora-kernel.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
1 /*
2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt2400pci
23         Abstract: rt2400pci device specific routines.
24         Supported chipsets: RT2460.
25  */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
38
39 /*
40  * Register access.
41  * All access to the CSR registers will go through the methods
42  * rt2x00pci_register_read and rt2x00pci_register_write.
43  * BBP and RF register require indirect register access,
44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
45  * These indirect registers work with busy bits,
46  * and we will try maximal REGISTER_BUSY_COUNT times to access
47  * the register while taking a REGISTER_BUSY_DELAY us delay
48  * between each attampt. When the busy bit is still set at that time,
49  * the access attempt is considered to have failed,
50  * and we will print an error.
51  */
52 #define WAIT_FOR_BBP(__dev, __reg) \
53         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54 #define WAIT_FOR_RF(__dev, __reg) \
55         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
56
57 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
58                                 const unsigned int word, const u8 value)
59 {
60         u32 reg;
61
62         mutex_lock(&rt2x00dev->csr_mutex);
63
64         /*
65          * Wait until the BBP becomes available, afterwards we
66          * can safely write the new data into the register.
67          */
68         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
69                 reg = 0;
70                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
71                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
72                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
73                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
74
75                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
76         }
77
78         mutex_unlock(&rt2x00dev->csr_mutex);
79 }
80
81 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
82                                const unsigned int word, u8 *value)
83 {
84         u32 reg;
85
86         mutex_lock(&rt2x00dev->csr_mutex);
87
88         /*
89          * Wait until the BBP becomes available, afterwards we
90          * can safely write the read request into the register.
91          * After the data has been written, we wait until hardware
92          * returns the correct value, if at any time the register
93          * doesn't become available in time, reg will be 0xffffffff
94          * which means we return 0xff to the caller.
95          */
96         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97                 reg = 0;
98                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
99                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
100                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
101
102                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
103
104                 WAIT_FOR_BBP(rt2x00dev, &reg);
105         }
106
107         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
108
109         mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
113                                const unsigned int word, const u32 value)
114 {
115         u32 reg;
116
117         mutex_lock(&rt2x00dev->csr_mutex);
118
119         /*
120          * Wait until the RF becomes available, afterwards we
121          * can safely write the new data into the register.
122          */
123         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
124                 reg = 0;
125                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
126                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
127                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
128                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
129
130                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
131                 rt2x00_rf_write(rt2x00dev, word, value);
132         }
133
134         mutex_unlock(&rt2x00dev->csr_mutex);
135 }
136
137 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
138 {
139         struct rt2x00_dev *rt2x00dev = eeprom->data;
140         u32 reg;
141
142         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
143
144         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
145         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
146         eeprom->reg_data_clock =
147             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
148         eeprom->reg_chip_select =
149             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
150 }
151
152 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
153 {
154         struct rt2x00_dev *rt2x00dev = eeprom->data;
155         u32 reg = 0;
156
157         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
159         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
160                            !!eeprom->reg_data_clock);
161         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
162                            !!eeprom->reg_chip_select);
163
164         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
165 }
166
167 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
168 static const struct rt2x00debug rt2400pci_rt2x00debug = {
169         .owner  = THIS_MODULE,
170         .csr    = {
171                 .read           = rt2x00pci_register_read,
172                 .write          = rt2x00pci_register_write,
173                 .flags          = RT2X00DEBUGFS_OFFSET,
174                 .word_base      = CSR_REG_BASE,
175                 .word_size      = sizeof(u32),
176                 .word_count     = CSR_REG_SIZE / sizeof(u32),
177         },
178         .eeprom = {
179                 .read           = rt2x00_eeprom_read,
180                 .write          = rt2x00_eeprom_write,
181                 .word_base      = EEPROM_BASE,
182                 .word_size      = sizeof(u16),
183                 .word_count     = EEPROM_SIZE / sizeof(u16),
184         },
185         .bbp    = {
186                 .read           = rt2400pci_bbp_read,
187                 .write          = rt2400pci_bbp_write,
188                 .word_base      = BBP_BASE,
189                 .word_size      = sizeof(u8),
190                 .word_count     = BBP_SIZE / sizeof(u8),
191         },
192         .rf     = {
193                 .read           = rt2x00_rf_read,
194                 .write          = rt2400pci_rf_write,
195                 .word_base      = RF_BASE,
196                 .word_size      = sizeof(u32),
197                 .word_count     = RF_SIZE / sizeof(u32),
198         },
199 };
200 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
201
202 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
203 {
204         u32 reg;
205
206         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
207         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
208 }
209
210 #ifdef CONFIG_RT2X00_LIB_LEDS
211 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
212                                      enum led_brightness brightness)
213 {
214         struct rt2x00_led *led =
215             container_of(led_cdev, struct rt2x00_led, led_dev);
216         unsigned int enabled = brightness != LED_OFF;
217         u32 reg;
218
219         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
220
221         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
222                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
223         else if (led->type == LED_TYPE_ACTIVITY)
224                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
225
226         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
227 }
228
229 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
230                                unsigned long *delay_on,
231                                unsigned long *delay_off)
232 {
233         struct rt2x00_led *led =
234             container_of(led_cdev, struct rt2x00_led, led_dev);
235         u32 reg;
236
237         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
238         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
239         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
240         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
241
242         return 0;
243 }
244
245 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
246                                struct rt2x00_led *led,
247                                enum led_type type)
248 {
249         led->rt2x00dev = rt2x00dev;
250         led->type = type;
251         led->led_dev.brightness_set = rt2400pci_brightness_set;
252         led->led_dev.blink_set = rt2400pci_blink_set;
253         led->flags = LED_INITIALIZED;
254 }
255 #endif /* CONFIG_RT2X00_LIB_LEDS */
256
257 /*
258  * Configuration handlers.
259  */
260 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
261                                     const unsigned int filter_flags)
262 {
263         u32 reg;
264
265         /*
266          * Start configuration steps.
267          * Note that the version error will always be dropped
268          * since there is no filter for it at this time.
269          */
270         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
271         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
272                            !(filter_flags & FIF_FCSFAIL));
273         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
274                            !(filter_flags & FIF_PLCPFAIL));
275         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
276                            !(filter_flags & FIF_CONTROL));
277         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
278                            !(filter_flags & FIF_PROMISC_IN_BSS));
279         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
280                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
281                            !rt2x00dev->intf_ap_count);
282         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
283         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
284 }
285
286 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
287                                   struct rt2x00_intf *intf,
288                                   struct rt2x00intf_conf *conf,
289                                   const unsigned int flags)
290 {
291         unsigned int bcn_preload;
292         u32 reg;
293
294         if (flags & CONFIG_UPDATE_TYPE) {
295                 /*
296                  * Enable beacon config
297                  */
298                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
299                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
300                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
301                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
302
303                 /*
304                  * Enable synchronisation.
305                  */
306                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
307                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
308                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
309                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
310                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
311         }
312
313         if (flags & CONFIG_UPDATE_MAC)
314                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
315                                               conf->mac, sizeof(conf->mac));
316
317         if (flags & CONFIG_UPDATE_BSSID)
318                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
319                                               conf->bssid, sizeof(conf->bssid));
320 }
321
322 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
323                                  struct rt2x00lib_erp *erp)
324 {
325         int preamble_mask;
326         u32 reg;
327
328         /*
329          * When short preamble is enabled, we should set bit 0x08
330          */
331         preamble_mask = erp->short_preamble << 3;
332
333         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
334         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, erp->ack_timeout);
335         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
336                            erp->ack_consume_time);
337         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
338         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
339         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
340
341         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
342         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
343         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
344         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
345         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
346
347         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
348         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
349         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
350         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
351         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
352
353         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
354         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
355         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
356         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
357         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
358
359         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
360         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
361         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
362         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
363         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
364
365         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
366
367         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
368         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
369         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
370
371         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
372         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
373         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
374         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
375
376         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
377         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
378         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
379         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
380
381         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
382         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
383         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
384         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
385 }
386
387 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
388                                  struct antenna_setup *ant)
389 {
390         u8 r1;
391         u8 r4;
392
393         /*
394          * We should never come here because rt2x00lib is supposed
395          * to catch this and send us the correct antenna explicitely.
396          */
397         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
398                ant->tx == ANTENNA_SW_DIVERSITY);
399
400         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
401         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
402
403         /*
404          * Configure the TX antenna.
405          */
406         switch (ant->tx) {
407         case ANTENNA_HW_DIVERSITY:
408                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
409                 break;
410         case ANTENNA_A:
411                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
412                 break;
413         case ANTENNA_B:
414         default:
415                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
416                 break;
417         }
418
419         /*
420          * Configure the RX antenna.
421          */
422         switch (ant->rx) {
423         case ANTENNA_HW_DIVERSITY:
424                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
425                 break;
426         case ANTENNA_A:
427                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
428                 break;
429         case ANTENNA_B:
430         default:
431                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
432                 break;
433         }
434
435         rt2400pci_bbp_write(rt2x00dev, 4, r4);
436         rt2400pci_bbp_write(rt2x00dev, 1, r1);
437 }
438
439 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
440                                      struct rf_channel *rf)
441 {
442         /*
443          * Switch on tuning bits.
444          */
445         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
446         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
447
448         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
449         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
450         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
451
452         /*
453          * RF2420 chipset don't need any additional actions.
454          */
455         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
456                 return;
457
458         /*
459          * For the RT2421 chipsets we need to write an invalid
460          * reference clock rate to activate auto_tune.
461          * After that we set the value back to the correct channel.
462          */
463         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
464         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
465         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
466
467         msleep(1);
468
469         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
470         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
471         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
472
473         msleep(1);
474
475         /*
476          * Switch off tuning bits.
477          */
478         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
479         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
480
481         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
482         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
483
484         /*
485          * Clear false CRC during channel switch.
486          */
487         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
488 }
489
490 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
491 {
492         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
493 }
494
495 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
496                                          struct rt2x00lib_conf *libconf)
497 {
498         u32 reg;
499
500         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
501         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
502                            libconf->conf->long_frame_max_tx_count);
503         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
504                            libconf->conf->short_frame_max_tx_count);
505         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
506 }
507
508 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
509                                 struct rt2x00lib_conf *libconf)
510 {
511         enum dev_state state =
512             (libconf->conf->flags & IEEE80211_CONF_PS) ?
513                 STATE_SLEEP : STATE_AWAKE;
514         u32 reg;
515
516         if (state == STATE_SLEEP) {
517                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
518                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
519                                    (rt2x00dev->beacon_int - 20) * 16);
520                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
521                                    libconf->conf->listen_interval - 1);
522
523                 /* We must first disable autowake before it can be enabled */
524                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
525                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
526
527                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
528                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
529         }
530
531         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
532 }
533
534 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
535                              struct rt2x00lib_conf *libconf,
536                              const unsigned int flags)
537 {
538         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
539                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
540         if (flags & IEEE80211_CONF_CHANGE_POWER)
541                 rt2400pci_config_txpower(rt2x00dev,
542                                          libconf->conf->power_level);
543         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
544                 rt2400pci_config_retry_limit(rt2x00dev, libconf);
545         if (flags & IEEE80211_CONF_CHANGE_PS)
546                 rt2400pci_config_ps(rt2x00dev, libconf);
547 }
548
549 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
550                                 const int cw_min, const int cw_max)
551 {
552         u32 reg;
553
554         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
555         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
556         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
557         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
558 }
559
560 /*
561  * Link tuning
562  */
563 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
564                                  struct link_qual *qual)
565 {
566         u32 reg;
567         u8 bbp;
568
569         /*
570          * Update FCS error count from register.
571          */
572         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
573         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
574
575         /*
576          * Update False CCA count from register.
577          */
578         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
579         qual->false_cca = bbp;
580 }
581
582 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
583                                      struct link_qual *qual, u8 vgc_level)
584 {
585         rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
586         qual->vgc_level = vgc_level;
587         qual->vgc_level_reg = vgc_level;
588 }
589
590 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
591                                   struct link_qual *qual)
592 {
593         rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
594 }
595
596 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
597                                  struct link_qual *qual, const u32 count)
598 {
599         /*
600          * The link tuner should not run longer then 60 seconds,
601          * and should run once every 2 seconds.
602          */
603         if (count > 60 || !(count & 1))
604                 return;
605
606         /*
607          * Base r13 link tuning on the false cca count.
608          */
609         if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
610                 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
611         else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
612                 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
613 }
614
615 /*
616  * Initialization functions.
617  */
618 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
619 {
620         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
621         u32 word;
622
623         if (entry->queue->qid == QID_RX) {
624                 rt2x00_desc_read(entry_priv->desc, 0, &word);
625
626                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
627         } else {
628                 rt2x00_desc_read(entry_priv->desc, 0, &word);
629
630                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
631                         rt2x00_get_field32(word, TXD_W0_VALID));
632         }
633 }
634
635 static void rt2400pci_clear_entry(struct queue_entry *entry)
636 {
637         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
638         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
639         u32 word;
640
641         if (entry->queue->qid == QID_RX) {
642                 rt2x00_desc_read(entry_priv->desc, 2, &word);
643                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
644                 rt2x00_desc_write(entry_priv->desc, 2, word);
645
646                 rt2x00_desc_read(entry_priv->desc, 1, &word);
647                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
648                 rt2x00_desc_write(entry_priv->desc, 1, word);
649
650                 rt2x00_desc_read(entry_priv->desc, 0, &word);
651                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
652                 rt2x00_desc_write(entry_priv->desc, 0, word);
653         } else {
654                 rt2x00_desc_read(entry_priv->desc, 0, &word);
655                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
656                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
657                 rt2x00_desc_write(entry_priv->desc, 0, word);
658         }
659 }
660
661 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
662 {
663         struct queue_entry_priv_pci *entry_priv;
664         u32 reg;
665
666         /*
667          * Initialize registers.
668          */
669         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
670         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
671         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
672         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
673         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
674         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
675
676         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
677         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
678         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
679                            entry_priv->desc_dma);
680         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
681
682         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
683         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
684         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
685                            entry_priv->desc_dma);
686         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
687
688         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
689         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
690         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
691                            entry_priv->desc_dma);
692         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
693
694         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
695         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
696         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
697                            entry_priv->desc_dma);
698         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
699
700         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
701         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
702         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
703         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
704
705         entry_priv = rt2x00dev->rx->entries[0].priv_data;
706         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
707         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
708                            entry_priv->desc_dma);
709         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
710
711         return 0;
712 }
713
714 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
715 {
716         u32 reg;
717
718         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
719         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
720         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
721         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
722
723         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
724         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
725         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
726         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
727         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
728
729         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
730         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
731                            (rt2x00dev->rx->data_size / 128));
732         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
733
734         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
735         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
736         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
737         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
738         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
739         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
740         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
741         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
742         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
743         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
744
745         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
746
747         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
748         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
749         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
750         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
751         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
752         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
753
754         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
755         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
756         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
757         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
758         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
759         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
760         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
761         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
762
763         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
764
765         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
766                 return -EBUSY;
767
768         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
769         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
770
771         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
772         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
773         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
774
775         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
776         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
777         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
778         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
779         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
780         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
781
782         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
783         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
784         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
785         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
786         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
787
788         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
789         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
790         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
791         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
792
793         /*
794          * We must clear the FCS and FIFO error count.
795          * These registers are cleared on read,
796          * so we may pass a useless variable to store the value.
797          */
798         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
799         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
800
801         return 0;
802 }
803
804 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
805 {
806         unsigned int i;
807         u8 value;
808
809         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
810                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
811                 if ((value != 0xff) && (value != 0x00))
812                         return 0;
813                 udelay(REGISTER_BUSY_DELAY);
814         }
815
816         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
817         return -EACCES;
818 }
819
820 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
821 {
822         unsigned int i;
823         u16 eeprom;
824         u8 reg_id;
825         u8 value;
826
827         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
828                 return -EACCES;
829
830         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
831         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
832         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
833         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
834         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
835         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
836         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
837         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
838         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
839         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
840         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
841         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
842         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
843         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
844
845         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
846                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
847
848                 if (eeprom != 0xffff && eeprom != 0x0000) {
849                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
850                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
851                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
852                 }
853         }
854
855         return 0;
856 }
857
858 /*
859  * Device state switch handlers.
860  */
861 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
862                                 enum dev_state state)
863 {
864         u32 reg;
865
866         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
867         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
868                            (state == STATE_RADIO_RX_OFF) ||
869                            (state == STATE_RADIO_RX_OFF_LINK));
870         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
871 }
872
873 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
874                                  enum dev_state state)
875 {
876         int mask = (state == STATE_RADIO_IRQ_OFF);
877         u32 reg;
878
879         /*
880          * When interrupts are being enabled, the interrupt registers
881          * should clear the register to assure a clean state.
882          */
883         if (state == STATE_RADIO_IRQ_ON) {
884                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
885                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
886         }
887
888         /*
889          * Only toggle the interrupts bits we are going to use.
890          * Non-checked interrupt bits are disabled by default.
891          */
892         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
893         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
894         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
895         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
896         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
897         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
898         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
899 }
900
901 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
902 {
903         /*
904          * Initialize all registers.
905          */
906         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
907                      rt2400pci_init_registers(rt2x00dev) ||
908                      rt2400pci_init_bbp(rt2x00dev)))
909                 return -EIO;
910
911         return 0;
912 }
913
914 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
915 {
916         /*
917          * Disable power
918          */
919         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
920 }
921
922 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
923                                enum dev_state state)
924 {
925         u32 reg;
926         unsigned int i;
927         char put_to_sleep;
928         char bbp_state;
929         char rf_state;
930
931         put_to_sleep = (state != STATE_AWAKE);
932
933         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
934         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
935         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
936         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
937         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
938         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
939
940         /*
941          * Device is not guaranteed to be in the requested state yet.
942          * We must wait until the register indicates that the
943          * device has entered the correct state.
944          */
945         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
946                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
947                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
948                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
949                 if (bbp_state == state && rf_state == state)
950                         return 0;
951                 msleep(10);
952         }
953
954         return -EBUSY;
955 }
956
957 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
958                                       enum dev_state state)
959 {
960         int retval = 0;
961
962         switch (state) {
963         case STATE_RADIO_ON:
964                 retval = rt2400pci_enable_radio(rt2x00dev);
965                 break;
966         case STATE_RADIO_OFF:
967                 rt2400pci_disable_radio(rt2x00dev);
968                 break;
969         case STATE_RADIO_RX_ON:
970         case STATE_RADIO_RX_ON_LINK:
971         case STATE_RADIO_RX_OFF:
972         case STATE_RADIO_RX_OFF_LINK:
973                 rt2400pci_toggle_rx(rt2x00dev, state);
974                 break;
975         case STATE_RADIO_IRQ_ON:
976         case STATE_RADIO_IRQ_OFF:
977                 rt2400pci_toggle_irq(rt2x00dev, state);
978                 break;
979         case STATE_DEEP_SLEEP:
980         case STATE_SLEEP:
981         case STATE_STANDBY:
982         case STATE_AWAKE:
983                 retval = rt2400pci_set_state(rt2x00dev, state);
984                 break;
985         default:
986                 retval = -ENOTSUPP;
987                 break;
988         }
989
990         if (unlikely(retval))
991                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
992                       state, retval);
993
994         return retval;
995 }
996
997 /*
998  * TX descriptor initialization
999  */
1000 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1001                                     struct sk_buff *skb,
1002                                     struct txentry_desc *txdesc)
1003 {
1004         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1005         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1006         __le32 *txd = skbdesc->desc;
1007         u32 word;
1008
1009         /*
1010          * Start writing the descriptor words.
1011          */
1012         rt2x00_desc_read(entry_priv->desc, 1, &word);
1013         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1014         rt2x00_desc_write(entry_priv->desc, 1, word);
1015
1016         rt2x00_desc_read(txd, 2, &word);
1017         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1018         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1019         rt2x00_desc_write(txd, 2, word);
1020
1021         rt2x00_desc_read(txd, 3, &word);
1022         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1023         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1024         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1025         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1026         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1027         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1028         rt2x00_desc_write(txd, 3, word);
1029
1030         rt2x00_desc_read(txd, 4, &word);
1031         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1032         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1033         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1034         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1035         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1036         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1037         rt2x00_desc_write(txd, 4, word);
1038
1039         rt2x00_desc_read(txd, 0, &word);
1040         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1041         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1042         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1043                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1044         rt2x00_set_field32(&word, TXD_W0_ACK,
1045                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1046         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1047                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1048         rt2x00_set_field32(&word, TXD_W0_RTS,
1049                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1050         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1051         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1052                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1053         rt2x00_desc_write(txd, 0, word);
1054 }
1055
1056 /*
1057  * TX data initialization
1058  */
1059 static void rt2400pci_write_beacon(struct queue_entry *entry)
1060 {
1061         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1062         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1063         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1064         u32 word;
1065         u32 reg;
1066
1067         /*
1068          * Disable beaconing while we are reloading the beacon data,
1069          * otherwise we might be sending out invalid data.
1070          */
1071         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1072         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1073         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1074         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1075         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1076
1077         /*
1078          * Replace rt2x00lib allocated descriptor with the
1079          * pointer to the _real_ hardware descriptor.
1080          * After that, map the beacon to DMA and update the
1081          * descriptor.
1082          */
1083         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1084         skbdesc->desc = entry_priv->desc;
1085
1086         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1087
1088         rt2x00_desc_read(entry_priv->desc, 1, &word);
1089         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1090         rt2x00_desc_write(entry_priv->desc, 1, word);
1091 }
1092
1093 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1094                                     const enum data_queue_qid queue)
1095 {
1096         u32 reg;
1097
1098         if (queue == QID_BEACON) {
1099                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1100                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1101                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1102                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1103                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1104                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1105                 }
1106                 return;
1107         }
1108
1109         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1110         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1111         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1112         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1113         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1114 }
1115
1116 static void rt2400pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1117                                     const enum data_queue_qid qid)
1118 {
1119         u32 reg;
1120
1121         if (qid == QID_BEACON) {
1122                 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1123         } else {
1124                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1125                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1126                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1127         }
1128 }
1129
1130 /*
1131  * RX control handlers
1132  */
1133 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1134                                   struct rxdone_entry_desc *rxdesc)
1135 {
1136         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1137         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1138         u32 word0;
1139         u32 word2;
1140         u32 word3;
1141         u32 word4;
1142         u64 tsf;
1143         u32 rx_low;
1144         u32 rx_high;
1145
1146         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1147         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1148         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1149         rt2x00_desc_read(entry_priv->desc, 4, &word4);
1150
1151         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1152                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1153         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1154                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1155
1156         /*
1157          * We only get the lower 32bits from the timestamp,
1158          * to get the full 64bits we must complement it with
1159          * the timestamp from get_tsf().
1160          * Note that when a wraparound of the lower 32bits
1161          * has occurred between the frame arrival and the get_tsf()
1162          * call, we must decrease the higher 32bits with 1 to get
1163          * to correct value.
1164          */
1165         tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1166         rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1167         rx_high = upper_32_bits(tsf);
1168
1169         if ((u32)tsf <= rx_low)
1170                 rx_high--;
1171
1172         /*
1173          * Obtain the status about this packet.
1174          * The signal is the PLCP value, and needs to be stripped
1175          * of the preamble bit (0x08).
1176          */
1177         rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1178         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1179         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1180             entry->queue->rt2x00dev->rssi_offset;
1181         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1182
1183         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1184         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1185                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1186 }
1187
1188 /*
1189  * Interrupt functions.
1190  */
1191 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1192                              const enum data_queue_qid queue_idx)
1193 {
1194         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1195         struct queue_entry_priv_pci *entry_priv;
1196         struct queue_entry *entry;
1197         struct txdone_entry_desc txdesc;
1198         u32 word;
1199
1200         while (!rt2x00queue_empty(queue)) {
1201                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1202                 entry_priv = entry->priv_data;
1203                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1204
1205                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1206                     !rt2x00_get_field32(word, TXD_W0_VALID))
1207                         break;
1208
1209                 /*
1210                  * Obtain the status about this packet.
1211                  */
1212                 txdesc.flags = 0;
1213                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1214                 case 0: /* Success */
1215                 case 1: /* Success with retry */
1216                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1217                         break;
1218                 case 2: /* Failure, excessive retries */
1219                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1220                         /* Don't break, this is a failed frame! */
1221                 default: /* Failure */
1222                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1223                 }
1224                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1225
1226                 rt2x00lib_txdone(entry, &txdesc);
1227         }
1228 }
1229
1230 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1231 {
1232         struct rt2x00_dev *rt2x00dev = dev_instance;
1233         u32 reg;
1234
1235         /*
1236          * Get the interrupt sources & saved to local variable.
1237          * Write register value back to clear pending interrupts.
1238          */
1239         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1240         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1241
1242         if (!reg)
1243                 return IRQ_NONE;
1244
1245         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1246                 return IRQ_HANDLED;
1247
1248         /*
1249          * Handle interrupts, walk through all bits
1250          * and run the tasks, the bits are checked in order of
1251          * priority.
1252          */
1253
1254         /*
1255          * 1 - Beacon timer expired interrupt.
1256          */
1257         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1258                 rt2x00lib_beacondone(rt2x00dev);
1259
1260         /*
1261          * 2 - Rx ring done interrupt.
1262          */
1263         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1264                 rt2x00pci_rxdone(rt2x00dev);
1265
1266         /*
1267          * 3 - Atim ring transmit done interrupt.
1268          */
1269         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1270                 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1271
1272         /*
1273          * 4 - Priority ring transmit done interrupt.
1274          */
1275         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1276                 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1277
1278         /*
1279          * 5 - Tx ring transmit done interrupt.
1280          */
1281         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1282                 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1283
1284         return IRQ_HANDLED;
1285 }
1286
1287 /*
1288  * Device probe functions.
1289  */
1290 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1291 {
1292         struct eeprom_93cx6 eeprom;
1293         u32 reg;
1294         u16 word;
1295         u8 *mac;
1296
1297         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1298
1299         eeprom.data = rt2x00dev;
1300         eeprom.register_read = rt2400pci_eepromregister_read;
1301         eeprom.register_write = rt2400pci_eepromregister_write;
1302         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1303             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1304         eeprom.reg_data_in = 0;
1305         eeprom.reg_data_out = 0;
1306         eeprom.reg_data_clock = 0;
1307         eeprom.reg_chip_select = 0;
1308
1309         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1310                                EEPROM_SIZE / sizeof(u16));
1311
1312         /*
1313          * Start validation of the data that has been read.
1314          */
1315         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1316         if (!is_valid_ether_addr(mac)) {
1317                 random_ether_addr(mac);
1318                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1319         }
1320
1321         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1322         if (word == 0xffff) {
1323                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1324                 return -EINVAL;
1325         }
1326
1327         return 0;
1328 }
1329
1330 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1331 {
1332         u32 reg;
1333         u16 value;
1334         u16 eeprom;
1335
1336         /*
1337          * Read EEPROM word for configuration.
1338          */
1339         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1340
1341         /*
1342          * Identify RF chipset.
1343          */
1344         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1345         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1346         rt2x00_set_chip_rf(rt2x00dev, value, reg);
1347
1348         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1349             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1350                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1351                 return -ENODEV;
1352         }
1353
1354         /*
1355          * Identify default antenna configuration.
1356          */
1357         rt2x00dev->default_ant.tx =
1358             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1359         rt2x00dev->default_ant.rx =
1360             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1361
1362         /*
1363          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1364          * I am not 100% sure about this, but the legacy drivers do not
1365          * indicate antenna swapping in software is required when
1366          * diversity is enabled.
1367          */
1368         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1369                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1370         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1371                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1372
1373         /*
1374          * Store led mode, for correct led behaviour.
1375          */
1376 #ifdef CONFIG_RT2X00_LIB_LEDS
1377         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1378
1379         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1380         if (value == LED_MODE_TXRX_ACTIVITY ||
1381             value == LED_MODE_DEFAULT ||
1382             value == LED_MODE_ASUS)
1383                 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1384                                    LED_TYPE_ACTIVITY);
1385 #endif /* CONFIG_RT2X00_LIB_LEDS */
1386
1387         /*
1388          * Detect if this device has an hardware controlled radio.
1389          */
1390         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1391                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1392
1393         /*
1394          * Check if the BBP tuning should be enabled.
1395          */
1396         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1397                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1398
1399         return 0;
1400 }
1401
1402 /*
1403  * RF value list for RF2420 & RF2421
1404  * Supports: 2.4 GHz
1405  */
1406 static const struct rf_channel rf_vals_b[] = {
1407         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1408         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1409         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1410         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1411         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1412         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1413         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1414         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1415         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1416         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1417         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1418         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1419         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1420         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1421 };
1422
1423 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1424 {
1425         struct hw_mode_spec *spec = &rt2x00dev->spec;
1426         struct channel_info *info;
1427         char *tx_power;
1428         unsigned int i;
1429
1430         /*
1431          * Initialize all hw fields.
1432          */
1433         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1434                                IEEE80211_HW_SIGNAL_DBM |
1435                                IEEE80211_HW_SUPPORTS_PS |
1436                                IEEE80211_HW_PS_NULLFUNC_STACK;
1437         rt2x00dev->hw->extra_tx_headroom = 0;
1438
1439         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1440         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1441                                 rt2x00_eeprom_addr(rt2x00dev,
1442                                                    EEPROM_MAC_ADDR_0));
1443
1444         /*
1445          * Initialize hw_mode information.
1446          */
1447         spec->supported_bands = SUPPORT_BAND_2GHZ;
1448         spec->supported_rates = SUPPORT_RATE_CCK;
1449
1450         spec->num_channels = ARRAY_SIZE(rf_vals_b);
1451         spec->channels = rf_vals_b;
1452
1453         /*
1454          * Create channel information array
1455          */
1456         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1457         if (!info)
1458                 return -ENOMEM;
1459
1460         spec->channels_info = info;
1461
1462         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1463         for (i = 0; i < 14; i++)
1464                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1465
1466         return 0;
1467 }
1468
1469 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1470 {
1471         int retval;
1472
1473         /*
1474          * Allocate eeprom data.
1475          */
1476         retval = rt2400pci_validate_eeprom(rt2x00dev);
1477         if (retval)
1478                 return retval;
1479
1480         retval = rt2400pci_init_eeprom(rt2x00dev);
1481         if (retval)
1482                 return retval;
1483
1484         /*
1485          * Initialize hw specifications.
1486          */
1487         retval = rt2400pci_probe_hw_mode(rt2x00dev);
1488         if (retval)
1489                 return retval;
1490
1491         /*
1492          * This device requires the atim queue and DMA-mapped skbs.
1493          */
1494         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1495         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1496
1497         /*
1498          * Set the rssi offset.
1499          */
1500         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1501
1502         return 0;
1503 }
1504
1505 /*
1506  * IEEE80211 stack callback functions.
1507  */
1508 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1509                              const struct ieee80211_tx_queue_params *params)
1510 {
1511         struct rt2x00_dev *rt2x00dev = hw->priv;
1512
1513         /*
1514          * We don't support variating cw_min and cw_max variables
1515          * per queue. So by default we only configure the TX queue,
1516          * and ignore all other configurations.
1517          */
1518         if (queue != 0)
1519                 return -EINVAL;
1520
1521         if (rt2x00mac_conf_tx(hw, queue, params))
1522                 return -EINVAL;
1523
1524         /*
1525          * Write configuration to register.
1526          */
1527         rt2400pci_config_cw(rt2x00dev,
1528                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1529
1530         return 0;
1531 }
1532
1533 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1534 {
1535         struct rt2x00_dev *rt2x00dev = hw->priv;
1536         u64 tsf;
1537         u32 reg;
1538
1539         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1540         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1541         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1542         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1543
1544         return tsf;
1545 }
1546
1547 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1548 {
1549         struct rt2x00_dev *rt2x00dev = hw->priv;
1550         u32 reg;
1551
1552         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1553         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1554 }
1555
1556 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1557         .tx                     = rt2x00mac_tx,
1558         .start                  = rt2x00mac_start,
1559         .stop                   = rt2x00mac_stop,
1560         .add_interface          = rt2x00mac_add_interface,
1561         .remove_interface       = rt2x00mac_remove_interface,
1562         .config                 = rt2x00mac_config,
1563         .configure_filter       = rt2x00mac_configure_filter,
1564         .set_tim                = rt2x00mac_set_tim,
1565         .get_stats              = rt2x00mac_get_stats,
1566         .bss_info_changed       = rt2x00mac_bss_info_changed,
1567         .conf_tx                = rt2400pci_conf_tx,
1568         .get_tx_stats           = rt2x00mac_get_tx_stats,
1569         .get_tsf                = rt2400pci_get_tsf,
1570         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1571         .rfkill_poll            = rt2x00mac_rfkill_poll,
1572 };
1573
1574 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1575         .irq_handler            = rt2400pci_interrupt,
1576         .probe_hw               = rt2400pci_probe_hw,
1577         .initialize             = rt2x00pci_initialize,
1578         .uninitialize           = rt2x00pci_uninitialize,
1579         .get_entry_state        = rt2400pci_get_entry_state,
1580         .clear_entry            = rt2400pci_clear_entry,
1581         .set_device_state       = rt2400pci_set_device_state,
1582         .rfkill_poll            = rt2400pci_rfkill_poll,
1583         .link_stats             = rt2400pci_link_stats,
1584         .reset_tuner            = rt2400pci_reset_tuner,
1585         .link_tuner             = rt2400pci_link_tuner,
1586         .write_tx_desc          = rt2400pci_write_tx_desc,
1587         .write_tx_data          = rt2x00pci_write_tx_data,
1588         .write_beacon           = rt2400pci_write_beacon,
1589         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1590         .kill_tx_queue          = rt2400pci_kill_tx_queue,
1591         .fill_rxdone            = rt2400pci_fill_rxdone,
1592         .config_filter          = rt2400pci_config_filter,
1593         .config_intf            = rt2400pci_config_intf,
1594         .config_erp             = rt2400pci_config_erp,
1595         .config_ant             = rt2400pci_config_ant,
1596         .config                 = rt2400pci_config,
1597 };
1598
1599 static const struct data_queue_desc rt2400pci_queue_rx = {
1600         .entry_num              = RX_ENTRIES,
1601         .data_size              = DATA_FRAME_SIZE,
1602         .desc_size              = RXD_DESC_SIZE,
1603         .priv_size              = sizeof(struct queue_entry_priv_pci),
1604 };
1605
1606 static const struct data_queue_desc rt2400pci_queue_tx = {
1607         .entry_num              = TX_ENTRIES,
1608         .data_size              = DATA_FRAME_SIZE,
1609         .desc_size              = TXD_DESC_SIZE,
1610         .priv_size              = sizeof(struct queue_entry_priv_pci),
1611 };
1612
1613 static const struct data_queue_desc rt2400pci_queue_bcn = {
1614         .entry_num              = BEACON_ENTRIES,
1615         .data_size              = MGMT_FRAME_SIZE,
1616         .desc_size              = TXD_DESC_SIZE,
1617         .priv_size              = sizeof(struct queue_entry_priv_pci),
1618 };
1619
1620 static const struct data_queue_desc rt2400pci_queue_atim = {
1621         .entry_num              = ATIM_ENTRIES,
1622         .data_size              = DATA_FRAME_SIZE,
1623         .desc_size              = TXD_DESC_SIZE,
1624         .priv_size              = sizeof(struct queue_entry_priv_pci),
1625 };
1626
1627 static const struct rt2x00_ops rt2400pci_ops = {
1628         .name           = KBUILD_MODNAME,
1629         .max_sta_intf   = 1,
1630         .max_ap_intf    = 1,
1631         .eeprom_size    = EEPROM_SIZE,
1632         .rf_size        = RF_SIZE,
1633         .tx_queues      = NUM_TX_QUEUES,
1634         .rx             = &rt2400pci_queue_rx,
1635         .tx             = &rt2400pci_queue_tx,
1636         .bcn            = &rt2400pci_queue_bcn,
1637         .atim           = &rt2400pci_queue_atim,
1638         .lib            = &rt2400pci_rt2x00_ops,
1639         .hw             = &rt2400pci_mac80211_ops,
1640 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1641         .debugfs        = &rt2400pci_rt2x00debug,
1642 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1643 };
1644
1645 /*
1646  * RT2400pci module information.
1647  */
1648 static struct pci_device_id rt2400pci_device_table[] = {
1649         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1650         { 0, }
1651 };
1652
1653 MODULE_AUTHOR(DRV_PROJECT);
1654 MODULE_VERSION(DRV_VERSION);
1655 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1656 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1657 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1658 MODULE_LICENSE("GPL");
1659
1660 static struct pci_driver rt2400pci_driver = {
1661         .name           = KBUILD_MODNAME,
1662         .id_table       = rt2400pci_device_table,
1663         .probe          = rt2x00pci_probe,
1664         .remove         = __devexit_p(rt2x00pci_remove),
1665         .suspend        = rt2x00pci_suspend,
1666         .resume         = rt2x00pci_resume,
1667 };
1668
1669 static int __init rt2400pci_init(void)
1670 {
1671         return pci_register_driver(&rt2400pci_driver);
1672 }
1673
1674 static void __exit rt2400pci_exit(void)
1675 {
1676         pci_unregister_driver(&rt2400pci_driver);
1677 }
1678
1679 module_init(rt2400pci_init);
1680 module_exit(rt2400pci_exit);