Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next
[pandora-kernel.git] / drivers / net / wireless / iwlwifi / iwl-tx.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4  *
5  * Portions of this file are derived from the ipw3945 project, as well
6  * as portions of the ieee80211 subsystem header files.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of version 2 of the GNU General Public License as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20  *
21  * The full GNU General Public License is included in this distribution in the
22  * file called LICENSE.
23  *
24  * Contact Information:
25  *  Intel Linux Wireless <ilw@linux.intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  *****************************************************************************/
29
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <net/mac80211.h>
34 #include "iwl-eeprom.h"
35 #include "iwl-agn.h"
36 #include "iwl-dev.h"
37 #include "iwl-core.h"
38 #include "iwl-sta.h"
39 #include "iwl-io.h"
40 #include "iwl-helpers.h"
41
42 /**
43  * iwl_txq_update_write_ptr - Send new write index to hardware
44  */
45 void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
46 {
47         u32 reg = 0;
48         int txq_id = txq->q.id;
49
50         if (txq->need_update == 0)
51                 return;
52
53         if (priv->cfg->base_params->shadow_reg_enable) {
54                 /* shadow register enabled */
55                 iwl_write32(priv, HBUS_TARG_WRPTR,
56                             txq->q.write_ptr | (txq_id << 8));
57         } else {
58                 /* if we're trying to save power */
59                 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
60                         /* wake up nic if it's powered down ...
61                          * uCode will wake up, and interrupt us again, so next
62                          * time we'll skip this part. */
63                         reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
64
65                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
66                                 IWL_DEBUG_INFO(priv,
67                                         "Tx queue %d requesting wakeup,"
68                                         " GP1 = 0x%x\n", txq_id, reg);
69                                 iwl_set_bit(priv, CSR_GP_CNTRL,
70                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
71                                 return;
72                         }
73
74                         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
75                                      txq->q.write_ptr | (txq_id << 8));
76
77                 /*
78                  * else not in power-save mode,
79                  * uCode will never sleep when we're
80                  * trying to tx (during RFKILL, we're not trying to tx).
81                  */
82                 } else
83                         iwl_write32(priv, HBUS_TARG_WRPTR,
84                                     txq->q.write_ptr | (txq_id << 8));
85         }
86         txq->need_update = 0;
87 }
88
89 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
90 {
91         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
92
93         dma_addr_t addr = get_unaligned_le32(&tb->lo);
94         if (sizeof(dma_addr_t) > sizeof(u32))
95                 addr |=
96                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
97
98         return addr;
99 }
100
101 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
102 {
103         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
104
105         return le16_to_cpu(tb->hi_n_len) >> 4;
106 }
107
108 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
109                                   dma_addr_t addr, u16 len)
110 {
111         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
112         u16 hi_n_len = len << 4;
113
114         put_unaligned_le32(addr, &tb->lo);
115         if (sizeof(dma_addr_t) > sizeof(u32))
116                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
117
118         tb->hi_n_len = cpu_to_le16(hi_n_len);
119
120         tfd->num_tbs = idx + 1;
121 }
122
123 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
124 {
125         return tfd->num_tbs & 0x1f;
126 }
127
128 static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta,
129                              struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
130 {
131         int i;
132         int num_tbs;
133
134         /* Sanity check on number of chunks */
135         num_tbs = iwl_tfd_get_num_tbs(tfd);
136
137         if (num_tbs >= IWL_NUM_OF_TBS) {
138                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
139                 /* @todo issue fatal error, it is quite serious situation */
140                 return;
141         }
142
143         /* Unmap tx_cmd */
144         if (num_tbs)
145                 dma_unmap_single(priv->bus.dev,
146                                 dma_unmap_addr(meta, mapping),
147                                 dma_unmap_len(meta, len),
148                                 DMA_BIDIRECTIONAL);
149
150         /* Unmap chunks, if any. */
151         for (i = 1; i < num_tbs; i++)
152                 dma_unmap_single(priv->bus.dev, iwl_tfd_tb_get_addr(tfd, i),
153                                 iwl_tfd_tb_get_len(tfd, i), dma_dir);
154 }
155
156 /**
157  * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
158  * @priv - driver private data
159  * @txq - tx queue
160  * @index - the index of the TFD to be freed
161  *
162  * Does NOT advance any TFD circular buffer read/write indexes
163  * Does NOT free the TFD itself (which is within circular buffer)
164  */
165 void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq,
166         int index)
167 {
168         struct iwl_tfd *tfd_tmp = txq->tfds;
169
170         iwlagn_unmap_tfd(priv, &txq->meta[index], &tfd_tmp[index],
171                          DMA_TO_DEVICE);
172
173         /* free SKB */
174         if (txq->txb) {
175                 struct sk_buff *skb;
176
177                 skb = txq->txb[index].skb;
178
179                 /* can be called from irqs-disabled context */
180                 if (skb) {
181                         dev_kfree_skb_any(skb);
182                         txq->txb[index].skb = NULL;
183                 }
184         }
185 }
186
187 int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv,
188                                  struct iwl_tx_queue *txq,
189                                  dma_addr_t addr, u16 len,
190                                  u8 reset)
191 {
192         struct iwl_queue *q;
193         struct iwl_tfd *tfd, *tfd_tmp;
194         u32 num_tbs;
195
196         q = &txq->q;
197         tfd_tmp = txq->tfds;
198         tfd = &tfd_tmp[q->write_ptr];
199
200         if (reset)
201                 memset(tfd, 0, sizeof(*tfd));
202
203         num_tbs = iwl_tfd_get_num_tbs(tfd);
204
205         /* Each TFD can point to a maximum 20 Tx buffers */
206         if (num_tbs >= IWL_NUM_OF_TBS) {
207                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
208                           IWL_NUM_OF_TBS);
209                 return -EINVAL;
210         }
211
212         if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
213                 return -EINVAL;
214
215         if (unlikely(addr & ~IWL_TX_DMA_MASK))
216                 IWL_ERR(priv, "Unaligned address = %llx\n",
217                           (unsigned long long)addr);
218
219         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
220
221         return 0;
222 }
223
224 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
225  * DMA services
226  *
227  * Theory of operation
228  *
229  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
230  * of buffer descriptors, each of which points to one or more data buffers for
231  * the device to read from or fill.  Driver and device exchange status of each
232  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
233  * entries in each circular buffer, to protect against confusing empty and full
234  * queue states.
235  *
236  * The device reads or writes the data in the queues via the device's several
237  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
238  *
239  * For Tx queue, there are low mark and high mark limits. If, after queuing
240  * the packet for Tx, free space become < low mark, Tx queue stopped. When
241  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
242  * Tx queue resumed.
243  *
244  ***************************************************/
245
246 int iwl_queue_space(const struct iwl_queue *q)
247 {
248         int s = q->read_ptr - q->write_ptr;
249
250         if (q->read_ptr > q->write_ptr)
251                 s -= q->n_bd;
252
253         if (s <= 0)
254                 s += q->n_window;
255         /* keep some reserve to not confuse empty and full situations */
256         s -= 2;
257         if (s < 0)
258                 s = 0;
259         return s;
260 }
261
262 /**
263  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
264  */
265 int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
266                           int count, int slots_num, u32 id)
267 {
268         q->n_bd = count;
269         q->n_window = slots_num;
270         q->id = id;
271
272         /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
273          * and iwl_queue_dec_wrap are broken. */
274         if (WARN_ON(!is_power_of_2(count)))
275                 return -EINVAL;
276
277         /* slots_num must be power-of-two size, otherwise
278          * get_cmd_index is broken. */
279         if (WARN_ON(!is_power_of_2(slots_num)))
280                 return -EINVAL;
281
282         q->low_mark = q->n_window / 4;
283         if (q->low_mark < 4)
284                 q->low_mark = 4;
285
286         q->high_mark = q->n_window / 8;
287         if (q->high_mark < 2)
288                 q->high_mark = 2;
289
290         q->write_ptr = q->read_ptr = 0;
291
292         return 0;
293 }
294
295 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
296
297 /**
298  * iwl_enqueue_hcmd - enqueue a uCode command
299  * @priv: device private data point
300  * @cmd: a point to the ucode command structure
301  *
302  * The function returns < 0 values to indicate the operation is
303  * failed. On success, it turns the index (> 0) of command in the
304  * command queue.
305  */
306 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
307 {
308         struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
309         struct iwl_queue *q = &txq->q;
310         struct iwl_device_cmd *out_cmd;
311         struct iwl_cmd_meta *out_meta;
312         dma_addr_t phys_addr;
313         unsigned long flags;
314         u32 idx;
315         u16 copy_size, cmd_size;
316         bool is_ct_kill = false;
317         bool had_nocopy = false;
318         int i;
319         u8 *cmd_dest;
320 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
321         const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
322         int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
323         int trace_idx;
324 #endif
325
326         if (test_bit(STATUS_FW_ERROR, &priv->status)) {
327                 IWL_WARN(priv, "fw recovery, no hcmd send\n");
328                 return -EIO;
329         }
330
331         if ((priv->ucode_owner == IWL_OWNERSHIP_TM) &&
332             !(cmd->flags & CMD_ON_DEMAND)) {
333                 IWL_DEBUG_HC(priv, "tm own the uCode, no regular hcmd send\n");
334                 return -EIO;
335         }
336
337         copy_size = sizeof(out_cmd->hdr);
338         cmd_size = sizeof(out_cmd->hdr);
339
340         /* need one for the header if the first is NOCOPY */
341         BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
342
343         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
344                 if (!cmd->len[i])
345                         continue;
346                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
347                         had_nocopy = true;
348                 } else {
349                         /* NOCOPY must not be followed by normal! */
350                         if (WARN_ON(had_nocopy))
351                                 return -EINVAL;
352                         copy_size += cmd->len[i];
353                 }
354                 cmd_size += cmd->len[i];
355         }
356
357         /*
358          * If any of the command structures end up being larger than
359          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
360          * allocated into separate TFDs, then we will need to
361          * increase the size of the buffers.
362          */
363         if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
364                 return -EINVAL;
365
366         if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
367                 IWL_WARN(priv, "Not sending command - %s KILL\n",
368                          iwl_is_rfkill(priv) ? "RF" : "CT");
369                 return -EIO;
370         }
371
372         spin_lock_irqsave(&priv->hcmd_lock, flags);
373
374         if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
375                 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
376
377                 IWL_ERR(priv, "No space in command queue\n");
378                 is_ct_kill = iwl_check_for_ct_kill(priv);
379                 if (!is_ct_kill) {
380                         IWL_ERR(priv, "Restarting adapter due to queue full\n");
381                         iwlagn_fw_error(priv, false);
382                 }
383                 return -ENOSPC;
384         }
385
386         idx = get_cmd_index(q, q->write_ptr);
387         out_cmd = txq->cmd[idx];
388         out_meta = &txq->meta[idx];
389
390         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
391         if (cmd->flags & CMD_WANT_SKB)
392                 out_meta->source = cmd;
393         if (cmd->flags & CMD_ASYNC)
394                 out_meta->callback = cmd->callback;
395
396         /* set up the header */
397
398         out_cmd->hdr.cmd = cmd->id;
399         out_cmd->hdr.flags = 0;
400         out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) |
401                                             INDEX_TO_SEQ(q->write_ptr));
402
403         /* and copy the data that needs to be copied */
404
405         cmd_dest = &out_cmd->cmd.payload[0];
406         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
407                 if (!cmd->len[i])
408                         continue;
409                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
410                         break;
411                 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
412                 cmd_dest += cmd->len[i];
413         }
414
415         IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
416                         "%d bytes at %d[%d]:%d\n",
417                         get_cmd_string(out_cmd->hdr.cmd),
418                         out_cmd->hdr.cmd,
419                         le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
420                         q->write_ptr, idx, priv->cmd_queue);
421
422         phys_addr = dma_map_single(priv->bus.dev, &out_cmd->hdr, copy_size,
423                                 DMA_BIDIRECTIONAL);
424         if (unlikely(dma_mapping_error(priv->bus.dev, phys_addr))) {
425                 idx = -ENOMEM;
426                 goto out;
427         }
428
429         dma_unmap_addr_set(out_meta, mapping, phys_addr);
430         dma_unmap_len_set(out_meta, len, copy_size);
431
432         iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, copy_size, 1);
433 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
434         trace_bufs[0] = &out_cmd->hdr;
435         trace_lens[0] = copy_size;
436         trace_idx = 1;
437 #endif
438
439         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
440                 if (!cmd->len[i])
441                         continue;
442                 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
443                         continue;
444                 phys_addr = dma_map_single(priv->bus.dev, (void *)cmd->data[i],
445                                            cmd->len[i], DMA_BIDIRECTIONAL);
446                 if (dma_mapping_error(priv->bus.dev, phys_addr)) {
447                         iwlagn_unmap_tfd(priv, out_meta,
448                                          &txq->tfds[q->write_ptr],
449                                          DMA_BIDIRECTIONAL);
450                         idx = -ENOMEM;
451                         goto out;
452                 }
453
454                 iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr,
455                                              cmd->len[i], 0);
456 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
457                 trace_bufs[trace_idx] = cmd->data[i];
458                 trace_lens[trace_idx] = cmd->len[i];
459                 trace_idx++;
460 #endif
461         }
462
463         out_meta->flags = cmd->flags;
464
465         txq->need_update = 1;
466
467         /* check that tracing gets all possible blocks */
468         BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
469 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
470         trace_iwlwifi_dev_hcmd(priv, cmd->flags,
471                                trace_bufs[0], trace_lens[0],
472                                trace_bufs[1], trace_lens[1],
473                                trace_bufs[2], trace_lens[2]);
474 #endif
475
476         /* Increment and update queue's write index */
477         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
478         iwl_txq_update_write_ptr(priv, txq);
479
480  out:
481         spin_unlock_irqrestore(&priv->hcmd_lock, flags);
482         return idx;
483 }
484
485 /**
486  * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
487  *
488  * When FW advances 'R' index, all entries between old and new 'R' index
489  * need to be reclaimed. As result, some free space forms.  If there is
490  * enough free space (> low mark), wake the stack that feeds us.
491  */
492 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx)
493 {
494         struct iwl_tx_queue *txq = &priv->txq[txq_id];
495         struct iwl_queue *q = &txq->q;
496         int nfreed = 0;
497
498         if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
499                 IWL_ERR(priv, "%s: Read index for DMA queue txq id (%d), "
500                           "index %d is out of range [0-%d] %d %d.\n", __func__,
501                           txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
502                 return;
503         }
504
505         for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
506              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
507
508                 if (nfreed++ > 0) {
509                         IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
510                                         q->write_ptr, q->read_ptr);
511                         iwlagn_fw_error(priv, false);
512                 }
513
514         }
515 }
516
517 /**
518  * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
519  * @rxb: Rx buffer to reclaim
520  *
521  * If an Rx buffer has an async callback associated with it the callback
522  * will be executed.  The attached skb (if present) will only be freed
523  * if the callback returns 1
524  */
525 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
526 {
527         struct iwl_rx_packet *pkt = rxb_addr(rxb);
528         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
529         int txq_id = SEQ_TO_QUEUE(sequence);
530         int index = SEQ_TO_INDEX(sequence);
531         int cmd_index;
532         struct iwl_device_cmd *cmd;
533         struct iwl_cmd_meta *meta;
534         struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
535         unsigned long flags;
536
537         /* If a Tx command is being handled and it isn't in the actual
538          * command queue then there a command routing bug has been introduced
539          * in the queue management code. */
540         if (WARN(txq_id != priv->cmd_queue,
541                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
542                   txq_id, priv->cmd_queue, sequence,
543                   priv->txq[priv->cmd_queue].q.read_ptr,
544                   priv->txq[priv->cmd_queue].q.write_ptr)) {
545                 iwl_print_hex_error(priv, pkt, 32);
546                 return;
547         }
548
549         cmd_index = get_cmd_index(&txq->q, index);
550         cmd = txq->cmd[cmd_index];
551         meta = &txq->meta[cmd_index];
552
553         iwlagn_unmap_tfd(priv, meta, &txq->tfds[index], DMA_BIDIRECTIONAL);
554
555         /* Input error checking is done when commands are added to queue. */
556         if (meta->flags & CMD_WANT_SKB) {
557                 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
558                 rxb->page = NULL;
559         } else if (meta->callback)
560                 meta->callback(priv, cmd, pkt);
561
562         spin_lock_irqsave(&priv->hcmd_lock, flags);
563
564         iwl_hcmd_queue_reclaim(priv, txq_id, index);
565
566         if (!(meta->flags & CMD_ASYNC)) {
567                 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
568                 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
569                                get_cmd_string(cmd->hdr.cmd));
570                 wake_up_interruptible(&priv->wait_command_queue);
571         }
572
573         meta->flags = 0;
574
575         spin_unlock_irqrestore(&priv->hcmd_lock, flags);
576 }