1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <net/mac80211.h>
34 #include "iwl-eeprom.h"
40 #include "iwl-helpers.h"
43 * iwl_txq_update_write_ptr - Send new write index to hardware
45 void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
48 int txq_id = txq->q.id;
50 if (txq->need_update == 0)
53 if (priv->cfg->base_params->shadow_reg_enable) {
54 /* shadow register enabled */
55 iwl_write32(priv, HBUS_TARG_WRPTR,
56 txq->q.write_ptr | (txq_id << 8));
58 /* if we're trying to save power */
59 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
60 /* wake up nic if it's powered down ...
61 * uCode will wake up, and interrupt us again, so next
62 * time we'll skip this part. */
63 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
65 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
67 "Tx queue %d requesting wakeup,"
68 " GP1 = 0x%x\n", txq_id, reg);
69 iwl_set_bit(priv, CSR_GP_CNTRL,
70 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
74 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
75 txq->q.write_ptr | (txq_id << 8));
78 * else not in power-save mode,
79 * uCode will never sleep when we're
80 * trying to tx (during RFKILL, we're not trying to tx).
83 iwl_write32(priv, HBUS_TARG_WRPTR,
84 txq->q.write_ptr | (txq_id << 8));
89 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
91 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
93 dma_addr_t addr = get_unaligned_le32(&tb->lo);
94 if (sizeof(dma_addr_t) > sizeof(u32))
96 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
101 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
103 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
105 return le16_to_cpu(tb->hi_n_len) >> 4;
108 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
109 dma_addr_t addr, u16 len)
111 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
112 u16 hi_n_len = len << 4;
114 put_unaligned_le32(addr, &tb->lo);
115 if (sizeof(dma_addr_t) > sizeof(u32))
116 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
118 tb->hi_n_len = cpu_to_le16(hi_n_len);
120 tfd->num_tbs = idx + 1;
123 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
125 return tfd->num_tbs & 0x1f;
128 static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta,
131 struct pci_dev *dev = priv->pci_dev;
135 /* Sanity check on number of chunks */
136 num_tbs = iwl_tfd_get_num_tbs(tfd);
138 if (num_tbs >= IWL_NUM_OF_TBS) {
139 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
140 /* @todo issue fatal error, it is quite serious situation */
146 pci_unmap_single(dev,
147 dma_unmap_addr(meta, mapping),
148 dma_unmap_len(meta, len),
149 PCI_DMA_BIDIRECTIONAL);
151 /* Unmap chunks, if any. */
152 for (i = 1; i < num_tbs; i++)
153 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
154 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
158 * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
159 * @priv - driver private data
162 * Does NOT advance any TFD circular buffer read/write indexes
163 * Does NOT free the TFD itself (which is within circular buffer)
165 void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
167 struct iwl_tfd *tfd_tmp = txq->tfds;
168 int index = txq->q.read_ptr;
170 iwlagn_unmap_tfd(priv, &txq->meta[index], &tfd_tmp[index]);
176 skb = txq->txb[txq->q.read_ptr].skb;
178 /* can be called from irqs-disabled context */
180 dev_kfree_skb_any(skb);
181 txq->txb[txq->q.read_ptr].skb = NULL;
186 int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv,
187 struct iwl_tx_queue *txq,
188 dma_addr_t addr, u16 len,
192 struct iwl_tfd *tfd, *tfd_tmp;
197 tfd = &tfd_tmp[q->write_ptr];
200 memset(tfd, 0, sizeof(*tfd));
202 num_tbs = iwl_tfd_get_num_tbs(tfd);
204 /* Each TFD can point to a maximum 20 Tx buffers */
205 if (num_tbs >= IWL_NUM_OF_TBS) {
206 IWL_ERR(priv, "Error can not send more than %d chunks\n",
211 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
214 if (unlikely(addr & ~IWL_TX_DMA_MASK))
215 IWL_ERR(priv, "Unaligned address = %llx\n",
216 (unsigned long long)addr);
218 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
224 * Tell nic where to find circular buffer of Tx Frame Descriptors for
225 * given Tx queue, and enable the DMA channel used for that queue.
227 * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
228 * channels supported in hardware.
230 static int iwlagn_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
232 int txq_id = txq->q.id;
234 /* Circular buffer (TFD queue in DRAM) physical base address */
235 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
236 txq->q.dma_addr >> 8);
242 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
244 void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
246 struct iwl_tx_queue *txq = &priv->txq[txq_id];
247 struct iwl_queue *q = &txq->q;
252 while (q->write_ptr != q->read_ptr) {
253 iwlagn_txq_free_tfd(priv, txq);
254 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
259 * iwl_tx_queue_free - Deallocate DMA queue.
260 * @txq: Transmit queue to deallocate.
262 * Empty queue by removing and destroying all BD's.
264 * 0-fill, but do not free "txq" descriptor structure.
266 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
268 struct iwl_tx_queue *txq = &priv->txq[txq_id];
269 struct device *dev = &priv->pci_dev->dev;
272 iwl_tx_queue_unmap(priv, txq_id);
274 /* De-alloc array of command/tx buffers */
275 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
278 /* De-alloc circular buffer of TFDs */
280 dma_free_coherent(dev, priv->hw_params.tfd_size *
281 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
283 /* De-alloc array of per-TFD driver data */
287 /* deallocate arrays */
293 /* 0-fill queue descriptor structure */
294 memset(txq, 0, sizeof(*txq));
298 * iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
300 void iwl_cmd_queue_unmap(struct iwl_priv *priv)
302 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
303 struct iwl_queue *q = &txq->q;
309 while (q->read_ptr != q->write_ptr) {
310 i = get_cmd_index(q, q->read_ptr);
312 if (txq->meta[i].flags & CMD_MAPPED) {
313 pci_unmap_single(priv->pci_dev,
314 dma_unmap_addr(&txq->meta[i], mapping),
315 dma_unmap_len(&txq->meta[i], len),
316 PCI_DMA_BIDIRECTIONAL);
317 txq->meta[i].flags = 0;
320 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
325 * iwl_cmd_queue_free - Deallocate DMA queue.
326 * @txq: Transmit queue to deallocate.
328 * Empty queue by removing and destroying all BD's.
330 * 0-fill, but do not free "txq" descriptor structure.
332 void iwl_cmd_queue_free(struct iwl_priv *priv)
334 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
335 struct device *dev = &priv->pci_dev->dev;
338 iwl_cmd_queue_unmap(priv);
340 /* De-alloc array of command/tx buffers */
341 for (i = 0; i < TFD_CMD_SLOTS; i++)
344 /* De-alloc circular buffer of TFDs */
346 dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
347 txq->tfds, txq->q.dma_addr);
349 /* deallocate arrays */
355 /* 0-fill queue descriptor structure */
356 memset(txq, 0, sizeof(*txq));
359 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
362 * Theory of operation
364 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
365 * of buffer descriptors, each of which points to one or more data buffers for
366 * the device to read from or fill. Driver and device exchange status of each
367 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
368 * entries in each circular buffer, to protect against confusing empty and full
371 * The device reads or writes the data in the queues via the device's several
372 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
374 * For Tx queue, there are low mark and high mark limits. If, after queuing
375 * the packet for Tx, free space become < low mark, Tx queue stopped. When
376 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
379 ***************************************************/
381 int iwl_queue_space(const struct iwl_queue *q)
383 int s = q->read_ptr - q->write_ptr;
385 if (q->read_ptr > q->write_ptr)
390 /* keep some reserve to not confuse empty and full situations */
399 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
401 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
402 int count, int slots_num, u32 id)
405 q->n_window = slots_num;
408 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
409 * and iwl_queue_dec_wrap are broken. */
410 if (WARN_ON(!is_power_of_2(count)))
413 /* slots_num must be power-of-two size, otherwise
414 * get_cmd_index is broken. */
415 if (WARN_ON(!is_power_of_2(slots_num)))
418 q->low_mark = q->n_window / 4;
422 q->high_mark = q->n_window / 8;
423 if (q->high_mark < 2)
426 q->write_ptr = q->read_ptr = 0;
432 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
434 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
435 struct iwl_tx_queue *txq, u32 id)
437 struct device *dev = &priv->pci_dev->dev;
438 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
440 /* Driver private data, only for Tx (not command) queues,
441 * not shared with device. */
442 if (id != priv->cmd_queue) {
443 txq->txb = kzalloc(sizeof(txq->txb[0]) *
444 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
446 IWL_ERR(priv, "kmalloc for auxiliary BD "
447 "structures failed\n");
454 /* Circular buffer of transmit frame descriptors (TFDs),
455 * shared with device */
456 txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
459 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
474 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
476 int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
477 int slots_num, u32 txq_id)
482 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * slots_num,
484 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * slots_num,
487 if (!txq->meta || !txq->cmd)
488 goto out_free_arrays;
490 len = sizeof(struct iwl_device_cmd);
491 for (i = 0; i < slots_num; i++) {
492 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
497 /* Alloc driver data array and TFD circular buffer */
498 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
502 txq->need_update = 0;
505 * For the default queues 0-3, set up the swq_id
506 * already -- all others need to get one later
507 * (if they need one at all).
510 iwl_set_swq_id(txq, txq_id, txq_id);
512 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
513 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
514 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
516 /* Initialize queue's high/low-water marks, and head/tail indexes */
517 ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
521 /* Tell device where to find queue */
522 iwlagn_tx_queue_init(priv, txq);
526 for (i = 0; i < slots_num; i++)
535 void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
536 int slots_num, u32 txq_id)
538 int actual_slots = slots_num;
540 if (txq_id == priv->cmd_queue)
543 memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots);
545 txq->need_update = 0;
547 /* Initialize queue's high/low-water marks, and head/tail indexes */
548 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
550 /* Tell device where to find queue */
551 iwlagn_tx_queue_init(priv, txq);
554 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
557 * iwl_enqueue_hcmd - enqueue a uCode command
558 * @priv: device private data point
559 * @cmd: a point to the ucode command structure
561 * The function returns < 0 values to indicate the operation is
562 * failed. On success, it turns the index (> 0) of command in the
565 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
567 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
568 struct iwl_queue *q = &txq->q;
569 struct iwl_device_cmd *out_cmd;
570 struct iwl_cmd_meta *out_meta;
571 dma_addr_t phys_addr;
574 u16 copy_size, cmd_size;
575 bool is_ct_kill = false;
576 bool had_nocopy = false;
579 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
580 const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
581 int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
585 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
586 IWL_WARN(priv, "fw recovery, no hcmd send\n");
590 copy_size = sizeof(out_cmd->hdr);
591 cmd_size = sizeof(out_cmd->hdr);
593 /* need one for the header if the first is NOCOPY */
594 BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
596 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
599 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
602 /* NOCOPY must not be followed by normal! */
603 if (WARN_ON(had_nocopy))
605 copy_size += cmd->len[i];
607 cmd_size += cmd->len[i];
611 * If any of the command structures end up being larger than
612 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
613 * allocated into separate TFDs, then we will need to
614 * increase the size of the buffers.
616 if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
619 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
620 IWL_WARN(priv, "Not sending command - %s KILL\n",
621 iwl_is_rfkill(priv) ? "RF" : "CT");
625 spin_lock_irqsave(&priv->hcmd_lock, flags);
627 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
628 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
630 IWL_ERR(priv, "No space in command queue\n");
631 is_ct_kill = iwl_check_for_ct_kill(priv);
633 IWL_ERR(priv, "Restarting adapter due to queue full\n");
634 iwlagn_fw_error(priv, false);
639 idx = get_cmd_index(q, q->write_ptr);
640 out_cmd = txq->cmd[idx];
641 out_meta = &txq->meta[idx];
643 if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
644 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
648 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
649 if (cmd->flags & CMD_WANT_SKB)
650 out_meta->source = cmd;
651 if (cmd->flags & CMD_ASYNC)
652 out_meta->callback = cmd->callback;
654 /* set up the header */
656 out_cmd->hdr.cmd = cmd->id;
657 out_cmd->hdr.flags = 0;
658 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) |
659 INDEX_TO_SEQ(q->write_ptr));
661 /* and copy the data that needs to be copied */
663 cmd_dest = &out_cmd->cmd.payload[0];
664 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
667 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
669 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
670 cmd_dest += cmd->len[i];
673 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
674 "%d bytes at %d[%d]:%d\n",
675 get_cmd_string(out_cmd->hdr.cmd),
677 le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
678 q->write_ptr, idx, priv->cmd_queue);
680 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
681 copy_size, PCI_DMA_BIDIRECTIONAL);
682 if (unlikely(pci_dma_mapping_error(priv->pci_dev, phys_addr))) {
687 dma_unmap_addr_set(out_meta, mapping, phys_addr);
688 dma_unmap_len_set(out_meta, len, copy_size);
690 iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr, copy_size, 1);
691 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
692 trace_bufs[0] = &out_cmd->hdr;
693 trace_lens[0] = copy_size;
697 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
700 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
702 phys_addr = pci_map_single(priv->pci_dev, (void *)cmd->data[i],
703 cmd->len[i], PCI_DMA_TODEVICE);
704 if (pci_dma_mapping_error(priv->pci_dev, phys_addr)) {
705 iwlagn_unmap_tfd(priv, out_meta,
706 &txq->tfds[q->write_ptr]);
711 iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr,
713 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
714 trace_bufs[trace_idx] = cmd->data[i];
715 trace_lens[trace_idx] = cmd->len[i];
720 out_meta->flags = cmd->flags | CMD_MAPPED;
722 txq->need_update = 1;
724 /* check that tracing gets all possible blocks */
725 BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
726 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
727 trace_iwlwifi_dev_hcmd(priv, cmd->flags,
728 trace_bufs[0], trace_lens[0],
729 trace_bufs[1], trace_lens[1],
730 trace_bufs[2], trace_lens[2]);
733 /* Increment and update queue's write index */
734 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
735 iwl_txq_update_write_ptr(priv, txq);
738 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
743 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
745 * When FW advances 'R' index, all entries between old and new 'R' index
746 * need to be reclaimed. As result, some free space forms. If there is
747 * enough free space (> low mark), wake the stack that feeds us.
749 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx)
751 struct iwl_tx_queue *txq = &priv->txq[txq_id];
752 struct iwl_queue *q = &txq->q;
755 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
756 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
757 "is out of range [0-%d] %d %d.\n", txq_id,
758 idx, q->n_bd, q->write_ptr, q->read_ptr);
762 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
763 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
766 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
767 q->write_ptr, q->read_ptr);
768 iwlagn_fw_error(priv, false);
775 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
776 * @rxb: Rx buffer to reclaim
778 * If an Rx buffer has an async callback associated with it the callback
779 * will be executed. The attached skb (if present) will only be freed
780 * if the callback returns 1
782 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
784 struct iwl_rx_packet *pkt = rxb_addr(rxb);
785 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
786 int txq_id = SEQ_TO_QUEUE(sequence);
787 int index = SEQ_TO_INDEX(sequence);
789 struct iwl_device_cmd *cmd;
790 struct iwl_cmd_meta *meta;
791 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
794 /* If a Tx command is being handled and it isn't in the actual
795 * command queue then there a command routing bug has been introduced
796 * in the queue management code. */
797 if (WARN(txq_id != priv->cmd_queue,
798 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
799 txq_id, priv->cmd_queue, sequence,
800 priv->txq[priv->cmd_queue].q.read_ptr,
801 priv->txq[priv->cmd_queue].q.write_ptr)) {
802 iwl_print_hex_error(priv, pkt, 32);
806 cmd_index = get_cmd_index(&txq->q, index);
807 cmd = txq->cmd[cmd_index];
808 meta = &txq->meta[cmd_index];
810 iwlagn_unmap_tfd(priv, meta, &txq->tfds[index]);
812 /* Input error checking is done when commands are added to queue. */
813 if (meta->flags & CMD_WANT_SKB) {
814 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
816 } else if (meta->callback)
817 meta->callback(priv, cmd, pkt);
819 spin_lock_irqsave(&priv->hcmd_lock, flags);
821 iwl_hcmd_queue_reclaim(priv, txq_id, index);
823 if (!(meta->flags & CMD_ASYNC)) {
824 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
825 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
826 get_cmd_string(cmd->hdr.cmd));
827 wake_up_interruptible(&priv->wait_command_queue);
830 /* Mark as unmapped */
833 spin_unlock_irqrestore(&priv->hcmd_lock, flags);