drivers/net/wireless/iwlwifi/iwl-trans-pcie.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  22  * USA
  23  *
  24  * The full GNU General Public License is included in this distribution
  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  30  *
  31  * BSD LICENSE
  32  *
  33  * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
  34  * All rights reserved.
  35  *
  36  * Redistribution and use in source and binary forms, with or without
  37  * modification, are permitted provided that the following conditions
  38  * are met:
  39  *
  40  *  * Redistributions of source code must retain the above copyright
  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
  46  *  * Neither the name Intel Corporation nor the names of its
  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/interrupt.h>
  64 #include <linux/debugfs.h>
  65 #include <linux/bitops.h>
  66 #include <linux/gfp.h>
  67
  68 #include "iwl-trans.h"
  69 #include "iwl-trans-pcie-int.h"
  70 #include "iwl-csr.h"
  71 #include "iwl-prph.h"
  72 #include "iwl-shared.h"
  73 #include "iwl-eeprom.h"
  74 #include "iwl-agn-hw.h"
  75
  76 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  77 {
  78         struct iwl_trans_pcie *trans_pcie =
  79                 IWL_TRANS_GET_PCIE_TRANS(trans);
  80         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  81         struct device *dev = bus(trans)->dev;
  82
  83         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  84
  85         spin_lock_init(&rxq->lock);
  86
  87         if (WARN_ON(rxq->bd || rxq->rb_stts))
  88                 return -EINVAL;
  89
  90         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  91         rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  92                                      &rxq->bd_dma, GFP_KERNEL);
  93         if (!rxq->bd)
  94                 goto err_bd;
  95         memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
  96
  97         /*Allocate the driver's pointer to receive buffer status */
  98         rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
  99                                           &rxq->rb_stts_dma, GFP_KERNEL);
 100         if (!rxq->rb_stts)
 101                 goto err_rb_stts;
 102         memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
 103
 104         return 0;
 105
 106 err_rb_stts:
 107         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 108                         rxq->bd, rxq->bd_dma);
 109         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 110         rxq->bd = NULL;
 111 err_bd:
 112         return -ENOMEM;
 113 }
 114
 115 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 116 {
 117         struct iwl_trans_pcie *trans_pcie =
 118                 IWL_TRANS_GET_PCIE_TRANS(trans);
 119         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 120         int i;
 121
 122         /* Fill the rx_used queue with _all_ of the Rx buffers */
 123         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 124                 /* In the reset function, these buffers may have been allocated
 125                  * to an SKB, so we need to unmap and free potential storage */
 126                 if (rxq->pool[i].page != NULL) {
 127                         dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
 128                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 129                                 DMA_FROM_DEVICE);
 130                         __free_pages(rxq->pool[i].page,
 131                                      hw_params(trans).rx_page_order);
 132                         rxq->pool[i].page = NULL;
 133                 }
 134                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 135         }
 136 }
 137
 138 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 139                                  struct iwl_rx_queue *rxq)
 140 {
 141         u32 rb_size;
 142         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 143         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 144
 145         if (iwlagn_mod_params.amsdu_size_8K)
 146                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 147         else
 148                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 149
 150         /* Stop Rx DMA */
 151         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 152
 153         /* Reset driver's Rx queue write index */
 154         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 155
 156         /* Tell device where to find RBD circular buffer in DRAM */
 157         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 158                            (u32)(rxq->bd_dma >> 8));
 159
 160         /* Tell device where in DRAM to update its Rx status */
 161         iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG,
 162                            rxq->rb_stts_dma >> 4);
 163
 164         /* Enable Rx DMA
 165          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 166          *      the credit mechanism in 5000 HW RX FIFO
 167          * Direct rx interrupts to hosts
 168          * Rx buffer size 4 or 8k
 169          * RB timeout 0x10
 170          * 256 RBDs
 171          */
 172         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG,
 173                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 174                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 175                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 176                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 177                            rb_size|
 178                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 179                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 180
 181         /* Set interrupt coalescing timer to default (2048 usecs) */
 182         iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 183 }
 184
 185 static int iwl_rx_init(struct iwl_trans *trans)
 186 {
 187         struct iwl_trans_pcie *trans_pcie =
 188                 IWL_TRANS_GET_PCIE_TRANS(trans);
 189         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 190
 191         int i, err;
 192         unsigned long flags;
 193
 194         if (!rxq->bd) {
 195                 err = iwl_trans_rx_alloc(trans);
 196                 if (err)
 197                         return err;
 198         }
 199
 200         spin_lock_irqsave(&rxq->lock, flags);
 201         INIT_LIST_HEAD(&rxq->rx_free);
 202         INIT_LIST_HEAD(&rxq->rx_used);
 203
 204         iwl_trans_rxq_free_rx_bufs(trans);
 205
 206         for (i = 0; i < RX_QUEUE_SIZE; i++)
 207                 rxq->queue[i] = NULL;
 208
 209         /* Set us so that we have processed and used all buffers, but have
 210          * not restocked the Rx queue with fresh buffers */
 211         rxq->read = rxq->write = 0;
 212         rxq->write_actual = 0;
 213         rxq->free_count = 0;
 214         spin_unlock_irqrestore(&rxq->lock, flags);
 215
 216         iwlagn_rx_replenish(trans);
 217
 218         iwl_trans_rx_hw_init(trans, rxq);
 219
 220         spin_lock_irqsave(&trans->shrd->lock, flags);
 221         rxq->need_update = 1;
 222         iwl_rx_queue_update_write_ptr(trans, rxq);
 223         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 224
 225         return 0;
 226 }
 227
 228 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 229 {
 230         struct iwl_trans_pcie *trans_pcie =
 231                 IWL_TRANS_GET_PCIE_TRANS(trans);
 232         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 233
 234         unsigned long flags;
 235
 236         /*if rxq->bd is NULL, it means that nothing has been allocated,
 237          * exit now */
 238         if (!rxq->bd) {
 239                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 240                 return;
 241         }
 242
 243         spin_lock_irqsave(&rxq->lock, flags);
 244         iwl_trans_rxq_free_rx_bufs(trans);
 245         spin_unlock_irqrestore(&rxq->lock, flags);
 246
 247         dma_free_coherent(bus(trans)->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 248                           rxq->bd, rxq->bd_dma);
 249         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 250         rxq->bd = NULL;
 251
 252         if (rxq->rb_stts)
 253                 dma_free_coherent(bus(trans)->dev,
 254                                   sizeof(struct iwl_rb_status),
 255                                   rxq->rb_stts, rxq->rb_stts_dma);
 256         else
 257                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 258         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 259         rxq->rb_stts = NULL;
 260 }
 261
 262 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 263 {
 264
 265         /* stop Rx DMA */
 266         iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 267         return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG,
 268                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 269 }
 270
 271 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 272                                     struct iwl_dma_ptr *ptr, size_t size)
 273 {
 274         if (WARN_ON(ptr->addr))
 275                 return -EINVAL;
 276
 277         ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
 278                                        &ptr->dma, GFP_KERNEL);
 279         if (!ptr->addr)
 280                 return -ENOMEM;
 281         ptr->size = size;
 282         return 0;
 283 }
 284
 285 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 286                                     struct iwl_dma_ptr *ptr)
 287 {
 288         if (unlikely(!ptr->addr))
 289                 return;
 290
 291         dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
 292         memset(ptr, 0, sizeof(*ptr));
 293 }
 294
 295 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 296                                 struct iwl_tx_queue *txq, int slots_num,
 297                                 u32 txq_id)
 298 {
 299         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 300         int i;
 301
 302         if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
 303                 return -EINVAL;
 304
 305         txq->q.n_window = slots_num;
 306
 307         txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
 308         txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
 309
 310         if (!txq->meta || !txq->cmd)
 311                 goto error;
 312
 313         if (txq_id == trans->shrd->cmd_queue)
 314                 for (i = 0; i < slots_num; i++) {
 315                         txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
 316                                                 GFP_KERNEL);
 317                         if (!txq->cmd[i])
 318                                 goto error;
 319                 }
 320
 321         /* Alloc driver data array and TFD circular buffer */
 322         /* Driver private data, only for Tx (not command) queues,
 323          * not shared with device. */
 324         if (txq_id != trans->shrd->cmd_queue) {
 325                 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
 326                                     GFP_KERNEL);
 327                 if (!txq->skbs) {
 328                         IWL_ERR(trans, "kmalloc for auxiliary BD "
 329                                   "structures failed\n");
 330                         goto error;
 331                 }
 332         } else {
 333                 txq->skbs = NULL;
 334         }
 335
 336         /* Circular buffer of transmit frame descriptors (TFDs),
 337          * shared with device */
 338         txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
 339                                        &txq->q.dma_addr, GFP_KERNEL);
 340         if (!txq->tfds) {
 341                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 342                 goto error;
 343         }
 344         txq->q.id = txq_id;
 345
 346         return 0;
 347 error:
 348         kfree(txq->skbs);
 349         txq->skbs = NULL;
 350         /* since txq->cmd has been zeroed,
 351          * all non allocated cmd[i] will be NULL */
 352         if (txq->cmd && txq_id == trans->shrd->cmd_queue)
 353                 for (i = 0; i < slots_num; i++)
 354                         kfree(txq->cmd[i]);
 355         kfree(txq->meta);
 356         kfree(txq->cmd);
 357         txq->meta = NULL;
 358         txq->cmd = NULL;
 359
 360         return -ENOMEM;
 361
 362 }
 363
 364 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 365                       int slots_num, u32 txq_id)
 366 {
 367         int ret;
 368
 369         txq->need_update = 0;
 370         memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
 371
 372         /*
 373          * For the default queues 0-3, set up the swq_id
 374          * already -- all others need to get one later
 375          * (if they need one at all).
 376          */
 377         if (txq_id < 4)
 378                 iwl_set_swq_id(txq, txq_id, txq_id);
 379
 380         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 381          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 382         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 383
 384         /* Initialize queue's high/low-water marks, and head/tail indexes */
 385         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 386                         txq_id);
 387         if (ret)
 388                 return ret;
 389
 390         /*
 391          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 392          * given Tx queue, and enable the DMA channel used for that queue.
 393          * Circular buffer (TFD queue in DRAM) physical base address */
 394         iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id),
 395                              txq->q.dma_addr >> 8);
 396
 397         return 0;
 398 }
 399
 400 /**
 401  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 402  */
 403 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 404 {
 405         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 406         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 407         struct iwl_queue *q = &txq->q;
 408         enum dma_data_direction dma_dir;
 409         unsigned long flags;
 410         spinlock_t *lock;
 411
 412         if (!q->n_bd)
 413                 return;
 414
 415         /* In the command queue, all the TBs are mapped as BIDI
 416          * so unmap them as such.
 417          */
 418         if (txq_id == trans->shrd->cmd_queue) {
 419                 dma_dir = DMA_BIDIRECTIONAL;
 420                 lock = &trans->hcmd_lock;
 421         } else {
 422                 dma_dir = DMA_TO_DEVICE;
 423                 lock = &trans->shrd->sta_lock;
 424         }
 425
 426         spin_lock_irqsave(lock, flags);
 427         while (q->write_ptr != q->read_ptr) {
 428                 /* The read_ptr needs to bound by q->n_window */
 429                 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
 430                                     dma_dir);
 431                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 432         }
 433         spin_unlock_irqrestore(lock, flags);
 434 }
 435
 436 /**
 437  * iwl_tx_queue_free - Deallocate DMA queue.
 438  * @txq: Transmit queue to deallocate.
 439  *
 440  * Empty queue by removing and destroying all BD's.
 441  * Free all buffers.
 442  * 0-fill, but do not free "txq" descriptor structure.
 443  */
 444 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 445 {
 446         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 447         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 448         struct device *dev = bus(trans)->dev;
 449         int i;
 450         if (WARN_ON(!txq))
 451                 return;
 452
 453         iwl_tx_queue_unmap(trans, txq_id);
 454
 455         /* De-alloc array of command/tx buffers */
 456
 457         if (txq_id == trans->shrd->cmd_queue)
 458                 for (i = 0; i < txq->q.n_window; i++)
 459                         kfree(txq->cmd[i]);
 460
 461         /* De-alloc circular buffer of TFDs */
 462         if (txq->q.n_bd) {
 463                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 464                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 465                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 466         }
 467
 468         /* De-alloc array of per-TFD driver data */
 469         kfree(txq->skbs);
 470         txq->skbs = NULL;
 471
 472         /* deallocate arrays */
 473         kfree(txq->cmd);
 474         kfree(txq->meta);
 475         txq->cmd = NULL;
 476         txq->meta = NULL;
 477
 478         /* 0-fill queue descriptor structure */
 479         memset(txq, 0, sizeof(*txq));
 480 }
 481
 482 /**
 483  * iwl_trans_tx_free - Free TXQ Context
 484  *
 485  * Destroy all TX DMA queues and structures
 486  */
 487 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 488 {
 489         int txq_id;
 490         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 491
 492         /* Tx queues */
 493         if (trans_pcie->txq) {
 494                 for (txq_id = 0;
 495                      txq_id < hw_params(trans).max_txq_num; txq_id++)
 496                         iwl_tx_queue_free(trans, txq_id);
 497         }
 498
 499         kfree(trans_pcie->txq);
 500         trans_pcie->txq = NULL;
 501
 502         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 503
 504         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 505 }
 506
 507 /**
 508  * iwl_trans_tx_alloc - allocate TX context
 509  * Allocate all Tx DMA structures and initialize them
 510  *
 511  * @param priv
 512  * @return error code
 513  */
 514 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 515 {
 516         int ret;
 517         int txq_id, slots_num;
 518         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 519
 520         u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
 521                         sizeof(struct iwlagn_scd_bc_tbl);
 522
 523         /*It is not allowed to alloc twice, so warn when this happens.
 524          * We cannot rely on the previous allocation, so free and fail */
 525         if (WARN_ON(trans_pcie->txq)) {
 526                 ret = -EINVAL;
 527                 goto error;
 528         }
 529
 530         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 531                                    scd_bc_tbls_size);
 532         if (ret) {
 533                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 534                 goto error;
 535         }
 536
 537         /* Alloc keep-warm buffer */
 538         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 539         if (ret) {
 540                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 541                 goto error;
 542         }
 543
 544         trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
 545                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 546         if (!trans_pcie->txq) {
 547                 IWL_ERR(trans, "Not enough memory for txq\n");
 548                 ret = ENOMEM;
 549                 goto error;
 550         }
 551
 552         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 553         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 554                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 555                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 556                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 557                                           slots_num, txq_id);
 558                 if (ret) {
 559                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 560                         goto error;
 561                 }
 562         }
 563
 564         return 0;
 565
 566 error:
 567         iwl_trans_pcie_tx_free(trans);
 568
 569         return ret;
 570 }
 571 static int iwl_tx_init(struct iwl_trans *trans)
 572 {
 573         int ret;
 574         int txq_id, slots_num;
 575         unsigned long flags;
 576         bool alloc = false;
 577         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 578
 579         if (!trans_pcie->txq) {
 580                 ret = iwl_trans_tx_alloc(trans);
 581                 if (ret)
 582                         goto error;
 583                 alloc = true;
 584         }
 585
 586         spin_lock_irqsave(&trans->shrd->lock, flags);
 587
 588         /* Turn off all Tx DMA fifos */
 589         iwl_write_prph(bus(trans), SCD_TXFACT, 0);
 590
 591         /* Tell NIC where to find the "keep warm" buffer */
 592         iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG,
 593                            trans_pcie->kw.dma >> 4);
 594
 595         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 596
 597         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 598         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 599                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 600                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 601                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 602                                          slots_num, txq_id);
 603                 if (ret) {
 604                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 605                         goto error;
 606                 }
 607         }
 608
 609         return 0;
 610 error:
 611         /*Upon error, free only if we allocated something */
 612         if (alloc)
 613                 iwl_trans_pcie_tx_free(trans);
 614         return ret;
 615 }
 616
 617 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 618 {
 619 /*
 620  * (for documentation purposes)
 621  * to set power to V_AUX, do:
 622
 623                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 624                         iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
 625                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 626                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 627  */
 628
 629         iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
 630                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 631                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 632 }
 633
 634 static int iwl_nic_init(struct iwl_trans *trans)
 635 {
 636         unsigned long flags;
 637
 638         /* nic_init */
 639         spin_lock_irqsave(&trans->shrd->lock, flags);
 640         iwl_apm_init(priv(trans));
 641
 642         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 643         iwl_write8(bus(trans), CSR_INT_COALESCING,
 644                 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 645
 646         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 647
 648         iwl_set_pwr_vmain(trans);
 649
 650         iwl_nic_config(priv(trans));
 651
 652         /* Allocate the RX queue, or reset if it is already allocated */
 653         iwl_rx_init(trans);
 654
 655         /* Allocate or reset and init all Tx and Command queues */
 656         if (iwl_tx_init(trans))
 657                 return -ENOMEM;
 658
 659         if (hw_params(trans).shadow_reg_enable) {
 660                 /* enable shadow regs in HW */
 661                 iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
 662                         0x800FFFFF);
 663         }
 664
 665         set_bit(STATUS_INIT, &trans->shrd->status);
 666
 667         return 0;
 668 }
 669
 670 #define HW_READY_TIMEOUT (50)
 671
 672 /* Note: returns poll_bit return value, which is >= 0 if success */
 673 static int iwl_set_hw_ready(struct iwl_trans *trans)
 674 {
 675         int ret;
 676
 677         iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 678                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 679
 680         /* See if we got it */
 681         ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 682                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 683                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 684                                 HW_READY_TIMEOUT);
 685
 686         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 687         return ret;
 688 }
 689
 690 /* Note: returns standard 0/-ERROR code */
 691 static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
 692 {
 693         int ret;
 694
 695         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 696
 697         ret = iwl_set_hw_ready(trans);
 698         if (ret >= 0)
 699                 return 0;
 700
 701         /* If HW is not ready, prepare the conditions to check again */
 702         iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 703                         CSR_HW_IF_CONFIG_REG_PREPARE);
 704
 705         ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
 706                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 707                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 708
 709         if (ret < 0)
 710                 return ret;
 711
 712         /* HW should be ready by now, check again. */
 713         ret = iwl_set_hw_ready(trans);
 714         if (ret >= 0)
 715                 return 0;
 716         return ret;
 717 }
 718
 719 #define IWL_AC_UNSET -1
 720
 721 struct queue_to_fifo_ac {
 722         s8 fifo, ac;
 723 };
 724
 725 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
 726         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 727         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 728         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 729         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 730         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 731         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 732         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 733         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 734         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 735         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 736         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 737 };
 738
 739 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
 740         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 741         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 742         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 743         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 744         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
 745         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
 746         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
 747         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
 748         { IWL_TX_FIFO_BE_IPAN, 2, },
 749         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 750         { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
 751 };
 752
 753 static const u8 iwlagn_bss_ac_to_fifo[] = {
 754         IWL_TX_FIFO_VO,
 755         IWL_TX_FIFO_VI,
 756         IWL_TX_FIFO_BE,
 757         IWL_TX_FIFO_BK,
 758 };
 759 static const u8 iwlagn_bss_ac_to_queue[] = {
 760         0, 1, 2, 3,
 761 };
 762 static const u8 iwlagn_pan_ac_to_fifo[] = {
 763         IWL_TX_FIFO_VO_IPAN,
 764         IWL_TX_FIFO_VI_IPAN,
 765         IWL_TX_FIFO_BE_IPAN,
 766         IWL_TX_FIFO_BK_IPAN,
 767 };
 768 static const u8 iwlagn_pan_ac_to_queue[] = {
 769         7, 6, 5, 4,
 770 };
 771
 772 static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
 773 {
 774         int ret;
 775         struct iwl_trans_pcie *trans_pcie =
 776                 IWL_TRANS_GET_PCIE_TRANS(trans);
 777
 778         trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
 779         trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
 780         trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
 781
 782         trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
 783         trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
 784
 785         trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
 786         trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
 787
 788         if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
 789              iwl_trans_pcie_prepare_card_hw(trans)) {
 790                 IWL_WARN(trans, "Exit HW not ready\n");
 791                 return -EIO;
 792         }
 793
 794         /* If platform's RF_KILL switch is NOT set to KILL */
 795         if (iwl_read32(bus(trans), CSR_GP_CNTRL) &
 796                         CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
 797                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 798         else
 799                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
 800
 801         if (iwl_is_rfkill(trans->shrd)) {
 802                 iwl_set_hw_rfkill_state(priv(trans), true);
 803                 iwl_enable_interrupts(trans);
 804                 return -ERFKILL;
 805         }
 806
 807         iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
 808
 809         ret = iwl_nic_init(trans);
 810         if (ret) {
 811                 IWL_ERR(trans, "Unable to init nic\n");
 812                 return ret;
 813         }
 814
 815         /* make sure rfkill handshake bits are cleared */
 816         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 817         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR,
 818                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 819
 820         /* clear (again), then enable host interrupts */
 821         iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
 822         iwl_enable_interrupts(trans);
 823
 824         /* really make sure rfkill handshake bits are cleared */
 825         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 826         iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 827
 828         return 0;
 829 }
 830
 831 /*
 832  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
 833  * must be called under priv->shrd->lock and mac access
 834  */
 835 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
 836 {
 837         iwl_write_prph(bus(trans), SCD_TXFACT, mask);
 838 }
 839
 840 static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
 841 {
 842         const struct queue_to_fifo_ac *queue_to_fifo;
 843         struct iwl_trans_pcie *trans_pcie =
 844                 IWL_TRANS_GET_PCIE_TRANS(trans);
 845         u32 a;
 846         unsigned long flags;
 847         int i, chan;
 848         u32 reg_val;
 849
 850         spin_lock_irqsave(&trans->shrd->lock, flags);
 851
 852         trans_pcie->scd_base_addr =
 853                 iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR);
 854         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
 855         /* reset conext data memory */
 856         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
 857                 a += 4)
 858                 iwl_write_targ_mem(bus(trans), a, 0);
 859         /* reset tx status memory */
 860         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
 861                 a += 4)
 862                 iwl_write_targ_mem(bus(trans), a, 0);
 863         for (; a < trans_pcie->scd_base_addr +
 864                SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
 865                a += 4)
 866                 iwl_write_targ_mem(bus(trans), a, 0);
 867
 868         iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR,
 869                        trans_pcie->scd_bc_tbls.dma >> 10);
 870
 871         /* Enable DMA channel */
 872         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
 873                 iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 874                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 875                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 876
 877         /* Update FH chicken bits */
 878         reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG);
 879         iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG,
 880                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 881
 882         iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
 883                 SCD_QUEUECHAIN_SEL_ALL(trans));
 884         iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
 885
 886         /* initiate the queues */
 887         for (i = 0; i < hw_params(trans).max_txq_num; i++) {
 888                 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
 889                 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
 890                 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
 891                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 892                 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
 893                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
 894                                 sizeof(u32),
 895                                 ((SCD_WIN_SIZE <<
 896                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 897                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 898                                 ((SCD_FRAME_LIMIT <<
 899                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 900                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 901         }
 902
 903         iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK,
 904                         IWL_MASK(0, hw_params(trans).max_txq_num));
 905
 906         /* Activate all Tx DMA/FIFO channels */
 907         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
 908
 909         /* map queues to FIFOs */
 910         if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
 911                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
 912         else
 913                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
 914
 915         iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
 916
 917         /* make sure all queue are not stopped */
 918         memset(&trans_pcie->queue_stopped[0], 0,
 919                 sizeof(trans_pcie->queue_stopped));
 920         for (i = 0; i < 4; i++)
 921                 atomic_set(&trans_pcie->queue_stop_count[i], 0);
 922
 923         /* reset to 0 to enable all the queue first */
 924         trans_pcie->txq_ctx_active_msk = 0;
 925
 926         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
 927                                                 IWLAGN_FIRST_AMPDU_QUEUE);
 928         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
 929                                                 IWLAGN_FIRST_AMPDU_QUEUE);
 930
 931         for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
 932                 int fifo = queue_to_fifo[i].fifo;
 933                 int ac = queue_to_fifo[i].ac;
 934
 935                 iwl_txq_ctx_activate(trans_pcie, i);
 936
 937                 if (fifo == IWL_TX_FIFO_UNUSED)
 938                         continue;
 939
 940                 if (ac != IWL_AC_UNSET)
 941                         iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
 942                 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
 943                                               fifo, 0);
 944         }
 945
 946         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 947
 948         /* Enable L1-Active */
 949         iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG,
 950                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 951 }
 952
 953 /**
 954  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
 955  */
 956 static int iwl_trans_tx_stop(struct iwl_trans *trans)
 957 {
 958         int ch, txq_id;
 959         unsigned long flags;
 960         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 961
 962         /* Turn off all Tx DMA fifos */
 963         spin_lock_irqsave(&trans->shrd->lock, flags);
 964
 965         iwl_trans_txq_set_sched(trans, 0);
 966
 967         /* Stop each Tx DMA channel, and wait for it to be idle */
 968         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
 969                 iwl_write_direct32(bus(trans),
 970                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
 971                 if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG,
 972                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
 973                                     1000))
 974                         IWL_ERR(trans, "Failing on timeout while stopping"
 975                             " DMA channel %d [0x%08x]", ch,
 976                             iwl_read_direct32(bus(trans),
 977                                               FH_TSSR_TX_STATUS_REG));
 978         }
 979         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 980
 981         if (!trans_pcie->txq) {
 982                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
 983                 return 0;
 984         }
 985
 986         /* Unmap DMA from host system and free skb's */
 987         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
 988                 iwl_tx_queue_unmap(trans, txq_id);
 989
 990         return 0;
 991 }
 992
 993 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 994 {
 995         unsigned long flags;
 996         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 997
 998         /* tell the device to stop sending interrupts */
 999         spin_lock_irqsave(&trans->shrd->lock, flags);
1000         iwl_disable_interrupts(trans);
1001         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1002
1003         /* device going down, Stop using ICT table */
1004         iwl_disable_ict(trans);
1005
1006         /*
1007          * If a HW restart happens during firmware loading,
1008          * then the firmware loading might call this function
1009          * and later it might be called again due to the
1010          * restart. So don't process again if the device is
1011          * already dead.
1012          */
1013         if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1014                 iwl_trans_tx_stop(trans);
1015                 iwl_trans_rx_stop(trans);
1016
1017                 /* Power-down device's busmaster DMA clocks */
1018                 iwl_write_prph(bus(trans), APMG_CLK_DIS_REG,
1019                                APMG_CLK_VAL_DMA_CLK_RQT);
1020                 udelay(5);
1021         }
1022
1023         /* Make sure (redundant) we've released our request to stay awake */
1024         iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1025                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1026
1027         /* Stop the device, and put it in low power state */
1028         iwl_apm_stop(priv(trans));
1029
1030         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1031          * Clean again the interrupt here
1032          */
1033         spin_lock_irqsave(&trans->shrd->lock, flags);
1034         iwl_disable_interrupts(trans);
1035         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1036
1037         /* wait to make sure we flush pending tasklet*/
1038         synchronize_irq(bus(trans)->irq);
1039         tasklet_kill(&trans_pcie->irq_tasklet);
1040
1041         /* stop and reset the on-board processor */
1042         iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1043 }
1044
1045 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1046                 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1047                 u8 sta_id)
1048 {
1049         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1050         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1051         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1052         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1053         struct iwl_cmd_meta *out_meta;
1054         struct iwl_tx_queue *txq;
1055         struct iwl_queue *q;
1056
1057         dma_addr_t phys_addr = 0;
1058         dma_addr_t txcmd_phys;
1059         dma_addr_t scratch_phys;
1060         u16 len, firstlen, secondlen;
1061         u16 seq_number = 0;
1062         u8 wait_write_ptr = 0;
1063         u8 txq_id;
1064         u8 tid = 0;
1065         bool is_agg = false;
1066         __le16 fc = hdr->frame_control;
1067         u8 hdr_len = ieee80211_hdrlen(fc);
1068
1069         /*
1070          * Send this frame after DTIM -- there's a special queue
1071          * reserved for this for contexts that support AP mode.
1072          */
1073         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1074                 txq_id = trans_pcie->mcast_queue[ctx];
1075
1076                 /*
1077                  * The microcode will clear the more data
1078                  * bit in the last frame it transmits.
1079                  */
1080                 hdr->frame_control |=
1081                         cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1082         } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1083                 txq_id = IWL_AUX_QUEUE;
1084         else
1085                 txq_id =
1086                     trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1087
1088         if (ieee80211_is_data_qos(fc) && !ieee80211_is_qos_nullfunc(fc)) {
1089                 u8 *qc = NULL;
1090                 struct iwl_tid_data *tid_data;
1091                 qc = ieee80211_get_qos_ctl(hdr);
1092                 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
1093                 tid_data = &trans->shrd->tid_data[sta_id][tid];
1094
1095                 if (WARN_ON_ONCE(tid >= IWL_MAX_TID_COUNT))
1096                         return -1;
1097
1098                 seq_number = tid_data->seq_number;
1099                 seq_number &= IEEE80211_SCTL_SEQ;
1100                 hdr->seq_ctrl = hdr->seq_ctrl &
1101                                 cpu_to_le16(IEEE80211_SCTL_FRAG);
1102                 hdr->seq_ctrl |= cpu_to_le16(seq_number);
1103                 seq_number += 0x10;
1104                 /* aggregation is on for this <sta,tid> */
1105                 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1106                         WARN_ON_ONCE(tid_data->agg.state != IWL_AGG_ON);
1107                         txq_id = tid_data->agg.txq_id;
1108                         is_agg = true;
1109                 }
1110         }
1111
1112         /* Copy MAC header from skb into command buffer */
1113         memcpy(tx_cmd->hdr, hdr, hdr_len);
1114
1115         txq = &trans_pcie->txq[txq_id];
1116         q = &txq->q;
1117
1118         /* Set up driver data for this TFD */
1119         txq->skbs[q->write_ptr] = skb;
1120         txq->cmd[q->write_ptr] = dev_cmd;
1121
1122         dev_cmd->hdr.cmd = REPLY_TX;
1123         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1124                                 INDEX_TO_SEQ(q->write_ptr)));
1125
1126         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1127         out_meta = &txq->meta[q->write_ptr];
1128
1129         /*
1130          * Use the first empty entry in this queue's command buffer array
1131          * to contain the Tx command and MAC header concatenated together
1132          * (payload data will be in another buffer).
1133          * Size of this varies, due to varying MAC header length.
1134          * If end is not dword aligned, we'll have 2 extra bytes at the end
1135          * of the MAC header (device reads on dword boundaries).
1136          * We'll tell device about this padding later.
1137          */
1138         len = sizeof(struct iwl_tx_cmd) +
1139                 sizeof(struct iwl_cmd_header) + hdr_len;
1140         firstlen = (len + 3) & ~3;
1141
1142         /* Tell NIC about any 2-byte padding after MAC header */
1143         if (firstlen != len)
1144                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1145
1146         /* Physical address of this Tx command's header (not MAC header!),
1147          * within command buffer array. */
1148         txcmd_phys = dma_map_single(bus(trans)->dev,
1149                                     &dev_cmd->hdr, firstlen,
1150                                     DMA_BIDIRECTIONAL);
1151         if (unlikely(dma_mapping_error(bus(trans)->dev, txcmd_phys)))
1152                 return -1;
1153         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1154         dma_unmap_len_set(out_meta, len, firstlen);
1155
1156         if (!ieee80211_has_morefrags(fc)) {
1157                 txq->need_update = 1;
1158         } else {
1159                 wait_write_ptr = 1;
1160                 txq->need_update = 0;
1161         }
1162
1163         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1164          * if any (802.11 null frames have no payload). */
1165         secondlen = skb->len - hdr_len;
1166         if (secondlen > 0) {
1167                 phys_addr = dma_map_single(bus(trans)->dev, skb->data + hdr_len,
1168                                            secondlen, DMA_TO_DEVICE);
1169                 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
1170                         dma_unmap_single(bus(trans)->dev,
1171                                          dma_unmap_addr(out_meta, mapping),
1172                                          dma_unmap_len(out_meta, len),
1173                                          DMA_BIDIRECTIONAL);
1174                         return -1;
1175                 }
1176         }
1177
1178         /* Attach buffers to TFD */
1179         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1180         if (secondlen > 0)
1181                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1182                                              secondlen, 0);
1183
1184         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1185                                 offsetof(struct iwl_tx_cmd, scratch);
1186
1187         /* take back ownership of DMA buffer to enable update */
1188         dma_sync_single_for_cpu(bus(trans)->dev, txcmd_phys, firstlen,
1189                         DMA_BIDIRECTIONAL);
1190         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1191         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1192
1193         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1194                      le16_to_cpu(dev_cmd->hdr.sequence));
1195         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1196         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1197         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1198
1199         /* Set up entry for this TFD in Tx byte-count array */
1200         if (is_agg)
1201                 iwl_trans_txq_update_byte_cnt_tbl(trans, txq,
1202                                                le16_to_cpu(tx_cmd->len));
1203
1204         dma_sync_single_for_device(bus(trans)->dev, txcmd_phys, firstlen,
1205                         DMA_BIDIRECTIONAL);
1206
1207         trace_iwlwifi_dev_tx(priv(trans),
1208                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1209                              sizeof(struct iwl_tfd),
1210                              &dev_cmd->hdr, firstlen,
1211                              skb->data + hdr_len, secondlen);
1212
1213         /* Tell device the write index *just past* this latest filled TFD */
1214         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1215         iwl_txq_update_write_ptr(trans, txq);
1216
1217         if (ieee80211_is_data_qos(fc) && !ieee80211_is_qos_nullfunc(fc)) {
1218                 trans->shrd->tid_data[sta_id][tid].tfds_in_queue++;
1219                 if (!ieee80211_has_morefrags(fc))
1220                         trans->shrd->tid_data[sta_id][tid].seq_number =
1221                                 seq_number;
1222         }
1223
1224         /*
1225          * At this point the frame is "transmitted" successfully
1226          * and we will get a TX status notification eventually,
1227          * regardless of the value of ret. "ret" only indicates
1228          * whether or not we should update the write pointer.
1229          */
1230         if (iwl_queue_space(q) < q->high_mark) {
1231                 if (wait_write_ptr) {
1232                         txq->need_update = 1;
1233                         iwl_txq_update_write_ptr(trans, txq);
1234                 } else {
1235                         iwl_stop_queue(trans, txq);
1236                 }
1237         }
1238         return 0;
1239 }
1240
1241 static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1242 {
1243         /* Remove all resets to allow NIC to operate */
1244         iwl_write32(bus(trans), CSR_RESET, 0);
1245 }
1246
1247 static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
1248 {
1249         struct iwl_trans_pcie *trans_pcie =
1250                 IWL_TRANS_GET_PCIE_TRANS(trans);
1251         int err;
1252
1253         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1254
1255         tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1256                 iwl_irq_tasklet, (unsigned long)trans);
1257
1258         iwl_alloc_isr_ict(trans);
1259
1260         err = request_irq(bus(trans)->irq, iwl_isr_ict, IRQF_SHARED,
1261                 DRV_NAME, trans);
1262         if (err) {
1263                 IWL_ERR(trans, "Error allocating IRQ %d\n", bus(trans)->irq);
1264                 iwl_free_isr_ict(trans);
1265                 return err;
1266         }
1267
1268         INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1269         return 0;
1270 }
1271
1272 static int iwlagn_txq_check_empty(struct iwl_trans *trans,
1273                            int sta_id, u8 tid, int txq_id)
1274 {
1275         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1276         struct iwl_queue *q = &trans_pcie->txq[txq_id].q;
1277         struct iwl_tid_data *tid_data = &trans->shrd->tid_data[sta_id][tid];
1278
1279         lockdep_assert_held(&trans->shrd->sta_lock);
1280
1281         switch (trans->shrd->tid_data[sta_id][tid].agg.state) {
1282         case IWL_EMPTYING_HW_QUEUE_DELBA:
1283                 /* We are reclaiming the last packet of the */
1284                 /* aggregated HW queue */
1285                 if ((txq_id  == tid_data->agg.txq_id) &&
1286                     (q->read_ptr == q->write_ptr)) {
1287                         IWL_DEBUG_HT(trans,
1288                                 "HW queue empty: continue DELBA flow\n");
1289                         iwl_trans_pcie_txq_agg_disable(trans, txq_id);
1290                         tid_data->agg.state = IWL_AGG_OFF;
1291                         iwl_stop_tx_ba_trans_ready(priv(trans),
1292                                                    NUM_IWL_RXON_CTX,
1293                                                    sta_id, tid);
1294                         iwl_wake_queue(trans, &trans_pcie->txq[txq_id]);
1295                 }
1296                 break;
1297         case IWL_EMPTYING_HW_QUEUE_ADDBA:
1298                 /* We are reclaiming the last packet of the queue */
1299                 if (tid_data->tfds_in_queue == 0) {
1300                         IWL_DEBUG_HT(trans,
1301                                 "HW queue empty: continue ADDBA flow\n");
1302                         tid_data->agg.state = IWL_AGG_ON;
1303                         iwl_start_tx_ba_trans_ready(priv(trans),
1304                                                     NUM_IWL_RXON_CTX,
1305                                                     sta_id, tid);
1306                 }
1307                 break;
1308         default:
1309                 break;
1310         }
1311
1312         return 0;
1313 }
1314
1315 static void iwl_free_tfds_in_queue(struct iwl_trans *trans,
1316                             int sta_id, int tid, int freed)
1317 {
1318         lockdep_assert_held(&trans->shrd->sta_lock);
1319
1320         if (trans->shrd->tid_data[sta_id][tid].tfds_in_queue >= freed)
1321                 trans->shrd->tid_data[sta_id][tid].tfds_in_queue -= freed;
1322         else {
1323                 IWL_DEBUG_TX(trans, "free more than tfds_in_queue (%u:%d)\n",
1324                         trans->shrd->tid_data[sta_id][tid].tfds_in_queue,
1325                         freed);
1326                 trans->shrd->tid_data[sta_id][tid].tfds_in_queue = 0;
1327         }
1328 }
1329
1330 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1331                       int txq_id, int ssn, u32 status,
1332                       struct sk_buff_head *skbs)
1333 {
1334         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1335         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1336         enum iwl_agg_state agg_state;
1337         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1338         int tfd_num = ssn & (txq->q.n_bd - 1);
1339         int freed = 0;
1340         bool cond;
1341
1342         txq->time_stamp = jiffies;
1343
1344         if (txq->sched_retry) {
1345                 agg_state =
1346                         trans->shrd->tid_data[txq->sta_id][txq->tid].agg.state;
1347                 cond = (agg_state != IWL_EMPTYING_HW_QUEUE_DELBA);
1348         } else {
1349                 cond = (status != TX_STATUS_FAIL_PASSIVE_NO_RX);
1350         }
1351
1352         if (txq->q.read_ptr != tfd_num) {
1353                 IWL_DEBUG_TX_REPLY(trans, "Retry scheduler reclaim "
1354                                 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1355                                 ssn , tfd_num, txq_id, txq->swq_id);
1356                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1357                 if (iwl_queue_space(&txq->q) > txq->q.low_mark && cond)
1358                         iwl_wake_queue(trans, txq);
1359         }
1360
1361         iwl_free_tfds_in_queue(trans, sta_id, tid, freed);
1362         iwlagn_txq_check_empty(trans, sta_id, tid, txq_id);
1363 }
1364
1365 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1366 {
1367         iwl_trans_pcie_tx_free(trans);
1368         iwl_trans_pcie_rx_free(trans);
1369         free_irq(bus(trans)->irq, trans);
1370         iwl_free_isr_ict(trans);
1371         trans->shrd->trans = NULL;
1372         kfree(trans);
1373 }
1374
1375 #ifdef CONFIG_PM_SLEEP
1376 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1377 {
1378         /*
1379          * This function is called when system goes into suspend state
1380          * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend
1381          * function first but since iwlagn_mac_stop() has no knowledge of
1382          * who the caller is,
1383          * it will not call apm_ops.stop() to stop the DMA operation.
1384          * Calling apm_ops.stop here to make sure we stop the DMA.
1385          *
1386          * But of course ... if we have configured WoWLAN then we did other
1387          * things already :-)
1388          */
1389         if (!trans->shrd->wowlan) {
1390                 iwl_apm_stop(priv(trans));
1391         } else {
1392                 iwl_disable_interrupts(trans);
1393                 iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
1394                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1395         }
1396
1397         return 0;
1398 }
1399
1400 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1401 {
1402         bool hw_rfkill = false;
1403
1404         iwl_enable_interrupts(trans);
1405
1406         if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1407                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1408                 hw_rfkill = true;
1409
1410         if (hw_rfkill)
1411                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1412         else
1413                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1414
1415         iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1416
1417         return 0;
1418 }
1419 #endif /* CONFIG_PM_SLEEP */
1420
1421 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1422                                           enum iwl_rxon_context_id ctx)
1423 {
1424         u8 ac, txq_id;
1425         struct iwl_trans_pcie *trans_pcie =
1426                 IWL_TRANS_GET_PCIE_TRANS(trans);
1427
1428         for (ac = 0; ac < AC_NUM; ac++) {
1429                 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1430                 IWL_DEBUG_INFO(trans, "Queue Status: Q[%d] %s\n",
1431                         ac,
1432                         (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1433                               ? "stopped" : "awake");
1434                 iwl_wake_queue(trans, &trans_pcie->txq[txq_id]);
1435         }
1436 }
1437
1438 const struct iwl_trans_ops trans_ops_pcie;
1439
1440 static struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd)
1441 {
1442         struct iwl_trans *iwl_trans = kzalloc(sizeof(struct iwl_trans) +
1443                                               sizeof(struct iwl_trans_pcie),
1444                                               GFP_KERNEL);
1445         if (iwl_trans) {
1446                 struct iwl_trans_pcie *trans_pcie =
1447                         IWL_TRANS_GET_PCIE_TRANS(iwl_trans);
1448                 iwl_trans->ops = &trans_ops_pcie;
1449                 iwl_trans->shrd = shrd;
1450                 trans_pcie->trans = iwl_trans;
1451                 spin_lock_init(&iwl_trans->hcmd_lock);
1452         }
1453
1454         return iwl_trans;
1455 }
1456
1457 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id)
1458 {
1459         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1460
1461         iwl_stop_queue(trans, &trans_pcie->txq[txq_id]);
1462 }
1463
1464 #define IWL_FLUSH_WAIT_MS       2000
1465
1466 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1467 {
1468         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1469         struct iwl_tx_queue *txq;
1470         struct iwl_queue *q;
1471         int cnt;
1472         unsigned long now = jiffies;
1473         int ret = 0;
1474
1475         /* waiting for all the tx frames complete might take a while */
1476         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1477                 if (cnt == trans->shrd->cmd_queue)
1478                         continue;
1479                 txq = &trans_pcie->txq[cnt];
1480                 q = &txq->q;
1481                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1482                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1483                         msleep(1);
1484
1485                 if (q->read_ptr != q->write_ptr) {
1486                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1487                         ret = -ETIMEDOUT;
1488                         break;
1489                 }
1490         }
1491         return ret;
1492 }
1493
1494 /*
1495  * On every watchdog tick we check (latest) time stamp. If it does not
1496  * change during timeout period and queue is not empty we reset firmware.
1497  */
1498 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1499 {
1500         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1501         struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1502         struct iwl_queue *q = &txq->q;
1503         unsigned long timeout;
1504
1505         if (q->read_ptr == q->write_ptr) {
1506                 txq->time_stamp = jiffies;
1507                 return 0;
1508         }
1509
1510         timeout = txq->time_stamp +
1511                   msecs_to_jiffies(hw_params(trans).wd_timeout);
1512
1513         if (time_after(jiffies, timeout)) {
1514                 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1515                         hw_params(trans).wd_timeout);
1516                 IWL_ERR(trans, "Current read_ptr %d write_ptr %d\n",
1517                         q->read_ptr, q->write_ptr);
1518                 return 1;
1519         }
1520
1521         return 0;
1522 }
1523
1524 static const char *get_fh_string(int cmd)
1525 {
1526         switch (cmd) {
1527         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1528         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1529         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1530         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1531         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1532         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1533         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1534         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1535         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1536         default:
1537                 return "UNKNOWN";
1538         }
1539 }
1540
1541 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1542 {
1543         int i;
1544 #ifdef CONFIG_IWLWIFI_DEBUG
1545         int pos = 0;
1546         size_t bufsz = 0;
1547 #endif
1548         static const u32 fh_tbl[] = {
1549                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1550                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1551                 FH_RSCSR_CHNL0_WPTR,
1552                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1553                 FH_MEM_RSSR_SHARED_CTRL_REG,
1554                 FH_MEM_RSSR_RX_STATUS_REG,
1555                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1556                 FH_TSSR_TX_STATUS_REG,
1557                 FH_TSSR_TX_ERROR_REG
1558         };
1559 #ifdef CONFIG_IWLWIFI_DEBUG
1560         if (display) {
1561                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1562                 *buf = kmalloc(bufsz, GFP_KERNEL);
1563                 if (!*buf)
1564                         return -ENOMEM;
1565                 pos += scnprintf(*buf + pos, bufsz - pos,
1566                                 "FH register values:\n");
1567                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1568                         pos += scnprintf(*buf + pos, bufsz - pos,
1569                                 "  %34s: 0X%08x\n",
1570                                 get_fh_string(fh_tbl[i]),
1571                                 iwl_read_direct32(bus(trans), fh_tbl[i]));
1572                 }
1573                 return pos;
1574         }
1575 #endif
1576         IWL_ERR(trans, "FH register values:\n");
1577         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1578                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1579                         get_fh_string(fh_tbl[i]),
1580                         iwl_read_direct32(bus(trans), fh_tbl[i]));
1581         }
1582         return 0;
1583 }
1584
1585 static const char *get_csr_string(int cmd)
1586 {
1587         switch (cmd) {
1588         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1589         IWL_CMD(CSR_INT_COALESCING);
1590         IWL_CMD(CSR_INT);
1591         IWL_CMD(CSR_INT_MASK);
1592         IWL_CMD(CSR_FH_INT_STATUS);
1593         IWL_CMD(CSR_GPIO_IN);
1594         IWL_CMD(CSR_RESET);
1595         IWL_CMD(CSR_GP_CNTRL);
1596         IWL_CMD(CSR_HW_REV);
1597         IWL_CMD(CSR_EEPROM_REG);
1598         IWL_CMD(CSR_EEPROM_GP);
1599         IWL_CMD(CSR_OTP_GP_REG);
1600         IWL_CMD(CSR_GIO_REG);
1601         IWL_CMD(CSR_GP_UCODE_REG);
1602         IWL_CMD(CSR_GP_DRIVER_REG);
1603         IWL_CMD(CSR_UCODE_DRV_GP1);
1604         IWL_CMD(CSR_UCODE_DRV_GP2);
1605         IWL_CMD(CSR_LED_REG);
1606         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1607         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1608         IWL_CMD(CSR_ANA_PLL_CFG);
1609         IWL_CMD(CSR_HW_REV_WA_REG);
1610         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1611         default:
1612                 return "UNKNOWN";
1613         }
1614 }
1615
1616 void iwl_dump_csr(struct iwl_trans *trans)
1617 {
1618         int i;
1619         static const u32 csr_tbl[] = {
1620                 CSR_HW_IF_CONFIG_REG,
1621                 CSR_INT_COALESCING,
1622                 CSR_INT,
1623                 CSR_INT_MASK,
1624                 CSR_FH_INT_STATUS,
1625                 CSR_GPIO_IN,
1626                 CSR_RESET,
1627                 CSR_GP_CNTRL,
1628                 CSR_HW_REV,
1629                 CSR_EEPROM_REG,
1630                 CSR_EEPROM_GP,
1631                 CSR_OTP_GP_REG,
1632                 CSR_GIO_REG,
1633                 CSR_GP_UCODE_REG,
1634                 CSR_GP_DRIVER_REG,
1635                 CSR_UCODE_DRV_GP1,
1636                 CSR_UCODE_DRV_GP2,
1637                 CSR_LED_REG,
1638                 CSR_DRAM_INT_TBL_REG,
1639                 CSR_GIO_CHICKEN_BITS,
1640                 CSR_ANA_PLL_CFG,
1641                 CSR_HW_REV_WA_REG,
1642                 CSR_DBG_HPET_MEM_REG
1643         };
1644         IWL_ERR(trans, "CSR values:\n");
1645         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1646                 "CSR_INT_PERIODIC_REG)\n");
1647         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1648                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1649                         get_csr_string(csr_tbl[i]),
1650                         iwl_read32(bus(trans), csr_tbl[i]));
1651         }
1652 }
1653
1654 #ifdef CONFIG_IWLWIFI_DEBUGFS
1655 /* create and remove of files */
1656 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1657         if (!debugfs_create_file(#name, mode, parent, trans,            \
1658                                  &iwl_dbgfs_##name##_ops))              \
1659                 return -ENOMEM;                                         \
1660 } while (0)
1661
1662 /* file operation */
1663 #define DEBUGFS_READ_FUNC(name)                                         \
1664 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1665                                         char __user *user_buf,          \
1666                                         size_t count, loff_t *ppos);
1667
1668 #define DEBUGFS_WRITE_FUNC(name)                                        \
1669 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1670                                         const char __user *user_buf,    \
1671                                         size_t count, loff_t *ppos);
1672
1673
1674 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1675 {
1676         file->private_data = inode->i_private;
1677         return 0;
1678 }
1679
1680 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1681         DEBUGFS_READ_FUNC(name);                                        \
1682 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1683         .read = iwl_dbgfs_##name##_read,                                \
1684         .open = iwl_dbgfs_open_file_generic,                            \
1685         .llseek = generic_file_llseek,                                  \
1686 };
1687
1688 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1689         DEBUGFS_WRITE_FUNC(name);                                       \
1690 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1691         .write = iwl_dbgfs_##name##_write,                              \
1692         .open = iwl_dbgfs_open_file_generic,                            \
1693         .llseek = generic_file_llseek,                                  \
1694 };
1695
1696 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1697         DEBUGFS_READ_FUNC(name);                                        \
1698         DEBUGFS_WRITE_FUNC(name);                                       \
1699 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1700         .write = iwl_dbgfs_##name##_write,                              \
1701         .read = iwl_dbgfs_##name##_read,                                \
1702         .open = iwl_dbgfs_open_file_generic,                            \
1703         .llseek = generic_file_llseek,                                  \
1704 };
1705
1706 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1707                                                 char __user *user_buf,
1708                                                 size_t count, loff_t *ppos)
1709 {
1710         struct iwl_trans *trans = file->private_data;
1711         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1712         struct iwl_tx_queue *txq;
1713         struct iwl_queue *q;
1714         char *buf;
1715         int pos = 0;
1716         int cnt;
1717         int ret;
1718         const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1719
1720         if (!trans_pcie->txq) {
1721                 IWL_ERR(trans, "txq not ready\n");
1722                 return -EAGAIN;
1723         }
1724         buf = kzalloc(bufsz, GFP_KERNEL);
1725         if (!buf)
1726                 return -ENOMEM;
1727
1728         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1729                 txq = &trans_pcie->txq[cnt];
1730                 q = &txq->q;
1731                 pos += scnprintf(buf + pos, bufsz - pos,
1732                                 "hwq %.2d: read=%u write=%u stop=%d"
1733                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
1734                                 cnt, q->read_ptr, q->write_ptr,
1735                                 !!test_bit(cnt, trans_pcie->queue_stopped),
1736                                 txq->swq_id, txq->swq_id & 3,
1737                                 (txq->swq_id >> 2) & 0x1f);
1738                 if (cnt >= 4)
1739                         continue;
1740                 /* for the ACs, display the stop count too */
1741                 pos += scnprintf(buf + pos, bufsz - pos,
1742                         "        stop-count: %d\n",
1743                         atomic_read(&trans_pcie->queue_stop_count[cnt]));
1744         }
1745         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1746         kfree(buf);
1747         return ret;
1748 }
1749
1750 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1751                                                 char __user *user_buf,
1752                                                 size_t count, loff_t *ppos) {
1753         struct iwl_trans *trans = file->private_data;
1754         struct iwl_trans_pcie *trans_pcie =
1755                 IWL_TRANS_GET_PCIE_TRANS(trans);
1756         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1757         char buf[256];
1758         int pos = 0;
1759         const size_t bufsz = sizeof(buf);
1760
1761         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1762                                                 rxq->read);
1763         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1764                                                 rxq->write);
1765         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1766                                                 rxq->free_count);
1767         if (rxq->rb_stts) {
1768                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1769                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1770         } else {
1771                 pos += scnprintf(buf + pos, bufsz - pos,
1772                                         "closed_rb_num: Not Allocated\n");
1773         }
1774         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1775 }
1776
1777 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1778                                          char __user *user_buf,
1779                                          size_t count, loff_t *ppos)
1780 {
1781         struct iwl_trans *trans = file->private_data;
1782         char *buf;
1783         int pos = 0;
1784         ssize_t ret = -ENOMEM;
1785
1786         ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1787         if (buf) {
1788                 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1789                 kfree(buf);
1790         }
1791         return ret;
1792 }
1793
1794 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1795                                         const char __user *user_buf,
1796                                         size_t count, loff_t *ppos)
1797 {
1798         struct iwl_trans *trans = file->private_data;
1799         u32 event_log_flag;
1800         char buf[8];
1801         int buf_size;
1802
1803         memset(buf, 0, sizeof(buf));
1804         buf_size = min(count, sizeof(buf) -  1);
1805         if (copy_from_user(buf, user_buf, buf_size))
1806                 return -EFAULT;
1807         if (sscanf(buf, "%d", &event_log_flag) != 1)
1808                 return -EFAULT;
1809         if (event_log_flag == 1)
1810                 iwl_dump_nic_event_log(trans, true, NULL, false);
1811
1812         return count;
1813 }
1814
1815 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1816                                         char __user *user_buf,
1817                                         size_t count, loff_t *ppos) {
1818
1819         struct iwl_trans *trans = file->private_data;
1820         struct iwl_trans_pcie *trans_pcie =
1821                 IWL_TRANS_GET_PCIE_TRANS(trans);
1822         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1823
1824         int pos = 0;
1825         char *buf;
1826         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1827         ssize_t ret;
1828
1829         buf = kzalloc(bufsz, GFP_KERNEL);
1830         if (!buf) {
1831                 IWL_ERR(trans, "Can not allocate Buffer\n");
1832                 return -ENOMEM;
1833         }
1834
1835         pos += scnprintf(buf + pos, bufsz - pos,
1836                         "Interrupt Statistics Report:\n");
1837
1838         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1839                 isr_stats->hw);
1840         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1841                 isr_stats->sw);
1842         if (isr_stats->sw || isr_stats->hw) {
1843                 pos += scnprintf(buf + pos, bufsz - pos,
1844                         "\tLast Restarting Code:  0x%X\n",
1845                         isr_stats->err_code);
1846         }
1847 #ifdef CONFIG_IWLWIFI_DEBUG
1848         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1849                 isr_stats->sch);
1850         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1851                 isr_stats->alive);
1852 #endif
1853         pos += scnprintf(buf + pos, bufsz - pos,
1854                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1855
1856         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1857                 isr_stats->ctkill);
1858
1859         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1860                 isr_stats->wakeup);
1861
1862         pos += scnprintf(buf + pos, bufsz - pos,
1863                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1864
1865         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1866                 isr_stats->tx);
1867
1868         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1869                 isr_stats->unhandled);
1870
1871         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1872         kfree(buf);
1873         return ret;
1874 }
1875
1876 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1877                                          const char __user *user_buf,
1878                                          size_t count, loff_t *ppos)
1879 {
1880         struct iwl_trans *trans = file->private_data;
1881         struct iwl_trans_pcie *trans_pcie =
1882                 IWL_TRANS_GET_PCIE_TRANS(trans);
1883         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1884
1885         char buf[8];
1886         int buf_size;
1887         u32 reset_flag;
1888
1889         memset(buf, 0, sizeof(buf));
1890         buf_size = min(count, sizeof(buf) -  1);
1891         if (copy_from_user(buf, user_buf, buf_size))
1892                 return -EFAULT;
1893         if (sscanf(buf, "%x", &reset_flag) != 1)
1894                 return -EFAULT;
1895         if (reset_flag == 0)
1896                 memset(isr_stats, 0, sizeof(*isr_stats));
1897
1898         return count;
1899 }
1900
1901 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1902                                          const char __user *user_buf,
1903                                          size_t count, loff_t *ppos)
1904 {
1905         struct iwl_trans *trans = file->private_data;
1906         char buf[8];
1907         int buf_size;
1908         int csr;
1909
1910         memset(buf, 0, sizeof(buf));
1911         buf_size = min(count, sizeof(buf) -  1);
1912         if (copy_from_user(buf, user_buf, buf_size))
1913                 return -EFAULT;
1914         if (sscanf(buf, "%d", &csr) != 1)
1915                 return -EFAULT;
1916
1917         iwl_dump_csr(trans);
1918
1919         return count;
1920 }
1921
1922 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1923                                          char __user *user_buf,
1924                                          size_t count, loff_t *ppos)
1925 {
1926         struct iwl_trans *trans = file->private_data;
1927         char *buf;
1928         int pos = 0;
1929         ssize_t ret = -EFAULT;
1930
1931         ret = pos = iwl_dump_fh(trans, &buf, true);
1932         if (buf) {
1933                 ret = simple_read_from_buffer(user_buf,
1934                                               count, ppos, buf, pos);
1935                 kfree(buf);
1936         }
1937
1938         return ret;
1939 }
1940
1941 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
1942 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1943 DEBUGFS_READ_FILE_OPS(fh_reg);
1944 DEBUGFS_READ_FILE_OPS(rx_queue);
1945 DEBUGFS_READ_FILE_OPS(tx_queue);
1946 DEBUGFS_WRITE_FILE_OPS(csr);
1947
1948 /*
1949  * Create the debugfs files and directories
1950  *
1951  */
1952 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1953                                         struct dentry *dir)
1954 {
1955         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1956         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1957         DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
1958         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1959         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1960         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1961         return 0;
1962 }
1963 #else
1964 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1965                                         struct dentry *dir)
1966 { return 0; }
1967
1968 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1969
1970 const struct iwl_trans_ops trans_ops_pcie = {
1971         .alloc = iwl_trans_pcie_alloc,
1972         .request_irq = iwl_trans_pcie_request_irq,
1973         .start_device = iwl_trans_pcie_start_device,
1974         .prepare_card_hw = iwl_trans_pcie_prepare_card_hw,
1975         .stop_device = iwl_trans_pcie_stop_device,
1976
1977         .tx_start = iwl_trans_pcie_tx_start,
1978         .wake_any_queue = iwl_trans_pcie_wake_any_queue,
1979
1980         .send_cmd = iwl_trans_pcie_send_cmd,
1981
1982         .tx = iwl_trans_pcie_tx,
1983         .reclaim = iwl_trans_pcie_reclaim,
1984
1985         .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
1986         .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
1987         .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
1988
1989         .kick_nic = iwl_trans_pcie_kick_nic,
1990
1991         .free = iwl_trans_pcie_free,
1992         .stop_queue = iwl_trans_pcie_stop_queue,
1993
1994         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1995
1996         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
1997         .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
1998
1999 #ifdef CONFIG_PM_SLEEP
2000         .suspend = iwl_trans_pcie_suspend,
2001         .resume = iwl_trans_pcie_resume,
2002 #endif
2003 };