1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #ifndef __iwl_trans_int_pcie_h__
30 #define __iwl_trans_int_pcie_h__
32 #include <linux/spinlock.h>
33 #include <linux/interrupt.h>
34 #include <linux/skbuff.h>
35 #include <linux/pci.h>
39 #include "iwl-shared.h"
40 #include "iwl-trans.h"
41 #include "iwl-debug.h"
48 /*This file includes the declaration that are internal to the
52 * struct isr_statistics - interrupt statistics
55 struct isr_statistics {
70 * struct iwl_rx_queue - Rx queue
71 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd)
72 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
75 * @read: Shared index to newest available Rx buffer
76 * @write: Shared index to oldest written Rx packet
77 * @free_count: Number of pre-allocated buffers in rx_free
79 * @rx_free: list of free SKBs for use
80 * @rx_used: List of Rx buffers with no SKB
81 * @need_update: flag to indicate we need to update read/write index
82 * @rb_stts: driver's pointer to receive buffer status
83 * @rb_stts_dma: bus address of receive buffer status
86 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
91 struct iwl_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
92 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
97 struct list_head rx_free;
98 struct list_head rx_used;
100 struct iwl_rb_status *rb_stts;
101 dma_addr_t rb_stts_dma;
112 * This queue number is required for proper operation
113 * because the ucode will stop/start the scheduler as
116 #define IWL_IPAN_MCAST_QUEUE 8
118 struct iwl_cmd_meta {
119 /* only for SYNC commands, iff the reply skb is wanted */
120 struct iwl_host_cmd *source;
124 DEFINE_DMA_UNMAP_ADDR(mapping);
125 DEFINE_DMA_UNMAP_LEN(len);
129 * Generic queue structure
131 * Contains common data for Rx and Tx queues.
133 * Note the difference between n_bd and n_window: the hardware
134 * always assumes 256 descriptors, so n_bd is always 256 (unless
135 * there might be HW changes in the future). For the normal TX
136 * queues, n_window, which is the size of the software queue data
137 * is also 256; however, for the command queue, n_window is only
138 * 32 since we don't need so many commands pending. Since the HW
139 * still uses 256 BDs for DMA though, n_bd stays 256. As a result,
140 * the software buffers (in the variables @meta, @txb in struct
141 * iwl_tx_queue) only have 32 entries, while the HW buffers (@tfds
142 * in the same struct) have 256.
143 * This means that we end up with the following:
144 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 |
145 * SW entries: | 0 | ... | 31 |
146 * where N is a number between 0 and 7. This means that the SW
147 * data is a window overlayed over the HW queue.
150 int n_bd; /* number of BDs in this queue */
151 int write_ptr; /* 1-st empty entry (index) host_w*/
152 int read_ptr; /* last used entry (index) host_r*/
153 /* use for monitoring and recovering the stuck queue */
154 dma_addr_t dma_addr; /* physical addr for BD's */
155 int n_window; /* safe queue window */
157 int low_mark; /* low watermark, resume queue if free
158 * space more than this */
159 int high_mark; /* high watermark, stop queue if free
160 * space less than this */
164 * struct iwl_tx_queue - Tx Queue for DMA
165 * @q: generic Rx/Tx queue descriptor
166 * @bd: base of circular buffer of TFDs
167 * @cmd: array of command/TX buffer pointers
168 * @meta: array of meta data for each command/tx buffer
169 * @dma_addr_cmd: physical address of cmd/tx buffer array
170 * @txb: array of per-TFD driver data
171 * @time_stamp: time (in jiffies) of last read_ptr change
172 * @need_update: indicates need to update read/write index
173 * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
174 * @sta_id: valid if sched_retry is set
175 * @tid: valid if sched_retry is set
177 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame
178 * descriptors) and required locking structures.
180 #define TFD_TX_CMD_SLOTS 256
181 #define TFD_CMD_SLOTS 32
183 struct iwl_tx_queue {
185 struct iwl_tfd *tfds;
186 struct iwl_device_cmd **cmd;
187 struct iwl_cmd_meta *meta;
188 struct sk_buff **skbs;
189 unsigned long time_stamp;
200 * struct iwl_trans_pcie - PCIe transport specific data
201 * @rxq: all the RX queue data
202 * @rx_replenish: work that will be called when buffers need to be allocated
203 * @trans: pointer to the generic transport area
204 * @scd_base_addr: scheduler sram base address in SRAM
205 * @scd_bc_tbls: pointer to the byte count table of the scheduler
206 * @kw: keep warm address
207 * @ac_to_fifo: to what fifo is a specifc AC mapped ?
208 * @ac_to_queue: to what tx queue is a specifc AC mapped ?
210 * @txq: Tx DMA processing queues
211 * @txq_ctx_active_msk: what queue is active
212 * queue_stopped: tracks what queue is stopped
213 * queue_stop_count: tracks what SW queue is stopped
215 struct iwl_trans_pcie {
216 struct iwl_rx_queue rxq;
217 struct work_struct rx_replenish;
218 struct iwl_trans *trans;
223 dma_addr_t ict_tbl_dma;
224 dma_addr_t aligned_ict_tbl_dma;
228 struct tasklet_struct irq_tasklet;
229 struct isr_statistics isr_stats;
233 struct iwl_dma_ptr scd_bc_tbls;
234 struct iwl_dma_ptr kw;
236 const u8 *ac_to_fifo[NUM_IWL_RXON_CTX];
237 const u8 *ac_to_queue[NUM_IWL_RXON_CTX];
238 u8 mcast_queue[NUM_IWL_RXON_CTX];
239 u8 agg_txq[IWLAGN_STATION_COUNT][IWL_MAX_TID_COUNT];
241 struct iwl_tx_queue *txq;
242 unsigned long txq_ctx_active_msk;
243 #define IWL_MAX_HW_QUEUES 32
244 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_HW_QUEUES)];
245 atomic_t queue_stop_count[4];
248 #define IWL_TRANS_GET_PCIE_TRANS(_iwl_trans) \
249 ((struct iwl_trans_pcie *) ((_iwl_trans)->trans_specific))
251 /*****************************************************
253 ******************************************************/
254 void iwl_bg_rx_replenish(struct work_struct *data);
255 void iwl_irq_tasklet(struct iwl_trans *trans);
256 void iwlagn_rx_replenish(struct iwl_trans *trans);
257 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
258 struct iwl_rx_queue *q);
260 /*****************************************************
262 ******************************************************/
263 int iwl_reset_ict(struct iwl_trans *trans);
264 void iwl_disable_ict(struct iwl_trans *trans);
265 int iwl_alloc_isr_ict(struct iwl_trans *trans);
266 void iwl_free_isr_ict(struct iwl_trans *trans);
267 irqreturn_t iwl_isr_ict(int irq, void *data);
269 /*****************************************************
271 ******************************************************/
272 void iwl_txq_update_write_ptr(struct iwl_trans *trans,
273 struct iwl_tx_queue *txq);
274 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
275 struct iwl_tx_queue *txq,
276 dma_addr_t addr, u16 len, u8 reset);
277 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id);
278 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
279 void iwl_tx_cmd_complete(struct iwl_trans *trans,
280 struct iwl_rx_mem_buffer *rxb, int handler_status);
281 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
282 struct iwl_tx_queue *txq,
284 int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans,
285 int sta_id, int tid);
286 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, int txq_id, u32 index);
287 void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
288 struct iwl_tx_queue *txq,
289 int tx_fifo_id, int scd_retry);
290 int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans, int sta_id, int tid);
291 void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
292 enum iwl_rxon_context_id ctx,
293 int sta_id, int tid, int frame_limit, u16 ssn);
294 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
295 int index, enum dma_data_direction dma_dir);
296 int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
297 struct sk_buff_head *skbs);
298 int iwl_queue_space(const struct iwl_queue *q);
300 /*****************************************************
302 ******************************************************/
303 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
304 char **buf, bool display);
305 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display);
306 void iwl_dump_csr(struct iwl_trans *trans);
308 /*****************************************************
310 ******************************************************/
311 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
313 clear_bit(STATUS_INT_ENABLED, &trans->shrd->status);
315 /* disable interrupts from uCode/NIC to host */
316 iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
318 /* acknowledge/clear/reset any interrupts still pending
319 * from uCode or flow handler (Rx/Tx DMA) */
320 iwl_write32(bus(trans), CSR_INT, 0xffffffff);
321 iwl_write32(bus(trans), CSR_FH_INT_STATUS, 0xffffffff);
322 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
325 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
327 struct iwl_trans_pcie *trans_pcie =
328 IWL_TRANS_GET_PCIE_TRANS(trans);
330 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
331 set_bit(STATUS_INT_ENABLED, &trans->shrd->status);
332 iwl_write32(bus(trans), CSR_INT_MASK, trans_pcie->inta_mask);
336 * we have 8 bits used like this:
340 * | | | | | | +-+-------- AC queue (0-3)
342 * | +-+-+-+-+------------ HW queue ID
344 * +---------------------- unused
346 static inline void iwl_set_swq_id(struct iwl_tx_queue *txq, u8 ac, u8 hwq)
348 BUG_ON(ac > 3); /* only have 2 bits */
349 BUG_ON(hwq > 31); /* only use 5 bits */
351 txq->swq_id = (hwq << 2) | ac;
354 static inline u8 iwl_get_queue_ac(struct iwl_tx_queue *txq)
356 return txq->swq_id & 0x3;
359 static inline void iwl_wake_queue(struct iwl_trans *trans,
360 struct iwl_tx_queue *txq, const char *msg)
362 u8 queue = txq->swq_id;
364 u8 hwq = (queue >> 2) & 0x1f;
365 struct iwl_trans_pcie *trans_pcie =
366 IWL_TRANS_GET_PCIE_TRANS(trans);
368 if (test_and_clear_bit(hwq, trans_pcie->queue_stopped)) {
369 if (atomic_dec_return(&trans_pcie->queue_stop_count[ac]) <= 0) {
370 iwl_wake_sw_queue(priv(trans), ac);
371 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d ac %d. %s",
374 IWL_DEBUG_TX_QUEUES(trans, "Don't wake hwq %d ac %d"
375 " stop count %d. %s",
376 hwq, ac, atomic_read(&trans_pcie->
377 queue_stop_count[ac]), msg);
382 static inline void iwl_stop_queue(struct iwl_trans *trans,
383 struct iwl_tx_queue *txq, const char *msg)
385 u8 queue = txq->swq_id;
387 u8 hwq = (queue >> 2) & 0x1f;
388 struct iwl_trans_pcie *trans_pcie =
389 IWL_TRANS_GET_PCIE_TRANS(trans);
391 if (!test_and_set_bit(hwq, trans_pcie->queue_stopped)) {
392 if (atomic_inc_return(&trans_pcie->queue_stop_count[ac]) > 0) {
393 iwl_stop_sw_queue(priv(trans), ac);
394 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d ac %d"
395 " stop count %d. %s",
396 hwq, ac, atomic_read(&trans_pcie->
397 queue_stop_count[ac]), msg);
399 IWL_DEBUG_TX_QUEUES(trans, "Don't stop hwq %d ac %d"
400 " stop count %d. %s",
401 hwq, ac, atomic_read(&trans_pcie->
402 queue_stop_count[ac]), msg);
405 IWL_DEBUG_TX_QUEUES(trans, "stop hwq %d, but it is stopped/ %s",
410 #ifdef ieee80211_stop_queue
411 #undef ieee80211_stop_queue
414 #define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
416 #ifdef ieee80211_wake_queue
417 #undef ieee80211_wake_queue
420 #define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
422 static inline void iwl_txq_ctx_activate(struct iwl_trans_pcie *trans_pcie,
425 set_bit(txq_id, &trans_pcie->txq_ctx_active_msk);
428 static inline void iwl_txq_ctx_deactivate(struct iwl_trans_pcie *trans_pcie,
431 clear_bit(txq_id, &trans_pcie->txq_ctx_active_msk);
434 static inline int iwl_queue_used(const struct iwl_queue *q, int i)
436 return q->write_ptr >= q->read_ptr ?
437 (i >= q->read_ptr && i < q->write_ptr) :
438 !(i < q->read_ptr && i >= q->write_ptr);
441 static inline u8 get_cmd_index(struct iwl_queue *q, u32 index)
443 return index & (q->n_window - 1);
446 #define IWL_TX_FIFO_BK 0 /* shared */
447 #define IWL_TX_FIFO_BE 1
448 #define IWL_TX_FIFO_VI 2 /* shared */
449 #define IWL_TX_FIFO_VO 3
450 #define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
451 #define IWL_TX_FIFO_BE_IPAN 4
452 #define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
453 #define IWL_TX_FIFO_VO_IPAN 5
454 /* re-uses the VO FIFO, uCode will properly flush/schedule */
455 #define IWL_TX_FIFO_AUX 5
456 #define IWL_TX_FIFO_UNUSED -1
458 /* AUX (TX during scan dwell) queue */
459 #define IWL_AUX_QUEUE 10
461 #endif /* __iwl_trans_int_pcie_h__ */