drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-agn-calib.h"
  61 #include "iwl-agn.h"
  62
  63
  64 /******************************************************************************
  65  *
  66  * module boiler plate
  67  *
  68  ******************************************************************************/
  69
  70 /*
  71  * module name, copyright, version, etc.
  72  */
  73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  74
  75 #ifdef CONFIG_IWLWIFI_DEBUG
  76 #define VD "d"
  77 #else
  78 #define VD
  79 #endif
  80
  81 #define DRV_VERSION     IWLWIFI_VERSION VD
  82
  83
  84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  85 MODULE_VERSION(DRV_VERSION);
  86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  87 MODULE_LICENSE("GPL");
  88 MODULE_ALIAS("iwl4965");
  89
  90 static int iwlagn_ant_coupling;
  91 static bool iwlagn_bt_ch_announce = 1;
  92
  93 void iwl_update_chain_flags(struct iwl_priv *priv)
  94 {
  95         struct iwl_rxon_context *ctx;
  96
  97         if (priv->cfg->ops->hcmd->set_rxon_chain) {
  98                 for_each_context(priv, ctx) {
  99                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 100                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
 101                                 iwlcore_commit_rxon(priv, ctx);
 102                 }
 103         }
 104 }
 105
 106 static void iwl_clear_free_frames(struct iwl_priv *priv)
 107 {
 108         struct list_head *element;
 109
 110         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 111                        priv->frames_count);
 112
 113         while (!list_empty(&priv->free_frames)) {
 114                 element = priv->free_frames.next;
 115                 list_del(element);
 116                 kfree(list_entry(element, struct iwl_frame, list));
 117                 priv->frames_count--;
 118         }
 119
 120         if (priv->frames_count) {
 121                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 122                             priv->frames_count);
 123                 priv->frames_count = 0;
 124         }
 125 }
 126
 127 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 128 {
 129         struct iwl_frame *frame;
 130         struct list_head *element;
 131         if (list_empty(&priv->free_frames)) {
 132                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 133                 if (!frame) {
 134                         IWL_ERR(priv, "Could not allocate frame!\n");
 135                         return NULL;
 136                 }
 137
 138                 priv->frames_count++;
 139                 return frame;
 140         }
 141
 142         element = priv->free_frames.next;
 143         list_del(element);
 144         return list_entry(element, struct iwl_frame, list);
 145 }
 146
 147 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 148 {
 149         memset(frame, 0, sizeof(*frame));
 150         list_add(&frame->list, &priv->free_frames);
 151 }
 152
 153 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 154                                  struct ieee80211_hdr *hdr,
 155                                  int left)
 156 {
 157         lockdep_assert_held(&priv->mutex);
 158
 159         if (!priv->beacon_skb)
 160                 return 0;
 161
 162         if (priv->beacon_skb->len > left)
 163                 return 0;
 164
 165         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
 166
 167         return priv->beacon_skb->len;
 168 }
 169
 170 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 171 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 172                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 173                                u8 *beacon, u32 frame_size)
 174 {
 175         u16 tim_idx;
 176         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 177
 178         /*
 179          * The index is relative to frame start but we start looking at the
 180          * variable-length part of the beacon.
 181          */
 182         tim_idx = mgmt->u.beacon.variable - beacon;
 183
 184         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 185         while ((tim_idx < (frame_size - 2)) &&
 186                         (beacon[tim_idx] != WLAN_EID_TIM))
 187                 tim_idx += beacon[tim_idx+1] + 2;
 188
 189         /* If TIM field was found, set variables */
 190         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 191                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 192                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 193         } else
 194                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 195 }
 196
 197 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 198                                        struct iwl_frame *frame)
 199 {
 200         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 201         u32 frame_size;
 202         u32 rate_flags;
 203         u32 rate;
 204         /*
 205          * We have to set up the TX command, the TX Beacon command, and the
 206          * beacon contents.
 207          */
 208
 209         lockdep_assert_held(&priv->mutex);
 210
 211         if (!priv->beacon_ctx) {
 212                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 213                 return 0;
 214         }
 215
 216         /* Initialize memory */
 217         tx_beacon_cmd = &frame->u.beacon;
 218         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 219
 220         /* Set up TX beacon contents */
 221         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 222                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 223         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 224                 return 0;
 225         if (!frame_size)
 226                 return 0;
 227
 228         /* Set up TX command fields */
 229         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 230         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 231         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 232         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 233                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 234
 235         /* Set up TX beacon command fields */
 236         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 237                            frame_size);
 238
 239         /* Set up packet rate and flags */
 240         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 241         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 242                                               priv->hw_params.valid_tx_ant);
 243         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 244         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 245                 rate_flags |= RATE_MCS_CCK_MSK;
 246         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 247                         rate_flags);
 248
 249         return sizeof(*tx_beacon_cmd) + frame_size;
 250 }
 251
 252 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
 253 {
 254         struct iwl_frame *frame;
 255         unsigned int frame_size;
 256         int rc;
 257
 258         frame = iwl_get_free_frame(priv);
 259         if (!frame) {
 260                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 261                           "command.\n");
 262                 return -ENOMEM;
 263         }
 264
 265         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 266         if (!frame_size) {
 267                 IWL_ERR(priv, "Error configuring the beacon command\n");
 268                 iwl_free_frame(priv, frame);
 269                 return -EINVAL;
 270         }
 271
 272         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 273                               &frame->u.cmd[0]);
 274
 275         iwl_free_frame(priv, frame);
 276
 277         return rc;
 278 }
 279
 280 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 281 {
 282         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 283
 284         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 285         if (sizeof(dma_addr_t) > sizeof(u32))
 286                 addr |=
 287                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 288
 289         return addr;
 290 }
 291
 292 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 293 {
 294         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 295
 296         return le16_to_cpu(tb->hi_n_len) >> 4;
 297 }
 298
 299 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 300                                   dma_addr_t addr, u16 len)
 301 {
 302         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 303         u16 hi_n_len = len << 4;
 304
 305         put_unaligned_le32(addr, &tb->lo);
 306         if (sizeof(dma_addr_t) > sizeof(u32))
 307                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 308
 309         tb->hi_n_len = cpu_to_le16(hi_n_len);
 310
 311         tfd->num_tbs = idx + 1;
 312 }
 313
 314 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 315 {
 316         return tfd->num_tbs & 0x1f;
 317 }
 318
 319 /**
 320  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 321  * @priv - driver private data
 322  * @txq - tx queue
 323  *
 324  * Does NOT advance any TFD circular buffer read/write indexes
 325  * Does NOT free the TFD itself (which is within circular buffer)
 326  */
 327 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 328 {
 329         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 330         struct iwl_tfd *tfd;
 331         struct pci_dev *dev = priv->pci_dev;
 332         int index = txq->q.read_ptr;
 333         int i;
 334         int num_tbs;
 335
 336         tfd = &tfd_tmp[index];
 337
 338         /* Sanity check on number of chunks */
 339         num_tbs = iwl_tfd_get_num_tbs(tfd);
 340
 341         if (num_tbs >= IWL_NUM_OF_TBS) {
 342                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 343                 /* @todo issue fatal error, it is quite serious situation */
 344                 return;
 345         }
 346
 347         /* Unmap tx_cmd */
 348         if (num_tbs)
 349                 pci_unmap_single(dev,
 350                                 dma_unmap_addr(&txq->meta[index], mapping),
 351                                 dma_unmap_len(&txq->meta[index], len),
 352                                 PCI_DMA_BIDIRECTIONAL);
 353
 354         /* Unmap chunks, if any. */
 355         for (i = 1; i < num_tbs; i++)
 356                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 357                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 358
 359         /* free SKB */
 360         if (txq->txb) {
 361                 struct sk_buff *skb;
 362
 363                 skb = txq->txb[txq->q.read_ptr].skb;
 364
 365                 /* can be called from irqs-disabled context */
 366                 if (skb) {
 367                         dev_kfree_skb_any(skb);
 368                         txq->txb[txq->q.read_ptr].skb = NULL;
 369                 }
 370         }
 371 }
 372
 373 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 374                                  struct iwl_tx_queue *txq,
 375                                  dma_addr_t addr, u16 len,
 376                                  u8 reset, u8 pad)
 377 {
 378         struct iwl_queue *q;
 379         struct iwl_tfd *tfd, *tfd_tmp;
 380         u32 num_tbs;
 381
 382         q = &txq->q;
 383         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 384         tfd = &tfd_tmp[q->write_ptr];
 385
 386         if (reset)
 387                 memset(tfd, 0, sizeof(*tfd));
 388
 389         num_tbs = iwl_tfd_get_num_tbs(tfd);
 390
 391         /* Each TFD can point to a maximum 20 Tx buffers */
 392         if (num_tbs >= IWL_NUM_OF_TBS) {
 393                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 394                           IWL_NUM_OF_TBS);
 395                 return -EINVAL;
 396         }
 397
 398         BUG_ON(addr & ~DMA_BIT_MASK(36));
 399         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 400                 IWL_ERR(priv, "Unaligned address = %llx\n",
 401                           (unsigned long long)addr);
 402
 403         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 404
 405         return 0;
 406 }
 407
 408 /*
 409  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 410  * given Tx queue, and enable the DMA channel used for that queue.
 411  *
 412  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 413  * channels supported in hardware.
 414  */
 415 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 416                          struct iwl_tx_queue *txq)
 417 {
 418         int txq_id = txq->q.id;
 419
 420         /* Circular buffer (TFD queue in DRAM) physical base address */
 421         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 422                              txq->q.dma_addr >> 8);
 423
 424         return 0;
 425 }
 426
 427 /******************************************************************************
 428  *
 429  * Generic RX handler implementations
 430  *
 431  ******************************************************************************/
 432 static void iwl_rx_reply_alive(struct iwl_priv *priv,
 433                                 struct iwl_rx_mem_buffer *rxb)
 434 {
 435         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 436         struct iwl_alive_resp *palive;
 437         struct delayed_work *pwork;
 438
 439         palive = &pkt->u.alive_frame;
 440
 441         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
 442                        "0x%01X 0x%01X\n",
 443                        palive->is_valid, palive->ver_type,
 444                        palive->ver_subtype);
 445
 446         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
 447                 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
 448                 memcpy(&priv->card_alive_init,
 449                        &pkt->u.alive_frame,
 450                        sizeof(struct iwl_init_alive_resp));
 451                 pwork = &priv->init_alive_start;
 452         } else {
 453                 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
 454                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
 455                        sizeof(struct iwl_alive_resp));
 456                 pwork = &priv->alive_start;
 457         }
 458
 459         /* We delay the ALIVE response by 5ms to
 460          * give the HW RF Kill time to activate... */
 461         if (palive->is_valid == UCODE_VALID_OK)
 462                 queue_delayed_work(priv->workqueue, pwork,
 463                                    msecs_to_jiffies(5));
 464         else
 465                 IWL_WARN(priv, "uCode did not respond OK.\n");
 466 }
 467
 468 static void iwl_bg_beacon_update(struct work_struct *work)
 469 {
 470         struct iwl_priv *priv =
 471                 container_of(work, struct iwl_priv, beacon_update);
 472         struct sk_buff *beacon;
 473
 474         mutex_lock(&priv->mutex);
 475         if (!priv->beacon_ctx) {
 476                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 477                 goto out;
 478         }
 479
 480         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 481                 /*
 482                  * The ucode will send beacon notifications even in
 483                  * IBSS mode, but we don't want to process them. But
 484                  * we need to defer the type check to here due to
 485                  * requiring locking around the beacon_ctx access.
 486                  */
 487                 goto out;
 488         }
 489
 490         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 491         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 492         if (!beacon) {
 493                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
 494                 goto out;
 495         }
 496
 497         /* new beacon skb is allocated every time; dispose previous.*/
 498         dev_kfree_skb(priv->beacon_skb);
 499
 500         priv->beacon_skb = beacon;
 501
 502         iwlagn_send_beacon_cmd(priv);
 503  out:
 504         mutex_unlock(&priv->mutex);
 505 }
 506
 507 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 508 {
 509         struct iwl_priv *priv =
 510                 container_of(work, struct iwl_priv, bt_runtime_config);
 511
 512         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 513                 return;
 514
 515         /* dont send host command if rf-kill is on */
 516         if (!iwl_is_ready_rf(priv))
 517                 return;
 518         priv->cfg->ops->hcmd->send_bt_config(priv);
 519 }
 520
 521 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 522 {
 523         struct iwl_priv *priv =
 524                 container_of(work, struct iwl_priv, bt_full_concurrency);
 525         struct iwl_rxon_context *ctx;
 526
 527         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 528                 return;
 529
 530         /* dont send host command if rf-kill is on */
 531         if (!iwl_is_ready_rf(priv))
 532                 return;
 533
 534         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 535                        priv->bt_full_concurrent ?
 536                        "full concurrency" : "3-wire");
 537
 538         /*
 539          * LQ & RXON updated cmds must be sent before BT Config cmd
 540          * to avoid 3-wire collisions
 541          */
 542         mutex_lock(&priv->mutex);
 543         for_each_context(priv, ctx) {
 544                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 545                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 546                 iwlcore_commit_rxon(priv, ctx);
 547         }
 548         mutex_unlock(&priv->mutex);
 549
 550         priv->cfg->ops->hcmd->send_bt_config(priv);
 551 }
 552
 553 /**
 554  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 555  *
 556  * This callback is provided in order to send a statistics request.
 557  *
 558  * This timer function is continually reset to execute within
 559  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 560  * was received.  We need to ensure we receive the statistics in order
 561  * to update the temperature used for calibrating the TXPOWER.
 562  */
 563 static void iwl_bg_statistics_periodic(unsigned long data)
 564 {
 565         struct iwl_priv *priv = (struct iwl_priv *)data;
 566
 567         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 568                 return;
 569
 570         /* dont send host command if rf-kill is on */
 571         if (!iwl_is_ready_rf(priv))
 572                 return;
 573
 574         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 575 }
 576
 577
 578 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 579                                         u32 start_idx, u32 num_events,
 580                                         u32 mode)
 581 {
 582         u32 i;
 583         u32 ptr;        /* SRAM byte address of log data */
 584         u32 ev, time, data; /* event log data */
 585         unsigned long reg_flags;
 586
 587         if (mode == 0)
 588                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 589         else
 590                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 591
 592         /* Make sure device is powered up for SRAM reads */
 593         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 594         if (iwl_grab_nic_access(priv)) {
 595                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 596                 return;
 597         }
 598
 599         /* Set starting address; reads will auto-increment */
 600         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 601         rmb();
 602
 603         /*
 604          * "time" is actually "data" for mode 0 (no timestamp).
 605          * place event id # at far right for easier visual parsing.
 606          */
 607         for (i = 0; i < num_events; i++) {
 608                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 609                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 610                 if (mode == 0) {
 611                         trace_iwlwifi_dev_ucode_cont_event(priv,
 612                                                         0, time, ev);
 613                 } else {
 614                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 615                         trace_iwlwifi_dev_ucode_cont_event(priv,
 616                                                 time, data, ev);
 617                 }
 618         }
 619         /* Allow device to power down */
 620         iwl_release_nic_access(priv);
 621         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 622 }
 623
 624 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 625 {
 626         u32 capacity;   /* event log capacity in # entries */
 627         u32 base;       /* SRAM byte address of event log header */
 628         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 629         u32 num_wraps;  /* # times uCode wrapped to top of log */
 630         u32 next_entry; /* index of next entry to be written by uCode */
 631
 632         if (priv->ucode_type == UCODE_INIT)
 633                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 634         else
 635                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 636         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 637                 capacity = iwl_read_targ_mem(priv, base);
 638                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 639                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 640                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 641         } else
 642                 return;
 643
 644         if (num_wraps == priv->event_log.num_wraps) {
 645                 iwl_print_cont_event_trace(priv,
 646                                        base, priv->event_log.next_entry,
 647                                        next_entry - priv->event_log.next_entry,
 648                                        mode);
 649                 priv->event_log.non_wraps_count++;
 650         } else {
 651                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 652                         priv->event_log.wraps_more_count++;
 653                 else
 654                         priv->event_log.wraps_once_count++;
 655                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 656                                 num_wraps - priv->event_log.num_wraps,
 657                                 next_entry, priv->event_log.next_entry);
 658                 if (next_entry < priv->event_log.next_entry) {
 659                         iwl_print_cont_event_trace(priv, base,
 660                                priv->event_log.next_entry,
 661                                capacity - priv->event_log.next_entry,
 662                                mode);
 663
 664                         iwl_print_cont_event_trace(priv, base, 0,
 665                                 next_entry, mode);
 666                 } else {
 667                         iwl_print_cont_event_trace(priv, base,
 668                                next_entry, capacity - next_entry,
 669                                mode);
 670
 671                         iwl_print_cont_event_trace(priv, base, 0,
 672                                 next_entry, mode);
 673                 }
 674         }
 675         priv->event_log.num_wraps = num_wraps;
 676         priv->event_log.next_entry = next_entry;
 677 }
 678
 679 /**
 680  * iwl_bg_ucode_trace - Timer callback to log ucode event
 681  *
 682  * The timer is continually set to execute every
 683  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 684  * this function is to perform continuous uCode event logging operation
 685  * if enabled
 686  */
 687 static void iwl_bg_ucode_trace(unsigned long data)
 688 {
 689         struct iwl_priv *priv = (struct iwl_priv *)data;
 690
 691         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 692                 return;
 693
 694         if (priv->event_log.ucode_trace) {
 695                 iwl_continuous_event_trace(priv);
 696                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 697                 mod_timer(&priv->ucode_trace,
 698                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 699         }
 700 }
 701
 702 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
 703                                 struct iwl_rx_mem_buffer *rxb)
 704 {
 705         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 706         struct iwl4965_beacon_notif *beacon =
 707                 (struct iwl4965_beacon_notif *)pkt->u.raw;
 708 #ifdef CONFIG_IWLWIFI_DEBUG
 709         u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
 710
 711         IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
 712                 "tsf %d %d rate %d\n",
 713                 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
 714                 beacon->beacon_notify_hdr.failure_frame,
 715                 le32_to_cpu(beacon->ibss_mgr_status),
 716                 le32_to_cpu(beacon->high_tsf),
 717                 le32_to_cpu(beacon->low_tsf), rate);
 718 #endif
 719
 720         priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
 721
 722         if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 723                 queue_work(priv->workqueue, &priv->beacon_update);
 724 }
 725
 726 /* Handle notification from uCode that card's power state is changing
 727  * due to software, hardware, or critical temperature RFKILL */
 728 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
 729                                     struct iwl_rx_mem_buffer *rxb)
 730 {
 731         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 732         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
 733         unsigned long status = priv->status;
 734
 735         IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
 736                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
 737                           (flags & SW_CARD_DISABLED) ? "Kill" : "On",
 738                           (flags & CT_CARD_DISABLED) ?
 739                           "Reached" : "Not reached");
 740
 741         if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
 742                      CT_CARD_DISABLED)) {
 743
 744                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
 745                             CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 746
 747                 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 748                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 749
 750                 if (!(flags & RXON_CARD_DISABLED)) {
 751                         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 752                                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 753                         iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 754                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 755                 }
 756                 if (flags & CT_CARD_DISABLED)
 757                         iwl_tt_enter_ct_kill(priv);
 758         }
 759         if (!(flags & CT_CARD_DISABLED))
 760                 iwl_tt_exit_ct_kill(priv);
 761
 762         if (flags & HW_CARD_DISABLED)
 763                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 764         else
 765                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 766
 767
 768         if (!(flags & RXON_CARD_DISABLED))
 769                 iwl_scan_cancel(priv);
 770
 771         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
 772              test_bit(STATUS_RF_KILL_HW, &priv->status)))
 773                 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
 774                         test_bit(STATUS_RF_KILL_HW, &priv->status));
 775         else
 776                 wake_up_interruptible(&priv->wait_command_queue);
 777 }
 778
 779 static void iwl_bg_tx_flush(struct work_struct *work)
 780 {
 781         struct iwl_priv *priv =
 782                 container_of(work, struct iwl_priv, tx_flush);
 783
 784         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 785                 return;
 786
 787         /* do nothing if rf-kill is on */
 788         if (!iwl_is_ready_rf(priv))
 789                 return;
 790
 791         if (priv->cfg->ops->lib->txfifo_flush) {
 792                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 793                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 794         }
 795 }
 796
 797 /**
 798  * iwl_setup_rx_handlers - Initialize Rx handler callbacks
 799  *
 800  * Setup the RX handlers for each of the reply types sent from the uCode
 801  * to the host.
 802  *
 803  * This function chains into the hardware specific files for them to setup
 804  * any hardware specific handlers as well.
 805  */
 806 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
 807 {
 808         priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
 809         priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
 810         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
 811         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
 812                         iwl_rx_spectrum_measure_notif;
 813         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
 814         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
 815             iwl_rx_pm_debug_statistics_notif;
 816         priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
 817
 818         /*
 819          * The same handler is used for both the REPLY to a discrete
 820          * statistics request from the host as well as for the periodic
 821          * statistics notifications (after received beacons) from the uCode.
 822          */
 823         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
 824         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
 825
 826         iwl_setup_rx_scan_handlers(priv);
 827
 828         /* status change handler */
 829         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
 830
 831         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
 832             iwl_rx_missed_beacon_notif;
 833         /* Rx handlers */
 834         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
 835         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
 836         /* block ack */
 837         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
 838         /* Set up hardware specific Rx handlers */
 839         priv->cfg->ops->lib->rx_handler_setup(priv);
 840 }
 841
 842 /**
 843  * iwl_rx_handle - Main entry function for receiving responses from uCode
 844  *
 845  * Uses the priv->rx_handlers callback function array to invoke
 846  * the appropriate handlers, including command responses,
 847  * frame-received notifications, and other notifications.
 848  */
 849 void iwl_rx_handle(struct iwl_priv *priv)
 850 {
 851         struct iwl_rx_mem_buffer *rxb;
 852         struct iwl_rx_packet *pkt;
 853         struct iwl_rx_queue *rxq = &priv->rxq;
 854         u32 r, i;
 855         int reclaim;
 856         unsigned long flags;
 857         u8 fill_rx = 0;
 858         u32 count = 8;
 859         int total_empty;
 860
 861         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 862          * buffer that the driver may process (last buffer filled by ucode). */
 863         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 864         i = rxq->read;
 865
 866         /* Rx interrupt, but nothing sent from uCode */
 867         if (i == r)
 868                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
 869
 870         /* calculate total frames need to be restock after handling RX */
 871         total_empty = r - rxq->write_actual;
 872         if (total_empty < 0)
 873                 total_empty += RX_QUEUE_SIZE;
 874
 875         if (total_empty > (RX_QUEUE_SIZE / 2))
 876                 fill_rx = 1;
 877
 878         while (i != r) {
 879                 int len;
 880
 881                 rxb = rxq->queue[i];
 882
 883                 /* If an RXB doesn't have a Rx queue slot associated with it,
 884                  * then a bug has been introduced in the queue refilling
 885                  * routines -- catch it here */
 886                 BUG_ON(rxb == NULL);
 887
 888                 rxq->queue[i] = NULL;
 889
 890                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
 891                                PAGE_SIZE << priv->hw_params.rx_page_order,
 892                                PCI_DMA_FROMDEVICE);
 893                 pkt = rxb_addr(rxb);
 894
 895                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 896                 len += sizeof(u32); /* account for status word */
 897                 trace_iwlwifi_dev_rx(priv, pkt, len);
 898
 899                 /* Reclaim a command buffer only if this packet is a response
 900                  *   to a (driver-originated) command.
 901                  * If the packet (e.g. Rx frame) originated from uCode,
 902                  *   there is no command buffer to reclaim.
 903                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 904                  *   but apparently a few don't get set; catch them here. */
 905                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 906                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 907                         (pkt->hdr.cmd != REPLY_RX) &&
 908                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 909                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 910                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 911                         (pkt->hdr.cmd != REPLY_TX);
 912
 913                 /* Based on type of command response or notification,
 914                  *   handle those that need handling via function in
 915                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
 916                 if (priv->rx_handlers[pkt->hdr.cmd]) {
 917                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
 918                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 919                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
 920                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
 921                 } else {
 922                         /* No handling needed */
 923                         IWL_DEBUG_RX(priv,
 924                                 "r %d i %d No handler needed for %s, 0x%02x\n",
 925                                 r, i, get_cmd_string(pkt->hdr.cmd),
 926                                 pkt->hdr.cmd);
 927                 }
 928
 929                 /*
 930                  * XXX: After here, we should always check rxb->page
 931                  * against NULL before touching it or its virtual
 932                  * memory (pkt). Because some rx_handler might have
 933                  * already taken or freed the pages.
 934                  */
 935
 936                 if (reclaim) {
 937                         /* Invoke any callbacks, transfer the buffer to caller,
 938                          * and fire off the (possibly) blocking iwl_send_cmd()
 939                          * as we reclaim the driver command queue */
 940                         if (rxb->page)
 941                                 iwl_tx_cmd_complete(priv, rxb);
 942                         else
 943                                 IWL_WARN(priv, "Claim null rxb?\n");
 944                 }
 945
 946                 /* Reuse the page if possible. For notification packets and
 947                  * SKBs that fail to Rx correctly, add them back into the
 948                  * rx_free list for reuse later. */
 949                 spin_lock_irqsave(&rxq->lock, flags);
 950                 if (rxb->page != NULL) {
 951                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
 952                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
 953                                 PCI_DMA_FROMDEVICE);
 954                         list_add_tail(&rxb->list, &rxq->rx_free);
 955                         rxq->free_count++;
 956                 } else
 957                         list_add_tail(&rxb->list, &rxq->rx_used);
 958
 959                 spin_unlock_irqrestore(&rxq->lock, flags);
 960
 961                 i = (i + 1) & RX_QUEUE_MASK;
 962                 /* If there are a lot of unused frames,
 963                  * restock the Rx queue so ucode wont assert. */
 964                 if (fill_rx) {
 965                         count++;
 966                         if (count >= 8) {
 967                                 rxq->read = i;
 968                                 iwlagn_rx_replenish_now(priv);
 969                                 count = 0;
 970                         }
 971                 }
 972         }
 973
 974         /* Backtrack one entry */
 975         rxq->read = i;
 976         if (fill_rx)
 977                 iwlagn_rx_replenish_now(priv);
 978         else
 979                 iwlagn_rx_queue_restock(priv);
 980 }
 981
 982 /* call this function to flush any scheduled tasklet */
 983 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
 984 {
 985         /* wait to make sure we flush pending tasklet*/
 986         synchronize_irq(priv->pci_dev->irq);
 987         tasklet_kill(&priv->irq_tasklet);
 988 }
 989
 990 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
 991 {
 992         u32 inta, handled = 0;
 993         u32 inta_fh;
 994         unsigned long flags;
 995         u32 i;
 996 #ifdef CONFIG_IWLWIFI_DEBUG
 997         u32 inta_mask;
 998 #endif
 999
1000         spin_lock_irqsave(&priv->lock, flags);
1001
1002         /* Ack/clear/reset pending uCode interrupts.
1003          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1004          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1005         inta = iwl_read32(priv, CSR_INT);
1006         iwl_write32(priv, CSR_INT, inta);
1007
1008         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1009          * Any new interrupts that happen after this, either while we're
1010          * in this tasklet, or later, will show up in next ISR/tasklet. */
1011         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1012         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1013
1014 #ifdef CONFIG_IWLWIFI_DEBUG
1015         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1016                 /* just for debug */
1017                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1018                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1019                               inta, inta_mask, inta_fh);
1020         }
1021 #endif
1022
1023         spin_unlock_irqrestore(&priv->lock, flags);
1024
1025         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1026          * atomic, make sure that inta covers all the interrupts that
1027          * we've discovered, even if FH interrupt came in just after
1028          * reading CSR_INT. */
1029         if (inta_fh & CSR49_FH_INT_RX_MASK)
1030                 inta |= CSR_INT_BIT_FH_RX;
1031         if (inta_fh & CSR49_FH_INT_TX_MASK)
1032                 inta |= CSR_INT_BIT_FH_TX;
1033
1034         /* Now service all interrupt bits discovered above. */
1035         if (inta & CSR_INT_BIT_HW_ERR) {
1036                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1037
1038                 /* Tell the device to stop sending interrupts */
1039                 iwl_disable_interrupts(priv);
1040
1041                 priv->isr_stats.hw++;
1042                 iwl_irq_handle_error(priv);
1043
1044                 handled |= CSR_INT_BIT_HW_ERR;
1045
1046                 return;
1047         }
1048
1049 #ifdef CONFIG_IWLWIFI_DEBUG
1050         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1051                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1052                 if (inta & CSR_INT_BIT_SCD) {
1053                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1054                                       "the frame/frames.\n");
1055                         priv->isr_stats.sch++;
1056                 }
1057
1058                 /* Alive notification via Rx interrupt will do the real work */
1059                 if (inta & CSR_INT_BIT_ALIVE) {
1060                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1061                         priv->isr_stats.alive++;
1062                 }
1063         }
1064 #endif
1065         /* Safely ignore these bits for debug checks below */
1066         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1067
1068         /* HW RF KILL switch toggled */
1069         if (inta & CSR_INT_BIT_RF_KILL) {
1070                 int hw_rf_kill = 0;
1071                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1072                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1073                         hw_rf_kill = 1;
1074
1075                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1076                                 hw_rf_kill ? "disable radio" : "enable radio");
1077
1078                 priv->isr_stats.rfkill++;
1079
1080                 /* driver only loads ucode once setting the interface up.
1081                  * the driver allows loading the ucode even if the radio
1082                  * is killed. Hence update the killswitch state here. The
1083                  * rfkill handler will care about restarting if needed.
1084                  */
1085                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1086                         if (hw_rf_kill)
1087                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1088                         else
1089                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1090                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1091                 }
1092
1093                 handled |= CSR_INT_BIT_RF_KILL;
1094         }
1095
1096         /* Chip got too hot and stopped itself */
1097         if (inta & CSR_INT_BIT_CT_KILL) {
1098                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1099                 priv->isr_stats.ctkill++;
1100                 handled |= CSR_INT_BIT_CT_KILL;
1101         }
1102
1103         /* Error detected by uCode */
1104         if (inta & CSR_INT_BIT_SW_ERR) {
1105                 IWL_ERR(priv, "Microcode SW error detected. "
1106                         " Restarting 0x%X.\n", inta);
1107                 priv->isr_stats.sw++;
1108                 iwl_irq_handle_error(priv);
1109                 handled |= CSR_INT_BIT_SW_ERR;
1110         }
1111
1112         /*
1113          * uCode wakes up after power-down sleep.
1114          * Tell device about any new tx or host commands enqueued,
1115          * and about any Rx buffers made available while asleep.
1116          */
1117         if (inta & CSR_INT_BIT_WAKEUP) {
1118                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1119                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1120                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1121                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1122                 priv->isr_stats.wakeup++;
1123                 handled |= CSR_INT_BIT_WAKEUP;
1124         }
1125
1126         /* All uCode command responses, including Tx command responses,
1127          * Rx "responses" (frame-received notification), and other
1128          * notifications from uCode come through here*/
1129         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1130                 iwl_rx_handle(priv);
1131                 priv->isr_stats.rx++;
1132                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1133         }
1134
1135         /* This "Tx" DMA channel is used only for loading uCode */
1136         if (inta & CSR_INT_BIT_FH_TX) {
1137                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1138                 priv->isr_stats.tx++;
1139                 handled |= CSR_INT_BIT_FH_TX;
1140                 /* Wake up uCode load routine, now that load is complete */
1141                 priv->ucode_write_complete = 1;
1142                 wake_up_interruptible(&priv->wait_command_queue);
1143         }
1144
1145         if (inta & ~handled) {
1146                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1147                 priv->isr_stats.unhandled++;
1148         }
1149
1150         if (inta & ~(priv->inta_mask)) {
1151                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1152                          inta & ~priv->inta_mask);
1153                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1154         }
1155
1156         /* Re-enable all interrupts */
1157         /* only Re-enable if diabled by irq */
1158         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1159                 iwl_enable_interrupts(priv);
1160
1161 #ifdef CONFIG_IWLWIFI_DEBUG
1162         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1163                 inta = iwl_read32(priv, CSR_INT);
1164                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1165                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1166                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1167                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1168         }
1169 #endif
1170 }
1171
1172 /* tasklet for iwlagn interrupt */
1173 static void iwl_irq_tasklet(struct iwl_priv *priv)
1174 {
1175         u32 inta = 0;
1176         u32 handled = 0;
1177         unsigned long flags;
1178         u32 i;
1179 #ifdef CONFIG_IWLWIFI_DEBUG
1180         u32 inta_mask;
1181 #endif
1182
1183         spin_lock_irqsave(&priv->lock, flags);
1184
1185         /* Ack/clear/reset pending uCode interrupts.
1186          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1187          */
1188         /* There is a hardware bug in the interrupt mask function that some
1189          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1190          * they are disabled in the CSR_INT_MASK register. Furthermore the
1191          * ICT interrupt handling mechanism has another bug that might cause
1192          * these unmasked interrupts fail to be detected. We workaround the
1193          * hardware bugs here by ACKing all the possible interrupts so that
1194          * interrupt coalescing can still be achieved.
1195          */
1196         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1197
1198         inta = priv->_agn.inta;
1199
1200 #ifdef CONFIG_IWLWIFI_DEBUG
1201         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1202                 /* just for debug */
1203                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1204                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1205                                 inta, inta_mask);
1206         }
1207 #endif
1208
1209         spin_unlock_irqrestore(&priv->lock, flags);
1210
1211         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1212         priv->_agn.inta = 0;
1213
1214         /* Now service all interrupt bits discovered above. */
1215         if (inta & CSR_INT_BIT_HW_ERR) {
1216                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1217
1218                 /* Tell the device to stop sending interrupts */
1219                 iwl_disable_interrupts(priv);
1220
1221                 priv->isr_stats.hw++;
1222                 iwl_irq_handle_error(priv);
1223
1224                 handled |= CSR_INT_BIT_HW_ERR;
1225
1226                 return;
1227         }
1228
1229 #ifdef CONFIG_IWLWIFI_DEBUG
1230         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1231                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1232                 if (inta & CSR_INT_BIT_SCD) {
1233                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1234                                       "the frame/frames.\n");
1235                         priv->isr_stats.sch++;
1236                 }
1237
1238                 /* Alive notification via Rx interrupt will do the real work */
1239                 if (inta & CSR_INT_BIT_ALIVE) {
1240                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1241                         priv->isr_stats.alive++;
1242                 }
1243         }
1244 #endif
1245         /* Safely ignore these bits for debug checks below */
1246         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1247
1248         /* HW RF KILL switch toggled */
1249         if (inta & CSR_INT_BIT_RF_KILL) {
1250                 int hw_rf_kill = 0;
1251                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1252                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1253                         hw_rf_kill = 1;
1254
1255                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1256                                 hw_rf_kill ? "disable radio" : "enable radio");
1257
1258                 priv->isr_stats.rfkill++;
1259
1260                 /* driver only loads ucode once setting the interface up.
1261                  * the driver allows loading the ucode even if the radio
1262                  * is killed. Hence update the killswitch state here. The
1263                  * rfkill handler will care about restarting if needed.
1264                  */
1265                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1266                         if (hw_rf_kill)
1267                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1268                         else
1269                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1270                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1271                 }
1272
1273                 handled |= CSR_INT_BIT_RF_KILL;
1274         }
1275
1276         /* Chip got too hot and stopped itself */
1277         if (inta & CSR_INT_BIT_CT_KILL) {
1278                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1279                 priv->isr_stats.ctkill++;
1280                 handled |= CSR_INT_BIT_CT_KILL;
1281         }
1282
1283         /* Error detected by uCode */
1284         if (inta & CSR_INT_BIT_SW_ERR) {
1285                 IWL_ERR(priv, "Microcode SW error detected. "
1286                         " Restarting 0x%X.\n", inta);
1287                 priv->isr_stats.sw++;
1288                 iwl_irq_handle_error(priv);
1289                 handled |= CSR_INT_BIT_SW_ERR;
1290         }
1291
1292         /* uCode wakes up after power-down sleep */
1293         if (inta & CSR_INT_BIT_WAKEUP) {
1294                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1295                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1296                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1297                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1298
1299                 priv->isr_stats.wakeup++;
1300
1301                 handled |= CSR_INT_BIT_WAKEUP;
1302         }
1303
1304         /* All uCode command responses, including Tx command responses,
1305          * Rx "responses" (frame-received notification), and other
1306          * notifications from uCode come through here*/
1307         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1308                         CSR_INT_BIT_RX_PERIODIC)) {
1309                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1310                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1311                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1312                         iwl_write32(priv, CSR_FH_INT_STATUS,
1313                                         CSR49_FH_INT_RX_MASK);
1314                 }
1315                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1316                         handled |= CSR_INT_BIT_RX_PERIODIC;
1317                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1318                 }
1319                 /* Sending RX interrupt require many steps to be done in the
1320                  * the device:
1321                  * 1- write interrupt to current index in ICT table.
1322                  * 2- dma RX frame.
1323                  * 3- update RX shared data to indicate last write index.
1324                  * 4- send interrupt.
1325                  * This could lead to RX race, driver could receive RX interrupt
1326                  * but the shared data changes does not reflect this;
1327                  * periodic interrupt will detect any dangling Rx activity.
1328                  */
1329
1330                 /* Disable periodic interrupt; we use it as just a one-shot. */
1331                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1332                             CSR_INT_PERIODIC_DIS);
1333                 iwl_rx_handle(priv);
1334
1335                 /*
1336                  * Enable periodic interrupt in 8 msec only if we received
1337                  * real RX interrupt (instead of just periodic int), to catch
1338                  * any dangling Rx interrupt.  If it was just the periodic
1339                  * interrupt, there was no dangling Rx activity, and no need
1340                  * to extend the periodic interrupt; one-shot is enough.
1341                  */
1342                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1343                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1344                                     CSR_INT_PERIODIC_ENA);
1345
1346                 priv->isr_stats.rx++;
1347         }
1348
1349         /* This "Tx" DMA channel is used only for loading uCode */
1350         if (inta & CSR_INT_BIT_FH_TX) {
1351                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1352                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1353                 priv->isr_stats.tx++;
1354                 handled |= CSR_INT_BIT_FH_TX;
1355                 /* Wake up uCode load routine, now that load is complete */
1356                 priv->ucode_write_complete = 1;
1357                 wake_up_interruptible(&priv->wait_command_queue);
1358         }
1359
1360         if (inta & ~handled) {
1361                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1362                 priv->isr_stats.unhandled++;
1363         }
1364
1365         if (inta & ~(priv->inta_mask)) {
1366                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1367                          inta & ~priv->inta_mask);
1368         }
1369
1370         /* Re-enable all interrupts */
1371         /* only Re-enable if diabled by irq */
1372         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1373                 iwl_enable_interrupts(priv);
1374 }
1375
1376 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1377 #define ACK_CNT_RATIO (50)
1378 #define BA_TIMEOUT_CNT (5)
1379 #define BA_TIMEOUT_MAX (16)
1380
1381 /**
1382  * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1383  *
1384  * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1385  * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1386  * operation state.
1387  */
1388 bool iwl_good_ack_health(struct iwl_priv *priv,
1389                                 struct iwl_rx_packet *pkt)
1390 {
1391         bool rc = true;
1392         int actual_ack_cnt_delta, expected_ack_cnt_delta;
1393         int ba_timeout_delta;
1394
1395         actual_ack_cnt_delta =
1396                 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1397                 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1398         expected_ack_cnt_delta =
1399                 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1400                 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1401         ba_timeout_delta =
1402                 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1403                 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1404         if ((priv->_agn.agg_tids_count > 0) &&
1405             (expected_ack_cnt_delta > 0) &&
1406             (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1407                 < ACK_CNT_RATIO) &&
1408             (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1409                 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1410                                 " expected_ack_cnt = %d\n",
1411                                 actual_ack_cnt_delta, expected_ack_cnt_delta);
1412
1413 #ifdef CONFIG_IWLWIFI_DEBUGFS
1414                 /*
1415                  * This is ifdef'ed on DEBUGFS because otherwise the
1416                  * statistics aren't available. If DEBUGFS is set but
1417                  * DEBUG is not, these will just compile out.
1418                  */
1419                 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1420                                 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1421                 IWL_DEBUG_RADIO(priv,
1422                                 "ack_or_ba_timeout_collision delta = %d\n",
1423                                 priv->_agn.delta_statistics.tx.
1424                                 ack_or_ba_timeout_collision);
1425 #endif
1426                 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1427                                 ba_timeout_delta);
1428                 if (!actual_ack_cnt_delta &&
1429                     (ba_timeout_delta >= BA_TIMEOUT_MAX))
1430                         rc = false;
1431         }
1432         return rc;
1433 }
1434
1435
1436 /*****************************************************************************
1437  *
1438  * sysfs attributes
1439  *
1440  *****************************************************************************/
1441
1442 #ifdef CONFIG_IWLWIFI_DEBUG
1443
1444 /*
1445  * The following adds a new attribute to the sysfs representation
1446  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1447  * used for controlling the debug level.
1448  *
1449  * See the level definitions in iwl for details.
1450  *
1451  * The debug_level being managed using sysfs below is a per device debug
1452  * level that is used instead of the global debug level if it (the per
1453  * device debug level) is set.
1454  */
1455 static ssize_t show_debug_level(struct device *d,
1456                                 struct device_attribute *attr, char *buf)
1457 {
1458         struct iwl_priv *priv = dev_get_drvdata(d);
1459         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1460 }
1461 static ssize_t store_debug_level(struct device *d,
1462                                 struct device_attribute *attr,
1463                                  const char *buf, size_t count)
1464 {
1465         struct iwl_priv *priv = dev_get_drvdata(d);
1466         unsigned long val;
1467         int ret;
1468
1469         ret = strict_strtoul(buf, 0, &val);
1470         if (ret)
1471                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1472         else {
1473                 priv->debug_level = val;
1474                 if (iwl_alloc_traffic_mem(priv))
1475                         IWL_ERR(priv,
1476                                 "Not enough memory to generate traffic log\n");
1477         }
1478         return strnlen(buf, count);
1479 }
1480
1481 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1482                         show_debug_level, store_debug_level);
1483
1484
1485 #endif /* CONFIG_IWLWIFI_DEBUG */
1486
1487
1488 static ssize_t show_temperature(struct device *d,
1489                                 struct device_attribute *attr, char *buf)
1490 {
1491         struct iwl_priv *priv = dev_get_drvdata(d);
1492
1493         if (!iwl_is_alive(priv))
1494                 return -EAGAIN;
1495
1496         return sprintf(buf, "%d\n", priv->temperature);
1497 }
1498
1499 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1500
1501 static ssize_t show_tx_power(struct device *d,
1502                              struct device_attribute *attr, char *buf)
1503 {
1504         struct iwl_priv *priv = dev_get_drvdata(d);
1505
1506         if (!iwl_is_ready_rf(priv))
1507                 return sprintf(buf, "off\n");
1508         else
1509                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1510 }
1511
1512 static ssize_t store_tx_power(struct device *d,
1513                               struct device_attribute *attr,
1514                               const char *buf, size_t count)
1515 {
1516         struct iwl_priv *priv = dev_get_drvdata(d);
1517         unsigned long val;
1518         int ret;
1519
1520         ret = strict_strtoul(buf, 10, &val);
1521         if (ret)
1522                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1523         else {
1524                 ret = iwl_set_tx_power(priv, val, false);
1525                 if (ret)
1526                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1527                                 ret);
1528                 else
1529                         ret = count;
1530         }
1531         return ret;
1532 }
1533
1534 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1535
1536 static struct attribute *iwl_sysfs_entries[] = {
1537         &dev_attr_temperature.attr,
1538         &dev_attr_tx_power.attr,
1539 #ifdef CONFIG_IWLWIFI_DEBUG
1540         &dev_attr_debug_level.attr,
1541 #endif
1542         NULL
1543 };
1544
1545 static struct attribute_group iwl_attribute_group = {
1546         .name = NULL,           /* put in device directory */
1547         .attrs = iwl_sysfs_entries,
1548 };
1549
1550 /******************************************************************************
1551  *
1552  * uCode download functions
1553  *
1554  ******************************************************************************/
1555
1556 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1557 {
1558         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1559         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1560         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1561         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1562         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1563         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1564 }
1565
1566 static void iwl_nic_start(struct iwl_priv *priv)
1567 {
1568         /* Remove all resets to allow NIC to operate */
1569         iwl_write32(priv, CSR_RESET, 0);
1570 }
1571
1572 struct iwlagn_ucode_capabilities {
1573         u32 max_probe_length;
1574         u32 standard_phy_calibration_size;
1575         bool pan;
1576 };
1577
1578 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1579 static int iwl_mac_setup_register(struct iwl_priv *priv,
1580                                   struct iwlagn_ucode_capabilities *capa);
1581
1582 #define UCODE_EXPERIMENTAL_INDEX        100
1583 #define UCODE_EXPERIMENTAL_TAG          "exp"
1584
1585 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1586 {
1587         const char *name_pre = priv->cfg->fw_name_pre;
1588         char tag[8];
1589
1590         if (first) {
1591 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1592                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1593                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1594         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1595 #endif
1596                 priv->fw_index = priv->cfg->ucode_api_max;
1597                 sprintf(tag, "%d", priv->fw_index);
1598         } else {
1599                 priv->fw_index--;
1600                 sprintf(tag, "%d", priv->fw_index);
1601         }
1602
1603         if (priv->fw_index < priv->cfg->ucode_api_min) {
1604                 IWL_ERR(priv, "no suitable firmware found!\n");
1605                 return -ENOENT;
1606         }
1607
1608         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1609
1610         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1611                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1612                                 ? "EXPERIMENTAL " : "",
1613                        priv->firmware_name);
1614
1615         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1616                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1617                                        iwl_ucode_callback);
1618 }
1619
1620 struct iwlagn_firmware_pieces {
1621         const void *inst, *data, *init, *init_data, *boot;
1622         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1623
1624         u32 build;
1625
1626         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1627         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1628 };
1629
1630 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1631                                        const struct firmware *ucode_raw,
1632                                        struct iwlagn_firmware_pieces *pieces)
1633 {
1634         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1635         u32 api_ver, hdr_size;
1636         const u8 *src;
1637
1638         priv->ucode_ver = le32_to_cpu(ucode->ver);
1639         api_ver = IWL_UCODE_API(priv->ucode_ver);
1640
1641         switch (api_ver) {
1642         default:
1643                 /*
1644                  * 4965 doesn't revision the firmware file format
1645                  * along with the API version, it always uses v1
1646                  * file format.
1647                  */
1648                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1649                                 CSR_HW_REV_TYPE_4965) {
1650                         hdr_size = 28;
1651                         if (ucode_raw->size < hdr_size) {
1652                                 IWL_ERR(priv, "File size too small!\n");
1653                                 return -EINVAL;
1654                         }
1655                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1656                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1657                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1658                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1659                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1660                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1661                         src = ucode->u.v2.data;
1662                         break;
1663                 }
1664                 /* fall through for 4965 */
1665         case 0:
1666         case 1:
1667         case 2:
1668                 hdr_size = 24;
1669                 if (ucode_raw->size < hdr_size) {
1670                         IWL_ERR(priv, "File size too small!\n");
1671                         return -EINVAL;
1672                 }
1673                 pieces->build = 0;
1674                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1675                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1676                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1677                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1678                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1679                 src = ucode->u.v1.data;
1680                 break;
1681         }
1682
1683         /* Verify size of file vs. image size info in file's header */
1684         if (ucode_raw->size != hdr_size + pieces->inst_size +
1685                                 pieces->data_size + pieces->init_size +
1686                                 pieces->init_data_size + pieces->boot_size) {
1687
1688                 IWL_ERR(priv,
1689                         "uCode file size %d does not match expected size\n",
1690                         (int)ucode_raw->size);
1691                 return -EINVAL;
1692         }
1693
1694         pieces->inst = src;
1695         src += pieces->inst_size;
1696         pieces->data = src;
1697         src += pieces->data_size;
1698         pieces->init = src;
1699         src += pieces->init_size;
1700         pieces->init_data = src;
1701         src += pieces->init_data_size;
1702         pieces->boot = src;
1703         src += pieces->boot_size;
1704
1705         return 0;
1706 }
1707
1708 static int iwlagn_wanted_ucode_alternative = 1;
1709
1710 static int iwlagn_load_firmware(struct iwl_priv *priv,
1711                                 const struct firmware *ucode_raw,
1712                                 struct iwlagn_firmware_pieces *pieces,
1713                                 struct iwlagn_ucode_capabilities *capa)
1714 {
1715         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1716         struct iwl_ucode_tlv *tlv;
1717         size_t len = ucode_raw->size;
1718         const u8 *data;
1719         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1720         u64 alternatives;
1721         u32 tlv_len;
1722         enum iwl_ucode_tlv_type tlv_type;
1723         const u8 *tlv_data;
1724
1725         if (len < sizeof(*ucode)) {
1726                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1727                 return -EINVAL;
1728         }
1729
1730         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1731                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1732                         le32_to_cpu(ucode->magic));
1733                 return -EINVAL;
1734         }
1735
1736         /*
1737          * Check which alternatives are present, and "downgrade"
1738          * when the chosen alternative is not present, warning
1739          * the user when that happens. Some files may not have
1740          * any alternatives, so don't warn in that case.
1741          */
1742         alternatives = le64_to_cpu(ucode->alternatives);
1743         tmp = wanted_alternative;
1744         if (wanted_alternative > 63)
1745                 wanted_alternative = 63;
1746         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1747                 wanted_alternative--;
1748         if (wanted_alternative && wanted_alternative != tmp)
1749                 IWL_WARN(priv,
1750                          "uCode alternative %d not available, choosing %d\n",
1751                          tmp, wanted_alternative);
1752
1753         priv->ucode_ver = le32_to_cpu(ucode->ver);
1754         pieces->build = le32_to_cpu(ucode->build);
1755         data = ucode->data;
1756
1757         len -= sizeof(*ucode);
1758
1759         while (len >= sizeof(*tlv)) {
1760                 u16 tlv_alt;
1761
1762                 len -= sizeof(*tlv);
1763                 tlv = (void *)data;
1764
1765                 tlv_len = le32_to_cpu(tlv->length);
1766                 tlv_type = le16_to_cpu(tlv->type);
1767                 tlv_alt = le16_to_cpu(tlv->alternative);
1768                 tlv_data = tlv->data;
1769
1770                 if (len < tlv_len) {
1771                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1772                                 len, tlv_len);
1773                         return -EINVAL;
1774                 }
1775                 len -= ALIGN(tlv_len, 4);
1776                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1777
1778                 /*
1779                  * Alternative 0 is always valid.
1780                  *
1781                  * Skip alternative TLVs that are not selected.
1782                  */
1783                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1784                         continue;
1785
1786                 switch (tlv_type) {
1787                 case IWL_UCODE_TLV_INST:
1788                         pieces->inst = tlv_data;
1789                         pieces->inst_size = tlv_len;
1790                         break;
1791                 case IWL_UCODE_TLV_DATA:
1792                         pieces->data = tlv_data;
1793                         pieces->data_size = tlv_len;
1794                         break;
1795                 case IWL_UCODE_TLV_INIT:
1796                         pieces->init = tlv_data;
1797                         pieces->init_size = tlv_len;
1798                         break;
1799                 case IWL_UCODE_TLV_INIT_DATA:
1800                         pieces->init_data = tlv_data;
1801                         pieces->init_data_size = tlv_len;
1802                         break;
1803                 case IWL_UCODE_TLV_BOOT:
1804                         pieces->boot = tlv_data;
1805                         pieces->boot_size = tlv_len;
1806                         break;
1807                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1808                         if (tlv_len != sizeof(u32))
1809                                 goto invalid_tlv_len;
1810                         capa->max_probe_length =
1811                                         le32_to_cpup((__le32 *)tlv_data);
1812                         break;
1813                 case IWL_UCODE_TLV_PAN:
1814                         if (tlv_len)
1815                                 goto invalid_tlv_len;
1816                         capa->pan = true;
1817                         break;
1818                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1819                         if (tlv_len != sizeof(u32))
1820                                 goto invalid_tlv_len;
1821                         pieces->init_evtlog_ptr =
1822                                         le32_to_cpup((__le32 *)tlv_data);
1823                         break;
1824                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1825                         if (tlv_len != sizeof(u32))
1826                                 goto invalid_tlv_len;
1827                         pieces->init_evtlog_size =
1828                                         le32_to_cpup((__le32 *)tlv_data);
1829                         break;
1830                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1831                         if (tlv_len != sizeof(u32))
1832                                 goto invalid_tlv_len;
1833                         pieces->init_errlog_ptr =
1834                                         le32_to_cpup((__le32 *)tlv_data);
1835                         break;
1836                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1837                         if (tlv_len != sizeof(u32))
1838                                 goto invalid_tlv_len;
1839                         pieces->inst_evtlog_ptr =
1840                                         le32_to_cpup((__le32 *)tlv_data);
1841                         break;
1842                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1843                         if (tlv_len != sizeof(u32))
1844                                 goto invalid_tlv_len;
1845                         pieces->inst_evtlog_size =
1846                                         le32_to_cpup((__le32 *)tlv_data);
1847                         break;
1848                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1849                         if (tlv_len != sizeof(u32))
1850                                 goto invalid_tlv_len;
1851                         pieces->inst_errlog_ptr =
1852                                         le32_to_cpup((__le32 *)tlv_data);
1853                         break;
1854                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1855                         if (tlv_len)
1856                                 goto invalid_tlv_len;
1857                         priv->enhance_sensitivity_table = true;
1858                         break;
1859                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1860                         if (tlv_len != sizeof(u32))
1861                                 goto invalid_tlv_len;
1862                         capa->standard_phy_calibration_size =
1863                                         le32_to_cpup((__le32 *)tlv_data);
1864                         break;
1865                 default:
1866                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1867                         break;
1868                 }
1869         }
1870
1871         if (len) {
1872                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1873                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1874                 return -EINVAL;
1875         }
1876
1877         return 0;
1878
1879  invalid_tlv_len:
1880         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1881         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1882
1883         return -EINVAL;
1884 }
1885
1886 /**
1887  * iwl_ucode_callback - callback when firmware was loaded
1888  *
1889  * If loaded successfully, copies the firmware into buffers
1890  * for the card to fetch (via DMA).
1891  */
1892 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1893 {
1894         struct iwl_priv *priv = context;
1895         struct iwl_ucode_header *ucode;
1896         int err;
1897         struct iwlagn_firmware_pieces pieces;
1898         const unsigned int api_max = priv->cfg->ucode_api_max;
1899         const unsigned int api_min = priv->cfg->ucode_api_min;
1900         u32 api_ver;
1901         char buildstr[25];
1902         u32 build;
1903         struct iwlagn_ucode_capabilities ucode_capa = {
1904                 .max_probe_length = 200,
1905                 .standard_phy_calibration_size =
1906                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1907         };
1908
1909         memset(&pieces, 0, sizeof(pieces));
1910
1911         if (!ucode_raw) {
1912                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1913                         IWL_ERR(priv,
1914                                 "request for firmware file '%s' failed.\n",
1915                                 priv->firmware_name);
1916                 goto try_again;
1917         }
1918
1919         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1920                        priv->firmware_name, ucode_raw->size);
1921
1922         /* Make sure that we got at least the API version number */
1923         if (ucode_raw->size < 4) {
1924                 IWL_ERR(priv, "File size way too small!\n");
1925                 goto try_again;
1926         }
1927
1928         /* Data from ucode file:  header followed by uCode images */
1929         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1930
1931         if (ucode->ver)
1932                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1933         else
1934                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1935                                            &ucode_capa);
1936
1937         if (err)
1938                 goto try_again;
1939
1940         api_ver = IWL_UCODE_API(priv->ucode_ver);
1941         build = pieces.build;
1942
1943         /*
1944          * api_ver should match the api version forming part of the
1945          * firmware filename ... but we don't check for that and only rely
1946          * on the API version read from firmware header from here on forward
1947          */
1948         /* no api version check required for experimental uCode */
1949         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1950                 if (api_ver < api_min || api_ver > api_max) {
1951                         IWL_ERR(priv,
1952                                 "Driver unable to support your firmware API. "
1953                                 "Driver supports v%u, firmware is v%u.\n",
1954                                 api_max, api_ver);
1955                         goto try_again;
1956                 }
1957
1958                 if (api_ver != api_max)
1959                         IWL_ERR(priv,
1960                                 "Firmware has old API version. Expected v%u, "
1961                                 "got v%u. New firmware can be obtained "
1962                                 "from http://www.intellinuxwireless.org.\n",
1963                                 api_max, api_ver);
1964         }
1965
1966         if (build)
1967                 sprintf(buildstr, " build %u%s", build,
1968                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1969                                 ? " (EXP)" : "");
1970         else
1971                 buildstr[0] = '\0';
1972
1973         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1974                  IWL_UCODE_MAJOR(priv->ucode_ver),
1975                  IWL_UCODE_MINOR(priv->ucode_ver),
1976                  IWL_UCODE_API(priv->ucode_ver),
1977                  IWL_UCODE_SERIAL(priv->ucode_ver),
1978                  buildstr);
1979
1980         snprintf(priv->hw->wiphy->fw_version,
1981                  sizeof(priv->hw->wiphy->fw_version),
1982                  "%u.%u.%u.%u%s",
1983                  IWL_UCODE_MAJOR(priv->ucode_ver),
1984                  IWL_UCODE_MINOR(priv->ucode_ver),
1985                  IWL_UCODE_API(priv->ucode_ver),
1986                  IWL_UCODE_SERIAL(priv->ucode_ver),
1987                  buildstr);
1988
1989         /*
1990          * For any of the failures below (before allocating pci memory)
1991          * we will try to load a version with a smaller API -- maybe the
1992          * user just got a corrupted version of the latest API.
1993          */
1994
1995         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1996                        priv->ucode_ver);
1997         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1998                        pieces.inst_size);
1999         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2000                        pieces.data_size);
2001         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2002                        pieces.init_size);
2003         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2004                        pieces.init_data_size);
2005         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2006                        pieces.boot_size);
2007
2008         /* Verify that uCode images will fit in card's SRAM */
2009         if (pieces.inst_size > priv->hw_params.max_inst_size) {
2010                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2011                         pieces.inst_size);
2012                 goto try_again;
2013         }
2014
2015         if (pieces.data_size > priv->hw_params.max_data_size) {
2016                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2017                         pieces.data_size);
2018                 goto try_again;
2019         }
2020
2021         if (pieces.init_size > priv->hw_params.max_inst_size) {
2022                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2023                         pieces.init_size);
2024                 goto try_again;
2025         }
2026
2027         if (pieces.init_data_size > priv->hw_params.max_data_size) {
2028                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2029                         pieces.init_data_size);
2030                 goto try_again;
2031         }
2032
2033         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2034                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2035                         pieces.boot_size);
2036                 goto try_again;
2037         }
2038
2039         /* Allocate ucode buffers for card's bus-master loading ... */
2040
2041         /* Runtime instructions and 2 copies of data:
2042          * 1) unmodified from disk
2043          * 2) backup cache for save/restore during power-downs */
2044         priv->ucode_code.len = pieces.inst_size;
2045         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2046
2047         priv->ucode_data.len = pieces.data_size;
2048         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2049
2050         priv->ucode_data_backup.len = pieces.data_size;
2051         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2052
2053         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2054             !priv->ucode_data_backup.v_addr)
2055                 goto err_pci_alloc;
2056
2057         /* Initialization instructions and data */
2058         if (pieces.init_size && pieces.init_data_size) {
2059                 priv->ucode_init.len = pieces.init_size;
2060                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2061
2062                 priv->ucode_init_data.len = pieces.init_data_size;
2063                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2064
2065                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2066                         goto err_pci_alloc;
2067         }
2068
2069         /* Bootstrap (instructions only, no data) */
2070         if (pieces.boot_size) {
2071                 priv->ucode_boot.len = pieces.boot_size;
2072                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2073
2074                 if (!priv->ucode_boot.v_addr)
2075                         goto err_pci_alloc;
2076         }
2077
2078         /* Now that we can no longer fail, copy information */
2079
2080         /*
2081          * The (size - 16) / 12 formula is based on the information recorded
2082          * for each event, which is of mode 1 (including timestamp) for all
2083          * new microcodes that include this information.
2084          */
2085         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2086         if (pieces.init_evtlog_size)
2087                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2088         else
2089                 priv->_agn.init_evtlog_size =
2090                         priv->cfg->base_params->max_event_log_size;
2091         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2092         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2093         if (pieces.inst_evtlog_size)
2094                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2095         else
2096                 priv->_agn.inst_evtlog_size =
2097                         priv->cfg->base_params->max_event_log_size;
2098         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2099
2100         if (ucode_capa.pan) {
2101                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2102                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2103         } else
2104                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2105
2106         /* Copy images into buffers for card's bus-master reads ... */
2107
2108         /* Runtime instructions (first block of data in file) */
2109         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2110                         pieces.inst_size);
2111         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2112
2113         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2114                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2115
2116         /*
2117          * Runtime data
2118          * NOTE:  Copy into backup buffer will be done in iwl_up()
2119          */
2120         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2121                         pieces.data_size);
2122         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2123         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2124
2125         /* Initialization instructions */
2126         if (pieces.init_size) {
2127                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2128                                 pieces.init_size);
2129                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2130         }
2131
2132         /* Initialization data */
2133         if (pieces.init_data_size) {
2134                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2135                                pieces.init_data_size);
2136                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2137                        pieces.init_data_size);
2138         }
2139
2140         /* Bootstrap instructions */
2141         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2142                         pieces.boot_size);
2143         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2144
2145         /*
2146          * figure out the offset of chain noise reset and gain commands
2147          * base on the size of standard phy calibration commands table size
2148          */
2149         if (ucode_capa.standard_phy_calibration_size >
2150             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2151                 ucode_capa.standard_phy_calibration_size =
2152                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2153
2154         priv->_agn.phy_calib_chain_noise_reset_cmd =
2155                 ucode_capa.standard_phy_calibration_size;
2156         priv->_agn.phy_calib_chain_noise_gain_cmd =
2157                 ucode_capa.standard_phy_calibration_size + 1;
2158
2159         /**************************************************
2160          * This is still part of probe() in a sense...
2161          *
2162          * 9. Setup and register with mac80211 and debugfs
2163          **************************************************/
2164         err = iwl_mac_setup_register(priv, &ucode_capa);
2165         if (err)
2166                 goto out_unbind;
2167
2168         err = iwl_dbgfs_register(priv, DRV_NAME);
2169         if (err)
2170                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2171
2172         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2173                                         &iwl_attribute_group);
2174         if (err) {
2175                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2176                 goto out_unbind;
2177         }
2178
2179         /* We have our copies now, allow OS release its copies */
2180         release_firmware(ucode_raw);
2181         complete(&priv->_agn.firmware_loading_complete);
2182         return;
2183
2184  try_again:
2185         /* try next, if any */
2186         if (iwl_request_firmware(priv, false))
2187                 goto out_unbind;
2188         release_firmware(ucode_raw);
2189         return;
2190
2191  err_pci_alloc:
2192         IWL_ERR(priv, "failed to allocate pci memory\n");
2193         iwl_dealloc_ucode_pci(priv);
2194  out_unbind:
2195         complete(&priv->_agn.firmware_loading_complete);
2196         device_release_driver(&priv->pci_dev->dev);
2197         release_firmware(ucode_raw);
2198 }
2199
2200 static const char *desc_lookup_text[] = {
2201         "OK",
2202         "FAIL",
2203         "BAD_PARAM",
2204         "BAD_CHECKSUM",
2205         "NMI_INTERRUPT_WDG",
2206         "SYSASSERT",
2207         "FATAL_ERROR",
2208         "BAD_COMMAND",
2209         "HW_ERROR_TUNE_LOCK",
2210         "HW_ERROR_TEMPERATURE",
2211         "ILLEGAL_CHAN_FREQ",
2212         "VCC_NOT_STABLE",
2213         "FH_ERROR",
2214         "NMI_INTERRUPT_HOST",
2215         "NMI_INTERRUPT_ACTION_PT",
2216         "NMI_INTERRUPT_UNKNOWN",
2217         "UCODE_VERSION_MISMATCH",
2218         "HW_ERROR_ABS_LOCK",
2219         "HW_ERROR_CAL_LOCK_FAIL",
2220         "NMI_INTERRUPT_INST_ACTION_PT",
2221         "NMI_INTERRUPT_DATA_ACTION_PT",
2222         "NMI_TRM_HW_ER",
2223         "NMI_INTERRUPT_TRM",
2224         "NMI_INTERRUPT_BREAK_POINT"
2225         "DEBUG_0",
2226         "DEBUG_1",
2227         "DEBUG_2",
2228         "DEBUG_3",
2229 };
2230
2231 static struct { char *name; u8 num; } advanced_lookup[] = {
2232         { "NMI_INTERRUPT_WDG", 0x34 },
2233         { "SYSASSERT", 0x35 },
2234         { "UCODE_VERSION_MISMATCH", 0x37 },
2235         { "BAD_COMMAND", 0x38 },
2236         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2237         { "FATAL_ERROR", 0x3D },
2238         { "NMI_TRM_HW_ERR", 0x46 },
2239         { "NMI_INTERRUPT_TRM", 0x4C },
2240         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2241         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2242         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2243         { "NMI_INTERRUPT_HOST", 0x66 },
2244         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2245         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2246         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2247         { "ADVANCED_SYSASSERT", 0 },
2248 };
2249
2250 static const char *desc_lookup(u32 num)
2251 {
2252         int i;
2253         int max = ARRAY_SIZE(desc_lookup_text);
2254
2255         if (num < max)
2256                 return desc_lookup_text[num];
2257
2258         max = ARRAY_SIZE(advanced_lookup) - 1;
2259         for (i = 0; i < max; i++) {
2260                 if (advanced_lookup[i].num == num)
2261                         break;;
2262         }
2263         return advanced_lookup[i].name;
2264 }
2265
2266 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2267 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2268
2269 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2270 {
2271         u32 data2, line;
2272         u32 desc, time, count, base, data1;
2273         u32 blink1, blink2, ilink1, ilink2;
2274         u32 pc, hcmd;
2275
2276         if (priv->ucode_type == UCODE_INIT) {
2277                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2278                 if (!base)
2279                         base = priv->_agn.init_errlog_ptr;
2280         } else {
2281                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2282                 if (!base)
2283                         base = priv->_agn.inst_errlog_ptr;
2284         }
2285
2286         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2287                 IWL_ERR(priv,
2288                         "Not valid error log pointer 0x%08X for %s uCode\n",
2289                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2290                 return;
2291         }
2292
2293         count = iwl_read_targ_mem(priv, base);
2294
2295         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2296                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2297                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2298                         priv->status, count);
2299         }
2300
2301         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2302         priv->isr_stats.err_code = desc;
2303         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2304         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2305         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2306         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2307         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2308         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2309         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2310         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2311         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2312         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2313
2314         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2315                                       blink1, blink2, ilink1, ilink2);
2316
2317         IWL_ERR(priv, "Desc                                  Time       "
2318                 "data1      data2      line\n");
2319         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2320                 desc_lookup(desc), desc, time, data1, data2, line);
2321         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2322         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2323                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2324 }
2325
2326 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2327
2328 /**
2329  * iwl_print_event_log - Dump error event log to syslog
2330  *
2331  */
2332 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2333                                u32 num_events, u32 mode,
2334                                int pos, char **buf, size_t bufsz)
2335 {
2336         u32 i;
2337         u32 base;       /* SRAM byte address of event log header */
2338         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2339         u32 ptr;        /* SRAM byte address of log data */
2340         u32 ev, time, data; /* event log data */
2341         unsigned long reg_flags;
2342
2343         if (num_events == 0)
2344                 return pos;
2345
2346         if (priv->ucode_type == UCODE_INIT) {
2347                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2348                 if (!base)
2349                         base = priv->_agn.init_evtlog_ptr;
2350         } else {
2351                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2352                 if (!base)
2353                         base = priv->_agn.inst_evtlog_ptr;
2354         }
2355
2356         if (mode == 0)
2357                 event_size = 2 * sizeof(u32);
2358         else
2359                 event_size = 3 * sizeof(u32);
2360
2361         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2362
2363         /* Make sure device is powered up for SRAM reads */
2364         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2365         iwl_grab_nic_access(priv);
2366
2367         /* Set starting address; reads will auto-increment */
2368         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2369         rmb();
2370
2371         /* "time" is actually "data" for mode 0 (no timestamp).
2372         * place event id # at far right for easier visual parsing. */
2373         for (i = 0; i < num_events; i++) {
2374                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2375                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2376                 if (mode == 0) {
2377                         /* data, ev */
2378                         if (bufsz) {
2379                                 pos += scnprintf(*buf + pos, bufsz - pos,
2380                                                 "EVT_LOG:0x%08x:%04u\n",
2381                                                 time, ev);
2382                         } else {
2383                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2384                                         time, ev);
2385                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2386                                         time, ev);
2387                         }
2388                 } else {
2389                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2390                         if (bufsz) {
2391                                 pos += scnprintf(*buf + pos, bufsz - pos,
2392                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2393                                                  time, data, ev);
2394                         } else {
2395                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2396                                         time, data, ev);
2397                                 trace_iwlwifi_dev_ucode_event(priv, time,
2398                                         data, ev);
2399                         }
2400                 }
2401         }
2402
2403         /* Allow device to power down */
2404         iwl_release_nic_access(priv);
2405         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2406         return pos;
2407 }
2408
2409 /**
2410  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2411  */
2412 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2413                                     u32 num_wraps, u32 next_entry,
2414                                     u32 size, u32 mode,
2415                                     int pos, char **buf, size_t bufsz)
2416 {
2417         /*
2418          * display the newest DEFAULT_LOG_ENTRIES entries
2419          * i.e the entries just before the next ont that uCode would fill.
2420          */
2421         if (num_wraps) {
2422                 if (next_entry < size) {
2423                         pos = iwl_print_event_log(priv,
2424                                                 capacity - (size - next_entry),
2425                                                 size - next_entry, mode,
2426                                                 pos, buf, bufsz);
2427                         pos = iwl_print_event_log(priv, 0,
2428                                                   next_entry, mode,
2429                                                   pos, buf, bufsz);
2430                 } else
2431                         pos = iwl_print_event_log(priv, next_entry - size,
2432                                                   size, mode, pos, buf, bufsz);
2433         } else {
2434                 if (next_entry < size) {
2435                         pos = iwl_print_event_log(priv, 0, next_entry,
2436                                                   mode, pos, buf, bufsz);
2437                 } else {
2438                         pos = iwl_print_event_log(priv, next_entry - size,
2439                                                   size, mode, pos, buf, bufsz);
2440                 }
2441         }
2442         return pos;
2443 }
2444
2445 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2446
2447 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2448                             char **buf, bool display)
2449 {
2450         u32 base;       /* SRAM byte address of event log header */
2451         u32 capacity;   /* event log capacity in # entries */
2452         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2453         u32 num_wraps;  /* # times uCode wrapped to top of log */
2454         u32 next_entry; /* index of next entry to be written by uCode */
2455         u32 size;       /* # entries that we'll print */
2456         u32 logsize;
2457         int pos = 0;
2458         size_t bufsz = 0;
2459
2460         if (priv->ucode_type == UCODE_INIT) {
2461                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2462                 logsize = priv->_agn.init_evtlog_size;
2463                 if (!base)
2464                         base = priv->_agn.init_evtlog_ptr;
2465         } else {
2466                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2467                 logsize = priv->_agn.inst_evtlog_size;
2468                 if (!base)
2469                         base = priv->_agn.inst_evtlog_ptr;
2470         }
2471
2472         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2473                 IWL_ERR(priv,
2474                         "Invalid event log pointer 0x%08X for %s uCode\n",
2475                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2476                 return -EINVAL;
2477         }
2478
2479         /* event log header */
2480         capacity = iwl_read_targ_mem(priv, base);
2481         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2482         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2483         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2484
2485         if (capacity > logsize) {
2486                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2487                         capacity, logsize);
2488                 capacity = logsize;
2489         }
2490
2491         if (next_entry > logsize) {
2492                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2493                         next_entry, logsize);
2494                 next_entry = logsize;
2495         }
2496
2497         size = num_wraps ? capacity : next_entry;
2498
2499         /* bail out if nothing in log */
2500         if (size == 0) {
2501                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2502                 return pos;
2503         }
2504
2505         /* enable/disable bt channel announcement */
2506         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2507
2508 #ifdef CONFIG_IWLWIFI_DEBUG
2509         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2510                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2511                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2512 #else
2513         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2514                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2515 #endif
2516         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2517                 size);
2518
2519 #ifdef CONFIG_IWLWIFI_DEBUG
2520         if (display) {
2521                 if (full_log)
2522                         bufsz = capacity * 48;
2523                 else
2524                         bufsz = size * 48;
2525                 *buf = kmalloc(bufsz, GFP_KERNEL);
2526                 if (!*buf)
2527                         return -ENOMEM;
2528         }
2529         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2530                 /*
2531                  * if uCode has wrapped back to top of log,
2532                  * start at the oldest entry,
2533                  * i.e the next one that uCode would fill.
2534                  */
2535                 if (num_wraps)
2536                         pos = iwl_print_event_log(priv, next_entry,
2537                                                 capacity - next_entry, mode,
2538                                                 pos, buf, bufsz);
2539                 /* (then/else) start at top of log */
2540                 pos = iwl_print_event_log(priv, 0,
2541                                           next_entry, mode, pos, buf, bufsz);
2542         } else
2543                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2544                                                 next_entry, size, mode,
2545                                                 pos, buf, bufsz);
2546 #else
2547         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2548                                         next_entry, size, mode,
2549                                         pos, buf, bufsz);
2550 #endif
2551         return pos;
2552 }
2553
2554 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2555 {
2556         struct iwl_ct_kill_config cmd;
2557         struct iwl_ct_kill_throttling_config adv_cmd;
2558         unsigned long flags;
2559         int ret = 0;
2560
2561         spin_lock_irqsave(&priv->lock, flags);
2562         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2563                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2564         spin_unlock_irqrestore(&priv->lock, flags);
2565         priv->thermal_throttle.ct_kill_toggle = false;
2566
2567         if (priv->cfg->base_params->support_ct_kill_exit) {
2568                 adv_cmd.critical_temperature_enter =
2569                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2570                 adv_cmd.critical_temperature_exit =
2571                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2572
2573                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2574                                        sizeof(adv_cmd), &adv_cmd);
2575                 if (ret)
2576                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2577                 else
2578                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2579                                         "succeeded, "
2580                                         "critical temperature enter is %d,"
2581                                         "exit is %d\n",
2582                                        priv->hw_params.ct_kill_threshold,
2583                                        priv->hw_params.ct_kill_exit_threshold);
2584         } else {
2585                 cmd.critical_temperature_R =
2586                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2587
2588                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2589                                        sizeof(cmd), &cmd);
2590                 if (ret)
2591                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2592                 else
2593                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2594                                         "succeeded, "
2595                                         "critical temperature is %d\n",
2596                                         priv->hw_params.ct_kill_threshold);
2597         }
2598 }
2599
2600 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2601 {
2602         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2603         struct iwl_host_cmd cmd = {
2604                 .id = CALIBRATION_CFG_CMD,
2605                 .len = sizeof(struct iwl_calib_cfg_cmd),
2606                 .data = &calib_cfg_cmd,
2607         };
2608
2609         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2610         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2611         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2612
2613         return iwl_send_cmd(priv, &cmd);
2614 }
2615
2616
2617 /**
2618  * iwl_alive_start - called after REPLY_ALIVE notification received
2619  *                   from protocol/runtime uCode (initialization uCode's
2620  *                   Alive gets handled by iwl_init_alive_start()).
2621  */
2622 static void iwl_alive_start(struct iwl_priv *priv)
2623 {
2624         int ret = 0;
2625         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2626
2627         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2628
2629         if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2630                 /* We had an error bringing up the hardware, so take it
2631                  * all the way back down so we can try again */
2632                 IWL_DEBUG_INFO(priv, "Alive failed.\n");
2633                 goto restart;
2634         }
2635
2636         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2637          * This is a paranoid check, because we would not have gotten the
2638          * "runtime" alive if code weren't properly loaded.  */
2639         if (iwl_verify_ucode(priv)) {
2640                 /* Runtime instruction load was bad;
2641                  * take it all the way back down so we can try again */
2642                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2643                 goto restart;
2644         }
2645
2646         ret = priv->cfg->ops->lib->alive_notify(priv);
2647         if (ret) {
2648                 IWL_WARN(priv,
2649                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2650                 goto restart;
2651         }
2652
2653
2654         /* After the ALIVE response, we can send host commands to the uCode */
2655         set_bit(STATUS_ALIVE, &priv->status);
2656
2657         if (priv->cfg->ops->lib->recover_from_tx_stall) {
2658                 /* Enable timer to monitor the driver queues */
2659                 mod_timer(&priv->monitor_recover,
2660                         jiffies +
2661                         msecs_to_jiffies(
2662                           priv->cfg->base_params->monitor_recover_period));
2663         }
2664
2665         if (iwl_is_rfkill(priv))
2666                 return;
2667
2668         /* download priority table before any calibration request */
2669         if (priv->cfg->bt_params &&
2670             priv->cfg->bt_params->advanced_bt_coexist) {
2671                 /* Configure Bluetooth device coexistence support */
2672                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2673                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2674                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2675                 priv->cfg->ops->hcmd->send_bt_config(priv);
2676                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2677                 iwlagn_send_prio_tbl(priv);
2678
2679                 /* FIXME: w/a to force change uCode BT state machine */
2680                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2681                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2682                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2683                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2684         }
2685         if (priv->hw_params.calib_rt_cfg)
2686                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2687
2688         ieee80211_wake_queues(priv->hw);
2689
2690         priv->active_rate = IWL_RATES_MASK;
2691
2692         /* Configure Tx antenna selection based on H/W config */
2693         if (priv->cfg->ops->hcmd->set_tx_ant)
2694                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2695
2696         if (iwl_is_associated_ctx(ctx)) {
2697                 struct iwl_rxon_cmd *active_rxon =
2698                                 (struct iwl_rxon_cmd *)&ctx->active;
2699                 /* apply any changes in staging */
2700                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2701                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2702         } else {
2703                 struct iwl_rxon_context *tmp;
2704                 /* Initialize our rx_config data */
2705                 for_each_context(priv, tmp)
2706                         iwl_connection_init_rx_config(priv, tmp);
2707
2708                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2709                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2710         }
2711
2712         if (priv->cfg->bt_params &&
2713             !priv->cfg->bt_params->advanced_bt_coexist) {
2714                 /* Configure Bluetooth device coexistence support */
2715                 priv->cfg->ops->hcmd->send_bt_config(priv);
2716         }
2717
2718         iwl_reset_run_time_calib(priv);
2719
2720         set_bit(STATUS_READY, &priv->status);
2721
2722         /* Configure the adapter for unassociated operation */
2723         iwlcore_commit_rxon(priv, ctx);
2724
2725         /* At this point, the NIC is initialized and operational */
2726         iwl_rf_kill_ct_config(priv);
2727
2728         iwl_leds_init(priv);
2729
2730         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2731         wake_up_interruptible(&priv->wait_command_queue);
2732
2733         iwl_power_update_mode(priv, true);
2734         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2735
2736
2737         return;
2738
2739  restart:
2740         queue_work(priv->workqueue, &priv->restart);
2741 }
2742
2743 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2744
2745 static void __iwl_down(struct iwl_priv *priv)
2746 {
2747         unsigned long flags;
2748         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2749
2750         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2751
2752         iwl_scan_cancel_timeout(priv, 200);
2753
2754         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2755
2756         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2757          * to prevent rearm timer */
2758         if (priv->cfg->ops->lib->recover_from_tx_stall)
2759                 del_timer_sync(&priv->monitor_recover);
2760
2761         iwl_clear_ucode_stations(priv, NULL);
2762         iwl_dealloc_bcast_stations(priv);
2763         iwl_clear_driver_stations(priv);
2764
2765         /* reset BT coex data */
2766         priv->bt_status = 0;
2767         if (priv->cfg->bt_params)
2768                 priv->bt_traffic_load =
2769                          priv->cfg->bt_params->bt_init_traffic_load;
2770         else
2771                 priv->bt_traffic_load = 0;
2772         priv->bt_sco_active = false;
2773         priv->bt_full_concurrent = false;
2774         priv->bt_ci_compliance = 0;
2775
2776         /* Unblock any waiting calls */
2777         wake_up_interruptible_all(&priv->wait_command_queue);
2778
2779         /* Wipe out the EXIT_PENDING status bit if we are not actually
2780          * exiting the module */
2781         if (!exit_pending)
2782                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2783
2784         /* stop and reset the on-board processor */
2785         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2786
2787         /* tell the device to stop sending interrupts */
2788         spin_lock_irqsave(&priv->lock, flags);
2789         iwl_disable_interrupts(priv);
2790         spin_unlock_irqrestore(&priv->lock, flags);
2791         iwl_synchronize_irq(priv);
2792
2793         if (priv->mac80211_registered)
2794                 ieee80211_stop_queues(priv->hw);
2795
2796         /* If we have not previously called iwl_init() then
2797          * clear all bits but the RF Kill bit and return */
2798         if (!iwl_is_init(priv)) {
2799                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2800                                         STATUS_RF_KILL_HW |
2801                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2802                                         STATUS_GEO_CONFIGURED |
2803                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2804                                         STATUS_EXIT_PENDING;
2805                 goto exit;
2806         }
2807
2808         /* ...otherwise clear out all the status bits but the RF Kill
2809          * bit and continue taking the NIC down. */
2810         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2811                                 STATUS_RF_KILL_HW |
2812                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2813                                 STATUS_GEO_CONFIGURED |
2814                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2815                                 STATUS_FW_ERROR |
2816                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2817                                 STATUS_EXIT_PENDING;
2818
2819         /* device going down, Stop using ICT table */
2820         if (priv->cfg->ops->lib->isr_ops.disable)
2821                 priv->cfg->ops->lib->isr_ops.disable(priv);
2822
2823         iwlagn_txq_ctx_stop(priv);
2824         iwlagn_rxq_stop(priv);
2825
2826         /* Power-down device's busmaster DMA clocks */
2827         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2828         udelay(5);
2829
2830         /* Make sure (redundant) we've released our request to stay awake */
2831         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2832
2833         /* Stop the device, and put it in low power state */
2834         iwl_apm_stop(priv);
2835
2836  exit:
2837         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2838
2839         dev_kfree_skb(priv->beacon_skb);
2840         priv->beacon_skb = NULL;
2841
2842         /* clear out any free frames */
2843         iwl_clear_free_frames(priv);
2844 }
2845
2846 static void iwl_down(struct iwl_priv *priv)
2847 {
2848         mutex_lock(&priv->mutex);
2849         __iwl_down(priv);
2850         mutex_unlock(&priv->mutex);
2851
2852         iwl_cancel_deferred_work(priv);
2853 }
2854
2855 #define HW_READY_TIMEOUT (50)
2856
2857 static int iwl_set_hw_ready(struct iwl_priv *priv)
2858 {
2859         int ret = 0;
2860
2861         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2862                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2863
2864         /* See if we got it */
2865         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2866                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2867                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2868                                 HW_READY_TIMEOUT);
2869         if (ret != -ETIMEDOUT)
2870                 priv->hw_ready = true;
2871         else
2872                 priv->hw_ready = false;
2873
2874         IWL_DEBUG_INFO(priv, "hardware %s\n",
2875                       (priv->hw_ready == 1) ? "ready" : "not ready");
2876         return ret;
2877 }
2878
2879 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2880 {
2881         int ret = 0;
2882
2883         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2884
2885         ret = iwl_set_hw_ready(priv);
2886         if (priv->hw_ready)
2887                 return ret;
2888
2889         /* If HW is not ready, prepare the conditions to check again */
2890         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2891                         CSR_HW_IF_CONFIG_REG_PREPARE);
2892
2893         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2894                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2895                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2896
2897         /* HW should be ready by now, check again. */
2898         if (ret != -ETIMEDOUT)
2899                 iwl_set_hw_ready(priv);
2900
2901         return ret;
2902 }
2903
2904 #define MAX_HW_RESTARTS 5
2905
2906 static int __iwl_up(struct iwl_priv *priv)
2907 {
2908         struct iwl_rxon_context *ctx;
2909         int i;
2910         int ret;
2911
2912         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2913                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2914                 return -EIO;
2915         }
2916
2917         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2918                 IWL_ERR(priv, "ucode not available for device bringup\n");
2919                 return -EIO;
2920         }
2921
2922         for_each_context(priv, ctx) {
2923                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2924                 if (ret) {
2925                         iwl_dealloc_bcast_stations(priv);
2926                         return ret;
2927                 }
2928         }
2929
2930         iwl_prepare_card_hw(priv);
2931
2932         if (!priv->hw_ready) {
2933                 IWL_WARN(priv, "Exit HW not ready\n");
2934                 return -EIO;
2935         }
2936
2937         /* If platform's RF_KILL switch is NOT set to KILL */
2938         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2939                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2940         else
2941                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2942
2943         if (iwl_is_rfkill(priv)) {
2944                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2945
2946                 iwl_enable_interrupts(priv);
2947                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2948                 return 0;
2949         }
2950
2951         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2952
2953         /* must be initialised before iwl_hw_nic_init */
2954         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2955                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2956         else
2957                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2958
2959         ret = iwlagn_hw_nic_init(priv);
2960         if (ret) {
2961                 IWL_ERR(priv, "Unable to init nic\n");
2962                 return ret;
2963         }
2964
2965         /* make sure rfkill handshake bits are cleared */
2966         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2967         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2968                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2969
2970         /* clear (again), then enable host interrupts */
2971         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2972         iwl_enable_interrupts(priv);
2973
2974         /* really make sure rfkill handshake bits are cleared */
2975         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2976         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2977
2978         /* Copy original ucode data image from disk into backup cache.
2979          * This will be used to initialize the on-board processor's
2980          * data SRAM for a clean start when the runtime program first loads. */
2981         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2982                priv->ucode_data.len);
2983
2984         for (i = 0; i < MAX_HW_RESTARTS; i++) {
2985
2986                 /* load bootstrap state machine,
2987                  * load bootstrap program into processor's memory,
2988                  * prepare to load the "initialize" uCode */
2989                 ret = priv->cfg->ops->lib->load_ucode(priv);
2990
2991                 if (ret) {
2992                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2993                                 ret);
2994                         continue;
2995                 }
2996
2997                 /* start card; "initialize" will load runtime ucode */
2998                 iwl_nic_start(priv);
2999
3000                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3001
3002                 return 0;
3003         }
3004
3005         set_bit(STATUS_EXIT_PENDING, &priv->status);
3006         __iwl_down(priv);
3007         clear_bit(STATUS_EXIT_PENDING, &priv->status);
3008
3009         /* tried to restart and config the device for as long as our
3010          * patience could withstand */
3011         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3012         return -EIO;
3013 }
3014
3015
3016 /*****************************************************************************
3017  *
3018  * Workqueue callbacks
3019  *
3020  *****************************************************************************/
3021
3022 static void iwl_bg_init_alive_start(struct work_struct *data)
3023 {
3024         struct iwl_priv *priv =
3025             container_of(data, struct iwl_priv, init_alive_start.work);
3026
3027         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3028                 return;
3029
3030         mutex_lock(&priv->mutex);
3031         priv->cfg->ops->lib->init_alive_start(priv);
3032         mutex_unlock(&priv->mutex);
3033 }
3034
3035 static void iwl_bg_alive_start(struct work_struct *data)
3036 {
3037         struct iwl_priv *priv =
3038             container_of(data, struct iwl_priv, alive_start.work);
3039
3040         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3041                 return;
3042
3043         /* enable dram interrupt */
3044         if (priv->cfg->ops->lib->isr_ops.reset)
3045                 priv->cfg->ops->lib->isr_ops.reset(priv);
3046
3047         mutex_lock(&priv->mutex);
3048         iwl_alive_start(priv);
3049         mutex_unlock(&priv->mutex);
3050 }
3051
3052 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3053 {
3054         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3055                         run_time_calib_work);
3056
3057         mutex_lock(&priv->mutex);
3058
3059         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3060             test_bit(STATUS_SCANNING, &priv->status)) {
3061                 mutex_unlock(&priv->mutex);
3062                 return;
3063         }
3064
3065         if (priv->start_calib) {
3066                 if (priv->cfg->bt_params &&
3067                     priv->cfg->bt_params->bt_statistics) {
3068                         iwl_chain_noise_calibration(priv,
3069                                         (void *)&priv->_agn.statistics_bt);
3070                         iwl_sensitivity_calibration(priv,
3071                                         (void *)&priv->_agn.statistics_bt);
3072                 } else {
3073                         iwl_chain_noise_calibration(priv,
3074                                         (void *)&priv->_agn.statistics);
3075                         iwl_sensitivity_calibration(priv,
3076                                         (void *)&priv->_agn.statistics);
3077                 }
3078         }
3079
3080         mutex_unlock(&priv->mutex);
3081 }
3082
3083 static void iwl_bg_restart(struct work_struct *data)
3084 {
3085         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3086
3087         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3088                 return;
3089
3090         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3091                 struct iwl_rxon_context *ctx;
3092                 bool bt_sco, bt_full_concurrent;
3093                 u8 bt_ci_compliance;
3094                 u8 bt_load;
3095                 u8 bt_status;
3096
3097                 mutex_lock(&priv->mutex);
3098                 for_each_context(priv, ctx)
3099                         ctx->vif = NULL;
3100                 priv->is_open = 0;
3101
3102                 /*
3103                  * __iwl_down() will clear the BT status variables,
3104                  * which is correct, but when we restart we really
3105                  * want to keep them so restore them afterwards.
3106                  *
3107                  * The restart process will later pick them up and
3108                  * re-configure the hw when we reconfigure the BT
3109                  * command.
3110                  */
3111                 bt_sco = priv->bt_sco_active;
3112                 bt_full_concurrent = priv->bt_full_concurrent;
3113                 bt_ci_compliance = priv->bt_ci_compliance;
3114                 bt_load = priv->bt_traffic_load;
3115                 bt_status = priv->bt_status;
3116
3117                 __iwl_down(priv);
3118
3119                 priv->bt_sco_active = bt_sco;
3120                 priv->bt_full_concurrent = bt_full_concurrent;
3121                 priv->bt_ci_compliance = bt_ci_compliance;
3122                 priv->bt_traffic_load = bt_load;
3123                 priv->bt_status = bt_status;
3124
3125                 mutex_unlock(&priv->mutex);
3126                 iwl_cancel_deferred_work(priv);
3127                 ieee80211_restart_hw(priv->hw);
3128         } else {
3129                 iwl_down(priv);
3130
3131                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3132                         return;
3133
3134                 mutex_lock(&priv->mutex);
3135                 __iwl_up(priv);
3136                 mutex_unlock(&priv->mutex);
3137         }
3138 }
3139
3140 static void iwl_bg_rx_replenish(struct work_struct *data)
3141 {
3142         struct iwl_priv *priv =
3143             container_of(data, struct iwl_priv, rx_replenish);
3144
3145         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3146                 return;
3147
3148         mutex_lock(&priv->mutex);
3149         iwlagn_rx_replenish(priv);
3150         mutex_unlock(&priv->mutex);
3151 }
3152
3153 /*****************************************************************************
3154  *
3155  * mac80211 entry point functions
3156  *
3157  *****************************************************************************/
3158
3159 #define UCODE_READY_TIMEOUT     (4 * HZ)
3160
3161 /*
3162  * Not a mac80211 entry point function, but it fits in with all the
3163  * other mac80211 functions grouped here.
3164  */
3165 static int iwl_mac_setup_register(struct iwl_priv *priv,
3166                                   struct iwlagn_ucode_capabilities *capa)
3167 {
3168         int ret;
3169         struct ieee80211_hw *hw = priv->hw;
3170         struct iwl_rxon_context *ctx;
3171
3172         hw->rate_control_algorithm = "iwl-agn-rs";
3173
3174         /* Tell mac80211 our characteristics */
3175         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3176                     IEEE80211_HW_AMPDU_AGGREGATION |
3177                     IEEE80211_HW_NEED_DTIM_PERIOD |
3178                     IEEE80211_HW_SPECTRUM_MGMT;
3179
3180         if (!priv->cfg->base_params->broken_powersave)
3181                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3182                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3183
3184         if (priv->cfg->sku & IWL_SKU_N)
3185                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3186                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3187
3188         hw->sta_data_size = sizeof(struct iwl_station_priv);
3189         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3190
3191         for_each_context(priv, ctx) {
3192                 hw->wiphy->interface_modes |= ctx->interface_modes;
3193                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3194         }
3195
3196         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3197                             WIPHY_FLAG_DISABLE_BEACON_HINTS;
3198
3199         /*
3200          * For now, disable PS by default because it affects
3201          * RX performance significantly.
3202          */
3203         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3204
3205         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3206         /* we create the 802.11 header and a zero-length SSID element */
3207         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3208
3209         /* Default value; 4 EDCA QOS priorities */
3210         hw->queues = 4;
3211
3212         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3213
3214         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3215                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3216                         &priv->bands[IEEE80211_BAND_2GHZ];
3217         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3218                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3219                         &priv->bands[IEEE80211_BAND_5GHZ];
3220
3221         ret = ieee80211_register_hw(priv->hw);
3222         if (ret) {
3223                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3224                 return ret;
3225         }
3226         priv->mac80211_registered = 1;
3227
3228         return 0;
3229 }
3230
3231
3232 int iwlagn_mac_start(struct ieee80211_hw *hw)
3233 {
3234         struct iwl_priv *priv = hw->priv;
3235         int ret;
3236
3237         IWL_DEBUG_MAC80211(priv, "enter\n");
3238
3239         /* we should be verifying the device is ready to be opened */
3240         mutex_lock(&priv->mutex);
3241         ret = __iwl_up(priv);
3242         mutex_unlock(&priv->mutex);
3243
3244         if (ret)
3245                 return ret;
3246
3247         if (iwl_is_rfkill(priv))
3248                 goto out;
3249
3250         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3251
3252         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3253          * mac80211 will not be run successfully. */
3254         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3255                         test_bit(STATUS_READY, &priv->status),
3256                         UCODE_READY_TIMEOUT);
3257         if (!ret) {
3258                 if (!test_bit(STATUS_READY, &priv->status)) {
3259                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3260                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3261                         return -ETIMEDOUT;
3262                 }
3263         }
3264
3265         iwl_led_start(priv);
3266
3267 out:
3268         priv->is_open = 1;
3269         IWL_DEBUG_MAC80211(priv, "leave\n");
3270         return 0;
3271 }
3272
3273 void iwlagn_mac_stop(struct ieee80211_hw *hw)
3274 {
3275         struct iwl_priv *priv = hw->priv;
3276
3277         IWL_DEBUG_MAC80211(priv, "enter\n");
3278
3279         if (!priv->is_open)
3280                 return;
3281
3282         priv->is_open = 0;
3283
3284         iwl_down(priv);
3285
3286         flush_workqueue(priv->workqueue);
3287
3288         /* enable interrupts again in order to receive rfkill changes */
3289         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3290         iwl_enable_interrupts(priv);
3291
3292         IWL_DEBUG_MAC80211(priv, "leave\n");
3293 }
3294
3295 int iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3296 {
3297         struct iwl_priv *priv = hw->priv;
3298
3299         IWL_DEBUG_MACDUMP(priv, "enter\n");
3300
3301         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3302                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3303
3304         if (iwlagn_tx_skb(priv, skb))
3305                 dev_kfree_skb_any(skb);
3306
3307         IWL_DEBUG_MACDUMP(priv, "leave\n");
3308         return NETDEV_TX_OK;
3309 }
3310
3311 void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3312                                 struct ieee80211_vif *vif,
3313                                 struct ieee80211_key_conf *keyconf,
3314                                 struct ieee80211_sta *sta,
3315                                 u32 iv32, u16 *phase1key)
3316 {
3317         struct iwl_priv *priv = hw->priv;
3318         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3319
3320         IWL_DEBUG_MAC80211(priv, "enter\n");
3321
3322         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3323                             iv32, phase1key);
3324
3325         IWL_DEBUG_MAC80211(priv, "leave\n");
3326 }
3327
3328 int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3329                        struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3330                        struct ieee80211_key_conf *key)
3331 {
3332         struct iwl_priv *priv = hw->priv;
3333         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3334         struct iwl_rxon_context *ctx = vif_priv->ctx;
3335         int ret;
3336         u8 sta_id;
3337         bool is_default_wep_key = false;
3338
3339         IWL_DEBUG_MAC80211(priv, "enter\n");
3340
3341         if (priv->cfg->mod_params->sw_crypto) {
3342                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3343                 return -EOPNOTSUPP;
3344         }
3345
3346         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3347         if (sta_id == IWL_INVALID_STATION)
3348                 return -EINVAL;
3349
3350         mutex_lock(&priv->mutex);
3351         iwl_scan_cancel_timeout(priv, 100);
3352
3353         /*
3354          * If we are getting WEP group key and we didn't receive any key mapping
3355          * so far, we are in legacy wep mode (group key only), otherwise we are
3356          * in 1X mode.
3357          * In legacy wep mode, we use another host command to the uCode.
3358          */
3359         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3360              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3361             !sta) {
3362                 if (cmd == SET_KEY)
3363                         is_default_wep_key = !ctx->key_mapping_keys;
3364                 else
3365                         is_default_wep_key =
3366                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3367         }
3368
3369         switch (cmd) {
3370         case SET_KEY:
3371                 if (is_default_wep_key)
3372                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3373                 else
3374                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3375                                                   key, sta_id);
3376
3377                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3378                 break;
3379         case DISABLE_KEY:
3380                 if (is_default_wep_key)
3381                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3382                 else
3383                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3384
3385                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3386                 break;
3387         default:
3388                 ret = -EINVAL;
3389         }
3390
3391         mutex_unlock(&priv->mutex);
3392         IWL_DEBUG_MAC80211(priv, "leave\n");
3393
3394         return ret;
3395 }
3396
3397 int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3398                             struct ieee80211_vif *vif,
3399                             enum ieee80211_ampdu_mlme_action action,
3400                             struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3401 {
3402         struct iwl_priv *priv = hw->priv;
3403         int ret = -EINVAL;
3404
3405         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3406                      sta->addr, tid);
3407
3408         if (!(priv->cfg->sku & IWL_SKU_N))
3409                 return -EACCES;
3410
3411         mutex_lock(&priv->mutex);
3412
3413         switch (action) {
3414         case IEEE80211_AMPDU_RX_START:
3415                 IWL_DEBUG_HT(priv, "start Rx\n");
3416                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3417                 break;
3418         case IEEE80211_AMPDU_RX_STOP:
3419                 IWL_DEBUG_HT(priv, "stop Rx\n");
3420                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3421                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3422                         ret = 0;
3423                 break;
3424         case IEEE80211_AMPDU_TX_START:
3425                 IWL_DEBUG_HT(priv, "start Tx\n");
3426                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3427                 if (ret == 0) {
3428                         priv->_agn.agg_tids_count++;
3429                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3430                                      priv->_agn.agg_tids_count);
3431                 }
3432                 break;
3433         case IEEE80211_AMPDU_TX_STOP:
3434                 IWL_DEBUG_HT(priv, "stop Tx\n");
3435                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3436                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3437                         priv->_agn.agg_tids_count--;
3438                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3439                                      priv->_agn.agg_tids_count);
3440                 }
3441                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3442                         ret = 0;
3443                 if (priv->cfg->ht_params &&
3444                     priv->cfg->ht_params->use_rts_for_aggregation) {
3445                         struct iwl_station_priv *sta_priv =
3446                                 (void *) sta->drv_priv;
3447                         /*
3448                          * switch off RTS/CTS if it was previously enabled
3449                          */
3450
3451                         sta_priv->lq_sta.lq.general_params.flags &=
3452                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3453                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3454                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3455                 }
3456                 break;
3457         case IEEE80211_AMPDU_TX_OPERATIONAL:
3458                 if (priv->cfg->ht_params &&
3459                     priv->cfg->ht_params->use_rts_for_aggregation) {
3460                         struct iwl_station_priv *sta_priv =
3461                                 (void *) sta->drv_priv;
3462
3463                         /*
3464                          * switch to RTS/CTS if it is the prefer protection
3465                          * method for HT traffic
3466                          */
3467
3468                         sta_priv->lq_sta.lq.general_params.flags |=
3469                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3470                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3471                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3472                 }
3473                 ret = 0;
3474                 break;
3475         }
3476         mutex_unlock(&priv->mutex);
3477
3478         return ret;
3479 }
3480
3481 int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3482                        struct ieee80211_vif *vif,
3483                        struct ieee80211_sta *sta)
3484 {
3485         struct iwl_priv *priv = hw->priv;
3486         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3487         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3488         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3489         int ret;
3490         u8 sta_id;
3491
3492         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3493                         sta->addr);
3494         mutex_lock(&priv->mutex);
3495         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3496                         sta->addr);
3497         sta_priv->common.sta_id = IWL_INVALID_STATION;
3498
3499         atomic_set(&sta_priv->pending_frames, 0);
3500         if (vif->type == NL80211_IFTYPE_AP)
3501                 sta_priv->client = true;
3502
3503         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3504                                      is_ap, sta, &sta_id);
3505         if (ret) {
3506                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3507                         sta->addr, ret);
3508                 /* Should we return success if return code is EEXIST ? */
3509                 mutex_unlock(&priv->mutex);
3510                 return ret;
3511         }
3512
3513         sta_priv->common.sta_id = sta_id;
3514
3515         /* Initialize rate scaling */
3516         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3517                        sta->addr);
3518         iwl_rs_rate_init(priv, sta, sta_id);
3519         mutex_unlock(&priv->mutex);
3520
3521         return 0;
3522 }
3523
3524 void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3525                                struct ieee80211_channel_switch *ch_switch)
3526 {
3527         struct iwl_priv *priv = hw->priv;
3528         const struct iwl_channel_info *ch_info;
3529         struct ieee80211_conf *conf = &hw->conf;
3530         struct ieee80211_channel *channel = ch_switch->channel;
3531         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3532         /*
3533          * MULTI-FIXME
3534          * When we add support for multiple interfaces, we need to
3535          * revisit this. The channel switch command in the device
3536          * only affects the BSS context, but what does that really
3537          * mean? And what if we get a CSA on the second interface?
3538          * This needs a lot of work.
3539          */
3540         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3541         u16 ch;
3542         unsigned long flags = 0;
3543
3544         IWL_DEBUG_MAC80211(priv, "enter\n");
3545
3546         if (iwl_is_rfkill(priv))
3547                 goto out_exit;
3548
3549         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3550             test_bit(STATUS_SCANNING, &priv->status))
3551                 goto out_exit;
3552
3553         if (!iwl_is_associated_ctx(ctx))
3554                 goto out_exit;
3555
3556         /* channel switch in progress */
3557         if (priv->switch_rxon.switch_in_progress == true)
3558                 goto out_exit;
3559
3560         mutex_lock(&priv->mutex);
3561         if (priv->cfg->ops->lib->set_channel_switch) {
3562
3563                 ch = channel->hw_value;
3564                 if (le16_to_cpu(ctx->active.channel) != ch) {
3565                         ch_info = iwl_get_channel_info(priv,
3566                                                        channel->band,
3567                                                        ch);
3568                         if (!is_channel_valid(ch_info)) {
3569                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3570                                 goto out;
3571                         }
3572                         spin_lock_irqsave(&priv->lock, flags);
3573
3574                         priv->current_ht_config.smps = conf->smps_mode;
3575
3576                         /* Configure HT40 channels */
3577                         ctx->ht.enabled = conf_is_ht(conf);
3578                         if (ctx->ht.enabled) {
3579                                 if (conf_is_ht40_minus(conf)) {
3580                                         ctx->ht.extension_chan_offset =
3581                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3582                                         ctx->ht.is_40mhz = true;
3583                                 } else if (conf_is_ht40_plus(conf)) {
3584                                         ctx->ht.extension_chan_offset =
3585                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3586                                         ctx->ht.is_40mhz = true;
3587                                 } else {
3588                                         ctx->ht.extension_chan_offset =
3589                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3590                                         ctx->ht.is_40mhz = false;
3591                                 }
3592                         } else
3593                                 ctx->ht.is_40mhz = false;
3594
3595                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3596                                 ctx->staging.flags = 0;
3597
3598                         iwl_set_rxon_channel(priv, channel, ctx);
3599                         iwl_set_rxon_ht(priv, ht_conf);
3600                         iwl_set_flags_for_band(priv, ctx, channel->band,
3601                                                ctx->vif);
3602                         spin_unlock_irqrestore(&priv->lock, flags);
3603
3604                         iwl_set_rate(priv);
3605                         /*
3606                          * at this point, staging_rxon has the
3607                          * configuration for channel switch
3608                          */
3609                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3610                                                                     ch_switch))
3611                                 priv->switch_rxon.switch_in_progress = false;
3612                 }
3613         }
3614 out:
3615         mutex_unlock(&priv->mutex);
3616 out_exit:
3617         if (!priv->switch_rxon.switch_in_progress)
3618                 ieee80211_chswitch_done(ctx->vif, false);
3619         IWL_DEBUG_MAC80211(priv, "leave\n");
3620 }
3621
3622 void iwlagn_configure_filter(struct ieee80211_hw *hw,
3623                              unsigned int changed_flags,
3624                              unsigned int *total_flags,
3625                              u64 multicast)
3626 {
3627         struct iwl_priv *priv = hw->priv;
3628         __le32 filter_or = 0, filter_nand = 0;
3629         struct iwl_rxon_context *ctx;
3630
3631 #define CHK(test, flag) do { \
3632         if (*total_flags & (test))              \
3633                 filter_or |= (flag);            \
3634         else                                    \
3635                 filter_nand |= (flag);          \
3636         } while (0)
3637
3638         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3639                         changed_flags, *total_flags);
3640
3641         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3642         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3643         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3644
3645 #undef CHK
3646
3647         mutex_lock(&priv->mutex);
3648
3649         for_each_context(priv, ctx) {
3650                 ctx->staging.filter_flags &= ~filter_nand;
3651                 ctx->staging.filter_flags |= filter_or;
3652
3653                 /*
3654                  * Not committing directly because hardware can perform a scan,
3655                  * but we'll eventually commit the filter flags change anyway.
3656                  */
3657         }
3658
3659         mutex_unlock(&priv->mutex);
3660
3661         /*
3662          * Receiving all multicast frames is always enabled by the
3663          * default flags setup in iwl_connection_init_rx_config()
3664          * since we currently do not support programming multicast
3665          * filters into the device.
3666          */
3667         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3668                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3669 }
3670
3671 void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3672 {
3673         struct iwl_priv *priv = hw->priv;
3674
3675         mutex_lock(&priv->mutex);
3676         IWL_DEBUG_MAC80211(priv, "enter\n");
3677
3678         /* do not support "flush" */
3679         if (!priv->cfg->ops->lib->txfifo_flush)
3680                 goto done;
3681
3682         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3683                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3684                 goto done;
3685         }
3686         if (iwl_is_rfkill(priv)) {
3687                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3688                 goto done;
3689         }
3690
3691         /*
3692          * mac80211 will not push any more frames for transmit
3693          * until the flush is completed
3694          */
3695         if (drop) {
3696                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3697                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3698                         IWL_ERR(priv, "flush request fail\n");
3699                         goto done;
3700                 }
3701         }
3702         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3703         iwlagn_wait_tx_queue_empty(priv);
3704 done:
3705         mutex_unlock(&priv->mutex);
3706         IWL_DEBUG_MAC80211(priv, "leave\n");
3707 }
3708
3709 /*****************************************************************************
3710  *
3711  * driver setup and teardown
3712  *
3713  *****************************************************************************/
3714
3715 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3716 {
3717         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3718
3719         init_waitqueue_head(&priv->wait_command_queue);
3720
3721         INIT_WORK(&priv->restart, iwl_bg_restart);
3722         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3723         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3724         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3725         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3726         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3727         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3728         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3729         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3730
3731         iwl_setup_scan_deferred_work(priv);
3732
3733         if (priv->cfg->ops->lib->setup_deferred_work)
3734                 priv->cfg->ops->lib->setup_deferred_work(priv);
3735
3736         init_timer(&priv->statistics_periodic);
3737         priv->statistics_periodic.data = (unsigned long)priv;
3738         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3739
3740         init_timer(&priv->ucode_trace);
3741         priv->ucode_trace.data = (unsigned long)priv;
3742         priv->ucode_trace.function = iwl_bg_ucode_trace;
3743
3744         if (priv->cfg->ops->lib->recover_from_tx_stall) {
3745                 init_timer(&priv->monitor_recover);
3746                 priv->monitor_recover.data = (unsigned long)priv;
3747                 priv->monitor_recover.function =
3748                         priv->cfg->ops->lib->recover_from_tx_stall;
3749         }
3750
3751         if (!priv->cfg->base_params->use_isr_legacy)
3752                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3753                         iwl_irq_tasklet, (unsigned long)priv);
3754         else
3755                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3756                         iwl_irq_tasklet_legacy, (unsigned long)priv);
3757 }
3758
3759 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3760 {
3761         if (priv->cfg->ops->lib->cancel_deferred_work)
3762                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3763
3764         cancel_delayed_work_sync(&priv->init_alive_start);
3765         cancel_delayed_work(&priv->alive_start);
3766         cancel_work_sync(&priv->run_time_calib_work);
3767         cancel_work_sync(&priv->beacon_update);
3768
3769         iwl_cancel_scan_deferred_work(priv);
3770
3771         cancel_work_sync(&priv->bt_full_concurrency);
3772         cancel_work_sync(&priv->bt_runtime_config);
3773
3774         del_timer_sync(&priv->statistics_periodic);
3775         del_timer_sync(&priv->ucode_trace);
3776 }
3777
3778 static void iwl_init_hw_rates(struct iwl_priv *priv,
3779                               struct ieee80211_rate *rates)
3780 {
3781         int i;
3782
3783         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3784                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3785                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3786                 rates[i].hw_value_short = i;
3787                 rates[i].flags = 0;
3788                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3789                         /*
3790                          * If CCK != 1M then set short preamble rate flag.
3791                          */
3792                         rates[i].flags |=
3793                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3794                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3795                 }
3796         }
3797 }
3798
3799 static int iwl_init_drv(struct iwl_priv *priv)
3800 {
3801         int ret;
3802
3803         spin_lock_init(&priv->sta_lock);
3804         spin_lock_init(&priv->hcmd_lock);
3805
3806         INIT_LIST_HEAD(&priv->free_frames);
3807
3808         mutex_init(&priv->mutex);
3809         mutex_init(&priv->sync_cmd_mutex);
3810
3811         priv->ieee_channels = NULL;
3812         priv->ieee_rates = NULL;
3813         priv->band = IEEE80211_BAND_2GHZ;
3814
3815         priv->iw_mode = NL80211_IFTYPE_STATION;
3816         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3817         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3818         priv->_agn.agg_tids_count = 0;
3819
3820         /* initialize force reset */
3821         priv->force_reset[IWL_RF_RESET].reset_duration =
3822                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3823         priv->force_reset[IWL_FW_RESET].reset_duration =
3824                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3825
3826         /* Choose which receivers/antennas to use */
3827         if (priv->cfg->ops->hcmd->set_rxon_chain)
3828                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3829                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3830
3831         iwl_init_scan_params(priv);
3832
3833         /* init bt coex */
3834         if (priv->cfg->bt_params &&
3835             priv->cfg->bt_params->advanced_bt_coexist) {
3836                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3837                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3838                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3839                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3840                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3841                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3842         }
3843
3844         /* Set the tx_power_user_lmt to the lowest power level
3845          * this value will get overwritten by channel max power avg
3846          * from eeprom */
3847         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3848         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3849
3850         ret = iwl_init_channel_map(priv);
3851         if (ret) {
3852                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3853                 goto err;
3854         }
3855
3856         ret = iwlcore_init_geos(priv);
3857         if (ret) {
3858                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3859                 goto err_free_channel_map;
3860         }
3861         iwl_init_hw_rates(priv, priv->ieee_rates);
3862
3863         return 0;
3864
3865 err_free_channel_map:
3866         iwl_free_channel_map(priv);
3867 err:
3868         return ret;
3869 }
3870
3871 static void iwl_uninit_drv(struct iwl_priv *priv)
3872 {
3873         iwl_calib_free_results(priv);
3874         iwlcore_free_geos(priv);
3875         iwl_free_channel_map(priv);
3876         kfree(priv->scan_cmd);
3877 }
3878
3879 #ifdef CONFIG_IWL5000
3880 struct ieee80211_ops iwlagn_hw_ops = {
3881         .tx = iwlagn_mac_tx,
3882         .start = iwlagn_mac_start,
3883         .stop = iwlagn_mac_stop,
3884         .add_interface = iwl_mac_add_interface,
3885         .remove_interface = iwl_mac_remove_interface,
3886         .change_interface = iwl_mac_change_interface,
3887         .config = iwlagn_mac_config,
3888         .configure_filter = iwlagn_configure_filter,
3889         .set_key = iwlagn_mac_set_key,
3890         .update_tkip_key = iwlagn_mac_update_tkip_key,
3891         .conf_tx = iwl_mac_conf_tx,
3892         .bss_info_changed = iwlagn_bss_info_changed,
3893         .ampdu_action = iwlagn_mac_ampdu_action,
3894         .hw_scan = iwl_mac_hw_scan,
3895         .sta_notify = iwlagn_mac_sta_notify,
3896         .sta_add = iwlagn_mac_sta_add,
3897         .sta_remove = iwl_mac_sta_remove,
3898         .channel_switch = iwlagn_mac_channel_switch,
3899         .flush = iwlagn_mac_flush,
3900         .tx_last_beacon = iwl_mac_tx_last_beacon,
3901 };
3902 #endif
3903
3904 static void iwl_hw_detect(struct iwl_priv *priv)
3905 {
3906         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
3907         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
3908         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
3909         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3910 }
3911
3912 static int iwl_set_hw_params(struct iwl_priv *priv)
3913 {
3914         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3915         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3916         if (priv->cfg->mod_params->amsdu_size_8K)
3917                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3918         else
3919                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3920
3921         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3922
3923         if (priv->cfg->mod_params->disable_11n)
3924                 priv->cfg->sku &= ~IWL_SKU_N;
3925
3926         /* Device-specific setup */
3927         return priv->cfg->ops->lib->set_hw_params(priv);
3928 }
3929
3930 static const u8 iwlagn_bss_ac_to_fifo[] = {
3931         IWL_TX_FIFO_VO,
3932         IWL_TX_FIFO_VI,
3933         IWL_TX_FIFO_BE,
3934         IWL_TX_FIFO_BK,
3935 };
3936
3937 static const u8 iwlagn_bss_ac_to_queue[] = {
3938         0, 1, 2, 3,
3939 };
3940
3941 static const u8 iwlagn_pan_ac_to_fifo[] = {
3942         IWL_TX_FIFO_VO_IPAN,
3943         IWL_TX_FIFO_VI_IPAN,
3944         IWL_TX_FIFO_BE_IPAN,
3945         IWL_TX_FIFO_BK_IPAN,
3946 };
3947
3948 static const u8 iwlagn_pan_ac_to_queue[] = {
3949         7, 6, 5, 4,
3950 };
3951
3952 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3953 {
3954         int err = 0, i;
3955         struct iwl_priv *priv;
3956         struct ieee80211_hw *hw;
3957         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3958         unsigned long flags;
3959         u16 pci_cmd, num_mac;
3960
3961         /************************
3962          * 1. Allocating HW data
3963          ************************/
3964
3965         /* Disabling hardware scan means that mac80211 will perform scans
3966          * "the hard way", rather than using device's scan. */
3967         if (cfg->mod_params->disable_hw_scan) {
3968                 dev_printk(KERN_DEBUG, &(pdev->dev),
3969                         "sw scan support is deprecated\n");
3970 #ifdef CONFIG_IWL5000
3971                 iwlagn_hw_ops.hw_scan = NULL;
3972 #endif
3973 #ifdef CONFIG_IWL4965
3974                 iwl4965_hw_ops.hw_scan = NULL;
3975 #endif
3976         }
3977
3978         hw = iwl_alloc_all(cfg);
3979         if (!hw) {
3980                 err = -ENOMEM;
3981                 goto out;
3982         }
3983         priv = hw->priv;
3984         /* At this point both hw and priv are allocated. */
3985
3986         /*
3987          * The default context is always valid,
3988          * more may be discovered when firmware
3989          * is loaded.
3990          */
3991         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3992
3993         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3994                 priv->contexts[i].ctxid = i;
3995
3996         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3997         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3998         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3999         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4000         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4001         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4002         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4003         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4004         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4005         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4006         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4007                 BIT(NL80211_IFTYPE_ADHOC);
4008         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4009                 BIT(NL80211_IFTYPE_STATION);
4010         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
4011         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4012         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4013         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4014
4015         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4016         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4017         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4018         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4019         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4020         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4021         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4022         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4023         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4024         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4025         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4026         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4027                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4028         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4029         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4030         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4031
4032         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4033
4034         SET_IEEE80211_DEV(hw, &pdev->dev);
4035
4036         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4037         priv->cfg = cfg;
4038         priv->pci_dev = pdev;
4039         priv->inta_mask = CSR_INI_SET_MASK;
4040
4041         /* is antenna coupling more than 35dB ? */
4042         priv->bt_ant_couple_ok =
4043                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4044                 true : false;
4045
4046         /* enable/disable bt channel announcement */
4047         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4048
4049         if (iwl_alloc_traffic_mem(priv))
4050                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4051
4052         /**************************
4053          * 2. Initializing PCI bus
4054          **************************/
4055         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4056                                 PCIE_LINK_STATE_CLKPM);
4057
4058         if (pci_enable_device(pdev)) {
4059                 err = -ENODEV;
4060                 goto out_ieee80211_free_hw;
4061         }
4062
4063         pci_set_master(pdev);
4064
4065         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4066         if (!err)
4067                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4068         if (err) {
4069                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4070                 if (!err)
4071                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4072                 /* both attempts failed: */
4073                 if (err) {
4074                         IWL_WARN(priv, "No suitable DMA available.\n");
4075                         goto out_pci_disable_device;
4076                 }
4077         }
4078
4079         err = pci_request_regions(pdev, DRV_NAME);
4080         if (err)
4081                 goto out_pci_disable_device;
4082
4083         pci_set_drvdata(pdev, priv);
4084
4085
4086         /***********************
4087          * 3. Read REV register
4088          ***********************/
4089         priv->hw_base = pci_iomap(pdev, 0, 0);
4090         if (!priv->hw_base) {
4091                 err = -ENODEV;
4092                 goto out_pci_release_regions;
4093         }
4094
4095         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4096                 (unsigned long long) pci_resource_len(pdev, 0));
4097         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4098
4099         /* these spin locks will be used in apm_ops.init and EEPROM access
4100          * we should init now
4101          */
4102         spin_lock_init(&priv->reg_lock);
4103         spin_lock_init(&priv->lock);
4104
4105         /*
4106          * stop and reset the on-board processor just in case it is in a
4107          * strange state ... like being left stranded by a primary kernel
4108          * and this is now the kdump kernel trying to start up
4109          */
4110         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4111
4112         iwl_hw_detect(priv);
4113         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4114                 priv->cfg->name, priv->hw_rev);
4115
4116         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4117          * PCI Tx retries from interfering with C3 CPU state */
4118         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4119
4120         iwl_prepare_card_hw(priv);
4121         if (!priv->hw_ready) {
4122                 IWL_WARN(priv, "Failed, HW not ready\n");
4123                 goto out_iounmap;
4124         }
4125
4126         /*****************
4127          * 4. Read EEPROM
4128          *****************/
4129         /* Read the EEPROM */
4130         err = iwl_eeprom_init(priv);
4131         if (err) {
4132                 IWL_ERR(priv, "Unable to init EEPROM\n");
4133                 goto out_iounmap;
4134         }
4135         err = iwl_eeprom_check_version(priv);
4136         if (err)
4137                 goto out_free_eeprom;
4138
4139         err = iwl_eeprom_check_sku(priv);
4140         if (err)
4141                 goto out_free_eeprom;
4142
4143         /* extract MAC Address */
4144         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4145         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4146         priv->hw->wiphy->addresses = priv->addresses;
4147         priv->hw->wiphy->n_addresses = 1;
4148         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4149         if (num_mac > 1) {
4150                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4151                        ETH_ALEN);
4152                 priv->addresses[1].addr[5]++;
4153                 priv->hw->wiphy->n_addresses++;
4154         }
4155
4156         /************************
4157          * 5. Setup HW constants
4158          ************************/
4159         if (iwl_set_hw_params(priv)) {
4160                 IWL_ERR(priv, "failed to set hw parameters\n");
4161                 goto out_free_eeprom;
4162         }
4163
4164         /*******************
4165          * 6. Setup priv
4166          *******************/
4167
4168         err = iwl_init_drv(priv);
4169         if (err)
4170                 goto out_free_eeprom;
4171         /* At this point both hw and priv are initialized. */
4172
4173         /********************
4174          * 7. Setup services
4175          ********************/
4176         spin_lock_irqsave(&priv->lock, flags);
4177         iwl_disable_interrupts(priv);
4178         spin_unlock_irqrestore(&priv->lock, flags);
4179
4180         pci_enable_msi(priv->pci_dev);
4181
4182         if (priv->cfg->ops->lib->isr_ops.alloc)
4183                 priv->cfg->ops->lib->isr_ops.alloc(priv);
4184
4185         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
4186                           IRQF_SHARED, DRV_NAME, priv);
4187         if (err) {
4188                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4189                 goto out_disable_msi;
4190         }
4191
4192         iwl_setup_deferred_work(priv);
4193         iwl_setup_rx_handlers(priv);
4194
4195         /*********************************************
4196          * 8. Enable interrupts and read RFKILL state
4197          *********************************************/
4198
4199         /* enable interrupts if needed: hw bug w/a */
4200         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4201         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4202                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4203                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4204         }
4205
4206         iwl_enable_interrupts(priv);
4207
4208         /* If platform's RF_KILL switch is NOT set to KILL */
4209         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4210                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4211         else
4212                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4213
4214         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4215                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4216
4217         iwl_power_initialize(priv);
4218         iwl_tt_initialize(priv);
4219
4220         init_completion(&priv->_agn.firmware_loading_complete);
4221
4222         err = iwl_request_firmware(priv, true);
4223         if (err)
4224                 goto out_destroy_workqueue;
4225
4226         return 0;
4227
4228  out_destroy_workqueue:
4229         destroy_workqueue(priv->workqueue);
4230         priv->workqueue = NULL;
4231         free_irq(priv->pci_dev->irq, priv);
4232         if (priv->cfg->ops->lib->isr_ops.free)
4233                 priv->cfg->ops->lib->isr_ops.free(priv);
4234  out_disable_msi:
4235         pci_disable_msi(priv->pci_dev);
4236         iwl_uninit_drv(priv);
4237  out_free_eeprom:
4238         iwl_eeprom_free(priv);
4239  out_iounmap:
4240         pci_iounmap(pdev, priv->hw_base);
4241  out_pci_release_regions:
4242         pci_set_drvdata(pdev, NULL);
4243         pci_release_regions(pdev);
4244  out_pci_disable_device:
4245         pci_disable_device(pdev);
4246  out_ieee80211_free_hw:
4247         iwl_free_traffic_mem(priv);
4248         ieee80211_free_hw(priv->hw);
4249  out:
4250         return err;
4251 }
4252
4253 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4254 {
4255         struct iwl_priv *priv = pci_get_drvdata(pdev);
4256         unsigned long flags;
4257
4258         if (!priv)
4259                 return;
4260
4261         wait_for_completion(&priv->_agn.firmware_loading_complete);
4262
4263         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4264
4265         iwl_dbgfs_unregister(priv);
4266         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4267
4268         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4269          * to be called and iwl_down since we are removing the device
4270          * we need to set STATUS_EXIT_PENDING bit.
4271          */
4272         set_bit(STATUS_EXIT_PENDING, &priv->status);
4273         if (priv->mac80211_registered) {
4274                 ieee80211_unregister_hw(priv->hw);
4275                 priv->mac80211_registered = 0;
4276         } else {
4277                 iwl_down(priv);
4278         }
4279
4280         /*
4281          * Make sure device is reset to low power before unloading driver.
4282          * This may be redundant with iwl_down(), but there are paths to
4283          * run iwl_down() without calling apm_ops.stop(), and there are
4284          * paths to avoid running iwl_down() at all before leaving driver.
4285          * This (inexpensive) call *makes sure* device is reset.
4286          */
4287         iwl_apm_stop(priv);
4288
4289         iwl_tt_exit(priv);
4290
4291         /* make sure we flush any pending irq or
4292          * tasklet for the driver
4293          */
4294         spin_lock_irqsave(&priv->lock, flags);
4295         iwl_disable_interrupts(priv);
4296         spin_unlock_irqrestore(&priv->lock, flags);
4297
4298         iwl_synchronize_irq(priv);
4299
4300         iwl_dealloc_ucode_pci(priv);
4301
4302         if (priv->rxq.bd)
4303                 iwlagn_rx_queue_free(priv, &priv->rxq);
4304         iwlagn_hw_txq_ctx_free(priv);
4305
4306         iwl_eeprom_free(priv);
4307
4308
4309         /*netif_stop_queue(dev); */
4310         flush_workqueue(priv->workqueue);
4311
4312         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4313          * priv->workqueue... so we can't take down the workqueue
4314          * until now... */
4315         destroy_workqueue(priv->workqueue);
4316         priv->workqueue = NULL;
4317         iwl_free_traffic_mem(priv);
4318
4319         free_irq(priv->pci_dev->irq, priv);
4320         pci_disable_msi(priv->pci_dev);
4321         pci_iounmap(pdev, priv->hw_base);
4322         pci_release_regions(pdev);
4323         pci_disable_device(pdev);
4324         pci_set_drvdata(pdev, NULL);
4325
4326         iwl_uninit_drv(priv);
4327
4328         if (priv->cfg->ops->lib->isr_ops.free)
4329                 priv->cfg->ops->lib->isr_ops.free(priv);
4330
4331         dev_kfree_skb(priv->beacon_skb);
4332
4333         ieee80211_free_hw(priv->hw);
4334 }
4335
4336
4337 /*****************************************************************************
4338  *
4339  * driver and module entry point
4340  *
4341  *****************************************************************************/
4342
4343 /* Hardware specific file defines the PCI IDs table for that hardware module */
4344 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4345 #ifdef CONFIG_IWL4965
4346         {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4347         {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4348 #endif /* CONFIG_IWL4965 */
4349 #ifdef CONFIG_IWL5000
4350 /* 5100 Series WiFi */
4351         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4352         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4353         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4354         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4355         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4356         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4357         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4358         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4359         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4360         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4361         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4362         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4363         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4364         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4365         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4366         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4367         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4368         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4369         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4370         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4371         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4372         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4373         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4374         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4375
4376 /* 5300 Series WiFi */
4377         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4378         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4379         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4380         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4381         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4382         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4383         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4384         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4385         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4386         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4387         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4388         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4389
4390 /* 5350 Series WiFi/WiMax */
4391         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4392         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4393         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4394
4395 /* 5150 Series Wifi/WiMax */
4396         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4397         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4398         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4399         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4400         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4401         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4402
4403         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4404         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4405         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4406         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4407
4408 /* 6x00 Series */
4409         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4410         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4411         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4412         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4413         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4414         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4415         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4416         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4417         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4418         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4419
4420 /* 6x00 Series Gen2a */
4421         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4422         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4423         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4424         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4425         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4426         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4427         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
4428
4429 /* 6x00 Series Gen2b */
4430         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4431         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4432         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4433         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl6000g2b_bg_cfg)},
4434         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4435         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl6000g2b_bg_cfg)},
4436         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4437         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4438         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4439         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4440         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4441         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4442         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4443         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4444         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4445         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
4446
4447 /* 6x50 WiFi/WiMax Series */
4448         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4449         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4450         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4451         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4452         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4453         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4454
4455 /* 6x50 WiFi/WiMax Series Gen2 */
4456         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4457         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4458         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4459         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4460         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4461         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4462
4463 /* 1000 Series WiFi */
4464         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4465         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4466         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4467         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4468         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4469         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4470         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4471         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4472         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4473         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4474         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4475         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4476
4477 /* 100 Series WiFi */
4478         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4479         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4480         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4481         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4482         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4483         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4484
4485 /* 130 Series WiFi */
4486         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4487         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4488         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4489         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4490         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4491         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4492
4493 #endif /* CONFIG_IWL5000 */
4494
4495         {0}
4496 };
4497 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4498
4499 static struct pci_driver iwl_driver = {
4500         .name = DRV_NAME,
4501         .id_table = iwl_hw_card_ids,
4502         .probe = iwl_pci_probe,
4503         .remove = __devexit_p(iwl_pci_remove),
4504         .driver.pm = IWL_PM_OPS,
4505 };
4506
4507 static int __init iwl_init(void)
4508 {
4509
4510         int ret;
4511         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4512         pr_info(DRV_COPYRIGHT "\n");
4513
4514         ret = iwlagn_rate_control_register();
4515         if (ret) {
4516                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4517                 return ret;
4518         }
4519
4520         ret = pci_register_driver(&iwl_driver);
4521         if (ret) {
4522                 pr_err("Unable to initialize PCI module\n");
4523                 goto error_register;
4524         }
4525
4526         return ret;
4527
4528 error_register:
4529         iwlagn_rate_control_unregister();
4530         return ret;
4531 }
4532
4533 static void __exit iwl_exit(void)
4534 {
4535         pci_unregister_driver(&iwl_driver);
4536         iwlagn_rate_control_unregister();
4537 }
4538
4539 module_exit(iwl_exit);
4540 module_init(iwl_init);
4541
4542 #ifdef CONFIG_IWLWIFI_DEBUG
4543 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4544 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4545 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4546 MODULE_PARM_DESC(debug, "debug output mask");
4547 #endif
4548
4549 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4550 MODULE_PARM_DESC(swcrypto50,
4551                  "using crypto in software (default 0 [hardware]) (deprecated)");
4552 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4553 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4554 module_param_named(queues_num50,
4555                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4556 MODULE_PARM_DESC(queues_num50,
4557                  "number of hw queues in 50xx series (deprecated)");
4558 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4559 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4560 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4561 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4562 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4563 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4564 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4565                    int, S_IRUGO);
4566 MODULE_PARM_DESC(amsdu_size_8K50,
4567                  "enable 8K amsdu size in 50XX series (deprecated)");
4568 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4569                    int, S_IRUGO);
4570 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4571 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4572 MODULE_PARM_DESC(fw_restart50,
4573                  "restart firmware in case of error (deprecated)");
4574 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4575 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4576 module_param_named(
4577         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4578 MODULE_PARM_DESC(disable_hw_scan,
4579                  "disable hardware scanning (default 0) (deprecated)");
4580
4581 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4582                    S_IRUGO);
4583 MODULE_PARM_DESC(ucode_alternative,
4584                  "specify ucode alternative to use from ucode file");
4585
4586 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4587 MODULE_PARM_DESC(antenna_coupling,
4588                  "specify antenna coupling in dB (defualt: 0 dB)");
4589
4590 module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4591 MODULE_PARM_DESC(bt_ch_announce,
4592                  "Enable BT channel announcement mode (default: enable)");