drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-agn-calib.h"
  61 #include "iwl-agn.h"
  62 #include "iwl-agn-led.h"
  63
  64
  65 /******************************************************************************
  66  *
  67  * module boiler plate
  68  *
  69  ******************************************************************************/
  70
  71 /*
  72  * module name, copyright, version, etc.
  73  */
  74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  75
  76 #ifdef CONFIG_IWLWIFI_DEBUG
  77 #define VD "d"
  78 #else
  79 #define VD
  80 #endif
  81
  82 #define DRV_VERSION     IWLWIFI_VERSION VD
  83
  84
  85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86 MODULE_VERSION(DRV_VERSION);
  87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  88 MODULE_LICENSE("GPL");
  89
  90 static int iwlagn_ant_coupling;
  91 static bool iwlagn_bt_ch_announce = 1;
  92
  93 void iwl_update_chain_flags(struct iwl_priv *priv)
  94 {
  95         struct iwl_rxon_context *ctx;
  96
  97         if (priv->cfg->ops->hcmd->set_rxon_chain) {
  98                 for_each_context(priv, ctx) {
  99                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 100                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
 101                                 iwlcore_commit_rxon(priv, ctx);
 102                 }
 103         }
 104 }
 105
 106 static void iwl_clear_free_frames(struct iwl_priv *priv)
 107 {
 108         struct list_head *element;
 109
 110         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 111                        priv->frames_count);
 112
 113         while (!list_empty(&priv->free_frames)) {
 114                 element = priv->free_frames.next;
 115                 list_del(element);
 116                 kfree(list_entry(element, struct iwl_frame, list));
 117                 priv->frames_count--;
 118         }
 119
 120         if (priv->frames_count) {
 121                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 122                             priv->frames_count);
 123                 priv->frames_count = 0;
 124         }
 125 }
 126
 127 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 128 {
 129         struct iwl_frame *frame;
 130         struct list_head *element;
 131         if (list_empty(&priv->free_frames)) {
 132                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 133                 if (!frame) {
 134                         IWL_ERR(priv, "Could not allocate frame!\n");
 135                         return NULL;
 136                 }
 137
 138                 priv->frames_count++;
 139                 return frame;
 140         }
 141
 142         element = priv->free_frames.next;
 143         list_del(element);
 144         return list_entry(element, struct iwl_frame, list);
 145 }
 146
 147 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 148 {
 149         memset(frame, 0, sizeof(*frame));
 150         list_add(&frame->list, &priv->free_frames);
 151 }
 152
 153 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 154                                  struct ieee80211_hdr *hdr,
 155                                  int left)
 156 {
 157         lockdep_assert_held(&priv->mutex);
 158
 159         if (!priv->beacon_skb)
 160                 return 0;
 161
 162         if (priv->beacon_skb->len > left)
 163                 return 0;
 164
 165         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
 166
 167         return priv->beacon_skb->len;
 168 }
 169
 170 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 171 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 172                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 173                                u8 *beacon, u32 frame_size)
 174 {
 175         u16 tim_idx;
 176         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 177
 178         /*
 179          * The index is relative to frame start but we start looking at the
 180          * variable-length part of the beacon.
 181          */
 182         tim_idx = mgmt->u.beacon.variable - beacon;
 183
 184         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 185         while ((tim_idx < (frame_size - 2)) &&
 186                         (beacon[tim_idx] != WLAN_EID_TIM))
 187                 tim_idx += beacon[tim_idx+1] + 2;
 188
 189         /* If TIM field was found, set variables */
 190         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 191                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 192                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 193         } else
 194                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 195 }
 196
 197 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 198                                        struct iwl_frame *frame)
 199 {
 200         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 201         u32 frame_size;
 202         u32 rate_flags;
 203         u32 rate;
 204         /*
 205          * We have to set up the TX command, the TX Beacon command, and the
 206          * beacon contents.
 207          */
 208
 209         lockdep_assert_held(&priv->mutex);
 210
 211         if (!priv->beacon_ctx) {
 212                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 213                 return 0;
 214         }
 215
 216         /* Initialize memory */
 217         tx_beacon_cmd = &frame->u.beacon;
 218         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 219
 220         /* Set up TX beacon contents */
 221         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 222                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 223         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 224                 return 0;
 225         if (!frame_size)
 226                 return 0;
 227
 228         /* Set up TX command fields */
 229         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 230         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 231         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 232         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 233                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 234
 235         /* Set up TX beacon command fields */
 236         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 237                            frame_size);
 238
 239         /* Set up packet rate and flags */
 240         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 241         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 242                                               priv->hw_params.valid_tx_ant);
 243         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 244         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 245                 rate_flags |= RATE_MCS_CCK_MSK;
 246         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 247                         rate_flags);
 248
 249         return sizeof(*tx_beacon_cmd) + frame_size;
 250 }
 251
 252 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
 253 {
 254         struct iwl_frame *frame;
 255         unsigned int frame_size;
 256         int rc;
 257
 258         frame = iwl_get_free_frame(priv);
 259         if (!frame) {
 260                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 261                           "command.\n");
 262                 return -ENOMEM;
 263         }
 264
 265         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 266         if (!frame_size) {
 267                 IWL_ERR(priv, "Error configuring the beacon command\n");
 268                 iwl_free_frame(priv, frame);
 269                 return -EINVAL;
 270         }
 271
 272         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 273                               &frame->u.cmd[0]);
 274
 275         iwl_free_frame(priv, frame);
 276
 277         return rc;
 278 }
 279
 280 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 281 {
 282         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 283
 284         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 285         if (sizeof(dma_addr_t) > sizeof(u32))
 286                 addr |=
 287                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 288
 289         return addr;
 290 }
 291
 292 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 293 {
 294         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 295
 296         return le16_to_cpu(tb->hi_n_len) >> 4;
 297 }
 298
 299 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 300                                   dma_addr_t addr, u16 len)
 301 {
 302         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 303         u16 hi_n_len = len << 4;
 304
 305         put_unaligned_le32(addr, &tb->lo);
 306         if (sizeof(dma_addr_t) > sizeof(u32))
 307                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 308
 309         tb->hi_n_len = cpu_to_le16(hi_n_len);
 310
 311         tfd->num_tbs = idx + 1;
 312 }
 313
 314 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 315 {
 316         return tfd->num_tbs & 0x1f;
 317 }
 318
 319 /**
 320  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 321  * @priv - driver private data
 322  * @txq - tx queue
 323  *
 324  * Does NOT advance any TFD circular buffer read/write indexes
 325  * Does NOT free the TFD itself (which is within circular buffer)
 326  */
 327 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 328 {
 329         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 330         struct iwl_tfd *tfd;
 331         struct pci_dev *dev = priv->pci_dev;
 332         int index = txq->q.read_ptr;
 333         int i;
 334         int num_tbs;
 335
 336         tfd = &tfd_tmp[index];
 337
 338         /* Sanity check on number of chunks */
 339         num_tbs = iwl_tfd_get_num_tbs(tfd);
 340
 341         if (num_tbs >= IWL_NUM_OF_TBS) {
 342                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 343                 /* @todo issue fatal error, it is quite serious situation */
 344                 return;
 345         }
 346
 347         /* Unmap tx_cmd */
 348         if (num_tbs)
 349                 pci_unmap_single(dev,
 350                                 dma_unmap_addr(&txq->meta[index], mapping),
 351                                 dma_unmap_len(&txq->meta[index], len),
 352                                 PCI_DMA_BIDIRECTIONAL);
 353
 354         /* Unmap chunks, if any. */
 355         for (i = 1; i < num_tbs; i++)
 356                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 357                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 358
 359         /* free SKB */
 360         if (txq->txb) {
 361                 struct sk_buff *skb;
 362
 363                 skb = txq->txb[txq->q.read_ptr].skb;
 364
 365                 /* can be called from irqs-disabled context */
 366                 if (skb) {
 367                         dev_kfree_skb_any(skb);
 368                         txq->txb[txq->q.read_ptr].skb = NULL;
 369                 }
 370         }
 371 }
 372
 373 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 374                                  struct iwl_tx_queue *txq,
 375                                  dma_addr_t addr, u16 len,
 376                                  u8 reset, u8 pad)
 377 {
 378         struct iwl_queue *q;
 379         struct iwl_tfd *tfd, *tfd_tmp;
 380         u32 num_tbs;
 381
 382         q = &txq->q;
 383         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 384         tfd = &tfd_tmp[q->write_ptr];
 385
 386         if (reset)
 387                 memset(tfd, 0, sizeof(*tfd));
 388
 389         num_tbs = iwl_tfd_get_num_tbs(tfd);
 390
 391         /* Each TFD can point to a maximum 20 Tx buffers */
 392         if (num_tbs >= IWL_NUM_OF_TBS) {
 393                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 394                           IWL_NUM_OF_TBS);
 395                 return -EINVAL;
 396         }
 397
 398         BUG_ON(addr & ~DMA_BIT_MASK(36));
 399         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 400                 IWL_ERR(priv, "Unaligned address = %llx\n",
 401                           (unsigned long long)addr);
 402
 403         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 404
 405         return 0;
 406 }
 407
 408 /*
 409  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 410  * given Tx queue, and enable the DMA channel used for that queue.
 411  *
 412  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 413  * channels supported in hardware.
 414  */
 415 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 416                          struct iwl_tx_queue *txq)
 417 {
 418         int txq_id = txq->q.id;
 419
 420         /* Circular buffer (TFD queue in DRAM) physical base address */
 421         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 422                              txq->q.dma_addr >> 8);
 423
 424         return 0;
 425 }
 426
 427 static void iwl_bg_beacon_update(struct work_struct *work)
 428 {
 429         struct iwl_priv *priv =
 430                 container_of(work, struct iwl_priv, beacon_update);
 431         struct sk_buff *beacon;
 432
 433         mutex_lock(&priv->mutex);
 434         if (!priv->beacon_ctx) {
 435                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 436                 goto out;
 437         }
 438
 439         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 440                 /*
 441                  * The ucode will send beacon notifications even in
 442                  * IBSS mode, but we don't want to process them. But
 443                  * we need to defer the type check to here due to
 444                  * requiring locking around the beacon_ctx access.
 445                  */
 446                 goto out;
 447         }
 448
 449         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 450         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 451         if (!beacon) {
 452                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
 453                 goto out;
 454         }
 455
 456         /* new beacon skb is allocated every time; dispose previous.*/
 457         dev_kfree_skb(priv->beacon_skb);
 458
 459         priv->beacon_skb = beacon;
 460
 461         iwlagn_send_beacon_cmd(priv);
 462  out:
 463         mutex_unlock(&priv->mutex);
 464 }
 465
 466 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 467 {
 468         struct iwl_priv *priv =
 469                 container_of(work, struct iwl_priv, bt_runtime_config);
 470
 471         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 472                 return;
 473
 474         /* dont send host command if rf-kill is on */
 475         if (!iwl_is_ready_rf(priv))
 476                 return;
 477         priv->cfg->ops->hcmd->send_bt_config(priv);
 478 }
 479
 480 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 481 {
 482         struct iwl_priv *priv =
 483                 container_of(work, struct iwl_priv, bt_full_concurrency);
 484         struct iwl_rxon_context *ctx;
 485
 486         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 487                 return;
 488
 489         /* dont send host command if rf-kill is on */
 490         if (!iwl_is_ready_rf(priv))
 491                 return;
 492
 493         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 494                        priv->bt_full_concurrent ?
 495                        "full concurrency" : "3-wire");
 496
 497         /*
 498          * LQ & RXON updated cmds must be sent before BT Config cmd
 499          * to avoid 3-wire collisions
 500          */
 501         mutex_lock(&priv->mutex);
 502         for_each_context(priv, ctx) {
 503                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 504                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 505                 iwlcore_commit_rxon(priv, ctx);
 506         }
 507         mutex_unlock(&priv->mutex);
 508
 509         priv->cfg->ops->hcmd->send_bt_config(priv);
 510 }
 511
 512 /**
 513  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 514  *
 515  * This callback is provided in order to send a statistics request.
 516  *
 517  * This timer function is continually reset to execute within
 518  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 519  * was received.  We need to ensure we receive the statistics in order
 520  * to update the temperature used for calibrating the TXPOWER.
 521  */
 522 static void iwl_bg_statistics_periodic(unsigned long data)
 523 {
 524         struct iwl_priv *priv = (struct iwl_priv *)data;
 525
 526         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 527                 return;
 528
 529         /* dont send host command if rf-kill is on */
 530         if (!iwl_is_ready_rf(priv))
 531                 return;
 532
 533         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 534 }
 535
 536
 537 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 538                                         u32 start_idx, u32 num_events,
 539                                         u32 mode)
 540 {
 541         u32 i;
 542         u32 ptr;        /* SRAM byte address of log data */
 543         u32 ev, time, data; /* event log data */
 544         unsigned long reg_flags;
 545
 546         if (mode == 0)
 547                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 548         else
 549                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 550
 551         /* Make sure device is powered up for SRAM reads */
 552         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 553         if (iwl_grab_nic_access(priv)) {
 554                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 555                 return;
 556         }
 557
 558         /* Set starting address; reads will auto-increment */
 559         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 560         rmb();
 561
 562         /*
 563          * "time" is actually "data" for mode 0 (no timestamp).
 564          * place event id # at far right for easier visual parsing.
 565          */
 566         for (i = 0; i < num_events; i++) {
 567                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 568                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 569                 if (mode == 0) {
 570                         trace_iwlwifi_dev_ucode_cont_event(priv,
 571                                                         0, time, ev);
 572                 } else {
 573                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 574                         trace_iwlwifi_dev_ucode_cont_event(priv,
 575                                                 time, data, ev);
 576                 }
 577         }
 578         /* Allow device to power down */
 579         iwl_release_nic_access(priv);
 580         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 581 }
 582
 583 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 584 {
 585         u32 capacity;   /* event log capacity in # entries */
 586         u32 base;       /* SRAM byte address of event log header */
 587         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 588         u32 num_wraps;  /* # times uCode wrapped to top of log */
 589         u32 next_entry; /* index of next entry to be written by uCode */
 590
 591         if (priv->ucode_type == UCODE_INIT)
 592                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 593         else
 594                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 595         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 596                 capacity = iwl_read_targ_mem(priv, base);
 597                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 598                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 599                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 600         } else
 601                 return;
 602
 603         if (num_wraps == priv->event_log.num_wraps) {
 604                 iwl_print_cont_event_trace(priv,
 605                                        base, priv->event_log.next_entry,
 606                                        next_entry - priv->event_log.next_entry,
 607                                        mode);
 608                 priv->event_log.non_wraps_count++;
 609         } else {
 610                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 611                         priv->event_log.wraps_more_count++;
 612                 else
 613                         priv->event_log.wraps_once_count++;
 614                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 615                                 num_wraps - priv->event_log.num_wraps,
 616                                 next_entry, priv->event_log.next_entry);
 617                 if (next_entry < priv->event_log.next_entry) {
 618                         iwl_print_cont_event_trace(priv, base,
 619                                priv->event_log.next_entry,
 620                                capacity - priv->event_log.next_entry,
 621                                mode);
 622
 623                         iwl_print_cont_event_trace(priv, base, 0,
 624                                 next_entry, mode);
 625                 } else {
 626                         iwl_print_cont_event_trace(priv, base,
 627                                next_entry, capacity - next_entry,
 628                                mode);
 629
 630                         iwl_print_cont_event_trace(priv, base, 0,
 631                                 next_entry, mode);
 632                 }
 633         }
 634         priv->event_log.num_wraps = num_wraps;
 635         priv->event_log.next_entry = next_entry;
 636 }
 637
 638 /**
 639  * iwl_bg_ucode_trace - Timer callback to log ucode event
 640  *
 641  * The timer is continually set to execute every
 642  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 643  * this function is to perform continuous uCode event logging operation
 644  * if enabled
 645  */
 646 static void iwl_bg_ucode_trace(unsigned long data)
 647 {
 648         struct iwl_priv *priv = (struct iwl_priv *)data;
 649
 650         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 651                 return;
 652
 653         if (priv->event_log.ucode_trace) {
 654                 iwl_continuous_event_trace(priv);
 655                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 656                 mod_timer(&priv->ucode_trace,
 657                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 658         }
 659 }
 660
 661 static void iwl_bg_tx_flush(struct work_struct *work)
 662 {
 663         struct iwl_priv *priv =
 664                 container_of(work, struct iwl_priv, tx_flush);
 665
 666         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 667                 return;
 668
 669         /* do nothing if rf-kill is on */
 670         if (!iwl_is_ready_rf(priv))
 671                 return;
 672
 673         if (priv->cfg->ops->lib->txfifo_flush) {
 674                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 675                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 676         }
 677 }
 678
 679 /**
 680  * iwl_rx_handle - Main entry function for receiving responses from uCode
 681  *
 682  * Uses the priv->rx_handlers callback function array to invoke
 683  * the appropriate handlers, including command responses,
 684  * frame-received notifications, and other notifications.
 685  */
 686 static void iwl_rx_handle(struct iwl_priv *priv)
 687 {
 688         struct iwl_rx_mem_buffer *rxb;
 689         struct iwl_rx_packet *pkt;
 690         struct iwl_rx_queue *rxq = &priv->rxq;
 691         u32 r, i;
 692         int reclaim;
 693         unsigned long flags;
 694         u8 fill_rx = 0;
 695         u32 count = 8;
 696         int total_empty;
 697
 698         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 699          * buffer that the driver may process (last buffer filled by ucode). */
 700         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 701         i = rxq->read;
 702
 703         /* Rx interrupt, but nothing sent from uCode */
 704         if (i == r)
 705                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
 706
 707         /* calculate total frames need to be restock after handling RX */
 708         total_empty = r - rxq->write_actual;
 709         if (total_empty < 0)
 710                 total_empty += RX_QUEUE_SIZE;
 711
 712         if (total_empty > (RX_QUEUE_SIZE / 2))
 713                 fill_rx = 1;
 714
 715         while (i != r) {
 716                 int len;
 717
 718                 rxb = rxq->queue[i];
 719
 720                 /* If an RXB doesn't have a Rx queue slot associated with it,
 721                  * then a bug has been introduced in the queue refilling
 722                  * routines -- catch it here */
 723                 BUG_ON(rxb == NULL);
 724
 725                 rxq->queue[i] = NULL;
 726
 727                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
 728                                PAGE_SIZE << priv->hw_params.rx_page_order,
 729                                PCI_DMA_FROMDEVICE);
 730                 pkt = rxb_addr(rxb);
 731
 732                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 733                 len += sizeof(u32); /* account for status word */
 734                 trace_iwlwifi_dev_rx(priv, pkt, len);
 735
 736                 /* Reclaim a command buffer only if this packet is a response
 737                  *   to a (driver-originated) command.
 738                  * If the packet (e.g. Rx frame) originated from uCode,
 739                  *   there is no command buffer to reclaim.
 740                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 741                  *   but apparently a few don't get set; catch them here. */
 742                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 743                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 744                         (pkt->hdr.cmd != REPLY_RX) &&
 745                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 746                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 747                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 748                         (pkt->hdr.cmd != REPLY_TX);
 749
 750                 /*
 751                  * Do the notification wait before RX handlers so
 752                  * even if the RX handler consumes the RXB we have
 753                  * access to it in the notification wait entry.
 754                  */
 755                 if (!list_empty(&priv->_agn.notif_waits)) {
 756                         struct iwl_notification_wait *w;
 757
 758                         spin_lock(&priv->_agn.notif_wait_lock);
 759                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
 760                                 if (w->cmd == pkt->hdr.cmd) {
 761                                         w->triggered = true;
 762                                         if (w->fn)
 763                                                 w->fn(priv, pkt);
 764                                 }
 765                         }
 766                         spin_unlock(&priv->_agn.notif_wait_lock);
 767
 768                         wake_up_all(&priv->_agn.notif_waitq);
 769                 }
 770
 771                 /* Based on type of command response or notification,
 772                  *   handle those that need handling via function in
 773                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
 774                 if (priv->rx_handlers[pkt->hdr.cmd]) {
 775                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
 776                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 777                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
 778                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
 779                 } else {
 780                         /* No handling needed */
 781                         IWL_DEBUG_RX(priv,
 782                                 "r %d i %d No handler needed for %s, 0x%02x\n",
 783                                 r, i, get_cmd_string(pkt->hdr.cmd),
 784                                 pkt->hdr.cmd);
 785                 }
 786
 787                 /*
 788                  * XXX: After here, we should always check rxb->page
 789                  * against NULL before touching it or its virtual
 790                  * memory (pkt). Because some rx_handler might have
 791                  * already taken or freed the pages.
 792                  */
 793
 794                 if (reclaim) {
 795                         /* Invoke any callbacks, transfer the buffer to caller,
 796                          * and fire off the (possibly) blocking iwl_send_cmd()
 797                          * as we reclaim the driver command queue */
 798                         if (rxb->page)
 799                                 iwl_tx_cmd_complete(priv, rxb);
 800                         else
 801                                 IWL_WARN(priv, "Claim null rxb?\n");
 802                 }
 803
 804                 /* Reuse the page if possible. For notification packets and
 805                  * SKBs that fail to Rx correctly, add them back into the
 806                  * rx_free list for reuse later. */
 807                 spin_lock_irqsave(&rxq->lock, flags);
 808                 if (rxb->page != NULL) {
 809                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
 810                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
 811                                 PCI_DMA_FROMDEVICE);
 812                         list_add_tail(&rxb->list, &rxq->rx_free);
 813                         rxq->free_count++;
 814                 } else
 815                         list_add_tail(&rxb->list, &rxq->rx_used);
 816
 817                 spin_unlock_irqrestore(&rxq->lock, flags);
 818
 819                 i = (i + 1) & RX_QUEUE_MASK;
 820                 /* If there are a lot of unused frames,
 821                  * restock the Rx queue so ucode wont assert. */
 822                 if (fill_rx) {
 823                         count++;
 824                         if (count >= 8) {
 825                                 rxq->read = i;
 826                                 iwlagn_rx_replenish_now(priv);
 827                                 count = 0;
 828                         }
 829                 }
 830         }
 831
 832         /* Backtrack one entry */
 833         rxq->read = i;
 834         if (fill_rx)
 835                 iwlagn_rx_replenish_now(priv);
 836         else
 837                 iwlagn_rx_queue_restock(priv);
 838 }
 839
 840 /* call this function to flush any scheduled tasklet */
 841 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
 842 {
 843         /* wait to make sure we flush pending tasklet*/
 844         synchronize_irq(priv->pci_dev->irq);
 845         tasklet_kill(&priv->irq_tasklet);
 846 }
 847
 848 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
 849 {
 850         u32 inta, handled = 0;
 851         u32 inta_fh;
 852         unsigned long flags;
 853         u32 i;
 854 #ifdef CONFIG_IWLWIFI_DEBUG
 855         u32 inta_mask;
 856 #endif
 857
 858         spin_lock_irqsave(&priv->lock, flags);
 859
 860         /* Ack/clear/reset pending uCode interrupts.
 861          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 862          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
 863         inta = iwl_read32(priv, CSR_INT);
 864         iwl_write32(priv, CSR_INT, inta);
 865
 866         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
 867          * Any new interrupts that happen after this, either while we're
 868          * in this tasklet, or later, will show up in next ISR/tasklet. */
 869         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
 870         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
 871
 872 #ifdef CONFIG_IWLWIFI_DEBUG
 873         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
 874                 /* just for debug */
 875                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
 876                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
 877                               inta, inta_mask, inta_fh);
 878         }
 879 #endif
 880
 881         spin_unlock_irqrestore(&priv->lock, flags);
 882
 883         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
 884          * atomic, make sure that inta covers all the interrupts that
 885          * we've discovered, even if FH interrupt came in just after
 886          * reading CSR_INT. */
 887         if (inta_fh & CSR49_FH_INT_RX_MASK)
 888                 inta |= CSR_INT_BIT_FH_RX;
 889         if (inta_fh & CSR49_FH_INT_TX_MASK)
 890                 inta |= CSR_INT_BIT_FH_TX;
 891
 892         /* Now service all interrupt bits discovered above. */
 893         if (inta & CSR_INT_BIT_HW_ERR) {
 894                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
 895
 896                 /* Tell the device to stop sending interrupts */
 897                 iwl_disable_interrupts(priv);
 898
 899                 priv->isr_stats.hw++;
 900                 iwl_irq_handle_error(priv);
 901
 902                 handled |= CSR_INT_BIT_HW_ERR;
 903
 904                 return;
 905         }
 906
 907 #ifdef CONFIG_IWLWIFI_DEBUG
 908         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
 909                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 910                 if (inta & CSR_INT_BIT_SCD) {
 911                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
 912                                       "the frame/frames.\n");
 913                         priv->isr_stats.sch++;
 914                 }
 915
 916                 /* Alive notification via Rx interrupt will do the real work */
 917                 if (inta & CSR_INT_BIT_ALIVE) {
 918                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
 919                         priv->isr_stats.alive++;
 920                 }
 921         }
 922 #endif
 923         /* Safely ignore these bits for debug checks below */
 924         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 925
 926         /* HW RF KILL switch toggled */
 927         if (inta & CSR_INT_BIT_RF_KILL) {
 928                 int hw_rf_kill = 0;
 929                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
 930                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
 931                         hw_rf_kill = 1;
 932
 933                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
 934                                 hw_rf_kill ? "disable radio" : "enable radio");
 935
 936                 priv->isr_stats.rfkill++;
 937
 938                 /* driver only loads ucode once setting the interface up.
 939                  * the driver allows loading the ucode even if the radio
 940                  * is killed. Hence update the killswitch state here. The
 941                  * rfkill handler will care about restarting if needed.
 942                  */
 943                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
 944                         if (hw_rf_kill)
 945                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 946                         else
 947                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 948                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
 949                 }
 950
 951                 handled |= CSR_INT_BIT_RF_KILL;
 952         }
 953
 954         /* Chip got too hot and stopped itself */
 955         if (inta & CSR_INT_BIT_CT_KILL) {
 956                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
 957                 priv->isr_stats.ctkill++;
 958                 handled |= CSR_INT_BIT_CT_KILL;
 959         }
 960
 961         /* Error detected by uCode */
 962         if (inta & CSR_INT_BIT_SW_ERR) {
 963                 IWL_ERR(priv, "Microcode SW error detected. "
 964                         " Restarting 0x%X.\n", inta);
 965                 priv->isr_stats.sw++;
 966                 iwl_irq_handle_error(priv);
 967                 handled |= CSR_INT_BIT_SW_ERR;
 968         }
 969
 970         /*
 971          * uCode wakes up after power-down sleep.
 972          * Tell device about any new tx or host commands enqueued,
 973          * and about any Rx buffers made available while asleep.
 974          */
 975         if (inta & CSR_INT_BIT_WAKEUP) {
 976                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
 977                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
 978                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
 979                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
 980                 priv->isr_stats.wakeup++;
 981                 handled |= CSR_INT_BIT_WAKEUP;
 982         }
 983
 984         /* All uCode command responses, including Tx command responses,
 985          * Rx "responses" (frame-received notification), and other
 986          * notifications from uCode come through here*/
 987         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
 988                 iwl_rx_handle(priv);
 989                 priv->isr_stats.rx++;
 990                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
 991         }
 992
 993         /* This "Tx" DMA channel is used only for loading uCode */
 994         if (inta & CSR_INT_BIT_FH_TX) {
 995                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
 996                 priv->isr_stats.tx++;
 997                 handled |= CSR_INT_BIT_FH_TX;
 998                 /* Wake up uCode load routine, now that load is complete */
 999                 priv->ucode_write_complete = 1;
1000                 wake_up_interruptible(&priv->wait_command_queue);
1001         }
1002
1003         if (inta & ~handled) {
1004                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1005                 priv->isr_stats.unhandled++;
1006         }
1007
1008         if (inta & ~(priv->inta_mask)) {
1009                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1010                          inta & ~priv->inta_mask);
1011                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1012         }
1013
1014         /* Re-enable all interrupts */
1015         /* only Re-enable if disabled by irq */
1016         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1017                 iwl_enable_interrupts(priv);
1018         /* Re-enable RF_KILL if it occurred */
1019         else if (handled & CSR_INT_BIT_RF_KILL)
1020                 iwl_enable_rfkill_int(priv);
1021
1022 #ifdef CONFIG_IWLWIFI_DEBUG
1023         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1024                 inta = iwl_read32(priv, CSR_INT);
1025                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1026                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1027                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1028                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1029         }
1030 #endif
1031 }
1032
1033 /* tasklet for iwlagn interrupt */
1034 static void iwl_irq_tasklet(struct iwl_priv *priv)
1035 {
1036         u32 inta = 0;
1037         u32 handled = 0;
1038         unsigned long flags;
1039         u32 i;
1040 #ifdef CONFIG_IWLWIFI_DEBUG
1041         u32 inta_mask;
1042 #endif
1043
1044         spin_lock_irqsave(&priv->lock, flags);
1045
1046         /* Ack/clear/reset pending uCode interrupts.
1047          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1048          */
1049         /* There is a hardware bug in the interrupt mask function that some
1050          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1051          * they are disabled in the CSR_INT_MASK register. Furthermore the
1052          * ICT interrupt handling mechanism has another bug that might cause
1053          * these unmasked interrupts fail to be detected. We workaround the
1054          * hardware bugs here by ACKing all the possible interrupts so that
1055          * interrupt coalescing can still be achieved.
1056          */
1057         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1058
1059         inta = priv->_agn.inta;
1060
1061 #ifdef CONFIG_IWLWIFI_DEBUG
1062         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1063                 /* just for debug */
1064                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1065                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1066                                 inta, inta_mask);
1067         }
1068 #endif
1069
1070         spin_unlock_irqrestore(&priv->lock, flags);
1071
1072         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1073         priv->_agn.inta = 0;
1074
1075         /* Now service all interrupt bits discovered above. */
1076         if (inta & CSR_INT_BIT_HW_ERR) {
1077                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1078
1079                 /* Tell the device to stop sending interrupts */
1080                 iwl_disable_interrupts(priv);
1081
1082                 priv->isr_stats.hw++;
1083                 iwl_irq_handle_error(priv);
1084
1085                 handled |= CSR_INT_BIT_HW_ERR;
1086
1087                 return;
1088         }
1089
1090 #ifdef CONFIG_IWLWIFI_DEBUG
1091         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1092                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1093                 if (inta & CSR_INT_BIT_SCD) {
1094                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1095                                       "the frame/frames.\n");
1096                         priv->isr_stats.sch++;
1097                 }
1098
1099                 /* Alive notification via Rx interrupt will do the real work */
1100                 if (inta & CSR_INT_BIT_ALIVE) {
1101                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1102                         priv->isr_stats.alive++;
1103                 }
1104         }
1105 #endif
1106         /* Safely ignore these bits for debug checks below */
1107         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1108
1109         /* HW RF KILL switch toggled */
1110         if (inta & CSR_INT_BIT_RF_KILL) {
1111                 int hw_rf_kill = 0;
1112                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1113                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1114                         hw_rf_kill = 1;
1115
1116                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1117                                 hw_rf_kill ? "disable radio" : "enable radio");
1118
1119                 priv->isr_stats.rfkill++;
1120
1121                 /* driver only loads ucode once setting the interface up.
1122                  * the driver allows loading the ucode even if the radio
1123                  * is killed. Hence update the killswitch state here. The
1124                  * rfkill handler will care about restarting if needed.
1125                  */
1126                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1127                         if (hw_rf_kill)
1128                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1129                         else
1130                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1131                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1132                 }
1133
1134                 handled |= CSR_INT_BIT_RF_KILL;
1135         }
1136
1137         /* Chip got too hot and stopped itself */
1138         if (inta & CSR_INT_BIT_CT_KILL) {
1139                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1140                 priv->isr_stats.ctkill++;
1141                 handled |= CSR_INT_BIT_CT_KILL;
1142         }
1143
1144         /* Error detected by uCode */
1145         if (inta & CSR_INT_BIT_SW_ERR) {
1146                 IWL_ERR(priv, "Microcode SW error detected. "
1147                         " Restarting 0x%X.\n", inta);
1148                 priv->isr_stats.sw++;
1149                 iwl_irq_handle_error(priv);
1150                 handled |= CSR_INT_BIT_SW_ERR;
1151         }
1152
1153         /* uCode wakes up after power-down sleep */
1154         if (inta & CSR_INT_BIT_WAKEUP) {
1155                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1156                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1157                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1158                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1159
1160                 priv->isr_stats.wakeup++;
1161
1162                 handled |= CSR_INT_BIT_WAKEUP;
1163         }
1164
1165         /* All uCode command responses, including Tx command responses,
1166          * Rx "responses" (frame-received notification), and other
1167          * notifications from uCode come through here*/
1168         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1169                         CSR_INT_BIT_RX_PERIODIC)) {
1170                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1171                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1172                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1173                         iwl_write32(priv, CSR_FH_INT_STATUS,
1174                                         CSR49_FH_INT_RX_MASK);
1175                 }
1176                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1177                         handled |= CSR_INT_BIT_RX_PERIODIC;
1178                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1179                 }
1180                 /* Sending RX interrupt require many steps to be done in the
1181                  * the device:
1182                  * 1- write interrupt to current index in ICT table.
1183                  * 2- dma RX frame.
1184                  * 3- update RX shared data to indicate last write index.
1185                  * 4- send interrupt.
1186                  * This could lead to RX race, driver could receive RX interrupt
1187                  * but the shared data changes does not reflect this;
1188                  * periodic interrupt will detect any dangling Rx activity.
1189                  */
1190
1191                 /* Disable periodic interrupt; we use it as just a one-shot. */
1192                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1193                             CSR_INT_PERIODIC_DIS);
1194                 iwl_rx_handle(priv);
1195
1196                 /*
1197                  * Enable periodic interrupt in 8 msec only if we received
1198                  * real RX interrupt (instead of just periodic int), to catch
1199                  * any dangling Rx interrupt.  If it was just the periodic
1200                  * interrupt, there was no dangling Rx activity, and no need
1201                  * to extend the periodic interrupt; one-shot is enough.
1202                  */
1203                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1204                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1205                                     CSR_INT_PERIODIC_ENA);
1206
1207                 priv->isr_stats.rx++;
1208         }
1209
1210         /* This "Tx" DMA channel is used only for loading uCode */
1211         if (inta & CSR_INT_BIT_FH_TX) {
1212                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1213                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1214                 priv->isr_stats.tx++;
1215                 handled |= CSR_INT_BIT_FH_TX;
1216                 /* Wake up uCode load routine, now that load is complete */
1217                 priv->ucode_write_complete = 1;
1218                 wake_up_interruptible(&priv->wait_command_queue);
1219         }
1220
1221         if (inta & ~handled) {
1222                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1223                 priv->isr_stats.unhandled++;
1224         }
1225
1226         if (inta & ~(priv->inta_mask)) {
1227                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1228                          inta & ~priv->inta_mask);
1229         }
1230
1231         /* Re-enable all interrupts */
1232         /* only Re-enable if disabled by irq */
1233         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1234                 iwl_enable_interrupts(priv);
1235         /* Re-enable RF_KILL if it occurred */
1236         else if (handled & CSR_INT_BIT_RF_KILL)
1237                 iwl_enable_rfkill_int(priv);
1238 }
1239
1240 /*****************************************************************************
1241  *
1242  * sysfs attributes
1243  *
1244  *****************************************************************************/
1245
1246 #ifdef CONFIG_IWLWIFI_DEBUG
1247
1248 /*
1249  * The following adds a new attribute to the sysfs representation
1250  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1251  * used for controlling the debug level.
1252  *
1253  * See the level definitions in iwl for details.
1254  *
1255  * The debug_level being managed using sysfs below is a per device debug
1256  * level that is used instead of the global debug level if it (the per
1257  * device debug level) is set.
1258  */
1259 static ssize_t show_debug_level(struct device *d,
1260                                 struct device_attribute *attr, char *buf)
1261 {
1262         struct iwl_priv *priv = dev_get_drvdata(d);
1263         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1264 }
1265 static ssize_t store_debug_level(struct device *d,
1266                                 struct device_attribute *attr,
1267                                  const char *buf, size_t count)
1268 {
1269         struct iwl_priv *priv = dev_get_drvdata(d);
1270         unsigned long val;
1271         int ret;
1272
1273         ret = strict_strtoul(buf, 0, &val);
1274         if (ret)
1275                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1276         else {
1277                 priv->debug_level = val;
1278                 if (iwl_alloc_traffic_mem(priv))
1279                         IWL_ERR(priv,
1280                                 "Not enough memory to generate traffic log\n");
1281         }
1282         return strnlen(buf, count);
1283 }
1284
1285 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1286                         show_debug_level, store_debug_level);
1287
1288
1289 #endif /* CONFIG_IWLWIFI_DEBUG */
1290
1291
1292 static ssize_t show_temperature(struct device *d,
1293                                 struct device_attribute *attr, char *buf)
1294 {
1295         struct iwl_priv *priv = dev_get_drvdata(d);
1296
1297         if (!iwl_is_alive(priv))
1298                 return -EAGAIN;
1299
1300         return sprintf(buf, "%d\n", priv->temperature);
1301 }
1302
1303 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1304
1305 static ssize_t show_tx_power(struct device *d,
1306                              struct device_attribute *attr, char *buf)
1307 {
1308         struct iwl_priv *priv = dev_get_drvdata(d);
1309
1310         if (!iwl_is_ready_rf(priv))
1311                 return sprintf(buf, "off\n");
1312         else
1313                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1314 }
1315
1316 static ssize_t store_tx_power(struct device *d,
1317                               struct device_attribute *attr,
1318                               const char *buf, size_t count)
1319 {
1320         struct iwl_priv *priv = dev_get_drvdata(d);
1321         unsigned long val;
1322         int ret;
1323
1324         ret = strict_strtoul(buf, 10, &val);
1325         if (ret)
1326                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1327         else {
1328                 ret = iwl_set_tx_power(priv, val, false);
1329                 if (ret)
1330                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1331                                 ret);
1332                 else
1333                         ret = count;
1334         }
1335         return ret;
1336 }
1337
1338 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1339
1340 static struct attribute *iwl_sysfs_entries[] = {
1341         &dev_attr_temperature.attr,
1342         &dev_attr_tx_power.attr,
1343 #ifdef CONFIG_IWLWIFI_DEBUG
1344         &dev_attr_debug_level.attr,
1345 #endif
1346         NULL
1347 };
1348
1349 static struct attribute_group iwl_attribute_group = {
1350         .name = NULL,           /* put in device directory */
1351         .attrs = iwl_sysfs_entries,
1352 };
1353
1354 /******************************************************************************
1355  *
1356  * uCode download functions
1357  *
1358  ******************************************************************************/
1359
1360 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1361 {
1362         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1363         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1364         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1365         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1366         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1367         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1368 }
1369
1370 static void iwl_nic_start(struct iwl_priv *priv)
1371 {
1372         /* Remove all resets to allow NIC to operate */
1373         iwl_write32(priv, CSR_RESET, 0);
1374 }
1375
1376 struct iwlagn_ucode_capabilities {
1377         u32 max_probe_length;
1378         u32 standard_phy_calibration_size;
1379         bool pan;
1380 };
1381
1382 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1383 static int iwl_mac_setup_register(struct iwl_priv *priv,
1384                                   struct iwlagn_ucode_capabilities *capa);
1385
1386 #define UCODE_EXPERIMENTAL_INDEX        100
1387 #define UCODE_EXPERIMENTAL_TAG          "exp"
1388
1389 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1390 {
1391         const char *name_pre = priv->cfg->fw_name_pre;
1392         char tag[8];
1393
1394         if (first) {
1395 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1396                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1397                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1398         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1399 #endif
1400                 priv->fw_index = priv->cfg->ucode_api_max;
1401                 sprintf(tag, "%d", priv->fw_index);
1402         } else {
1403                 priv->fw_index--;
1404                 sprintf(tag, "%d", priv->fw_index);
1405         }
1406
1407         if (priv->fw_index < priv->cfg->ucode_api_min) {
1408                 IWL_ERR(priv, "no suitable firmware found!\n");
1409                 return -ENOENT;
1410         }
1411
1412         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1413
1414         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1415                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1416                                 ? "EXPERIMENTAL " : "",
1417                        priv->firmware_name);
1418
1419         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1420                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1421                                        iwl_ucode_callback);
1422 }
1423
1424 struct iwlagn_firmware_pieces {
1425         const void *inst, *data, *init, *init_data, *boot;
1426         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1427
1428         u32 build;
1429
1430         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1431         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1432 };
1433
1434 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1435                                        const struct firmware *ucode_raw,
1436                                        struct iwlagn_firmware_pieces *pieces)
1437 {
1438         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1439         u32 api_ver, hdr_size;
1440         const u8 *src;
1441
1442         priv->ucode_ver = le32_to_cpu(ucode->ver);
1443         api_ver = IWL_UCODE_API(priv->ucode_ver);
1444
1445         switch (api_ver) {
1446         default:
1447                 /*
1448                  * 4965 doesn't revision the firmware file format
1449                  * along with the API version, it always uses v1
1450                  * file format.
1451                  */
1452                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1453                                 CSR_HW_REV_TYPE_4965) {
1454                         hdr_size = 28;
1455                         if (ucode_raw->size < hdr_size) {
1456                                 IWL_ERR(priv, "File size too small!\n");
1457                                 return -EINVAL;
1458                         }
1459                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1460                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1461                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1462                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1463                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1464                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1465                         src = ucode->u.v2.data;
1466                         break;
1467                 }
1468                 /* fall through for 4965 */
1469         case 0:
1470         case 1:
1471         case 2:
1472                 hdr_size = 24;
1473                 if (ucode_raw->size < hdr_size) {
1474                         IWL_ERR(priv, "File size too small!\n");
1475                         return -EINVAL;
1476                 }
1477                 pieces->build = 0;
1478                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1479                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1480                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1481                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1482                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1483                 src = ucode->u.v1.data;
1484                 break;
1485         }
1486
1487         /* Verify size of file vs. image size info in file's header */
1488         if (ucode_raw->size != hdr_size + pieces->inst_size +
1489                                 pieces->data_size + pieces->init_size +
1490                                 pieces->init_data_size + pieces->boot_size) {
1491
1492                 IWL_ERR(priv,
1493                         "uCode file size %d does not match expected size\n",
1494                         (int)ucode_raw->size);
1495                 return -EINVAL;
1496         }
1497
1498         pieces->inst = src;
1499         src += pieces->inst_size;
1500         pieces->data = src;
1501         src += pieces->data_size;
1502         pieces->init = src;
1503         src += pieces->init_size;
1504         pieces->init_data = src;
1505         src += pieces->init_data_size;
1506         pieces->boot = src;
1507         src += pieces->boot_size;
1508
1509         return 0;
1510 }
1511
1512 static int iwlagn_wanted_ucode_alternative = 1;
1513
1514 static int iwlagn_load_firmware(struct iwl_priv *priv,
1515                                 const struct firmware *ucode_raw,
1516                                 struct iwlagn_firmware_pieces *pieces,
1517                                 struct iwlagn_ucode_capabilities *capa)
1518 {
1519         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1520         struct iwl_ucode_tlv *tlv;
1521         size_t len = ucode_raw->size;
1522         const u8 *data;
1523         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1524         u64 alternatives;
1525         u32 tlv_len;
1526         enum iwl_ucode_tlv_type tlv_type;
1527         const u8 *tlv_data;
1528
1529         if (len < sizeof(*ucode)) {
1530                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1531                 return -EINVAL;
1532         }
1533
1534         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1535                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1536                         le32_to_cpu(ucode->magic));
1537                 return -EINVAL;
1538         }
1539
1540         /*
1541          * Check which alternatives are present, and "downgrade"
1542          * when the chosen alternative is not present, warning
1543          * the user when that happens. Some files may not have
1544          * any alternatives, so don't warn in that case.
1545          */
1546         alternatives = le64_to_cpu(ucode->alternatives);
1547         tmp = wanted_alternative;
1548         if (wanted_alternative > 63)
1549                 wanted_alternative = 63;
1550         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1551                 wanted_alternative--;
1552         if (wanted_alternative && wanted_alternative != tmp)
1553                 IWL_WARN(priv,
1554                          "uCode alternative %d not available, choosing %d\n",
1555                          tmp, wanted_alternative);
1556
1557         priv->ucode_ver = le32_to_cpu(ucode->ver);
1558         pieces->build = le32_to_cpu(ucode->build);
1559         data = ucode->data;
1560
1561         len -= sizeof(*ucode);
1562
1563         while (len >= sizeof(*tlv)) {
1564                 u16 tlv_alt;
1565
1566                 len -= sizeof(*tlv);
1567                 tlv = (void *)data;
1568
1569                 tlv_len = le32_to_cpu(tlv->length);
1570                 tlv_type = le16_to_cpu(tlv->type);
1571                 tlv_alt = le16_to_cpu(tlv->alternative);
1572                 tlv_data = tlv->data;
1573
1574                 if (len < tlv_len) {
1575                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1576                                 len, tlv_len);
1577                         return -EINVAL;
1578                 }
1579                 len -= ALIGN(tlv_len, 4);
1580                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1581
1582                 /*
1583                  * Alternative 0 is always valid.
1584                  *
1585                  * Skip alternative TLVs that are not selected.
1586                  */
1587                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1588                         continue;
1589
1590                 switch (tlv_type) {
1591                 case IWL_UCODE_TLV_INST:
1592                         pieces->inst = tlv_data;
1593                         pieces->inst_size = tlv_len;
1594                         break;
1595                 case IWL_UCODE_TLV_DATA:
1596                         pieces->data = tlv_data;
1597                         pieces->data_size = tlv_len;
1598                         break;
1599                 case IWL_UCODE_TLV_INIT:
1600                         pieces->init = tlv_data;
1601                         pieces->init_size = tlv_len;
1602                         break;
1603                 case IWL_UCODE_TLV_INIT_DATA:
1604                         pieces->init_data = tlv_data;
1605                         pieces->init_data_size = tlv_len;
1606                         break;
1607                 case IWL_UCODE_TLV_BOOT:
1608                         pieces->boot = tlv_data;
1609                         pieces->boot_size = tlv_len;
1610                         break;
1611                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1612                         if (tlv_len != sizeof(u32))
1613                                 goto invalid_tlv_len;
1614                         capa->max_probe_length =
1615                                         le32_to_cpup((__le32 *)tlv_data);
1616                         break;
1617                 case IWL_UCODE_TLV_PAN:
1618                         if (tlv_len)
1619                                 goto invalid_tlv_len;
1620                         capa->pan = true;
1621                         break;
1622                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1623                         if (tlv_len != sizeof(u32))
1624                                 goto invalid_tlv_len;
1625                         pieces->init_evtlog_ptr =
1626                                         le32_to_cpup((__le32 *)tlv_data);
1627                         break;
1628                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1629                         if (tlv_len != sizeof(u32))
1630                                 goto invalid_tlv_len;
1631                         pieces->init_evtlog_size =
1632                                         le32_to_cpup((__le32 *)tlv_data);
1633                         break;
1634                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1635                         if (tlv_len != sizeof(u32))
1636                                 goto invalid_tlv_len;
1637                         pieces->init_errlog_ptr =
1638                                         le32_to_cpup((__le32 *)tlv_data);
1639                         break;
1640                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1641                         if (tlv_len != sizeof(u32))
1642                                 goto invalid_tlv_len;
1643                         pieces->inst_evtlog_ptr =
1644                                         le32_to_cpup((__le32 *)tlv_data);
1645                         break;
1646                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1647                         if (tlv_len != sizeof(u32))
1648                                 goto invalid_tlv_len;
1649                         pieces->inst_evtlog_size =
1650                                         le32_to_cpup((__le32 *)tlv_data);
1651                         break;
1652                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1653                         if (tlv_len != sizeof(u32))
1654                                 goto invalid_tlv_len;
1655                         pieces->inst_errlog_ptr =
1656                                         le32_to_cpup((__le32 *)tlv_data);
1657                         break;
1658                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1659                         if (tlv_len)
1660                                 goto invalid_tlv_len;
1661                         priv->enhance_sensitivity_table = true;
1662                         break;
1663                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1664                         if (tlv_len != sizeof(u32))
1665                                 goto invalid_tlv_len;
1666                         capa->standard_phy_calibration_size =
1667                                         le32_to_cpup((__le32 *)tlv_data);
1668                         break;
1669                 default:
1670                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1671                         break;
1672                 }
1673         }
1674
1675         if (len) {
1676                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1677                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1678                 return -EINVAL;
1679         }
1680
1681         return 0;
1682
1683  invalid_tlv_len:
1684         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1685         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1686
1687         return -EINVAL;
1688 }
1689
1690 /**
1691  * iwl_ucode_callback - callback when firmware was loaded
1692  *
1693  * If loaded successfully, copies the firmware into buffers
1694  * for the card to fetch (via DMA).
1695  */
1696 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1697 {
1698         struct iwl_priv *priv = context;
1699         struct iwl_ucode_header *ucode;
1700         int err;
1701         struct iwlagn_firmware_pieces pieces;
1702         const unsigned int api_max = priv->cfg->ucode_api_max;
1703         const unsigned int api_min = priv->cfg->ucode_api_min;
1704         u32 api_ver;
1705         char buildstr[25];
1706         u32 build;
1707         struct iwlagn_ucode_capabilities ucode_capa = {
1708                 .max_probe_length = 200,
1709                 .standard_phy_calibration_size =
1710                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1711         };
1712
1713         memset(&pieces, 0, sizeof(pieces));
1714
1715         if (!ucode_raw) {
1716                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1717                         IWL_ERR(priv,
1718                                 "request for firmware file '%s' failed.\n",
1719                                 priv->firmware_name);
1720                 goto try_again;
1721         }
1722
1723         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1724                        priv->firmware_name, ucode_raw->size);
1725
1726         /* Make sure that we got at least the API version number */
1727         if (ucode_raw->size < 4) {
1728                 IWL_ERR(priv, "File size way too small!\n");
1729                 goto try_again;
1730         }
1731
1732         /* Data from ucode file:  header followed by uCode images */
1733         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1734
1735         if (ucode->ver)
1736                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1737         else
1738                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1739                                            &ucode_capa);
1740
1741         if (err)
1742                 goto try_again;
1743
1744         api_ver = IWL_UCODE_API(priv->ucode_ver);
1745         build = pieces.build;
1746
1747         /*
1748          * api_ver should match the api version forming part of the
1749          * firmware filename ... but we don't check for that and only rely
1750          * on the API version read from firmware header from here on forward
1751          */
1752         /* no api version check required for experimental uCode */
1753         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1754                 if (api_ver < api_min || api_ver > api_max) {
1755                         IWL_ERR(priv,
1756                                 "Driver unable to support your firmware API. "
1757                                 "Driver supports v%u, firmware is v%u.\n",
1758                                 api_max, api_ver);
1759                         goto try_again;
1760                 }
1761
1762                 if (api_ver != api_max)
1763                         IWL_ERR(priv,
1764                                 "Firmware has old API version. Expected v%u, "
1765                                 "got v%u. New firmware can be obtained "
1766                                 "from http://www.intellinuxwireless.org.\n",
1767                                 api_max, api_ver);
1768         }
1769
1770         if (build)
1771                 sprintf(buildstr, " build %u%s", build,
1772                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1773                                 ? " (EXP)" : "");
1774         else
1775                 buildstr[0] = '\0';
1776
1777         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1778                  IWL_UCODE_MAJOR(priv->ucode_ver),
1779                  IWL_UCODE_MINOR(priv->ucode_ver),
1780                  IWL_UCODE_API(priv->ucode_ver),
1781                  IWL_UCODE_SERIAL(priv->ucode_ver),
1782                  buildstr);
1783
1784         snprintf(priv->hw->wiphy->fw_version,
1785                  sizeof(priv->hw->wiphy->fw_version),
1786                  "%u.%u.%u.%u%s",
1787                  IWL_UCODE_MAJOR(priv->ucode_ver),
1788                  IWL_UCODE_MINOR(priv->ucode_ver),
1789                  IWL_UCODE_API(priv->ucode_ver),
1790                  IWL_UCODE_SERIAL(priv->ucode_ver),
1791                  buildstr);
1792
1793         /*
1794          * For any of the failures below (before allocating pci memory)
1795          * we will try to load a version with a smaller API -- maybe the
1796          * user just got a corrupted version of the latest API.
1797          */
1798
1799         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1800                        priv->ucode_ver);
1801         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1802                        pieces.inst_size);
1803         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1804                        pieces.data_size);
1805         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1806                        pieces.init_size);
1807         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1808                        pieces.init_data_size);
1809         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
1810                        pieces.boot_size);
1811
1812         /* Verify that uCode images will fit in card's SRAM */
1813         if (pieces.inst_size > priv->hw_params.max_inst_size) {
1814                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1815                         pieces.inst_size);
1816                 goto try_again;
1817         }
1818
1819         if (pieces.data_size > priv->hw_params.max_data_size) {
1820                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1821                         pieces.data_size);
1822                 goto try_again;
1823         }
1824
1825         if (pieces.init_size > priv->hw_params.max_inst_size) {
1826                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1827                         pieces.init_size);
1828                 goto try_again;
1829         }
1830
1831         if (pieces.init_data_size > priv->hw_params.max_data_size) {
1832                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1833                         pieces.init_data_size);
1834                 goto try_again;
1835         }
1836
1837         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
1838                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
1839                         pieces.boot_size);
1840                 goto try_again;
1841         }
1842
1843         /* Allocate ucode buffers for card's bus-master loading ... */
1844
1845         /* Runtime instructions and 2 copies of data:
1846          * 1) unmodified from disk
1847          * 2) backup cache for save/restore during power-downs */
1848         priv->ucode_code.len = pieces.inst_size;
1849         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1850
1851         priv->ucode_data.len = pieces.data_size;
1852         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1853
1854         priv->ucode_data_backup.len = pieces.data_size;
1855         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1856
1857         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1858             !priv->ucode_data_backup.v_addr)
1859                 goto err_pci_alloc;
1860
1861         /* Initialization instructions and data */
1862         if (pieces.init_size && pieces.init_data_size) {
1863                 priv->ucode_init.len = pieces.init_size;
1864                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1865
1866                 priv->ucode_init_data.len = pieces.init_data_size;
1867                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1868
1869                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1870                         goto err_pci_alloc;
1871         }
1872
1873         /* Bootstrap (instructions only, no data) */
1874         if (pieces.boot_size) {
1875                 priv->ucode_boot.len = pieces.boot_size;
1876                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
1877
1878                 if (!priv->ucode_boot.v_addr)
1879                         goto err_pci_alloc;
1880         }
1881
1882         /* Now that we can no longer fail, copy information */
1883
1884         /*
1885          * The (size - 16) / 12 formula is based on the information recorded
1886          * for each event, which is of mode 1 (including timestamp) for all
1887          * new microcodes that include this information.
1888          */
1889         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1890         if (pieces.init_evtlog_size)
1891                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1892         else
1893                 priv->_agn.init_evtlog_size =
1894                         priv->cfg->base_params->max_event_log_size;
1895         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1896         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1897         if (pieces.inst_evtlog_size)
1898                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1899         else
1900                 priv->_agn.inst_evtlog_size =
1901                         priv->cfg->base_params->max_event_log_size;
1902         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1903
1904         if (ucode_capa.pan) {
1905                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1906                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1907         } else
1908                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1909
1910         /* Copy images into buffers for card's bus-master reads ... */
1911
1912         /* Runtime instructions (first block of data in file) */
1913         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1914                         pieces.inst_size);
1915         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1916
1917         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1918                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1919
1920         /*
1921          * Runtime data
1922          * NOTE:  Copy into backup buffer will be done in iwl_up()
1923          */
1924         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1925                         pieces.data_size);
1926         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1927         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
1928
1929         /* Initialization instructions */
1930         if (pieces.init_size) {
1931                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1932                                 pieces.init_size);
1933                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
1934         }
1935
1936         /* Initialization data */
1937         if (pieces.init_data_size) {
1938                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1939                                pieces.init_data_size);
1940                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1941                        pieces.init_data_size);
1942         }
1943
1944         /* Bootstrap instructions */
1945         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
1946                         pieces.boot_size);
1947         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
1948
1949         /*
1950          * figure out the offset of chain noise reset and gain commands
1951          * base on the size of standard phy calibration commands table size
1952          */
1953         if (ucode_capa.standard_phy_calibration_size >
1954             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1955                 ucode_capa.standard_phy_calibration_size =
1956                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1957
1958         priv->_agn.phy_calib_chain_noise_reset_cmd =
1959                 ucode_capa.standard_phy_calibration_size;
1960         priv->_agn.phy_calib_chain_noise_gain_cmd =
1961                 ucode_capa.standard_phy_calibration_size + 1;
1962
1963         /**************************************************
1964          * This is still part of probe() in a sense...
1965          *
1966          * 9. Setup and register with mac80211 and debugfs
1967          **************************************************/
1968         err = iwl_mac_setup_register(priv, &ucode_capa);
1969         if (err)
1970                 goto out_unbind;
1971
1972         err = iwl_dbgfs_register(priv, DRV_NAME);
1973         if (err)
1974                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1975
1976         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1977                                         &iwl_attribute_group);
1978         if (err) {
1979                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1980                 goto out_unbind;
1981         }
1982
1983         /* We have our copies now, allow OS release its copies */
1984         release_firmware(ucode_raw);
1985         complete(&priv->_agn.firmware_loading_complete);
1986         return;
1987
1988  try_again:
1989         /* try next, if any */
1990         if (iwl_request_firmware(priv, false))
1991                 goto out_unbind;
1992         release_firmware(ucode_raw);
1993         return;
1994
1995  err_pci_alloc:
1996         IWL_ERR(priv, "failed to allocate pci memory\n");
1997         iwl_dealloc_ucode_pci(priv);
1998  out_unbind:
1999         complete(&priv->_agn.firmware_loading_complete);
2000         device_release_driver(&priv->pci_dev->dev);
2001         release_firmware(ucode_raw);
2002 }
2003
2004 static const char *desc_lookup_text[] = {
2005         "OK",
2006         "FAIL",
2007         "BAD_PARAM",
2008         "BAD_CHECKSUM",
2009         "NMI_INTERRUPT_WDG",
2010         "SYSASSERT",
2011         "FATAL_ERROR",
2012         "BAD_COMMAND",
2013         "HW_ERROR_TUNE_LOCK",
2014         "HW_ERROR_TEMPERATURE",
2015         "ILLEGAL_CHAN_FREQ",
2016         "VCC_NOT_STABLE",
2017         "FH_ERROR",
2018         "NMI_INTERRUPT_HOST",
2019         "NMI_INTERRUPT_ACTION_PT",
2020         "NMI_INTERRUPT_UNKNOWN",
2021         "UCODE_VERSION_MISMATCH",
2022         "HW_ERROR_ABS_LOCK",
2023         "HW_ERROR_CAL_LOCK_FAIL",
2024         "NMI_INTERRUPT_INST_ACTION_PT",
2025         "NMI_INTERRUPT_DATA_ACTION_PT",
2026         "NMI_TRM_HW_ER",
2027         "NMI_INTERRUPT_TRM",
2028         "NMI_INTERRUPT_BREAK_POINT"
2029         "DEBUG_0",
2030         "DEBUG_1",
2031         "DEBUG_2",
2032         "DEBUG_3",
2033 };
2034
2035 static struct { char *name; u8 num; } advanced_lookup[] = {
2036         { "NMI_INTERRUPT_WDG", 0x34 },
2037         { "SYSASSERT", 0x35 },
2038         { "UCODE_VERSION_MISMATCH", 0x37 },
2039         { "BAD_COMMAND", 0x38 },
2040         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2041         { "FATAL_ERROR", 0x3D },
2042         { "NMI_TRM_HW_ERR", 0x46 },
2043         { "NMI_INTERRUPT_TRM", 0x4C },
2044         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2045         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2046         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2047         { "NMI_INTERRUPT_HOST", 0x66 },
2048         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2049         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2050         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2051         { "ADVANCED_SYSASSERT", 0 },
2052 };
2053
2054 static const char *desc_lookup(u32 num)
2055 {
2056         int i;
2057         int max = ARRAY_SIZE(desc_lookup_text);
2058
2059         if (num < max)
2060                 return desc_lookup_text[num];
2061
2062         max = ARRAY_SIZE(advanced_lookup) - 1;
2063         for (i = 0; i < max; i++) {
2064                 if (advanced_lookup[i].num == num)
2065                         break;;
2066         }
2067         return advanced_lookup[i].name;
2068 }
2069
2070 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2071 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2072
2073 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2074 {
2075         u32 data2, line;
2076         u32 desc, time, count, base, data1;
2077         u32 blink1, blink2, ilink1, ilink2;
2078         u32 pc, hcmd;
2079
2080         if (priv->ucode_type == UCODE_INIT) {
2081                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2082                 if (!base)
2083                         base = priv->_agn.init_errlog_ptr;
2084         } else {
2085                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2086                 if (!base)
2087                         base = priv->_agn.inst_errlog_ptr;
2088         }
2089
2090         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2091                 IWL_ERR(priv,
2092                         "Not valid error log pointer 0x%08X for %s uCode\n",
2093                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2094                 return;
2095         }
2096
2097         count = iwl_read_targ_mem(priv, base);
2098
2099         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2100                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2101                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2102                         priv->status, count);
2103         }
2104
2105         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2106         priv->isr_stats.err_code = desc;
2107         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2108         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2109         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2110         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2111         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2112         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2113         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2114         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2115         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2116         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2117
2118         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2119                                       blink1, blink2, ilink1, ilink2);
2120
2121         IWL_ERR(priv, "Desc                                  Time       "
2122                 "data1      data2      line\n");
2123         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2124                 desc_lookup(desc), desc, time, data1, data2, line);
2125         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2126         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2127                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2128 }
2129
2130 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2131
2132 /**
2133  * iwl_print_event_log - Dump error event log to syslog
2134  *
2135  */
2136 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2137                                u32 num_events, u32 mode,
2138                                int pos, char **buf, size_t bufsz)
2139 {
2140         u32 i;
2141         u32 base;       /* SRAM byte address of event log header */
2142         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2143         u32 ptr;        /* SRAM byte address of log data */
2144         u32 ev, time, data; /* event log data */
2145         unsigned long reg_flags;
2146
2147         if (num_events == 0)
2148                 return pos;
2149
2150         if (priv->ucode_type == UCODE_INIT) {
2151                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2152                 if (!base)
2153                         base = priv->_agn.init_evtlog_ptr;
2154         } else {
2155                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2156                 if (!base)
2157                         base = priv->_agn.inst_evtlog_ptr;
2158         }
2159
2160         if (mode == 0)
2161                 event_size = 2 * sizeof(u32);
2162         else
2163                 event_size = 3 * sizeof(u32);
2164
2165         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2166
2167         /* Make sure device is powered up for SRAM reads */
2168         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2169         iwl_grab_nic_access(priv);
2170
2171         /* Set starting address; reads will auto-increment */
2172         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2173         rmb();
2174
2175         /* "time" is actually "data" for mode 0 (no timestamp).
2176         * place event id # at far right for easier visual parsing. */
2177         for (i = 0; i < num_events; i++) {
2178                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2179                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2180                 if (mode == 0) {
2181                         /* data, ev */
2182                         if (bufsz) {
2183                                 pos += scnprintf(*buf + pos, bufsz - pos,
2184                                                 "EVT_LOG:0x%08x:%04u\n",
2185                                                 time, ev);
2186                         } else {
2187                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2188                                         time, ev);
2189                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2190                                         time, ev);
2191                         }
2192                 } else {
2193                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2194                         if (bufsz) {
2195                                 pos += scnprintf(*buf + pos, bufsz - pos,
2196                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2197                                                  time, data, ev);
2198                         } else {
2199                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2200                                         time, data, ev);
2201                                 trace_iwlwifi_dev_ucode_event(priv, time,
2202                                         data, ev);
2203                         }
2204                 }
2205         }
2206
2207         /* Allow device to power down */
2208         iwl_release_nic_access(priv);
2209         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2210         return pos;
2211 }
2212
2213 /**
2214  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2215  */
2216 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2217                                     u32 num_wraps, u32 next_entry,
2218                                     u32 size, u32 mode,
2219                                     int pos, char **buf, size_t bufsz)
2220 {
2221         /*
2222          * display the newest DEFAULT_LOG_ENTRIES entries
2223          * i.e the entries just before the next ont that uCode would fill.
2224          */
2225         if (num_wraps) {
2226                 if (next_entry < size) {
2227                         pos = iwl_print_event_log(priv,
2228                                                 capacity - (size - next_entry),
2229                                                 size - next_entry, mode,
2230                                                 pos, buf, bufsz);
2231                         pos = iwl_print_event_log(priv, 0,
2232                                                   next_entry, mode,
2233                                                   pos, buf, bufsz);
2234                 } else
2235                         pos = iwl_print_event_log(priv, next_entry - size,
2236                                                   size, mode, pos, buf, bufsz);
2237         } else {
2238                 if (next_entry < size) {
2239                         pos = iwl_print_event_log(priv, 0, next_entry,
2240                                                   mode, pos, buf, bufsz);
2241                 } else {
2242                         pos = iwl_print_event_log(priv, next_entry - size,
2243                                                   size, mode, pos, buf, bufsz);
2244                 }
2245         }
2246         return pos;
2247 }
2248
2249 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2250
2251 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2252                             char **buf, bool display)
2253 {
2254         u32 base;       /* SRAM byte address of event log header */
2255         u32 capacity;   /* event log capacity in # entries */
2256         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2257         u32 num_wraps;  /* # times uCode wrapped to top of log */
2258         u32 next_entry; /* index of next entry to be written by uCode */
2259         u32 size;       /* # entries that we'll print */
2260         u32 logsize;
2261         int pos = 0;
2262         size_t bufsz = 0;
2263
2264         if (priv->ucode_type == UCODE_INIT) {
2265                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2266                 logsize = priv->_agn.init_evtlog_size;
2267                 if (!base)
2268                         base = priv->_agn.init_evtlog_ptr;
2269         } else {
2270                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2271                 logsize = priv->_agn.inst_evtlog_size;
2272                 if (!base)
2273                         base = priv->_agn.inst_evtlog_ptr;
2274         }
2275
2276         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2277                 IWL_ERR(priv,
2278                         "Invalid event log pointer 0x%08X for %s uCode\n",
2279                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2280                 return -EINVAL;
2281         }
2282
2283         /* event log header */
2284         capacity = iwl_read_targ_mem(priv, base);
2285         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2286         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2287         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2288
2289         if (capacity > logsize) {
2290                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2291                         capacity, logsize);
2292                 capacity = logsize;
2293         }
2294
2295         if (next_entry > logsize) {
2296                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2297                         next_entry, logsize);
2298                 next_entry = logsize;
2299         }
2300
2301         size = num_wraps ? capacity : next_entry;
2302
2303         /* bail out if nothing in log */
2304         if (size == 0) {
2305                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2306                 return pos;
2307         }
2308
2309         /* enable/disable bt channel inhibition */
2310         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2311
2312 #ifdef CONFIG_IWLWIFI_DEBUG
2313         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2314                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2315                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2316 #else
2317         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2318                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2319 #endif
2320         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2321                 size);
2322
2323 #ifdef CONFIG_IWLWIFI_DEBUG
2324         if (display) {
2325                 if (full_log)
2326                         bufsz = capacity * 48;
2327                 else
2328                         bufsz = size * 48;
2329                 *buf = kmalloc(bufsz, GFP_KERNEL);
2330                 if (!*buf)
2331                         return -ENOMEM;
2332         }
2333         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2334                 /*
2335                  * if uCode has wrapped back to top of log,
2336                  * start at the oldest entry,
2337                  * i.e the next one that uCode would fill.
2338                  */
2339                 if (num_wraps)
2340                         pos = iwl_print_event_log(priv, next_entry,
2341                                                 capacity - next_entry, mode,
2342                                                 pos, buf, bufsz);
2343                 /* (then/else) start at top of log */
2344                 pos = iwl_print_event_log(priv, 0,
2345                                           next_entry, mode, pos, buf, bufsz);
2346         } else
2347                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2348                                                 next_entry, size, mode,
2349                                                 pos, buf, bufsz);
2350 #else
2351         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2352                                         next_entry, size, mode,
2353                                         pos, buf, bufsz);
2354 #endif
2355         return pos;
2356 }
2357
2358 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2359 {
2360         struct iwl_ct_kill_config cmd;
2361         struct iwl_ct_kill_throttling_config adv_cmd;
2362         unsigned long flags;
2363         int ret = 0;
2364
2365         spin_lock_irqsave(&priv->lock, flags);
2366         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2367                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2368         spin_unlock_irqrestore(&priv->lock, flags);
2369         priv->thermal_throttle.ct_kill_toggle = false;
2370
2371         if (priv->cfg->base_params->support_ct_kill_exit) {
2372                 adv_cmd.critical_temperature_enter =
2373                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2374                 adv_cmd.critical_temperature_exit =
2375                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2376
2377                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2378                                        sizeof(adv_cmd), &adv_cmd);
2379                 if (ret)
2380                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2381                 else
2382                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2383                                         "succeeded, "
2384                                         "critical temperature enter is %d,"
2385                                         "exit is %d\n",
2386                                        priv->hw_params.ct_kill_threshold,
2387                                        priv->hw_params.ct_kill_exit_threshold);
2388         } else {
2389                 cmd.critical_temperature_R =
2390                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2391
2392                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2393                                        sizeof(cmd), &cmd);
2394                 if (ret)
2395                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2396                 else
2397                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2398                                         "succeeded, "
2399                                         "critical temperature is %d\n",
2400                                         priv->hw_params.ct_kill_threshold);
2401         }
2402 }
2403
2404 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2405 {
2406         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2407         struct iwl_host_cmd cmd = {
2408                 .id = CALIBRATION_CFG_CMD,
2409                 .len = sizeof(struct iwl_calib_cfg_cmd),
2410                 .data = &calib_cfg_cmd,
2411         };
2412
2413         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2414         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2415         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2416
2417         return iwl_send_cmd(priv, &cmd);
2418 }
2419
2420
2421 /**
2422  * iwl_alive_start - called after REPLY_ALIVE notification received
2423  *                   from protocol/runtime uCode (initialization uCode's
2424  *                   Alive gets handled by iwl_init_alive_start()).
2425  */
2426 static void iwl_alive_start(struct iwl_priv *priv)
2427 {
2428         int ret = 0;
2429         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2430
2431         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2432
2433         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2434          * This is a paranoid check, because we would not have gotten the
2435          * "runtime" alive if code weren't properly loaded.  */
2436         if (iwl_verify_ucode(priv)) {
2437                 /* Runtime instruction load was bad;
2438                  * take it all the way back down so we can try again */
2439                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2440                 goto restart;
2441         }
2442
2443         ret = priv->cfg->ops->lib->alive_notify(priv);
2444         if (ret) {
2445                 IWL_WARN(priv,
2446                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2447                 goto restart;
2448         }
2449
2450
2451         /* After the ALIVE response, we can send host commands to the uCode */
2452         set_bit(STATUS_ALIVE, &priv->status);
2453
2454         /* Enable watchdog to monitor the driver tx queues */
2455         iwl_setup_watchdog(priv);
2456
2457         if (iwl_is_rfkill(priv))
2458                 return;
2459
2460         /* download priority table before any calibration request */
2461         if (priv->cfg->bt_params &&
2462             priv->cfg->bt_params->advanced_bt_coexist) {
2463                 /* Configure Bluetooth device coexistence support */
2464                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2465                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2466                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2467                 priv->cfg->ops->hcmd->send_bt_config(priv);
2468                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2469                 iwlagn_send_prio_tbl(priv);
2470
2471                 /* FIXME: w/a to force change uCode BT state machine */
2472                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2473                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2474                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2475                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2476         }
2477         if (priv->hw_params.calib_rt_cfg)
2478                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2479
2480         ieee80211_wake_queues(priv->hw);
2481
2482         priv->active_rate = IWL_RATES_MASK;
2483
2484         /* Configure Tx antenna selection based on H/W config */
2485         if (priv->cfg->ops->hcmd->set_tx_ant)
2486                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2487
2488         if (iwl_is_associated_ctx(ctx)) {
2489                 struct iwl_rxon_cmd *active_rxon =
2490                                 (struct iwl_rxon_cmd *)&ctx->active;
2491                 /* apply any changes in staging */
2492                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2493                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2494         } else {
2495                 struct iwl_rxon_context *tmp;
2496                 /* Initialize our rx_config data */
2497                 for_each_context(priv, tmp)
2498                         iwl_connection_init_rx_config(priv, tmp);
2499
2500                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2501                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2502         }
2503
2504         if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2505             !priv->cfg->bt_params->advanced_bt_coexist)) {
2506                 /*
2507                  * default is 2-wire BT coexexistence support
2508                  */
2509                 priv->cfg->ops->hcmd->send_bt_config(priv);
2510         }
2511
2512         iwl_reset_run_time_calib(priv);
2513
2514         set_bit(STATUS_READY, &priv->status);
2515
2516         /* Configure the adapter for unassociated operation */
2517         iwlcore_commit_rxon(priv, ctx);
2518
2519         /* At this point, the NIC is initialized and operational */
2520         iwl_rf_kill_ct_config(priv);
2521
2522         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2523         wake_up_interruptible(&priv->wait_command_queue);
2524
2525         iwl_power_update_mode(priv, true);
2526         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2527
2528
2529         return;
2530
2531  restart:
2532         queue_work(priv->workqueue, &priv->restart);
2533 }
2534
2535 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2536
2537 static void __iwl_down(struct iwl_priv *priv)
2538 {
2539         unsigned long flags;
2540         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2541
2542         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2543
2544         iwl_scan_cancel_timeout(priv, 200);
2545
2546         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2547
2548         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2549          * to prevent rearm timer */
2550         del_timer_sync(&priv->watchdog);
2551
2552         iwl_clear_ucode_stations(priv, NULL);
2553         iwl_dealloc_bcast_stations(priv);
2554         iwl_clear_driver_stations(priv);
2555
2556         /* reset BT coex data */
2557         priv->bt_status = 0;
2558         if (priv->cfg->bt_params)
2559                 priv->bt_traffic_load =
2560                          priv->cfg->bt_params->bt_init_traffic_load;
2561         else
2562                 priv->bt_traffic_load = 0;
2563         priv->bt_full_concurrent = false;
2564         priv->bt_ci_compliance = 0;
2565
2566         /* Unblock any waiting calls */
2567         wake_up_interruptible_all(&priv->wait_command_queue);
2568
2569         /* Wipe out the EXIT_PENDING status bit if we are not actually
2570          * exiting the module */
2571         if (!exit_pending)
2572                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2573
2574         /* stop and reset the on-board processor */
2575         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2576
2577         /* tell the device to stop sending interrupts */
2578         spin_lock_irqsave(&priv->lock, flags);
2579         iwl_disable_interrupts(priv);
2580         spin_unlock_irqrestore(&priv->lock, flags);
2581         iwl_synchronize_irq(priv);
2582
2583         if (priv->mac80211_registered)
2584                 ieee80211_stop_queues(priv->hw);
2585
2586         /* If we have not previously called iwl_init() then
2587          * clear all bits but the RF Kill bit and return */
2588         if (!iwl_is_init(priv)) {
2589                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2590                                         STATUS_RF_KILL_HW |
2591                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2592                                         STATUS_GEO_CONFIGURED |
2593                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2594                                         STATUS_EXIT_PENDING;
2595                 goto exit;
2596         }
2597
2598         /* ...otherwise clear out all the status bits but the RF Kill
2599          * bit and continue taking the NIC down. */
2600         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2601                                 STATUS_RF_KILL_HW |
2602                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2603                                 STATUS_GEO_CONFIGURED |
2604                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2605                                 STATUS_FW_ERROR |
2606                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2607                                 STATUS_EXIT_PENDING;
2608
2609         /* device going down, Stop using ICT table */
2610         if (priv->cfg->ops->lib->isr_ops.disable)
2611                 priv->cfg->ops->lib->isr_ops.disable(priv);
2612
2613         iwlagn_txq_ctx_stop(priv);
2614         iwlagn_rxq_stop(priv);
2615
2616         /* Power-down device's busmaster DMA clocks */
2617         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2618         udelay(5);
2619
2620         /* Make sure (redundant) we've released our request to stay awake */
2621         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2622
2623         /* Stop the device, and put it in low power state */
2624         iwl_apm_stop(priv);
2625
2626  exit:
2627         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2628
2629         dev_kfree_skb(priv->beacon_skb);
2630         priv->beacon_skb = NULL;
2631
2632         /* clear out any free frames */
2633         iwl_clear_free_frames(priv);
2634 }
2635
2636 static void iwl_down(struct iwl_priv *priv)
2637 {
2638         mutex_lock(&priv->mutex);
2639         __iwl_down(priv);
2640         mutex_unlock(&priv->mutex);
2641
2642         iwl_cancel_deferred_work(priv);
2643 }
2644
2645 #define HW_READY_TIMEOUT (50)
2646
2647 static int iwl_set_hw_ready(struct iwl_priv *priv)
2648 {
2649         int ret = 0;
2650
2651         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2652                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2653
2654         /* See if we got it */
2655         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2656                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2657                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2658                                 HW_READY_TIMEOUT);
2659         if (ret != -ETIMEDOUT)
2660                 priv->hw_ready = true;
2661         else
2662                 priv->hw_ready = false;
2663
2664         IWL_DEBUG_INFO(priv, "hardware %s\n",
2665                       (priv->hw_ready == 1) ? "ready" : "not ready");
2666         return ret;
2667 }
2668
2669 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2670 {
2671         int ret = 0;
2672
2673         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2674
2675         ret = iwl_set_hw_ready(priv);
2676         if (priv->hw_ready)
2677                 return ret;
2678
2679         /* If HW is not ready, prepare the conditions to check again */
2680         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2681                         CSR_HW_IF_CONFIG_REG_PREPARE);
2682
2683         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2684                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2685                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2686
2687         /* HW should be ready by now, check again. */
2688         if (ret != -ETIMEDOUT)
2689                 iwl_set_hw_ready(priv);
2690
2691         return ret;
2692 }
2693
2694 #define MAX_HW_RESTARTS 5
2695
2696 static int __iwl_up(struct iwl_priv *priv)
2697 {
2698         struct iwl_rxon_context *ctx;
2699         int i;
2700         int ret;
2701
2702         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2703                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2704                 return -EIO;
2705         }
2706
2707         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2708                 IWL_ERR(priv, "ucode not available for device bringup\n");
2709                 return -EIO;
2710         }
2711
2712         for_each_context(priv, ctx) {
2713                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2714                 if (ret) {
2715                         iwl_dealloc_bcast_stations(priv);
2716                         return ret;
2717                 }
2718         }
2719
2720         iwl_prepare_card_hw(priv);
2721
2722         if (!priv->hw_ready) {
2723                 IWL_WARN(priv, "Exit HW not ready\n");
2724                 return -EIO;
2725         }
2726
2727         /* If platform's RF_KILL switch is NOT set to KILL */
2728         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2729                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2730         else
2731                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2732
2733         if (iwl_is_rfkill(priv)) {
2734                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2735
2736                 iwl_enable_interrupts(priv);
2737                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2738                 return 0;
2739         }
2740
2741         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2742
2743         /* must be initialised before iwl_hw_nic_init */
2744         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2745                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2746         else
2747                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2748
2749         ret = iwlagn_hw_nic_init(priv);
2750         if (ret) {
2751                 IWL_ERR(priv, "Unable to init nic\n");
2752                 return ret;
2753         }
2754
2755         /* make sure rfkill handshake bits are cleared */
2756         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2757         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2758                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2759
2760         /* clear (again), then enable host interrupts */
2761         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2762         iwl_enable_interrupts(priv);
2763
2764         /* really make sure rfkill handshake bits are cleared */
2765         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2766         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2767
2768         /* Copy original ucode data image from disk into backup cache.
2769          * This will be used to initialize the on-board processor's
2770          * data SRAM for a clean start when the runtime program first loads. */
2771         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2772                priv->ucode_data.len);
2773
2774         for (i = 0; i < MAX_HW_RESTARTS; i++) {
2775
2776                 /* load bootstrap state machine,
2777                  * load bootstrap program into processor's memory,
2778                  * prepare to load the "initialize" uCode */
2779                 ret = priv->cfg->ops->lib->load_ucode(priv);
2780
2781                 if (ret) {
2782                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2783                                 ret);
2784                         continue;
2785                 }
2786
2787                 /* start card; "initialize" will load runtime ucode */
2788                 iwl_nic_start(priv);
2789
2790                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2791
2792                 return 0;
2793         }
2794
2795         set_bit(STATUS_EXIT_PENDING, &priv->status);
2796         __iwl_down(priv);
2797         clear_bit(STATUS_EXIT_PENDING, &priv->status);
2798
2799         /* tried to restart and config the device for as long as our
2800          * patience could withstand */
2801         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2802         return -EIO;
2803 }
2804
2805
2806 /*****************************************************************************
2807  *
2808  * Workqueue callbacks
2809  *
2810  *****************************************************************************/
2811
2812 static void iwl_bg_init_alive_start(struct work_struct *data)
2813 {
2814         struct iwl_priv *priv =
2815             container_of(data, struct iwl_priv, init_alive_start.work);
2816
2817         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2818                 return;
2819
2820         mutex_lock(&priv->mutex);
2821         priv->cfg->ops->lib->init_alive_start(priv);
2822         mutex_unlock(&priv->mutex);
2823 }
2824
2825 static void iwl_bg_alive_start(struct work_struct *data)
2826 {
2827         struct iwl_priv *priv =
2828             container_of(data, struct iwl_priv, alive_start.work);
2829
2830         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2831                 return;
2832
2833         /* enable dram interrupt */
2834         if (priv->cfg->ops->lib->isr_ops.reset)
2835                 priv->cfg->ops->lib->isr_ops.reset(priv);
2836
2837         mutex_lock(&priv->mutex);
2838         iwl_alive_start(priv);
2839         mutex_unlock(&priv->mutex);
2840 }
2841
2842 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2843 {
2844         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2845                         run_time_calib_work);
2846
2847         mutex_lock(&priv->mutex);
2848
2849         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2850             test_bit(STATUS_SCANNING, &priv->status)) {
2851                 mutex_unlock(&priv->mutex);
2852                 return;
2853         }
2854
2855         if (priv->start_calib) {
2856                 if (iwl_bt_statistics(priv)) {
2857                         iwl_chain_noise_calibration(priv,
2858                                         (void *)&priv->_agn.statistics_bt);
2859                         iwl_sensitivity_calibration(priv,
2860                                         (void *)&priv->_agn.statistics_bt);
2861                 } else {
2862                         iwl_chain_noise_calibration(priv,
2863                                         (void *)&priv->_agn.statistics);
2864                         iwl_sensitivity_calibration(priv,
2865                                         (void *)&priv->_agn.statistics);
2866                 }
2867         }
2868
2869         mutex_unlock(&priv->mutex);
2870 }
2871
2872 static void iwl_bg_restart(struct work_struct *data)
2873 {
2874         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2875
2876         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2877                 return;
2878
2879         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2880                 struct iwl_rxon_context *ctx;
2881                 bool bt_full_concurrent;
2882                 u8 bt_ci_compliance;
2883                 u8 bt_load;
2884                 u8 bt_status;
2885
2886                 mutex_lock(&priv->mutex);
2887                 for_each_context(priv, ctx)
2888                         ctx->vif = NULL;
2889                 priv->is_open = 0;
2890
2891                 /*
2892                  * __iwl_down() will clear the BT status variables,
2893                  * which is correct, but when we restart we really
2894                  * want to keep them so restore them afterwards.
2895                  *
2896                  * The restart process will later pick them up and
2897                  * re-configure the hw when we reconfigure the BT
2898                  * command.
2899                  */
2900                 bt_full_concurrent = priv->bt_full_concurrent;
2901                 bt_ci_compliance = priv->bt_ci_compliance;
2902                 bt_load = priv->bt_traffic_load;
2903                 bt_status = priv->bt_status;
2904
2905                 __iwl_down(priv);
2906
2907                 priv->bt_full_concurrent = bt_full_concurrent;
2908                 priv->bt_ci_compliance = bt_ci_compliance;
2909                 priv->bt_traffic_load = bt_load;
2910                 priv->bt_status = bt_status;
2911
2912                 mutex_unlock(&priv->mutex);
2913                 iwl_cancel_deferred_work(priv);
2914                 ieee80211_restart_hw(priv->hw);
2915         } else {
2916                 iwl_down(priv);
2917
2918                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2919                         return;
2920
2921                 mutex_lock(&priv->mutex);
2922                 __iwl_up(priv);
2923                 mutex_unlock(&priv->mutex);
2924         }
2925 }
2926
2927 static void iwl_bg_rx_replenish(struct work_struct *data)
2928 {
2929         struct iwl_priv *priv =
2930             container_of(data, struct iwl_priv, rx_replenish);
2931
2932         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2933                 return;
2934
2935         mutex_lock(&priv->mutex);
2936         iwlagn_rx_replenish(priv);
2937         mutex_unlock(&priv->mutex);
2938 }
2939
2940 static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2941                                  struct ieee80211_channel *chan,
2942                                  enum nl80211_channel_type channel_type,
2943                                  unsigned int wait)
2944 {
2945         struct iwl_priv *priv = hw->priv;
2946         int ret;
2947
2948         /* Not supported if we don't have PAN */
2949         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2950                 ret = -EOPNOTSUPP;
2951                 goto free;
2952         }
2953
2954         /* Not supported on pre-P2P firmware */
2955         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2956                                         BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2957                 ret = -EOPNOTSUPP;
2958                 goto free;
2959         }
2960
2961         mutex_lock(&priv->mutex);
2962
2963         if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2964                 /*
2965                  * If the PAN context is free, use the normal
2966                  * way of doing remain-on-channel offload + TX.
2967                  */
2968                 ret = 1;
2969                 goto out;
2970         }
2971
2972         /* TODO: queue up if scanning? */
2973         if (test_bit(STATUS_SCANNING, &priv->status) ||
2974             priv->_agn.offchan_tx_skb) {
2975                 ret = -EBUSY;
2976                 goto out;
2977         }
2978
2979         /*
2980          * max_scan_ie_len doesn't include the blank SSID or the header,
2981          * so need to add that again here.
2982          */
2983         if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2984                 ret = -ENOBUFS;
2985                 goto out;
2986         }
2987
2988         priv->_agn.offchan_tx_skb = skb;
2989         priv->_agn.offchan_tx_timeout = wait;
2990         priv->_agn.offchan_tx_chan = chan;
2991
2992         ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2993                                 IWL_SCAN_OFFCH_TX, chan->band);
2994         if (ret)
2995                 priv->_agn.offchan_tx_skb = NULL;
2996  out:
2997         mutex_unlock(&priv->mutex);
2998  free:
2999         if (ret < 0)
3000                 kfree_skb(skb);
3001
3002         return ret;
3003 }
3004
3005 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
3006 {
3007         struct iwl_priv *priv = hw->priv;
3008         int ret;
3009
3010         mutex_lock(&priv->mutex);
3011
3012         if (!priv->_agn.offchan_tx_skb)
3013                 return -EINVAL;
3014
3015         priv->_agn.offchan_tx_skb = NULL;
3016
3017         ret = iwl_scan_cancel_timeout(priv, 200);
3018         if (ret)
3019                 ret = -EIO;
3020         mutex_unlock(&priv->mutex);
3021
3022         return ret;
3023 }
3024
3025 /*****************************************************************************
3026  *
3027  * mac80211 entry point functions
3028  *
3029  *****************************************************************************/
3030
3031 #define UCODE_READY_TIMEOUT     (4 * HZ)
3032
3033 /*
3034  * Not a mac80211 entry point function, but it fits in with all the
3035  * other mac80211 functions grouped here.
3036  */
3037 static int iwl_mac_setup_register(struct iwl_priv *priv,
3038                                   struct iwlagn_ucode_capabilities *capa)
3039 {
3040         int ret;
3041         struct ieee80211_hw *hw = priv->hw;
3042         struct iwl_rxon_context *ctx;
3043
3044         hw->rate_control_algorithm = "iwl-agn-rs";
3045
3046         /* Tell mac80211 our characteristics */
3047         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3048                     IEEE80211_HW_AMPDU_AGGREGATION |
3049                     IEEE80211_HW_NEED_DTIM_PERIOD |
3050                     IEEE80211_HW_SPECTRUM_MGMT |
3051                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
3052
3053         hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3054
3055         if (!priv->cfg->base_params->broken_powersave)
3056                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3057                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3058
3059         if (priv->cfg->sku & IWL_SKU_N)
3060                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3061                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3062
3063         hw->sta_data_size = sizeof(struct iwl_station_priv);
3064         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3065
3066         for_each_context(priv, ctx) {
3067                 hw->wiphy->interface_modes |= ctx->interface_modes;
3068                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3069         }
3070
3071         hw->wiphy->max_remain_on_channel_duration = 1000;
3072
3073         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3074                             WIPHY_FLAG_DISABLE_BEACON_HINTS |
3075                             WIPHY_FLAG_IBSS_RSN;
3076
3077         /*
3078          * For now, disable PS by default because it affects
3079          * RX performance significantly.
3080          */
3081         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3082
3083         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3084         /* we create the 802.11 header and a zero-length SSID element */
3085         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3086
3087         /* Default value; 4 EDCA QOS priorities */
3088         hw->queues = 4;
3089
3090         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3091
3092         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3093                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3094                         &priv->bands[IEEE80211_BAND_2GHZ];
3095         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3096                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3097                         &priv->bands[IEEE80211_BAND_5GHZ];
3098
3099         iwl_leds_init(priv);
3100
3101         ret = ieee80211_register_hw(priv->hw);
3102         if (ret) {
3103                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3104                 return ret;
3105         }
3106         priv->mac80211_registered = 1;
3107
3108         return 0;
3109 }
3110
3111
3112 int iwlagn_mac_start(struct ieee80211_hw *hw)
3113 {
3114         struct iwl_priv *priv = hw->priv;
3115         int ret;
3116
3117         IWL_DEBUG_MAC80211(priv, "enter\n");
3118
3119         /* we should be verifying the device is ready to be opened */
3120         mutex_lock(&priv->mutex);
3121         ret = __iwl_up(priv);
3122         mutex_unlock(&priv->mutex);
3123
3124         if (ret)
3125                 return ret;
3126
3127         if (iwl_is_rfkill(priv))
3128                 goto out;
3129
3130         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3131
3132         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3133          * mac80211 will not be run successfully. */
3134         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3135                         test_bit(STATUS_READY, &priv->status),
3136                         UCODE_READY_TIMEOUT);
3137         if (!ret) {
3138                 if (!test_bit(STATUS_READY, &priv->status)) {
3139                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3140                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3141                         return -ETIMEDOUT;
3142                 }
3143         }
3144
3145         iwlagn_led_enable(priv);
3146
3147 out:
3148         priv->is_open = 1;
3149         IWL_DEBUG_MAC80211(priv, "leave\n");
3150         return 0;
3151 }
3152
3153 void iwlagn_mac_stop(struct ieee80211_hw *hw)
3154 {
3155         struct iwl_priv *priv = hw->priv;
3156
3157         IWL_DEBUG_MAC80211(priv, "enter\n");
3158
3159         if (!priv->is_open)
3160                 return;
3161
3162         priv->is_open = 0;
3163
3164         iwl_down(priv);
3165
3166         flush_workqueue(priv->workqueue);
3167
3168         /* User space software may expect getting rfkill changes
3169          * even if interface is down */
3170         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3171         iwl_enable_rfkill_int(priv);
3172
3173         IWL_DEBUG_MAC80211(priv, "leave\n");
3174 }
3175
3176 void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3177 {
3178         struct iwl_priv *priv = hw->priv;
3179
3180         IWL_DEBUG_MACDUMP(priv, "enter\n");
3181
3182         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3183                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3184
3185         if (iwlagn_tx_skb(priv, skb))
3186                 dev_kfree_skb_any(skb);
3187
3188         IWL_DEBUG_MACDUMP(priv, "leave\n");
3189 }
3190
3191 void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3192                                 struct ieee80211_vif *vif,
3193                                 struct ieee80211_key_conf *keyconf,
3194                                 struct ieee80211_sta *sta,
3195                                 u32 iv32, u16 *phase1key)
3196 {
3197         struct iwl_priv *priv = hw->priv;
3198         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3199
3200         IWL_DEBUG_MAC80211(priv, "enter\n");
3201
3202         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3203                             iv32, phase1key);
3204
3205         IWL_DEBUG_MAC80211(priv, "leave\n");
3206 }
3207
3208 int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3209                        struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3210                        struct ieee80211_key_conf *key)
3211 {
3212         struct iwl_priv *priv = hw->priv;
3213         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3214         struct iwl_rxon_context *ctx = vif_priv->ctx;
3215         int ret;
3216         u8 sta_id;
3217         bool is_default_wep_key = false;
3218
3219         IWL_DEBUG_MAC80211(priv, "enter\n");
3220
3221         if (priv->cfg->mod_params->sw_crypto) {
3222                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3223                 return -EOPNOTSUPP;
3224         }
3225
3226         /*
3227          * To support IBSS RSN, don't program group keys in IBSS, the
3228          * hardware will then not attempt to decrypt the frames.
3229          */
3230         if (vif->type == NL80211_IFTYPE_ADHOC &&
3231             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3232                 return -EOPNOTSUPP;
3233
3234         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3235         if (sta_id == IWL_INVALID_STATION)
3236                 return -EINVAL;
3237
3238         mutex_lock(&priv->mutex);
3239         iwl_scan_cancel_timeout(priv, 100);
3240
3241         /*
3242          * If we are getting WEP group key and we didn't receive any key mapping
3243          * so far, we are in legacy wep mode (group key only), otherwise we are
3244          * in 1X mode.
3245          * In legacy wep mode, we use another host command to the uCode.
3246          */
3247         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3248              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3249             !sta) {
3250                 if (cmd == SET_KEY)
3251                         is_default_wep_key = !ctx->key_mapping_keys;
3252                 else
3253                         is_default_wep_key =
3254                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3255         }
3256
3257         switch (cmd) {
3258         case SET_KEY:
3259                 if (is_default_wep_key)
3260                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3261                 else
3262                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3263                                                   key, sta_id);
3264
3265                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3266                 break;
3267         case DISABLE_KEY:
3268                 if (is_default_wep_key)
3269                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3270                 else
3271                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3272
3273                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3274                 break;
3275         default:
3276                 ret = -EINVAL;
3277         }
3278
3279         mutex_unlock(&priv->mutex);
3280         IWL_DEBUG_MAC80211(priv, "leave\n");
3281
3282         return ret;
3283 }
3284
3285 int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3286                             struct ieee80211_vif *vif,
3287                             enum ieee80211_ampdu_mlme_action action,
3288                             struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3289                             u8 buf_size)
3290 {
3291         struct iwl_priv *priv = hw->priv;
3292         int ret = -EINVAL;
3293         struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3294
3295         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3296                      sta->addr, tid);
3297
3298         if (!(priv->cfg->sku & IWL_SKU_N))
3299                 return -EACCES;
3300
3301         mutex_lock(&priv->mutex);
3302
3303         switch (action) {
3304         case IEEE80211_AMPDU_RX_START:
3305                 IWL_DEBUG_HT(priv, "start Rx\n");
3306                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3307                 break;
3308         case IEEE80211_AMPDU_RX_STOP:
3309                 IWL_DEBUG_HT(priv, "stop Rx\n");
3310                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3311                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3312                         ret = 0;
3313                 break;
3314         case IEEE80211_AMPDU_TX_START:
3315                 IWL_DEBUG_HT(priv, "start Tx\n");
3316                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3317                 if (ret == 0) {
3318                         priv->_agn.agg_tids_count++;
3319                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3320                                      priv->_agn.agg_tids_count);
3321                 }
3322                 break;
3323         case IEEE80211_AMPDU_TX_STOP:
3324                 IWL_DEBUG_HT(priv, "stop Tx\n");
3325                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3326                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3327                         priv->_agn.agg_tids_count--;
3328                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3329                                      priv->_agn.agg_tids_count);
3330                 }
3331                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3332                         ret = 0;
3333                 if (priv->cfg->ht_params &&
3334                     priv->cfg->ht_params->use_rts_for_aggregation) {
3335                         struct iwl_station_priv *sta_priv =
3336                                 (void *) sta->drv_priv;
3337                         /*
3338                          * switch off RTS/CTS if it was previously enabled
3339                          */
3340
3341                         sta_priv->lq_sta.lq.general_params.flags &=
3342                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3343                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3344                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3345                 }
3346                 break;
3347         case IEEE80211_AMPDU_TX_OPERATIONAL:
3348                 /*
3349                  * If the limit is 0, then it wasn't initialised yet,
3350                  * use the default. We can do that since we take the
3351                  * minimum below, and we don't want to go above our
3352                  * default due to hardware restrictions.
3353                  */
3354                 if (sta_priv->max_agg_bufsize == 0)
3355                         sta_priv->max_agg_bufsize =
3356                                 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3357
3358                 /*
3359                  * Even though in theory the peer could have different
3360                  * aggregation reorder buffer sizes for different sessions,
3361                  * our ucode doesn't allow for that and has a global limit
3362                  * for each station. Therefore, use the minimum of all the
3363                  * aggregation sessions and our default value.
3364                  */
3365                 sta_priv->max_agg_bufsize =
3366                         min(sta_priv->max_agg_bufsize, buf_size);
3367
3368                 if (priv->cfg->ht_params &&
3369                     priv->cfg->ht_params->use_rts_for_aggregation) {
3370                         /*
3371                          * switch to RTS/CTS if it is the prefer protection
3372                          * method for HT traffic
3373                          */
3374
3375                         sta_priv->lq_sta.lq.general_params.flags |=
3376                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3377                 }
3378
3379                 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3380                         sta_priv->max_agg_bufsize;
3381
3382                 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3383                                 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3384                 ret = 0;
3385                 break;
3386         }
3387         mutex_unlock(&priv->mutex);
3388
3389         return ret;
3390 }
3391
3392 int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3393                        struct ieee80211_vif *vif,
3394                        struct ieee80211_sta *sta)
3395 {
3396         struct iwl_priv *priv = hw->priv;
3397         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3398         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3399         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3400         int ret;
3401         u8 sta_id;
3402
3403         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3404                         sta->addr);
3405         mutex_lock(&priv->mutex);
3406         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3407                         sta->addr);
3408         sta_priv->common.sta_id = IWL_INVALID_STATION;
3409
3410         atomic_set(&sta_priv->pending_frames, 0);
3411         if (vif->type == NL80211_IFTYPE_AP)
3412                 sta_priv->client = true;
3413
3414         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3415                                      is_ap, sta, &sta_id);
3416         if (ret) {
3417                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3418                         sta->addr, ret);
3419                 /* Should we return success if return code is EEXIST ? */
3420                 mutex_unlock(&priv->mutex);
3421                 return ret;
3422         }
3423
3424         sta_priv->common.sta_id = sta_id;
3425
3426         /* Initialize rate scaling */
3427         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3428                        sta->addr);
3429         iwl_rs_rate_init(priv, sta, sta_id);
3430         mutex_unlock(&priv->mutex);
3431
3432         return 0;
3433 }
3434
3435 void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3436                                struct ieee80211_channel_switch *ch_switch)
3437 {
3438         struct iwl_priv *priv = hw->priv;
3439         const struct iwl_channel_info *ch_info;
3440         struct ieee80211_conf *conf = &hw->conf;
3441         struct ieee80211_channel *channel = ch_switch->channel;
3442         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3443         /*
3444          * MULTI-FIXME
3445          * When we add support for multiple interfaces, we need to
3446          * revisit this. The channel switch command in the device
3447          * only affects the BSS context, but what does that really
3448          * mean? And what if we get a CSA on the second interface?
3449          * This needs a lot of work.
3450          */
3451         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3452         u16 ch;
3453         unsigned long flags = 0;
3454
3455         IWL_DEBUG_MAC80211(priv, "enter\n");
3456
3457         if (iwl_is_rfkill(priv))
3458                 goto out_exit;
3459
3460         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3461             test_bit(STATUS_SCANNING, &priv->status))
3462                 goto out_exit;
3463
3464         if (!iwl_is_associated_ctx(ctx))
3465                 goto out_exit;
3466
3467         /* channel switch in progress */
3468         if (priv->switch_rxon.switch_in_progress == true)
3469                 goto out_exit;
3470
3471         mutex_lock(&priv->mutex);
3472         if (priv->cfg->ops->lib->set_channel_switch) {
3473
3474                 ch = channel->hw_value;
3475                 if (le16_to_cpu(ctx->active.channel) != ch) {
3476                         ch_info = iwl_get_channel_info(priv,
3477                                                        channel->band,
3478                                                        ch);
3479                         if (!is_channel_valid(ch_info)) {
3480                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3481                                 goto out;
3482                         }
3483                         spin_lock_irqsave(&priv->lock, flags);
3484
3485                         priv->current_ht_config.smps = conf->smps_mode;
3486
3487                         /* Configure HT40 channels */
3488                         ctx->ht.enabled = conf_is_ht(conf);
3489                         if (ctx->ht.enabled) {
3490                                 if (conf_is_ht40_minus(conf)) {
3491                                         ctx->ht.extension_chan_offset =
3492                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3493                                         ctx->ht.is_40mhz = true;
3494                                 } else if (conf_is_ht40_plus(conf)) {
3495                                         ctx->ht.extension_chan_offset =
3496                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3497                                         ctx->ht.is_40mhz = true;
3498                                 } else {
3499                                         ctx->ht.extension_chan_offset =
3500                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3501                                         ctx->ht.is_40mhz = false;
3502                                 }
3503                         } else
3504                                 ctx->ht.is_40mhz = false;
3505
3506                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3507                                 ctx->staging.flags = 0;
3508
3509                         iwl_set_rxon_channel(priv, channel, ctx);
3510                         iwl_set_rxon_ht(priv, ht_conf);
3511                         iwl_set_flags_for_band(priv, ctx, channel->band,
3512                                                ctx->vif);
3513                         spin_unlock_irqrestore(&priv->lock, flags);
3514
3515                         iwl_set_rate(priv);
3516                         /*
3517                          * at this point, staging_rxon has the
3518                          * configuration for channel switch
3519                          */
3520                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3521                                                                     ch_switch))
3522                                 priv->switch_rxon.switch_in_progress = false;
3523                 }
3524         }
3525 out:
3526         mutex_unlock(&priv->mutex);
3527 out_exit:
3528         if (!priv->switch_rxon.switch_in_progress)
3529                 ieee80211_chswitch_done(ctx->vif, false);
3530         IWL_DEBUG_MAC80211(priv, "leave\n");
3531 }
3532
3533 void iwlagn_configure_filter(struct ieee80211_hw *hw,
3534                              unsigned int changed_flags,
3535                              unsigned int *total_flags,
3536                              u64 multicast)
3537 {
3538         struct iwl_priv *priv = hw->priv;
3539         __le32 filter_or = 0, filter_nand = 0;
3540         struct iwl_rxon_context *ctx;
3541
3542 #define CHK(test, flag) do { \
3543         if (*total_flags & (test))              \
3544                 filter_or |= (flag);            \
3545         else                                    \
3546                 filter_nand |= (flag);          \
3547         } while (0)
3548
3549         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3550                         changed_flags, *total_flags);
3551
3552         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3553         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3554         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3555         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3556
3557 #undef CHK
3558
3559         mutex_lock(&priv->mutex);
3560
3561         for_each_context(priv, ctx) {
3562                 ctx->staging.filter_flags &= ~filter_nand;
3563                 ctx->staging.filter_flags |= filter_or;
3564
3565                 /*
3566                  * Not committing directly because hardware can perform a scan,
3567                  * but we'll eventually commit the filter flags change anyway.
3568                  */
3569         }
3570
3571         mutex_unlock(&priv->mutex);
3572
3573         /*
3574          * Receiving all multicast frames is always enabled by the
3575          * default flags setup in iwl_connection_init_rx_config()
3576          * since we currently do not support programming multicast
3577          * filters into the device.
3578          */
3579         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3580                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3581 }
3582
3583 void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3584 {
3585         struct iwl_priv *priv = hw->priv;
3586
3587         mutex_lock(&priv->mutex);
3588         IWL_DEBUG_MAC80211(priv, "enter\n");
3589
3590         /* do not support "flush" */
3591         if (!priv->cfg->ops->lib->txfifo_flush)
3592                 goto done;
3593
3594         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3595                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3596                 goto done;
3597         }
3598         if (iwl_is_rfkill(priv)) {
3599                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3600                 goto done;
3601         }
3602
3603         /*
3604          * mac80211 will not push any more frames for transmit
3605          * until the flush is completed
3606          */
3607         if (drop) {
3608                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3609                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3610                         IWL_ERR(priv, "flush request fail\n");
3611                         goto done;
3612                 }
3613         }
3614         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3615         iwlagn_wait_tx_queue_empty(priv);
3616 done:
3617         mutex_unlock(&priv->mutex);
3618         IWL_DEBUG_MAC80211(priv, "leave\n");
3619 }
3620
3621 static void iwlagn_disable_roc(struct iwl_priv *priv)
3622 {
3623         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3624         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3625
3626         lockdep_assert_held(&priv->mutex);
3627
3628         if (!ctx->is_active)
3629                 return;
3630
3631         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3632         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3633         iwl_set_rxon_channel(priv, chan, ctx);
3634         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3635
3636         priv->_agn.hw_roc_channel = NULL;
3637
3638         iwlcore_commit_rxon(priv, ctx);
3639
3640         ctx->is_active = false;
3641 }
3642
3643 static void iwlagn_bg_roc_done(struct work_struct *work)
3644 {
3645         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3646                                              _agn.hw_roc_work.work);
3647
3648         mutex_lock(&priv->mutex);
3649         ieee80211_remain_on_channel_expired(priv->hw);
3650         iwlagn_disable_roc(priv);
3651         mutex_unlock(&priv->mutex);
3652 }
3653
3654 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3655                                      struct ieee80211_channel *channel,
3656                                      enum nl80211_channel_type channel_type,
3657                                      int duration)
3658 {
3659         struct iwl_priv *priv = hw->priv;
3660         int err = 0;
3661
3662         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3663                 return -EOPNOTSUPP;
3664
3665         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3666                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3667                 return -EOPNOTSUPP;
3668
3669         mutex_lock(&priv->mutex);
3670
3671         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3672             test_bit(STATUS_SCAN_HW, &priv->status)) {
3673                 err = -EBUSY;
3674                 goto out;
3675         }
3676
3677         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3678         priv->_agn.hw_roc_channel = channel;
3679         priv->_agn.hw_roc_chantype = channel_type;
3680         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3681         iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3682         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3683                            msecs_to_jiffies(duration + 20));
3684
3685         msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3686         ieee80211_ready_on_channel(priv->hw);
3687
3688  out:
3689         mutex_unlock(&priv->mutex);
3690
3691         return err;
3692 }
3693
3694 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3695 {
3696         struct iwl_priv *priv = hw->priv;
3697
3698         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3699                 return -EOPNOTSUPP;
3700
3701         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3702
3703         mutex_lock(&priv->mutex);
3704         iwlagn_disable_roc(priv);
3705         mutex_unlock(&priv->mutex);
3706
3707         return 0;
3708 }
3709
3710 /*****************************************************************************
3711  *
3712  * driver setup and teardown
3713  *
3714  *****************************************************************************/
3715
3716 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3717 {
3718         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3719
3720         init_waitqueue_head(&priv->wait_command_queue);
3721
3722         INIT_WORK(&priv->restart, iwl_bg_restart);
3723         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3724         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3725         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3726         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3727         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3728         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3729         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3730         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3731         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3732
3733         iwl_setup_scan_deferred_work(priv);
3734
3735         if (priv->cfg->ops->lib->setup_deferred_work)
3736                 priv->cfg->ops->lib->setup_deferred_work(priv);
3737
3738         init_timer(&priv->statistics_periodic);
3739         priv->statistics_periodic.data = (unsigned long)priv;
3740         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3741
3742         init_timer(&priv->ucode_trace);
3743         priv->ucode_trace.data = (unsigned long)priv;
3744         priv->ucode_trace.function = iwl_bg_ucode_trace;
3745
3746         init_timer(&priv->watchdog);
3747         priv->watchdog.data = (unsigned long)priv;
3748         priv->watchdog.function = iwl_bg_watchdog;
3749
3750         if (!priv->cfg->base_params->use_isr_legacy)
3751                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3752                         iwl_irq_tasklet, (unsigned long)priv);
3753         else
3754                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3755                         iwl_irq_tasklet_legacy, (unsigned long)priv);
3756 }
3757
3758 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3759 {
3760         if (priv->cfg->ops->lib->cancel_deferred_work)
3761                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3762
3763         cancel_delayed_work_sync(&priv->init_alive_start);
3764         cancel_delayed_work(&priv->alive_start);
3765         cancel_work_sync(&priv->run_time_calib_work);
3766         cancel_work_sync(&priv->beacon_update);
3767
3768         iwl_cancel_scan_deferred_work(priv);
3769
3770         cancel_work_sync(&priv->bt_full_concurrency);
3771         cancel_work_sync(&priv->bt_runtime_config);
3772
3773         del_timer_sync(&priv->statistics_periodic);
3774         del_timer_sync(&priv->ucode_trace);
3775 }
3776
3777 static void iwl_init_hw_rates(struct iwl_priv *priv,
3778                               struct ieee80211_rate *rates)
3779 {
3780         int i;
3781
3782         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3783                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3784                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3785                 rates[i].hw_value_short = i;
3786                 rates[i].flags = 0;
3787                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3788                         /*
3789                          * If CCK != 1M then set short preamble rate flag.
3790                          */
3791                         rates[i].flags |=
3792                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3793                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3794                 }
3795         }
3796 }
3797
3798 static int iwl_init_drv(struct iwl_priv *priv)
3799 {
3800         int ret;
3801
3802         spin_lock_init(&priv->sta_lock);
3803         spin_lock_init(&priv->hcmd_lock);
3804
3805         INIT_LIST_HEAD(&priv->free_frames);
3806
3807         mutex_init(&priv->mutex);
3808         mutex_init(&priv->sync_cmd_mutex);
3809
3810         priv->ieee_channels = NULL;
3811         priv->ieee_rates = NULL;
3812         priv->band = IEEE80211_BAND_2GHZ;
3813
3814         priv->iw_mode = NL80211_IFTYPE_STATION;
3815         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3816         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3817         priv->_agn.agg_tids_count = 0;
3818
3819         /* initialize force reset */
3820         priv->force_reset[IWL_RF_RESET].reset_duration =
3821                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3822         priv->force_reset[IWL_FW_RESET].reset_duration =
3823                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3824
3825         priv->rx_statistics_jiffies = jiffies;
3826
3827         /* Choose which receivers/antennas to use */
3828         if (priv->cfg->ops->hcmd->set_rxon_chain)
3829                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3830                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3831
3832         iwl_init_scan_params(priv);
3833
3834         /* init bt coex */
3835         if (priv->cfg->bt_params &&
3836             priv->cfg->bt_params->advanced_bt_coexist) {
3837                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3838                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3839                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3840                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3841                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3842                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3843         }
3844
3845         /* Set the tx_power_user_lmt to the lowest power level
3846          * this value will get overwritten by channel max power avg
3847          * from eeprom */
3848         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3849         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3850
3851         ret = iwl_init_channel_map(priv);
3852         if (ret) {
3853                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3854                 goto err;
3855         }
3856
3857         ret = iwlcore_init_geos(priv);
3858         if (ret) {
3859                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3860                 goto err_free_channel_map;
3861         }
3862         iwl_init_hw_rates(priv, priv->ieee_rates);
3863
3864         return 0;
3865
3866 err_free_channel_map:
3867         iwl_free_channel_map(priv);
3868 err:
3869         return ret;
3870 }
3871
3872 static void iwl_uninit_drv(struct iwl_priv *priv)
3873 {
3874         iwl_calib_free_results(priv);
3875         iwlcore_free_geos(priv);
3876         iwl_free_channel_map(priv);
3877         kfree(priv->scan_cmd);
3878 }
3879
3880 struct ieee80211_ops iwlagn_hw_ops = {
3881         .tx = iwlagn_mac_tx,
3882         .start = iwlagn_mac_start,
3883         .stop = iwlagn_mac_stop,
3884         .add_interface = iwl_mac_add_interface,
3885         .remove_interface = iwl_mac_remove_interface,
3886         .change_interface = iwl_mac_change_interface,
3887         .config = iwlagn_mac_config,
3888         .configure_filter = iwlagn_configure_filter,
3889         .set_key = iwlagn_mac_set_key,
3890         .update_tkip_key = iwlagn_mac_update_tkip_key,
3891         .conf_tx = iwl_mac_conf_tx,
3892         .bss_info_changed = iwlagn_bss_info_changed,
3893         .ampdu_action = iwlagn_mac_ampdu_action,
3894         .hw_scan = iwl_mac_hw_scan,
3895         .sta_notify = iwlagn_mac_sta_notify,
3896         .sta_add = iwlagn_mac_sta_add,
3897         .sta_remove = iwl_mac_sta_remove,
3898         .channel_switch = iwlagn_mac_channel_switch,
3899         .flush = iwlagn_mac_flush,
3900         .tx_last_beacon = iwl_mac_tx_last_beacon,
3901         .remain_on_channel = iwl_mac_remain_on_channel,
3902         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3903         .offchannel_tx = iwl_mac_offchannel_tx,
3904         .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3905 };
3906
3907 static void iwl_hw_detect(struct iwl_priv *priv)
3908 {
3909         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
3910         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
3911         priv->rev_id = priv->pci_dev->revision;
3912         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3913 }
3914
3915 static int iwl_set_hw_params(struct iwl_priv *priv)
3916 {
3917         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3918         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3919         if (priv->cfg->mod_params->amsdu_size_8K)
3920                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3921         else
3922                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3923
3924         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3925
3926         if (priv->cfg->mod_params->disable_11n)
3927                 priv->cfg->sku &= ~IWL_SKU_N;
3928
3929         /* Device-specific setup */
3930         return priv->cfg->ops->lib->set_hw_params(priv);
3931 }
3932
3933 static const u8 iwlagn_bss_ac_to_fifo[] = {
3934         IWL_TX_FIFO_VO,
3935         IWL_TX_FIFO_VI,
3936         IWL_TX_FIFO_BE,
3937         IWL_TX_FIFO_BK,
3938 };
3939
3940 static const u8 iwlagn_bss_ac_to_queue[] = {
3941         0, 1, 2, 3,
3942 };
3943
3944 static const u8 iwlagn_pan_ac_to_fifo[] = {
3945         IWL_TX_FIFO_VO_IPAN,
3946         IWL_TX_FIFO_VI_IPAN,
3947         IWL_TX_FIFO_BE_IPAN,
3948         IWL_TX_FIFO_BK_IPAN,
3949 };
3950
3951 static const u8 iwlagn_pan_ac_to_queue[] = {
3952         7, 6, 5, 4,
3953 };
3954
3955 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3956 {
3957         int err = 0, i;
3958         struct iwl_priv *priv;
3959         struct ieee80211_hw *hw;
3960         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3961         unsigned long flags;
3962         u16 pci_cmd, num_mac;
3963
3964         /************************
3965          * 1. Allocating HW data
3966          ************************/
3967
3968         /* Disabling hardware scan means that mac80211 will perform scans
3969          * "the hard way", rather than using device's scan. */
3970         if (cfg->mod_params->disable_hw_scan) {
3971                 dev_printk(KERN_DEBUG, &(pdev->dev),
3972                         "sw scan support is deprecated\n");
3973                 iwlagn_hw_ops.hw_scan = NULL;
3974         }
3975
3976         hw = iwl_alloc_all(cfg);
3977         if (!hw) {
3978                 err = -ENOMEM;
3979                 goto out;
3980         }
3981         priv = hw->priv;
3982         /* At this point both hw and priv are allocated. */
3983
3984         /*
3985          * The default context is always valid,
3986          * more may be discovered when firmware
3987          * is loaded.
3988          */
3989         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3990
3991         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3992                 priv->contexts[i].ctxid = i;
3993
3994         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3995         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3996         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3997         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3998         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
3999         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4000         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4001         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4002         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4003         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4004         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4005                 BIT(NL80211_IFTYPE_ADHOC);
4006         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4007                 BIT(NL80211_IFTYPE_STATION);
4008         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
4009         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4010         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4011         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4012
4013         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4014         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4015         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4016         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4017         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4018         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4019         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4020         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4021         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4022         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4023         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4024         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4025                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4026 #ifdef CONFIG_IWL_P2P
4027         priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
4028                 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
4029 #endif
4030         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4031         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4032         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4033
4034         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4035
4036         SET_IEEE80211_DEV(hw, &pdev->dev);
4037
4038         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4039         priv->cfg = cfg;
4040         priv->pci_dev = pdev;
4041         priv->inta_mask = CSR_INI_SET_MASK;
4042
4043         /* is antenna coupling more than 35dB ? */
4044         priv->bt_ant_couple_ok =
4045                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4046                 true : false;
4047
4048         /* enable/disable bt channel inhibition */
4049         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4050         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
4051                        (priv->bt_ch_announce) ? "On" : "Off");
4052
4053         if (iwl_alloc_traffic_mem(priv))
4054                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4055
4056         /**************************
4057          * 2. Initializing PCI bus
4058          **************************/
4059         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4060                                 PCIE_LINK_STATE_CLKPM);
4061
4062         if (pci_enable_device(pdev)) {
4063                 err = -ENODEV;
4064                 goto out_ieee80211_free_hw;
4065         }
4066
4067         pci_set_master(pdev);
4068
4069         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4070         if (!err)
4071                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4072         if (err) {
4073                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4074                 if (!err)
4075                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4076                 /* both attempts failed: */
4077                 if (err) {
4078                         IWL_WARN(priv, "No suitable DMA available.\n");
4079                         goto out_pci_disable_device;
4080                 }
4081         }
4082
4083         err = pci_request_regions(pdev, DRV_NAME);
4084         if (err)
4085                 goto out_pci_disable_device;
4086
4087         pci_set_drvdata(pdev, priv);
4088
4089
4090         /***********************
4091          * 3. Read REV register
4092          ***********************/
4093         priv->hw_base = pci_iomap(pdev, 0, 0);
4094         if (!priv->hw_base) {
4095                 err = -ENODEV;
4096                 goto out_pci_release_regions;
4097         }
4098
4099         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4100                 (unsigned long long) pci_resource_len(pdev, 0));
4101         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4102
4103         /* these spin locks will be used in apm_ops.init and EEPROM access
4104          * we should init now
4105          */
4106         spin_lock_init(&priv->reg_lock);
4107         spin_lock_init(&priv->lock);
4108
4109         /*
4110          * stop and reset the on-board processor just in case it is in a
4111          * strange state ... like being left stranded by a primary kernel
4112          * and this is now the kdump kernel trying to start up
4113          */
4114         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4115
4116         iwl_hw_detect(priv);
4117         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4118                 priv->cfg->name, priv->hw_rev);
4119
4120         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4121          * PCI Tx retries from interfering with C3 CPU state */
4122         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4123
4124         iwl_prepare_card_hw(priv);
4125         if (!priv->hw_ready) {
4126                 IWL_WARN(priv, "Failed, HW not ready\n");
4127                 goto out_iounmap;
4128         }
4129
4130         /*****************
4131          * 4. Read EEPROM
4132          *****************/
4133         /* Read the EEPROM */
4134         err = iwl_eeprom_init(priv);
4135         if (err) {
4136                 IWL_ERR(priv, "Unable to init EEPROM\n");
4137                 goto out_iounmap;
4138         }
4139         err = iwl_eeprom_check_version(priv);
4140         if (err)
4141                 goto out_free_eeprom;
4142
4143         err = iwl_eeprom_check_sku(priv);
4144         if (err)
4145                 goto out_free_eeprom;
4146
4147         /* extract MAC Address */
4148         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4149         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4150         priv->hw->wiphy->addresses = priv->addresses;
4151         priv->hw->wiphy->n_addresses = 1;
4152         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4153         if (num_mac > 1) {
4154                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4155                        ETH_ALEN);
4156                 priv->addresses[1].addr[5]++;
4157                 priv->hw->wiphy->n_addresses++;
4158         }
4159
4160         /************************
4161          * 5. Setup HW constants
4162          ************************/
4163         if (iwl_set_hw_params(priv)) {
4164                 IWL_ERR(priv, "failed to set hw parameters\n");
4165                 goto out_free_eeprom;
4166         }
4167
4168         /*******************
4169          * 6. Setup priv
4170          *******************/
4171
4172         err = iwl_init_drv(priv);
4173         if (err)
4174                 goto out_free_eeprom;
4175         /* At this point both hw and priv are initialized. */
4176
4177         /********************
4178          * 7. Setup services
4179          ********************/
4180         spin_lock_irqsave(&priv->lock, flags);
4181         iwl_disable_interrupts(priv);
4182         spin_unlock_irqrestore(&priv->lock, flags);
4183
4184         pci_enable_msi(priv->pci_dev);
4185
4186         if (priv->cfg->ops->lib->isr_ops.alloc)
4187                 priv->cfg->ops->lib->isr_ops.alloc(priv);
4188
4189         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
4190                           IRQF_SHARED, DRV_NAME, priv);
4191         if (err) {
4192                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4193                 goto out_disable_msi;
4194         }
4195
4196         iwl_setup_deferred_work(priv);
4197         iwl_setup_rx_handlers(priv);
4198
4199         /*********************************************
4200          * 8. Enable interrupts and read RFKILL state
4201          *********************************************/
4202
4203         /* enable rfkill interrupt: hw bug w/a */
4204         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4205         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4206                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4207                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4208         }
4209
4210         iwl_enable_rfkill_int(priv);
4211
4212         /* If platform's RF_KILL switch is NOT set to KILL */
4213         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4214                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4215         else
4216                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4217
4218         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4219                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4220
4221         iwl_power_initialize(priv);
4222         iwl_tt_initialize(priv);
4223
4224         init_completion(&priv->_agn.firmware_loading_complete);
4225
4226         err = iwl_request_firmware(priv, true);
4227         if (err)
4228                 goto out_destroy_workqueue;
4229
4230         return 0;
4231
4232  out_destroy_workqueue:
4233         destroy_workqueue(priv->workqueue);
4234         priv->workqueue = NULL;
4235         free_irq(priv->pci_dev->irq, priv);
4236         if (priv->cfg->ops->lib->isr_ops.free)
4237                 priv->cfg->ops->lib->isr_ops.free(priv);
4238  out_disable_msi:
4239         pci_disable_msi(priv->pci_dev);
4240         iwl_uninit_drv(priv);
4241  out_free_eeprom:
4242         iwl_eeprom_free(priv);
4243  out_iounmap:
4244         pci_iounmap(pdev, priv->hw_base);
4245  out_pci_release_regions:
4246         pci_set_drvdata(pdev, NULL);
4247         pci_release_regions(pdev);
4248  out_pci_disable_device:
4249         pci_disable_device(pdev);
4250  out_ieee80211_free_hw:
4251         iwl_free_traffic_mem(priv);
4252         ieee80211_free_hw(priv->hw);
4253  out:
4254         return err;
4255 }
4256
4257 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4258 {
4259         struct iwl_priv *priv = pci_get_drvdata(pdev);
4260         unsigned long flags;
4261
4262         if (!priv)
4263                 return;
4264
4265         wait_for_completion(&priv->_agn.firmware_loading_complete);
4266
4267         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4268
4269         iwl_dbgfs_unregister(priv);
4270         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4271
4272         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4273          * to be called and iwl_down since we are removing the device
4274          * we need to set STATUS_EXIT_PENDING bit.
4275          */
4276         set_bit(STATUS_EXIT_PENDING, &priv->status);
4277
4278         iwl_leds_exit(priv);
4279
4280         if (priv->mac80211_registered) {
4281                 ieee80211_unregister_hw(priv->hw);
4282                 priv->mac80211_registered = 0;
4283         } else {
4284                 iwl_down(priv);
4285         }
4286
4287         /*
4288          * Make sure device is reset to low power before unloading driver.
4289          * This may be redundant with iwl_down(), but there are paths to
4290          * run iwl_down() without calling apm_ops.stop(), and there are
4291          * paths to avoid running iwl_down() at all before leaving driver.
4292          * This (inexpensive) call *makes sure* device is reset.
4293          */
4294         iwl_apm_stop(priv);
4295
4296         iwl_tt_exit(priv);
4297
4298         /* make sure we flush any pending irq or
4299          * tasklet for the driver
4300          */
4301         spin_lock_irqsave(&priv->lock, flags);
4302         iwl_disable_interrupts(priv);
4303         spin_unlock_irqrestore(&priv->lock, flags);
4304
4305         iwl_synchronize_irq(priv);
4306
4307         iwl_dealloc_ucode_pci(priv);
4308
4309         if (priv->rxq.bd)
4310                 iwlagn_rx_queue_free(priv, &priv->rxq);
4311         iwlagn_hw_txq_ctx_free(priv);
4312
4313         iwl_eeprom_free(priv);
4314
4315
4316         /*netif_stop_queue(dev); */
4317         flush_workqueue(priv->workqueue);
4318
4319         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4320          * priv->workqueue... so we can't take down the workqueue
4321          * until now... */
4322         destroy_workqueue(priv->workqueue);
4323         priv->workqueue = NULL;
4324         iwl_free_traffic_mem(priv);
4325
4326         free_irq(priv->pci_dev->irq, priv);
4327         pci_disable_msi(priv->pci_dev);
4328         pci_iounmap(pdev, priv->hw_base);
4329         pci_release_regions(pdev);
4330         pci_disable_device(pdev);
4331         pci_set_drvdata(pdev, NULL);
4332
4333         iwl_uninit_drv(priv);
4334
4335         if (priv->cfg->ops->lib->isr_ops.free)
4336                 priv->cfg->ops->lib->isr_ops.free(priv);
4337
4338         dev_kfree_skb(priv->beacon_skb);
4339
4340         ieee80211_free_hw(priv->hw);
4341 }
4342
4343
4344 /*****************************************************************************
4345  *
4346  * driver and module entry point
4347  *
4348  *****************************************************************************/
4349
4350 /* Hardware specific file defines the PCI IDs table for that hardware module */
4351 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4352         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4353         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4354         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4355         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4356         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4357         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4358         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4359         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4360         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4361         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4362         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4363         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4364         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4365         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4366         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4367         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4368         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4369         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4370         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4371         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4372         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4373         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4374         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4375         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4376
4377 /* 5300 Series WiFi */
4378         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4379         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4380         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4381         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4382         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4383         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4384         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4385         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4386         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4387         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4388         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4389         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4390
4391 /* 5350 Series WiFi/WiMax */
4392         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4393         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4394         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4395
4396 /* 5150 Series Wifi/WiMax */
4397         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4398         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4399         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4400         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4401         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4402         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4403
4404         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4405         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4406         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4407         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4408
4409 /* 6x00 Series */
4410         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4411         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4412         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4413         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4414         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4415         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4416         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4417         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4418         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4419         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4420
4421 /* 6x05 Series */
4422         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4423         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4424         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4425         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4426         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4427         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4428         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4429
4430 /* 6x30 Series */
4431         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4432         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4433         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4434         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4435         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4436         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4437         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4438         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4439         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4440         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4441         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4442         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4443         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4444         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4445         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4446         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4447
4448 /* 6x50 WiFi/WiMax Series */
4449         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4450         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4451         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4452         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4453         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4454         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4455
4456 /* 6150 WiFi/WiMax Series */
4457         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4458         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4459         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4460         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4461         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4462         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4463
4464 /* 1000 Series WiFi */
4465         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4466         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4467         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4468         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4469         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4470         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4471         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4472         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4473         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4474         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4475         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4476         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4477
4478 /* 100 Series WiFi */
4479         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4480         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4481         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4482         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4483         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4484         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4485
4486 /* 130 Series WiFi */
4487         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4488         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4489         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4490         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4491         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4492         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4493
4494 /* 2x00 Series */
4495         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4496         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4497         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4498         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4499         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4500         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4501
4502 /* 2x30 Series */
4503         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4504         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4505         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4506         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4507         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4508         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4509
4510 /* 6x35 Series */
4511         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4512         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4513         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4514         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4515         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4516         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4517         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4518         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4519         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4520
4521 /* 200 Series */
4522         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4523         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4524         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4525         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4526         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4527         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4528
4529 /* 230 Series */
4530         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4531         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4532         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4533         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4534         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4535         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4536
4537         {0}
4538 };
4539 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4540
4541 static struct pci_driver iwl_driver = {
4542         .name = DRV_NAME,
4543         .id_table = iwl_hw_card_ids,
4544         .probe = iwl_pci_probe,
4545         .remove = __devexit_p(iwl_pci_remove),
4546         .driver.pm = IWL_PM_OPS,
4547 };
4548
4549 static int __init iwl_init(void)
4550 {
4551
4552         int ret;
4553         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4554         pr_info(DRV_COPYRIGHT "\n");
4555
4556         ret = iwlagn_rate_control_register();
4557         if (ret) {
4558                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4559                 return ret;
4560         }
4561
4562         ret = pci_register_driver(&iwl_driver);
4563         if (ret) {
4564                 pr_err("Unable to initialize PCI module\n");
4565                 goto error_register;
4566         }
4567
4568         return ret;
4569
4570 error_register:
4571         iwlagn_rate_control_unregister();
4572         return ret;
4573 }
4574
4575 static void __exit iwl_exit(void)
4576 {
4577         pci_unregister_driver(&iwl_driver);
4578         iwlagn_rate_control_unregister();
4579 }
4580
4581 module_exit(iwl_exit);
4582 module_init(iwl_init);
4583
4584 #ifdef CONFIG_IWLWIFI_DEBUG
4585 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4586 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4587 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4588 MODULE_PARM_DESC(debug, "debug output mask");
4589 #endif
4590
4591 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4592 MODULE_PARM_DESC(swcrypto50,
4593                  "using crypto in software (default 0 [hardware]) (deprecated)");
4594 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4595 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4596 module_param_named(queues_num50,
4597                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4598 MODULE_PARM_DESC(queues_num50,
4599                  "number of hw queues in 50xx series (deprecated)");
4600 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4601 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4602 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4603 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4604 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4605 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4606 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4607                    int, S_IRUGO);
4608 MODULE_PARM_DESC(amsdu_size_8K50,
4609                  "enable 8K amsdu size in 50XX series (deprecated)");
4610 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4611                    int, S_IRUGO);
4612 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4613 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4614 MODULE_PARM_DESC(fw_restart50,
4615                  "restart firmware in case of error (deprecated)");
4616 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4617 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4618 module_param_named(
4619         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4620 MODULE_PARM_DESC(disable_hw_scan,
4621                  "disable hardware scanning (default 0) (deprecated)");
4622
4623 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4624                    S_IRUGO);
4625 MODULE_PARM_DESC(ucode_alternative,
4626                  "specify ucode alternative to use from ucode file");
4627
4628 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4629 MODULE_PARM_DESC(antenna_coupling,
4630                  "specify antenna coupling in dB (defualt: 0 dB)");
4631
4632 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4633 MODULE_PARM_DESC(bt_ch_inhibition,
4634                  "Disable BT channel inhibition (default: enable)");
4635
4636 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4637 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4638
4639 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4640 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");