drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-agn-calib.h"
  61 #include "iwl-agn.h"
  62 #include "iwl-agn-led.h"
  63
  64
  65 /******************************************************************************
  66  *
  67  * module boiler plate
  68  *
  69  ******************************************************************************/
  70
  71 /*
  72  * module name, copyright, version, etc.
  73  */
  74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  75
  76 #ifdef CONFIG_IWLWIFI_DEBUG
  77 #define VD "d"
  78 #else
  79 #define VD
  80 #endif
  81
  82 #define DRV_VERSION     IWLWIFI_VERSION VD
  83
  84
  85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86 MODULE_VERSION(DRV_VERSION);
  87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  88 MODULE_LICENSE("GPL");
  89 MODULE_ALIAS("iwl4965");
  90
  91 static int iwlagn_ant_coupling;
  92 static bool iwlagn_bt_ch_announce = 1;
  93
  94 void iwl_update_chain_flags(struct iwl_priv *priv)
  95 {
  96         struct iwl_rxon_context *ctx;
  97
  98         if (priv->cfg->ops->hcmd->set_rxon_chain) {
  99                 for_each_context(priv, ctx) {
 100                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 101                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
 102                                 iwlcore_commit_rxon(priv, ctx);
 103                 }
 104         }
 105 }
 106
 107 static void iwl_clear_free_frames(struct iwl_priv *priv)
 108 {
 109         struct list_head *element;
 110
 111         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 112                        priv->frames_count);
 113
 114         while (!list_empty(&priv->free_frames)) {
 115                 element = priv->free_frames.next;
 116                 list_del(element);
 117                 kfree(list_entry(element, struct iwl_frame, list));
 118                 priv->frames_count--;
 119         }
 120
 121         if (priv->frames_count) {
 122                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 123                             priv->frames_count);
 124                 priv->frames_count = 0;
 125         }
 126 }
 127
 128 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 129 {
 130         struct iwl_frame *frame;
 131         struct list_head *element;
 132         if (list_empty(&priv->free_frames)) {
 133                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 134                 if (!frame) {
 135                         IWL_ERR(priv, "Could not allocate frame!\n");
 136                         return NULL;
 137                 }
 138
 139                 priv->frames_count++;
 140                 return frame;
 141         }
 142
 143         element = priv->free_frames.next;
 144         list_del(element);
 145         return list_entry(element, struct iwl_frame, list);
 146 }
 147
 148 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 149 {
 150         memset(frame, 0, sizeof(*frame));
 151         list_add(&frame->list, &priv->free_frames);
 152 }
 153
 154 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 155                                  struct ieee80211_hdr *hdr,
 156                                  int left)
 157 {
 158         lockdep_assert_held(&priv->mutex);
 159
 160         if (!priv->beacon_skb)
 161                 return 0;
 162
 163         if (priv->beacon_skb->len > left)
 164                 return 0;
 165
 166         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
 167
 168         return priv->beacon_skb->len;
 169 }
 170
 171 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 172 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 173                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 174                                u8 *beacon, u32 frame_size)
 175 {
 176         u16 tim_idx;
 177         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 178
 179         /*
 180          * The index is relative to frame start but we start looking at the
 181          * variable-length part of the beacon.
 182          */
 183         tim_idx = mgmt->u.beacon.variable - beacon;
 184
 185         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 186         while ((tim_idx < (frame_size - 2)) &&
 187                         (beacon[tim_idx] != WLAN_EID_TIM))
 188                 tim_idx += beacon[tim_idx+1] + 2;
 189
 190         /* If TIM field was found, set variables */
 191         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 192                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 193                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 194         } else
 195                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 196 }
 197
 198 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 199                                        struct iwl_frame *frame)
 200 {
 201         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 202         u32 frame_size;
 203         u32 rate_flags;
 204         u32 rate;
 205         /*
 206          * We have to set up the TX command, the TX Beacon command, and the
 207          * beacon contents.
 208          */
 209
 210         lockdep_assert_held(&priv->mutex);
 211
 212         if (!priv->beacon_ctx) {
 213                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 214                 return 0;
 215         }
 216
 217         /* Initialize memory */
 218         tx_beacon_cmd = &frame->u.beacon;
 219         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 220
 221         /* Set up TX beacon contents */
 222         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 223                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 224         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 225                 return 0;
 226         if (!frame_size)
 227                 return 0;
 228
 229         /* Set up TX command fields */
 230         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 231         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 232         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 233         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 234                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 235
 236         /* Set up TX beacon command fields */
 237         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 238                            frame_size);
 239
 240         /* Set up packet rate and flags */
 241         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 242         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 243                                               priv->hw_params.valid_tx_ant);
 244         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 245         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 246                 rate_flags |= RATE_MCS_CCK_MSK;
 247         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 248                         rate_flags);
 249
 250         return sizeof(*tx_beacon_cmd) + frame_size;
 251 }
 252
 253 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
 254 {
 255         struct iwl_frame *frame;
 256         unsigned int frame_size;
 257         int rc;
 258
 259         frame = iwl_get_free_frame(priv);
 260         if (!frame) {
 261                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 262                           "command.\n");
 263                 return -ENOMEM;
 264         }
 265
 266         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 267         if (!frame_size) {
 268                 IWL_ERR(priv, "Error configuring the beacon command\n");
 269                 iwl_free_frame(priv, frame);
 270                 return -EINVAL;
 271         }
 272
 273         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 274                               &frame->u.cmd[0]);
 275
 276         iwl_free_frame(priv, frame);
 277
 278         return rc;
 279 }
 280
 281 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 282 {
 283         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 284
 285         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 286         if (sizeof(dma_addr_t) > sizeof(u32))
 287                 addr |=
 288                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 289
 290         return addr;
 291 }
 292
 293 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 294 {
 295         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 296
 297         return le16_to_cpu(tb->hi_n_len) >> 4;
 298 }
 299
 300 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 301                                   dma_addr_t addr, u16 len)
 302 {
 303         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 304         u16 hi_n_len = len << 4;
 305
 306         put_unaligned_le32(addr, &tb->lo);
 307         if (sizeof(dma_addr_t) > sizeof(u32))
 308                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 309
 310         tb->hi_n_len = cpu_to_le16(hi_n_len);
 311
 312         tfd->num_tbs = idx + 1;
 313 }
 314
 315 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 316 {
 317         return tfd->num_tbs & 0x1f;
 318 }
 319
 320 /**
 321  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 322  * @priv - driver private data
 323  * @txq - tx queue
 324  *
 325  * Does NOT advance any TFD circular buffer read/write indexes
 326  * Does NOT free the TFD itself (which is within circular buffer)
 327  */
 328 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 329 {
 330         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 331         struct iwl_tfd *tfd;
 332         struct pci_dev *dev = priv->pci_dev;
 333         int index = txq->q.read_ptr;
 334         int i;
 335         int num_tbs;
 336
 337         tfd = &tfd_tmp[index];
 338
 339         /* Sanity check on number of chunks */
 340         num_tbs = iwl_tfd_get_num_tbs(tfd);
 341
 342         if (num_tbs >= IWL_NUM_OF_TBS) {
 343                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 344                 /* @todo issue fatal error, it is quite serious situation */
 345                 return;
 346         }
 347
 348         /* Unmap tx_cmd */
 349         if (num_tbs)
 350                 pci_unmap_single(dev,
 351                                 dma_unmap_addr(&txq->meta[index], mapping),
 352                                 dma_unmap_len(&txq->meta[index], len),
 353                                 PCI_DMA_BIDIRECTIONAL);
 354
 355         /* Unmap chunks, if any. */
 356         for (i = 1; i < num_tbs; i++)
 357                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 358                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 359
 360         /* free SKB */
 361         if (txq->txb) {
 362                 struct sk_buff *skb;
 363
 364                 skb = txq->txb[txq->q.read_ptr].skb;
 365
 366                 /* can be called from irqs-disabled context */
 367                 if (skb) {
 368                         dev_kfree_skb_any(skb);
 369                         txq->txb[txq->q.read_ptr].skb = NULL;
 370                 }
 371         }
 372 }
 373
 374 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 375                                  struct iwl_tx_queue *txq,
 376                                  dma_addr_t addr, u16 len,
 377                                  u8 reset, u8 pad)
 378 {
 379         struct iwl_queue *q;
 380         struct iwl_tfd *tfd, *tfd_tmp;
 381         u32 num_tbs;
 382
 383         q = &txq->q;
 384         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 385         tfd = &tfd_tmp[q->write_ptr];
 386
 387         if (reset)
 388                 memset(tfd, 0, sizeof(*tfd));
 389
 390         num_tbs = iwl_tfd_get_num_tbs(tfd);
 391
 392         /* Each TFD can point to a maximum 20 Tx buffers */
 393         if (num_tbs >= IWL_NUM_OF_TBS) {
 394                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 395                           IWL_NUM_OF_TBS);
 396                 return -EINVAL;
 397         }
 398
 399         BUG_ON(addr & ~DMA_BIT_MASK(36));
 400         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 401                 IWL_ERR(priv, "Unaligned address = %llx\n",
 402                           (unsigned long long)addr);
 403
 404         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 405
 406         return 0;
 407 }
 408
 409 /*
 410  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 411  * given Tx queue, and enable the DMA channel used for that queue.
 412  *
 413  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 414  * channels supported in hardware.
 415  */
 416 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 417                          struct iwl_tx_queue *txq)
 418 {
 419         int txq_id = txq->q.id;
 420
 421         /* Circular buffer (TFD queue in DRAM) physical base address */
 422         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 423                              txq->q.dma_addr >> 8);
 424
 425         return 0;
 426 }
 427
 428 /******************************************************************************
 429  *
 430  * Generic RX handler implementations
 431  *
 432  ******************************************************************************/
 433 static void iwl_rx_reply_alive(struct iwl_priv *priv,
 434                                 struct iwl_rx_mem_buffer *rxb)
 435 {
 436         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 437         struct iwl_alive_resp *palive;
 438         struct delayed_work *pwork;
 439
 440         palive = &pkt->u.alive_frame;
 441
 442         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
 443                        "0x%01X 0x%01X\n",
 444                        palive->is_valid, palive->ver_type,
 445                        palive->ver_subtype);
 446
 447         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
 448                 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
 449                 memcpy(&priv->card_alive_init,
 450                        &pkt->u.alive_frame,
 451                        sizeof(struct iwl_init_alive_resp));
 452                 pwork = &priv->init_alive_start;
 453         } else {
 454                 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
 455                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
 456                        sizeof(struct iwl_alive_resp));
 457                 pwork = &priv->alive_start;
 458         }
 459
 460         /* We delay the ALIVE response by 5ms to
 461          * give the HW RF Kill time to activate... */
 462         if (palive->is_valid == UCODE_VALID_OK)
 463                 queue_delayed_work(priv->workqueue, pwork,
 464                                    msecs_to_jiffies(5));
 465         else {
 466                 IWL_WARN(priv, "%s uCode did not respond OK.\n",
 467                         (palive->ver_subtype == INITIALIZE_SUBTYPE) ?
 468                         "init" : "runtime");
 469                 queue_work(priv->workqueue, &priv->restart);
 470         }
 471 }
 472
 473 static void iwl_bg_beacon_update(struct work_struct *work)
 474 {
 475         struct iwl_priv *priv =
 476                 container_of(work, struct iwl_priv, beacon_update);
 477         struct sk_buff *beacon;
 478
 479         mutex_lock(&priv->mutex);
 480         if (!priv->beacon_ctx) {
 481                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 482                 goto out;
 483         }
 484
 485         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 486                 /*
 487                  * The ucode will send beacon notifications even in
 488                  * IBSS mode, but we don't want to process them. But
 489                  * we need to defer the type check to here due to
 490                  * requiring locking around the beacon_ctx access.
 491                  */
 492                 goto out;
 493         }
 494
 495         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 496         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 497         if (!beacon) {
 498                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
 499                 goto out;
 500         }
 501
 502         /* new beacon skb is allocated every time; dispose previous.*/
 503         dev_kfree_skb(priv->beacon_skb);
 504
 505         priv->beacon_skb = beacon;
 506
 507         iwlagn_send_beacon_cmd(priv);
 508  out:
 509         mutex_unlock(&priv->mutex);
 510 }
 511
 512 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 513 {
 514         struct iwl_priv *priv =
 515                 container_of(work, struct iwl_priv, bt_runtime_config);
 516
 517         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 518                 return;
 519
 520         /* dont send host command if rf-kill is on */
 521         if (!iwl_is_ready_rf(priv))
 522                 return;
 523         priv->cfg->ops->hcmd->send_bt_config(priv);
 524 }
 525
 526 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 527 {
 528         struct iwl_priv *priv =
 529                 container_of(work, struct iwl_priv, bt_full_concurrency);
 530         struct iwl_rxon_context *ctx;
 531
 532         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 533                 return;
 534
 535         /* dont send host command if rf-kill is on */
 536         if (!iwl_is_ready_rf(priv))
 537                 return;
 538
 539         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 540                        priv->bt_full_concurrent ?
 541                        "full concurrency" : "3-wire");
 542
 543         /*
 544          * LQ & RXON updated cmds must be sent before BT Config cmd
 545          * to avoid 3-wire collisions
 546          */
 547         mutex_lock(&priv->mutex);
 548         for_each_context(priv, ctx) {
 549                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 550                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 551                 iwlcore_commit_rxon(priv, ctx);
 552         }
 553         mutex_unlock(&priv->mutex);
 554
 555         priv->cfg->ops->hcmd->send_bt_config(priv);
 556 }
 557
 558 /**
 559  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 560  *
 561  * This callback is provided in order to send a statistics request.
 562  *
 563  * This timer function is continually reset to execute within
 564  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 565  * was received.  We need to ensure we receive the statistics in order
 566  * to update the temperature used for calibrating the TXPOWER.
 567  */
 568 static void iwl_bg_statistics_periodic(unsigned long data)
 569 {
 570         struct iwl_priv *priv = (struct iwl_priv *)data;
 571
 572         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 573                 return;
 574
 575         /* dont send host command if rf-kill is on */
 576         if (!iwl_is_ready_rf(priv))
 577                 return;
 578
 579         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 580 }
 581
 582
 583 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 584                                         u32 start_idx, u32 num_events,
 585                                         u32 mode)
 586 {
 587         u32 i;
 588         u32 ptr;        /* SRAM byte address of log data */
 589         u32 ev, time, data; /* event log data */
 590         unsigned long reg_flags;
 591
 592         if (mode == 0)
 593                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 594         else
 595                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 596
 597         /* Make sure device is powered up for SRAM reads */
 598         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 599         if (iwl_grab_nic_access(priv)) {
 600                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 601                 return;
 602         }
 603
 604         /* Set starting address; reads will auto-increment */
 605         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 606         rmb();
 607
 608         /*
 609          * "time" is actually "data" for mode 0 (no timestamp).
 610          * place event id # at far right for easier visual parsing.
 611          */
 612         for (i = 0; i < num_events; i++) {
 613                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 614                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 615                 if (mode == 0) {
 616                         trace_iwlwifi_dev_ucode_cont_event(priv,
 617                                                         0, time, ev);
 618                 } else {
 619                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 620                         trace_iwlwifi_dev_ucode_cont_event(priv,
 621                                                 time, data, ev);
 622                 }
 623         }
 624         /* Allow device to power down */
 625         iwl_release_nic_access(priv);
 626         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 627 }
 628
 629 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 630 {
 631         u32 capacity;   /* event log capacity in # entries */
 632         u32 base;       /* SRAM byte address of event log header */
 633         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 634         u32 num_wraps;  /* # times uCode wrapped to top of log */
 635         u32 next_entry; /* index of next entry to be written by uCode */
 636
 637         if (priv->ucode_type == UCODE_INIT)
 638                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 639         else
 640                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 641         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 642                 capacity = iwl_read_targ_mem(priv, base);
 643                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 644                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 645                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 646         } else
 647                 return;
 648
 649         if (num_wraps == priv->event_log.num_wraps) {
 650                 iwl_print_cont_event_trace(priv,
 651                                        base, priv->event_log.next_entry,
 652                                        next_entry - priv->event_log.next_entry,
 653                                        mode);
 654                 priv->event_log.non_wraps_count++;
 655         } else {
 656                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 657                         priv->event_log.wraps_more_count++;
 658                 else
 659                         priv->event_log.wraps_once_count++;
 660                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 661                                 num_wraps - priv->event_log.num_wraps,
 662                                 next_entry, priv->event_log.next_entry);
 663                 if (next_entry < priv->event_log.next_entry) {
 664                         iwl_print_cont_event_trace(priv, base,
 665                                priv->event_log.next_entry,
 666                                capacity - priv->event_log.next_entry,
 667                                mode);
 668
 669                         iwl_print_cont_event_trace(priv, base, 0,
 670                                 next_entry, mode);
 671                 } else {
 672                         iwl_print_cont_event_trace(priv, base,
 673                                next_entry, capacity - next_entry,
 674                                mode);
 675
 676                         iwl_print_cont_event_trace(priv, base, 0,
 677                                 next_entry, mode);
 678                 }
 679         }
 680         priv->event_log.num_wraps = num_wraps;
 681         priv->event_log.next_entry = next_entry;
 682 }
 683
 684 /**
 685  * iwl_bg_ucode_trace - Timer callback to log ucode event
 686  *
 687  * The timer is continually set to execute every
 688  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 689  * this function is to perform continuous uCode event logging operation
 690  * if enabled
 691  */
 692 static void iwl_bg_ucode_trace(unsigned long data)
 693 {
 694         struct iwl_priv *priv = (struct iwl_priv *)data;
 695
 696         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 697                 return;
 698
 699         if (priv->event_log.ucode_trace) {
 700                 iwl_continuous_event_trace(priv);
 701                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 702                 mod_timer(&priv->ucode_trace,
 703                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 704         }
 705 }
 706
 707 static void iwlagn_rx_beacon_notif(struct iwl_priv *priv,
 708                                    struct iwl_rx_mem_buffer *rxb)
 709 {
 710         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 711         struct iwlagn_beacon_notif *beacon = (void *)pkt->u.raw;
 712 #ifdef CONFIG_IWLWIFI_DEBUG
 713         u16 status = le16_to_cpu(beacon->beacon_notify_hdr.status.status);
 714         u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
 715
 716         IWL_DEBUG_RX(priv, "beacon status %#x, retries:%d ibssmgr:%d "
 717                 "tsf:0x%.8x%.8x rate:%d\n",
 718                 status & TX_STATUS_MSK,
 719                 beacon->beacon_notify_hdr.failure_frame,
 720                 le32_to_cpu(beacon->ibss_mgr_status),
 721                 le32_to_cpu(beacon->high_tsf),
 722                 le32_to_cpu(beacon->low_tsf), rate);
 723 #endif
 724
 725         priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
 726
 727         if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 728                 queue_work(priv->workqueue, &priv->beacon_update);
 729 }
 730
 731 /* Handle notification from uCode that card's power state is changing
 732  * due to software, hardware, or critical temperature RFKILL */
 733 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
 734                                     struct iwl_rx_mem_buffer *rxb)
 735 {
 736         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 737         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
 738         unsigned long status = priv->status;
 739
 740         IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
 741                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
 742                           (flags & SW_CARD_DISABLED) ? "Kill" : "On",
 743                           (flags & CT_CARD_DISABLED) ?
 744                           "Reached" : "Not reached");
 745
 746         if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
 747                      CT_CARD_DISABLED)) {
 748
 749                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
 750                             CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 751
 752                 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 753                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 754
 755                 if (!(flags & RXON_CARD_DISABLED)) {
 756                         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 757                                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 758                         iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 759                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 760                 }
 761                 if (flags & CT_CARD_DISABLED)
 762                         iwl_tt_enter_ct_kill(priv);
 763         }
 764         if (!(flags & CT_CARD_DISABLED))
 765                 iwl_tt_exit_ct_kill(priv);
 766
 767         if (flags & HW_CARD_DISABLED)
 768                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 769         else
 770                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 771
 772
 773         if (!(flags & RXON_CARD_DISABLED))
 774                 iwl_scan_cancel(priv);
 775
 776         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
 777              test_bit(STATUS_RF_KILL_HW, &priv->status)))
 778                 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
 779                         test_bit(STATUS_RF_KILL_HW, &priv->status));
 780         else
 781                 wake_up_interruptible(&priv->wait_command_queue);
 782 }
 783
 784 static void iwl_bg_tx_flush(struct work_struct *work)
 785 {
 786         struct iwl_priv *priv =
 787                 container_of(work, struct iwl_priv, tx_flush);
 788
 789         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 790                 return;
 791
 792         /* do nothing if rf-kill is on */
 793         if (!iwl_is_ready_rf(priv))
 794                 return;
 795
 796         if (priv->cfg->ops->lib->txfifo_flush) {
 797                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 798                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 799         }
 800 }
 801
 802 /**
 803  * iwl_setup_rx_handlers - Initialize Rx handler callbacks
 804  *
 805  * Setup the RX handlers for each of the reply types sent from the uCode
 806  * to the host.
 807  *
 808  * This function chains into the hardware specific files for them to setup
 809  * any hardware specific handlers as well.
 810  */
 811 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
 812 {
 813         priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
 814         priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
 815         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
 816         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
 817                         iwl_rx_spectrum_measure_notif;
 818         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
 819         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
 820             iwl_rx_pm_debug_statistics_notif;
 821         priv->rx_handlers[BEACON_NOTIFICATION] = iwlagn_rx_beacon_notif;
 822
 823         /*
 824          * The same handler is used for both the REPLY to a discrete
 825          * statistics request from the host as well as for the periodic
 826          * statistics notifications (after received beacons) from the uCode.
 827          */
 828         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
 829         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
 830
 831         iwl_setup_rx_scan_handlers(priv);
 832
 833         /* status change handler */
 834         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
 835
 836         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
 837             iwl_rx_missed_beacon_notif;
 838         /* Rx handlers */
 839         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
 840         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
 841         /* block ack */
 842         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
 843         /* Set up hardware specific Rx handlers */
 844         priv->cfg->ops->lib->rx_handler_setup(priv);
 845 }
 846
 847 /**
 848  * iwl_rx_handle - Main entry function for receiving responses from uCode
 849  *
 850  * Uses the priv->rx_handlers callback function array to invoke
 851  * the appropriate handlers, including command responses,
 852  * frame-received notifications, and other notifications.
 853  */
 854 static void iwl_rx_handle(struct iwl_priv *priv)
 855 {
 856         struct iwl_rx_mem_buffer *rxb;
 857         struct iwl_rx_packet *pkt;
 858         struct iwl_rx_queue *rxq = &priv->rxq;
 859         u32 r, i;
 860         int reclaim;
 861         unsigned long flags;
 862         u8 fill_rx = 0;
 863         u32 count = 8;
 864         int total_empty;
 865
 866         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 867          * buffer that the driver may process (last buffer filled by ucode). */
 868         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 869         i = rxq->read;
 870
 871         /* Rx interrupt, but nothing sent from uCode */
 872         if (i == r)
 873                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
 874
 875         /* calculate total frames need to be restock after handling RX */
 876         total_empty = r - rxq->write_actual;
 877         if (total_empty < 0)
 878                 total_empty += RX_QUEUE_SIZE;
 879
 880         if (total_empty > (RX_QUEUE_SIZE / 2))
 881                 fill_rx = 1;
 882
 883         while (i != r) {
 884                 int len;
 885
 886                 rxb = rxq->queue[i];
 887
 888                 /* If an RXB doesn't have a Rx queue slot associated with it,
 889                  * then a bug has been introduced in the queue refilling
 890                  * routines -- catch it here */
 891                 BUG_ON(rxb == NULL);
 892
 893                 rxq->queue[i] = NULL;
 894
 895                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
 896                                PAGE_SIZE << priv->hw_params.rx_page_order,
 897                                PCI_DMA_FROMDEVICE);
 898                 pkt = rxb_addr(rxb);
 899
 900                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 901                 len += sizeof(u32); /* account for status word */
 902                 trace_iwlwifi_dev_rx(priv, pkt, len);
 903
 904                 /* Reclaim a command buffer only if this packet is a response
 905                  *   to a (driver-originated) command.
 906                  * If the packet (e.g. Rx frame) originated from uCode,
 907                  *   there is no command buffer to reclaim.
 908                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 909                  *   but apparently a few don't get set; catch them here. */
 910                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 911                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 912                         (pkt->hdr.cmd != REPLY_RX) &&
 913                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 914                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 915                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 916                         (pkt->hdr.cmd != REPLY_TX);
 917
 918                 /*
 919                  * Do the notification wait before RX handlers so
 920                  * even if the RX handler consumes the RXB we have
 921                  * access to it in the notification wait entry.
 922                  */
 923                 if (!list_empty(&priv->_agn.notif_waits)) {
 924                         struct iwl_notification_wait *w;
 925
 926                         spin_lock(&priv->_agn.notif_wait_lock);
 927                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
 928                                 if (w->cmd == pkt->hdr.cmd) {
 929                                         w->triggered = true;
 930                                         if (w->fn)
 931                                                 w->fn(priv, pkt);
 932                                 }
 933                         }
 934                         spin_unlock(&priv->_agn.notif_wait_lock);
 935
 936                         wake_up_all(&priv->_agn.notif_waitq);
 937                 }
 938
 939                 /* Based on type of command response or notification,
 940                  *   handle those that need handling via function in
 941                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
 942                 if (priv->rx_handlers[pkt->hdr.cmd]) {
 943                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
 944                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 945                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
 946                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
 947                 } else {
 948                         /* No handling needed */
 949                         IWL_DEBUG_RX(priv,
 950                                 "r %d i %d No handler needed for %s, 0x%02x\n",
 951                                 r, i, get_cmd_string(pkt->hdr.cmd),
 952                                 pkt->hdr.cmd);
 953                 }
 954
 955                 /*
 956                  * XXX: After here, we should always check rxb->page
 957                  * against NULL before touching it or its virtual
 958                  * memory (pkt). Because some rx_handler might have
 959                  * already taken or freed the pages.
 960                  */
 961
 962                 if (reclaim) {
 963                         /* Invoke any callbacks, transfer the buffer to caller,
 964                          * and fire off the (possibly) blocking iwl_send_cmd()
 965                          * as we reclaim the driver command queue */
 966                         if (rxb->page)
 967                                 iwl_tx_cmd_complete(priv, rxb);
 968                         else
 969                                 IWL_WARN(priv, "Claim null rxb?\n");
 970                 }
 971
 972                 /* Reuse the page if possible. For notification packets and
 973                  * SKBs that fail to Rx correctly, add them back into the
 974                  * rx_free list for reuse later. */
 975                 spin_lock_irqsave(&rxq->lock, flags);
 976                 if (rxb->page != NULL) {
 977                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
 978                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
 979                                 PCI_DMA_FROMDEVICE);
 980                         list_add_tail(&rxb->list, &rxq->rx_free);
 981                         rxq->free_count++;
 982                 } else
 983                         list_add_tail(&rxb->list, &rxq->rx_used);
 984
 985                 spin_unlock_irqrestore(&rxq->lock, flags);
 986
 987                 i = (i + 1) & RX_QUEUE_MASK;
 988                 /* If there are a lot of unused frames,
 989                  * restock the Rx queue so ucode wont assert. */
 990                 if (fill_rx) {
 991                         count++;
 992                         if (count >= 8) {
 993                                 rxq->read = i;
 994                                 iwlagn_rx_replenish_now(priv);
 995                                 count = 0;
 996                         }
 997                 }
 998         }
 999
1000         /* Backtrack one entry */
1001         rxq->read = i;
1002         if (fill_rx)
1003                 iwlagn_rx_replenish_now(priv);
1004         else
1005                 iwlagn_rx_queue_restock(priv);
1006 }
1007
1008 /* call this function to flush any scheduled tasklet */
1009 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1010 {
1011         /* wait to make sure we flush pending tasklet*/
1012         synchronize_irq(priv->pci_dev->irq);
1013         tasklet_kill(&priv->irq_tasklet);
1014 }
1015
1016 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1017 {
1018         u32 inta, handled = 0;
1019         u32 inta_fh;
1020         unsigned long flags;
1021         u32 i;
1022 #ifdef CONFIG_IWLWIFI_DEBUG
1023         u32 inta_mask;
1024 #endif
1025
1026         spin_lock_irqsave(&priv->lock, flags);
1027
1028         /* Ack/clear/reset pending uCode interrupts.
1029          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1030          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1031         inta = iwl_read32(priv, CSR_INT);
1032         iwl_write32(priv, CSR_INT, inta);
1033
1034         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1035          * Any new interrupts that happen after this, either while we're
1036          * in this tasklet, or later, will show up in next ISR/tasklet. */
1037         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1038         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1039
1040 #ifdef CONFIG_IWLWIFI_DEBUG
1041         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1042                 /* just for debug */
1043                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1044                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1045                               inta, inta_mask, inta_fh);
1046         }
1047 #endif
1048
1049         spin_unlock_irqrestore(&priv->lock, flags);
1050
1051         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1052          * atomic, make sure that inta covers all the interrupts that
1053          * we've discovered, even if FH interrupt came in just after
1054          * reading CSR_INT. */
1055         if (inta_fh & CSR49_FH_INT_RX_MASK)
1056                 inta |= CSR_INT_BIT_FH_RX;
1057         if (inta_fh & CSR49_FH_INT_TX_MASK)
1058                 inta |= CSR_INT_BIT_FH_TX;
1059
1060         /* Now service all interrupt bits discovered above. */
1061         if (inta & CSR_INT_BIT_HW_ERR) {
1062                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1063
1064                 /* Tell the device to stop sending interrupts */
1065                 iwl_disable_interrupts(priv);
1066
1067                 priv->isr_stats.hw++;
1068                 iwl_irq_handle_error(priv);
1069
1070                 handled |= CSR_INT_BIT_HW_ERR;
1071
1072                 return;
1073         }
1074
1075 #ifdef CONFIG_IWLWIFI_DEBUG
1076         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1077                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1078                 if (inta & CSR_INT_BIT_SCD) {
1079                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1080                                       "the frame/frames.\n");
1081                         priv->isr_stats.sch++;
1082                 }
1083
1084                 /* Alive notification via Rx interrupt will do the real work */
1085                 if (inta & CSR_INT_BIT_ALIVE) {
1086                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1087                         priv->isr_stats.alive++;
1088                 }
1089         }
1090 #endif
1091         /* Safely ignore these bits for debug checks below */
1092         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1093
1094         /* HW RF KILL switch toggled */
1095         if (inta & CSR_INT_BIT_RF_KILL) {
1096                 int hw_rf_kill = 0;
1097                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1098                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1099                         hw_rf_kill = 1;
1100
1101                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1102                                 hw_rf_kill ? "disable radio" : "enable radio");
1103
1104                 priv->isr_stats.rfkill++;
1105
1106                 /* driver only loads ucode once setting the interface up.
1107                  * the driver allows loading the ucode even if the radio
1108                  * is killed. Hence update the killswitch state here. The
1109                  * rfkill handler will care about restarting if needed.
1110                  */
1111                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1112                         if (hw_rf_kill)
1113                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1114                         else
1115                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1116                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1117                 }
1118
1119                 handled |= CSR_INT_BIT_RF_KILL;
1120         }
1121
1122         /* Chip got too hot and stopped itself */
1123         if (inta & CSR_INT_BIT_CT_KILL) {
1124                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1125                 priv->isr_stats.ctkill++;
1126                 handled |= CSR_INT_BIT_CT_KILL;
1127         }
1128
1129         /* Error detected by uCode */
1130         if (inta & CSR_INT_BIT_SW_ERR) {
1131                 IWL_ERR(priv, "Microcode SW error detected. "
1132                         " Restarting 0x%X.\n", inta);
1133                 priv->isr_stats.sw++;
1134                 iwl_irq_handle_error(priv);
1135                 handled |= CSR_INT_BIT_SW_ERR;
1136         }
1137
1138         /*
1139          * uCode wakes up after power-down sleep.
1140          * Tell device about any new tx or host commands enqueued,
1141          * and about any Rx buffers made available while asleep.
1142          */
1143         if (inta & CSR_INT_BIT_WAKEUP) {
1144                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1145                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1146                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1147                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1148                 priv->isr_stats.wakeup++;
1149                 handled |= CSR_INT_BIT_WAKEUP;
1150         }
1151
1152         /* All uCode command responses, including Tx command responses,
1153          * Rx "responses" (frame-received notification), and other
1154          * notifications from uCode come through here*/
1155         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1156                 iwl_rx_handle(priv);
1157                 priv->isr_stats.rx++;
1158                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1159         }
1160
1161         /* This "Tx" DMA channel is used only for loading uCode */
1162         if (inta & CSR_INT_BIT_FH_TX) {
1163                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1164                 priv->isr_stats.tx++;
1165                 handled |= CSR_INT_BIT_FH_TX;
1166                 /* Wake up uCode load routine, now that load is complete */
1167                 priv->ucode_write_complete = 1;
1168                 wake_up_interruptible(&priv->wait_command_queue);
1169         }
1170
1171         if (inta & ~handled) {
1172                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1173                 priv->isr_stats.unhandled++;
1174         }
1175
1176         if (inta & ~(priv->inta_mask)) {
1177                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1178                          inta & ~priv->inta_mask);
1179                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1180         }
1181
1182         /* Re-enable all interrupts */
1183         /* only Re-enable if disabled by irq */
1184         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1185                 iwl_enable_interrupts(priv);
1186         /* Re-enable RF_KILL if it occurred */
1187         else if (handled & CSR_INT_BIT_RF_KILL)
1188                 iwl_enable_rfkill_int(priv);
1189
1190 #ifdef CONFIG_IWLWIFI_DEBUG
1191         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1192                 inta = iwl_read32(priv, CSR_INT);
1193                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1194                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1195                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1196                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1197         }
1198 #endif
1199 }
1200
1201 /* tasklet for iwlagn interrupt */
1202 static void iwl_irq_tasklet(struct iwl_priv *priv)
1203 {
1204         u32 inta = 0;
1205         u32 handled = 0;
1206         unsigned long flags;
1207         u32 i;
1208 #ifdef CONFIG_IWLWIFI_DEBUG
1209         u32 inta_mask;
1210 #endif
1211
1212         spin_lock_irqsave(&priv->lock, flags);
1213
1214         /* Ack/clear/reset pending uCode interrupts.
1215          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1216          */
1217         /* There is a hardware bug in the interrupt mask function that some
1218          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1219          * they are disabled in the CSR_INT_MASK register. Furthermore the
1220          * ICT interrupt handling mechanism has another bug that might cause
1221          * these unmasked interrupts fail to be detected. We workaround the
1222          * hardware bugs here by ACKing all the possible interrupts so that
1223          * interrupt coalescing can still be achieved.
1224          */
1225         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1226
1227         inta = priv->_agn.inta;
1228
1229 #ifdef CONFIG_IWLWIFI_DEBUG
1230         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1231                 /* just for debug */
1232                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1233                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1234                                 inta, inta_mask);
1235         }
1236 #endif
1237
1238         spin_unlock_irqrestore(&priv->lock, flags);
1239
1240         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1241         priv->_agn.inta = 0;
1242
1243         /* Now service all interrupt bits discovered above. */
1244         if (inta & CSR_INT_BIT_HW_ERR) {
1245                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1246
1247                 /* Tell the device to stop sending interrupts */
1248                 iwl_disable_interrupts(priv);
1249
1250                 priv->isr_stats.hw++;
1251                 iwl_irq_handle_error(priv);
1252
1253                 handled |= CSR_INT_BIT_HW_ERR;
1254
1255                 return;
1256         }
1257
1258 #ifdef CONFIG_IWLWIFI_DEBUG
1259         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1260                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1261                 if (inta & CSR_INT_BIT_SCD) {
1262                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1263                                       "the frame/frames.\n");
1264                         priv->isr_stats.sch++;
1265                 }
1266
1267                 /* Alive notification via Rx interrupt will do the real work */
1268                 if (inta & CSR_INT_BIT_ALIVE) {
1269                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1270                         priv->isr_stats.alive++;
1271                 }
1272         }
1273 #endif
1274         /* Safely ignore these bits for debug checks below */
1275         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1276
1277         /* HW RF KILL switch toggled */
1278         if (inta & CSR_INT_BIT_RF_KILL) {
1279                 int hw_rf_kill = 0;
1280                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1281                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1282                         hw_rf_kill = 1;
1283
1284                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1285                                 hw_rf_kill ? "disable radio" : "enable radio");
1286
1287                 priv->isr_stats.rfkill++;
1288
1289                 /* driver only loads ucode once setting the interface up.
1290                  * the driver allows loading the ucode even if the radio
1291                  * is killed. Hence update the killswitch state here. The
1292                  * rfkill handler will care about restarting if needed.
1293                  */
1294                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1295                         if (hw_rf_kill)
1296                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1297                         else
1298                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1299                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1300                 }
1301
1302                 handled |= CSR_INT_BIT_RF_KILL;
1303         }
1304
1305         /* Chip got too hot and stopped itself */
1306         if (inta & CSR_INT_BIT_CT_KILL) {
1307                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1308                 priv->isr_stats.ctkill++;
1309                 handled |= CSR_INT_BIT_CT_KILL;
1310         }
1311
1312         /* Error detected by uCode */
1313         if (inta & CSR_INT_BIT_SW_ERR) {
1314                 IWL_ERR(priv, "Microcode SW error detected. "
1315                         " Restarting 0x%X.\n", inta);
1316                 priv->isr_stats.sw++;
1317                 iwl_irq_handle_error(priv);
1318                 handled |= CSR_INT_BIT_SW_ERR;
1319         }
1320
1321         /* uCode wakes up after power-down sleep */
1322         if (inta & CSR_INT_BIT_WAKEUP) {
1323                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1324                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1325                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1326                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1327
1328                 priv->isr_stats.wakeup++;
1329
1330                 handled |= CSR_INT_BIT_WAKEUP;
1331         }
1332
1333         /* All uCode command responses, including Tx command responses,
1334          * Rx "responses" (frame-received notification), and other
1335          * notifications from uCode come through here*/
1336         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1337                         CSR_INT_BIT_RX_PERIODIC)) {
1338                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1339                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1340                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1341                         iwl_write32(priv, CSR_FH_INT_STATUS,
1342                                         CSR49_FH_INT_RX_MASK);
1343                 }
1344                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1345                         handled |= CSR_INT_BIT_RX_PERIODIC;
1346                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1347                 }
1348                 /* Sending RX interrupt require many steps to be done in the
1349                  * the device:
1350                  * 1- write interrupt to current index in ICT table.
1351                  * 2- dma RX frame.
1352                  * 3- update RX shared data to indicate last write index.
1353                  * 4- send interrupt.
1354                  * This could lead to RX race, driver could receive RX interrupt
1355                  * but the shared data changes does not reflect this;
1356                  * periodic interrupt will detect any dangling Rx activity.
1357                  */
1358
1359                 /* Disable periodic interrupt; we use it as just a one-shot. */
1360                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1361                             CSR_INT_PERIODIC_DIS);
1362                 iwl_rx_handle(priv);
1363
1364                 /*
1365                  * Enable periodic interrupt in 8 msec only if we received
1366                  * real RX interrupt (instead of just periodic int), to catch
1367                  * any dangling Rx interrupt.  If it was just the periodic
1368                  * interrupt, there was no dangling Rx activity, and no need
1369                  * to extend the periodic interrupt; one-shot is enough.
1370                  */
1371                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1372                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1373                                     CSR_INT_PERIODIC_ENA);
1374
1375                 priv->isr_stats.rx++;
1376         }
1377
1378         /* This "Tx" DMA channel is used only for loading uCode */
1379         if (inta & CSR_INT_BIT_FH_TX) {
1380                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1381                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1382                 priv->isr_stats.tx++;
1383                 handled |= CSR_INT_BIT_FH_TX;
1384                 /* Wake up uCode load routine, now that load is complete */
1385                 priv->ucode_write_complete = 1;
1386                 wake_up_interruptible(&priv->wait_command_queue);
1387         }
1388
1389         if (inta & ~handled) {
1390                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1391                 priv->isr_stats.unhandled++;
1392         }
1393
1394         if (inta & ~(priv->inta_mask)) {
1395                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1396                          inta & ~priv->inta_mask);
1397         }
1398
1399         /* Re-enable all interrupts */
1400         /* only Re-enable if disabled by irq */
1401         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1402                 iwl_enable_interrupts(priv);
1403         /* Re-enable RF_KILL if it occurred */
1404         else if (handled & CSR_INT_BIT_RF_KILL)
1405                 iwl_enable_rfkill_int(priv);
1406 }
1407
1408 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1409 #define ACK_CNT_RATIO (50)
1410 #define BA_TIMEOUT_CNT (5)
1411 #define BA_TIMEOUT_MAX (16)
1412
1413 /**
1414  * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1415  *
1416  * When the ACK count ratio is low and aggregated BA timeout retries exceeding
1417  * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1418  * operation state.
1419  */
1420 bool iwl_good_ack_health(struct iwl_priv *priv, struct iwl_rx_packet *pkt)
1421 {
1422         int actual_delta, expected_delta, ba_timeout_delta;
1423         struct statistics_tx *cur, *old;
1424
1425         if (priv->_agn.agg_tids_count)
1426                 return true;
1427
1428         if (iwl_bt_statistics(priv)) {
1429                 cur = &pkt->u.stats_bt.tx;
1430                 old = &priv->_agn.statistics_bt.tx;
1431         } else {
1432                 cur = &pkt->u.stats.tx;
1433                 old = &priv->_agn.statistics.tx;
1434         }
1435
1436         actual_delta = le32_to_cpu(cur->actual_ack_cnt) -
1437                        le32_to_cpu(old->actual_ack_cnt);
1438         expected_delta = le32_to_cpu(cur->expected_ack_cnt) -
1439                          le32_to_cpu(old->expected_ack_cnt);
1440
1441         /* Values should not be negative, but we do not trust the firmware */
1442         if (actual_delta <= 0 || expected_delta <= 0)
1443                 return true;
1444
1445         ba_timeout_delta = le32_to_cpu(cur->agg.ba_timeout) -
1446                            le32_to_cpu(old->agg.ba_timeout);
1447
1448         if ((actual_delta * 100 / expected_delta) < ACK_CNT_RATIO &&
1449             ba_timeout_delta > BA_TIMEOUT_CNT) {
1450                 IWL_DEBUG_RADIO(priv, "deltas: actual %d expected %d ba_timeout %d\n",
1451                                 actual_delta, expected_delta, ba_timeout_delta);
1452
1453 #ifdef CONFIG_IWLWIFI_DEBUGFS
1454                 /*
1455                  * This is ifdef'ed on DEBUGFS because otherwise the
1456                  * statistics aren't available. If DEBUGFS is set but
1457                  * DEBUG is not, these will just compile out.
1458                  */
1459                 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta %d\n",
1460                                 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1461                 IWL_DEBUG_RADIO(priv,
1462                                 "ack_or_ba_timeout_collision delta %d\n",
1463                                 priv->_agn.delta_statistics.tx.ack_or_ba_timeout_collision);
1464 #endif
1465
1466                 if (ba_timeout_delta >= BA_TIMEOUT_MAX)
1467                         return false;
1468         }
1469
1470         return true;
1471 }
1472
1473
1474 /*****************************************************************************
1475  *
1476  * sysfs attributes
1477  *
1478  *****************************************************************************/
1479
1480 #ifdef CONFIG_IWLWIFI_DEBUG
1481
1482 /*
1483  * The following adds a new attribute to the sysfs representation
1484  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1485  * used for controlling the debug level.
1486  *
1487  * See the level definitions in iwl for details.
1488  *
1489  * The debug_level being managed using sysfs below is a per device debug
1490  * level that is used instead of the global debug level if it (the per
1491  * device debug level) is set.
1492  */
1493 static ssize_t show_debug_level(struct device *d,
1494                                 struct device_attribute *attr, char *buf)
1495 {
1496         struct iwl_priv *priv = dev_get_drvdata(d);
1497         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1498 }
1499 static ssize_t store_debug_level(struct device *d,
1500                                 struct device_attribute *attr,
1501                                  const char *buf, size_t count)
1502 {
1503         struct iwl_priv *priv = dev_get_drvdata(d);
1504         unsigned long val;
1505         int ret;
1506
1507         ret = strict_strtoul(buf, 0, &val);
1508         if (ret)
1509                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1510         else {
1511                 priv->debug_level = val;
1512                 if (iwl_alloc_traffic_mem(priv))
1513                         IWL_ERR(priv,
1514                                 "Not enough memory to generate traffic log\n");
1515         }
1516         return strnlen(buf, count);
1517 }
1518
1519 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1520                         show_debug_level, store_debug_level);
1521
1522
1523 #endif /* CONFIG_IWLWIFI_DEBUG */
1524
1525
1526 static ssize_t show_temperature(struct device *d,
1527                                 struct device_attribute *attr, char *buf)
1528 {
1529         struct iwl_priv *priv = dev_get_drvdata(d);
1530
1531         if (!iwl_is_alive(priv))
1532                 return -EAGAIN;
1533
1534         return sprintf(buf, "%d\n", priv->temperature);
1535 }
1536
1537 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1538
1539 static ssize_t show_tx_power(struct device *d,
1540                              struct device_attribute *attr, char *buf)
1541 {
1542         struct iwl_priv *priv = dev_get_drvdata(d);
1543
1544         if (!iwl_is_ready_rf(priv))
1545                 return sprintf(buf, "off\n");
1546         else
1547                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1548 }
1549
1550 static ssize_t store_tx_power(struct device *d,
1551                               struct device_attribute *attr,
1552                               const char *buf, size_t count)
1553 {
1554         struct iwl_priv *priv = dev_get_drvdata(d);
1555         unsigned long val;
1556         int ret;
1557
1558         ret = strict_strtoul(buf, 10, &val);
1559         if (ret)
1560                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1561         else {
1562                 ret = iwl_set_tx_power(priv, val, false);
1563                 if (ret)
1564                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1565                                 ret);
1566                 else
1567                         ret = count;
1568         }
1569         return ret;
1570 }
1571
1572 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1573
1574 static struct attribute *iwl_sysfs_entries[] = {
1575         &dev_attr_temperature.attr,
1576         &dev_attr_tx_power.attr,
1577 #ifdef CONFIG_IWLWIFI_DEBUG
1578         &dev_attr_debug_level.attr,
1579 #endif
1580         NULL
1581 };
1582
1583 static struct attribute_group iwl_attribute_group = {
1584         .name = NULL,           /* put in device directory */
1585         .attrs = iwl_sysfs_entries,
1586 };
1587
1588 /******************************************************************************
1589  *
1590  * uCode download functions
1591  *
1592  ******************************************************************************/
1593
1594 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1595 {
1596         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1597         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1598         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1599         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1600         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1601         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1602 }
1603
1604 static void iwl_nic_start(struct iwl_priv *priv)
1605 {
1606         /* Remove all resets to allow NIC to operate */
1607         iwl_write32(priv, CSR_RESET, 0);
1608 }
1609
1610 struct iwlagn_ucode_capabilities {
1611         u32 max_probe_length;
1612         u32 standard_phy_calibration_size;
1613         bool pan;
1614 };
1615
1616 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1617 static int iwl_mac_setup_register(struct iwl_priv *priv,
1618                                   struct iwlagn_ucode_capabilities *capa);
1619
1620 #define UCODE_EXPERIMENTAL_INDEX        100
1621 #define UCODE_EXPERIMENTAL_TAG          "exp"
1622
1623 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1624 {
1625         const char *name_pre = priv->cfg->fw_name_pre;
1626         char tag[8];
1627
1628         if (first) {
1629 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1630                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1631                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1632         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1633 #endif
1634                 priv->fw_index = priv->cfg->ucode_api_max;
1635                 sprintf(tag, "%d", priv->fw_index);
1636         } else {
1637                 priv->fw_index--;
1638                 sprintf(tag, "%d", priv->fw_index);
1639         }
1640
1641         if (priv->fw_index < priv->cfg->ucode_api_min) {
1642                 IWL_ERR(priv, "no suitable firmware found!\n");
1643                 return -ENOENT;
1644         }
1645
1646         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1647
1648         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1649                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1650                                 ? "EXPERIMENTAL " : "",
1651                        priv->firmware_name);
1652
1653         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1654                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1655                                        iwl_ucode_callback);
1656 }
1657
1658 struct iwlagn_firmware_pieces {
1659         const void *inst, *data, *init, *init_data, *boot;
1660         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1661
1662         u32 build;
1663
1664         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1665         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1666 };
1667
1668 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1669                                        const struct firmware *ucode_raw,
1670                                        struct iwlagn_firmware_pieces *pieces)
1671 {
1672         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1673         u32 api_ver, hdr_size;
1674         const u8 *src;
1675
1676         priv->ucode_ver = le32_to_cpu(ucode->ver);
1677         api_ver = IWL_UCODE_API(priv->ucode_ver);
1678
1679         switch (api_ver) {
1680         default:
1681                 /*
1682                  * 4965 doesn't revision the firmware file format
1683                  * along with the API version, it always uses v1
1684                  * file format.
1685                  */
1686                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1687                                 CSR_HW_REV_TYPE_4965) {
1688                         hdr_size = 28;
1689                         if (ucode_raw->size < hdr_size) {
1690                                 IWL_ERR(priv, "File size too small!\n");
1691                                 return -EINVAL;
1692                         }
1693                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1694                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1695                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1696                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1697                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1698                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1699                         src = ucode->u.v2.data;
1700                         break;
1701                 }
1702                 /* fall through for 4965 */
1703         case 0:
1704         case 1:
1705         case 2:
1706                 hdr_size = 24;
1707                 if (ucode_raw->size < hdr_size) {
1708                         IWL_ERR(priv, "File size too small!\n");
1709                         return -EINVAL;
1710                 }
1711                 pieces->build = 0;
1712                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1713                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1714                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1715                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1716                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1717                 src = ucode->u.v1.data;
1718                 break;
1719         }
1720
1721         /* Verify size of file vs. image size info in file's header */
1722         if (ucode_raw->size != hdr_size + pieces->inst_size +
1723                                 pieces->data_size + pieces->init_size +
1724                                 pieces->init_data_size + pieces->boot_size) {
1725
1726                 IWL_ERR(priv,
1727                         "uCode file size %d does not match expected size\n",
1728                         (int)ucode_raw->size);
1729                 return -EINVAL;
1730         }
1731
1732         pieces->inst = src;
1733         src += pieces->inst_size;
1734         pieces->data = src;
1735         src += pieces->data_size;
1736         pieces->init = src;
1737         src += pieces->init_size;
1738         pieces->init_data = src;
1739         src += pieces->init_data_size;
1740         pieces->boot = src;
1741         src += pieces->boot_size;
1742
1743         return 0;
1744 }
1745
1746 static int iwlagn_wanted_ucode_alternative = 1;
1747
1748 static int iwlagn_load_firmware(struct iwl_priv *priv,
1749                                 const struct firmware *ucode_raw,
1750                                 struct iwlagn_firmware_pieces *pieces,
1751                                 struct iwlagn_ucode_capabilities *capa)
1752 {
1753         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1754         struct iwl_ucode_tlv *tlv;
1755         size_t len = ucode_raw->size;
1756         const u8 *data;
1757         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1758         u64 alternatives;
1759         u32 tlv_len;
1760         enum iwl_ucode_tlv_type tlv_type;
1761         const u8 *tlv_data;
1762
1763         if (len < sizeof(*ucode)) {
1764                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1765                 return -EINVAL;
1766         }
1767
1768         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1769                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1770                         le32_to_cpu(ucode->magic));
1771                 return -EINVAL;
1772         }
1773
1774         /*
1775          * Check which alternatives are present, and "downgrade"
1776          * when the chosen alternative is not present, warning
1777          * the user when that happens. Some files may not have
1778          * any alternatives, so don't warn in that case.
1779          */
1780         alternatives = le64_to_cpu(ucode->alternatives);
1781         tmp = wanted_alternative;
1782         if (wanted_alternative > 63)
1783                 wanted_alternative = 63;
1784         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1785                 wanted_alternative--;
1786         if (wanted_alternative && wanted_alternative != tmp)
1787                 IWL_WARN(priv,
1788                          "uCode alternative %d not available, choosing %d\n",
1789                          tmp, wanted_alternative);
1790
1791         priv->ucode_ver = le32_to_cpu(ucode->ver);
1792         pieces->build = le32_to_cpu(ucode->build);
1793         data = ucode->data;
1794
1795         len -= sizeof(*ucode);
1796
1797         while (len >= sizeof(*tlv)) {
1798                 u16 tlv_alt;
1799
1800                 len -= sizeof(*tlv);
1801                 tlv = (void *)data;
1802
1803                 tlv_len = le32_to_cpu(tlv->length);
1804                 tlv_type = le16_to_cpu(tlv->type);
1805                 tlv_alt = le16_to_cpu(tlv->alternative);
1806                 tlv_data = tlv->data;
1807
1808                 if (len < tlv_len) {
1809                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1810                                 len, tlv_len);
1811                         return -EINVAL;
1812                 }
1813                 len -= ALIGN(tlv_len, 4);
1814                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1815
1816                 /*
1817                  * Alternative 0 is always valid.
1818                  *
1819                  * Skip alternative TLVs that are not selected.
1820                  */
1821                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1822                         continue;
1823
1824                 switch (tlv_type) {
1825                 case IWL_UCODE_TLV_INST:
1826                         pieces->inst = tlv_data;
1827                         pieces->inst_size = tlv_len;
1828                         break;
1829                 case IWL_UCODE_TLV_DATA:
1830                         pieces->data = tlv_data;
1831                         pieces->data_size = tlv_len;
1832                         break;
1833                 case IWL_UCODE_TLV_INIT:
1834                         pieces->init = tlv_data;
1835                         pieces->init_size = tlv_len;
1836                         break;
1837                 case IWL_UCODE_TLV_INIT_DATA:
1838                         pieces->init_data = tlv_data;
1839                         pieces->init_data_size = tlv_len;
1840                         break;
1841                 case IWL_UCODE_TLV_BOOT:
1842                         pieces->boot = tlv_data;
1843                         pieces->boot_size = tlv_len;
1844                         break;
1845                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1846                         if (tlv_len != sizeof(u32))
1847                                 goto invalid_tlv_len;
1848                         capa->max_probe_length =
1849                                         le32_to_cpup((__le32 *)tlv_data);
1850                         break;
1851                 case IWL_UCODE_TLV_PAN:
1852                         if (tlv_len)
1853                                 goto invalid_tlv_len;
1854                         capa->pan = true;
1855                         break;
1856                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1857                         if (tlv_len != sizeof(u32))
1858                                 goto invalid_tlv_len;
1859                         pieces->init_evtlog_ptr =
1860                                         le32_to_cpup((__le32 *)tlv_data);
1861                         break;
1862                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1863                         if (tlv_len != sizeof(u32))
1864                                 goto invalid_tlv_len;
1865                         pieces->init_evtlog_size =
1866                                         le32_to_cpup((__le32 *)tlv_data);
1867                         break;
1868                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1869                         if (tlv_len != sizeof(u32))
1870                                 goto invalid_tlv_len;
1871                         pieces->init_errlog_ptr =
1872                                         le32_to_cpup((__le32 *)tlv_data);
1873                         break;
1874                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1875                         if (tlv_len != sizeof(u32))
1876                                 goto invalid_tlv_len;
1877                         pieces->inst_evtlog_ptr =
1878                                         le32_to_cpup((__le32 *)tlv_data);
1879                         break;
1880                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1881                         if (tlv_len != sizeof(u32))
1882                                 goto invalid_tlv_len;
1883                         pieces->inst_evtlog_size =
1884                                         le32_to_cpup((__le32 *)tlv_data);
1885                         break;
1886                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1887                         if (tlv_len != sizeof(u32))
1888                                 goto invalid_tlv_len;
1889                         pieces->inst_errlog_ptr =
1890                                         le32_to_cpup((__le32 *)tlv_data);
1891                         break;
1892                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1893                         if (tlv_len)
1894                                 goto invalid_tlv_len;
1895                         priv->enhance_sensitivity_table = true;
1896                         break;
1897                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1898                         if (tlv_len != sizeof(u32))
1899                                 goto invalid_tlv_len;
1900                         capa->standard_phy_calibration_size =
1901                                         le32_to_cpup((__le32 *)tlv_data);
1902                         break;
1903                 default:
1904                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1905                         break;
1906                 }
1907         }
1908
1909         if (len) {
1910                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1911                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1912                 return -EINVAL;
1913         }
1914
1915         return 0;
1916
1917  invalid_tlv_len:
1918         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1919         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1920
1921         return -EINVAL;
1922 }
1923
1924 /**
1925  * iwl_ucode_callback - callback when firmware was loaded
1926  *
1927  * If loaded successfully, copies the firmware into buffers
1928  * for the card to fetch (via DMA).
1929  */
1930 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1931 {
1932         struct iwl_priv *priv = context;
1933         struct iwl_ucode_header *ucode;
1934         int err;
1935         struct iwlagn_firmware_pieces pieces;
1936         const unsigned int api_max = priv->cfg->ucode_api_max;
1937         const unsigned int api_min = priv->cfg->ucode_api_min;
1938         u32 api_ver;
1939         char buildstr[25];
1940         u32 build;
1941         struct iwlagn_ucode_capabilities ucode_capa = {
1942                 .max_probe_length = 200,
1943                 .standard_phy_calibration_size =
1944                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1945         };
1946
1947         memset(&pieces, 0, sizeof(pieces));
1948
1949         if (!ucode_raw) {
1950                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1951                         IWL_ERR(priv,
1952                                 "request for firmware file '%s' failed.\n",
1953                                 priv->firmware_name);
1954                 goto try_again;
1955         }
1956
1957         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1958                        priv->firmware_name, ucode_raw->size);
1959
1960         /* Make sure that we got at least the API version number */
1961         if (ucode_raw->size < 4) {
1962                 IWL_ERR(priv, "File size way too small!\n");
1963                 goto try_again;
1964         }
1965
1966         /* Data from ucode file:  header followed by uCode images */
1967         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1968
1969         if (ucode->ver)
1970                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1971         else
1972                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1973                                            &ucode_capa);
1974
1975         if (err)
1976                 goto try_again;
1977
1978         api_ver = IWL_UCODE_API(priv->ucode_ver);
1979         build = pieces.build;
1980
1981         /*
1982          * api_ver should match the api version forming part of the
1983          * firmware filename ... but we don't check for that and only rely
1984          * on the API version read from firmware header from here on forward
1985          */
1986         /* no api version check required for experimental uCode */
1987         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1988                 if (api_ver < api_min || api_ver > api_max) {
1989                         IWL_ERR(priv,
1990                                 "Driver unable to support your firmware API. "
1991                                 "Driver supports v%u, firmware is v%u.\n",
1992                                 api_max, api_ver);
1993                         goto try_again;
1994                 }
1995
1996                 if (api_ver != api_max)
1997                         IWL_ERR(priv,
1998                                 "Firmware has old API version. Expected v%u, "
1999                                 "got v%u. New firmware can be obtained "
2000                                 "from http://www.intellinuxwireless.org.\n",
2001                                 api_max, api_ver);
2002         }
2003
2004         if (build)
2005                 sprintf(buildstr, " build %u%s", build,
2006                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2007                                 ? " (EXP)" : "");
2008         else
2009                 buildstr[0] = '\0';
2010
2011         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2012                  IWL_UCODE_MAJOR(priv->ucode_ver),
2013                  IWL_UCODE_MINOR(priv->ucode_ver),
2014                  IWL_UCODE_API(priv->ucode_ver),
2015                  IWL_UCODE_SERIAL(priv->ucode_ver),
2016                  buildstr);
2017
2018         snprintf(priv->hw->wiphy->fw_version,
2019                  sizeof(priv->hw->wiphy->fw_version),
2020                  "%u.%u.%u.%u%s",
2021                  IWL_UCODE_MAJOR(priv->ucode_ver),
2022                  IWL_UCODE_MINOR(priv->ucode_ver),
2023                  IWL_UCODE_API(priv->ucode_ver),
2024                  IWL_UCODE_SERIAL(priv->ucode_ver),
2025                  buildstr);
2026
2027         /*
2028          * For any of the failures below (before allocating pci memory)
2029          * we will try to load a version with a smaller API -- maybe the
2030          * user just got a corrupted version of the latest API.
2031          */
2032
2033         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2034                        priv->ucode_ver);
2035         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2036                        pieces.inst_size);
2037         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2038                        pieces.data_size);
2039         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2040                        pieces.init_size);
2041         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2042                        pieces.init_data_size);
2043         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2044                        pieces.boot_size);
2045
2046         /* Verify that uCode images will fit in card's SRAM */
2047         if (pieces.inst_size > priv->hw_params.max_inst_size) {
2048                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2049                         pieces.inst_size);
2050                 goto try_again;
2051         }
2052
2053         if (pieces.data_size > priv->hw_params.max_data_size) {
2054                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2055                         pieces.data_size);
2056                 goto try_again;
2057         }
2058
2059         if (pieces.init_size > priv->hw_params.max_inst_size) {
2060                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2061                         pieces.init_size);
2062                 goto try_again;
2063         }
2064
2065         if (pieces.init_data_size > priv->hw_params.max_data_size) {
2066                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2067                         pieces.init_data_size);
2068                 goto try_again;
2069         }
2070
2071         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2072                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2073                         pieces.boot_size);
2074                 goto try_again;
2075         }
2076
2077         /* Allocate ucode buffers for card's bus-master loading ... */
2078
2079         /* Runtime instructions and 2 copies of data:
2080          * 1) unmodified from disk
2081          * 2) backup cache for save/restore during power-downs */
2082         priv->ucode_code.len = pieces.inst_size;
2083         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2084
2085         priv->ucode_data.len = pieces.data_size;
2086         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2087
2088         priv->ucode_data_backup.len = pieces.data_size;
2089         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2090
2091         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2092             !priv->ucode_data_backup.v_addr)
2093                 goto err_pci_alloc;
2094
2095         /* Initialization instructions and data */
2096         if (pieces.init_size && pieces.init_data_size) {
2097                 priv->ucode_init.len = pieces.init_size;
2098                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2099
2100                 priv->ucode_init_data.len = pieces.init_data_size;
2101                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2102
2103                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2104                         goto err_pci_alloc;
2105         }
2106
2107         /* Bootstrap (instructions only, no data) */
2108         if (pieces.boot_size) {
2109                 priv->ucode_boot.len = pieces.boot_size;
2110                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2111
2112                 if (!priv->ucode_boot.v_addr)
2113                         goto err_pci_alloc;
2114         }
2115
2116         /* Now that we can no longer fail, copy information */
2117
2118         /*
2119          * The (size - 16) / 12 formula is based on the information recorded
2120          * for each event, which is of mode 1 (including timestamp) for all
2121          * new microcodes that include this information.
2122          */
2123         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2124         if (pieces.init_evtlog_size)
2125                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2126         else
2127                 priv->_agn.init_evtlog_size =
2128                         priv->cfg->base_params->max_event_log_size;
2129         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2130         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2131         if (pieces.inst_evtlog_size)
2132                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2133         else
2134                 priv->_agn.inst_evtlog_size =
2135                         priv->cfg->base_params->max_event_log_size;
2136         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2137
2138         if (ucode_capa.pan) {
2139                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2140                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2141         } else
2142                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2143
2144         /* Copy images into buffers for card's bus-master reads ... */
2145
2146         /* Runtime instructions (first block of data in file) */
2147         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2148                         pieces.inst_size);
2149         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2150
2151         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2152                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2153
2154         /*
2155          * Runtime data
2156          * NOTE:  Copy into backup buffer will be done in iwl_up()
2157          */
2158         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2159                         pieces.data_size);
2160         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2161         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2162
2163         /* Initialization instructions */
2164         if (pieces.init_size) {
2165                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2166                                 pieces.init_size);
2167                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2168         }
2169
2170         /* Initialization data */
2171         if (pieces.init_data_size) {
2172                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2173                                pieces.init_data_size);
2174                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2175                        pieces.init_data_size);
2176         }
2177
2178         /* Bootstrap instructions */
2179         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2180                         pieces.boot_size);
2181         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2182
2183         /*
2184          * figure out the offset of chain noise reset and gain commands
2185          * base on the size of standard phy calibration commands table size
2186          */
2187         if (ucode_capa.standard_phy_calibration_size >
2188             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2189                 ucode_capa.standard_phy_calibration_size =
2190                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2191
2192         priv->_agn.phy_calib_chain_noise_reset_cmd =
2193                 ucode_capa.standard_phy_calibration_size;
2194         priv->_agn.phy_calib_chain_noise_gain_cmd =
2195                 ucode_capa.standard_phy_calibration_size + 1;
2196
2197         /**************************************************
2198          * This is still part of probe() in a sense...
2199          *
2200          * 9. Setup and register with mac80211 and debugfs
2201          **************************************************/
2202         err = iwl_mac_setup_register(priv, &ucode_capa);
2203         if (err)
2204                 goto out_unbind;
2205
2206         err = iwl_dbgfs_register(priv, DRV_NAME);
2207         if (err)
2208                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2209
2210         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2211                                         &iwl_attribute_group);
2212         if (err) {
2213                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2214                 goto out_unbind;
2215         }
2216
2217         /* We have our copies now, allow OS release its copies */
2218         release_firmware(ucode_raw);
2219         complete(&priv->_agn.firmware_loading_complete);
2220         return;
2221
2222  try_again:
2223         /* try next, if any */
2224         if (iwl_request_firmware(priv, false))
2225                 goto out_unbind;
2226         release_firmware(ucode_raw);
2227         return;
2228
2229  err_pci_alloc:
2230         IWL_ERR(priv, "failed to allocate pci memory\n");
2231         iwl_dealloc_ucode_pci(priv);
2232  out_unbind:
2233         complete(&priv->_agn.firmware_loading_complete);
2234         device_release_driver(&priv->pci_dev->dev);
2235         release_firmware(ucode_raw);
2236 }
2237
2238 static const char *desc_lookup_text[] = {
2239         "OK",
2240         "FAIL",
2241         "BAD_PARAM",
2242         "BAD_CHECKSUM",
2243         "NMI_INTERRUPT_WDG",
2244         "SYSASSERT",
2245         "FATAL_ERROR",
2246         "BAD_COMMAND",
2247         "HW_ERROR_TUNE_LOCK",
2248         "HW_ERROR_TEMPERATURE",
2249         "ILLEGAL_CHAN_FREQ",
2250         "VCC_NOT_STABLE",
2251         "FH_ERROR",
2252         "NMI_INTERRUPT_HOST",
2253         "NMI_INTERRUPT_ACTION_PT",
2254         "NMI_INTERRUPT_UNKNOWN",
2255         "UCODE_VERSION_MISMATCH",
2256         "HW_ERROR_ABS_LOCK",
2257         "HW_ERROR_CAL_LOCK_FAIL",
2258         "NMI_INTERRUPT_INST_ACTION_PT",
2259         "NMI_INTERRUPT_DATA_ACTION_PT",
2260         "NMI_TRM_HW_ER",
2261         "NMI_INTERRUPT_TRM",
2262         "NMI_INTERRUPT_BREAK_POINT"
2263         "DEBUG_0",
2264         "DEBUG_1",
2265         "DEBUG_2",
2266         "DEBUG_3",
2267 };
2268
2269 static struct { char *name; u8 num; } advanced_lookup[] = {
2270         { "NMI_INTERRUPT_WDG", 0x34 },
2271         { "SYSASSERT", 0x35 },
2272         { "UCODE_VERSION_MISMATCH", 0x37 },
2273         { "BAD_COMMAND", 0x38 },
2274         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2275         { "FATAL_ERROR", 0x3D },
2276         { "NMI_TRM_HW_ERR", 0x46 },
2277         { "NMI_INTERRUPT_TRM", 0x4C },
2278         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2279         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2280         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2281         { "NMI_INTERRUPT_HOST", 0x66 },
2282         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2283         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2284         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2285         { "ADVANCED_SYSASSERT", 0 },
2286 };
2287
2288 static const char *desc_lookup(u32 num)
2289 {
2290         int i;
2291         int max = ARRAY_SIZE(desc_lookup_text);
2292
2293         if (num < max)
2294                 return desc_lookup_text[num];
2295
2296         max = ARRAY_SIZE(advanced_lookup) - 1;
2297         for (i = 0; i < max; i++) {
2298                 if (advanced_lookup[i].num == num)
2299                         break;;
2300         }
2301         return advanced_lookup[i].name;
2302 }
2303
2304 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2305 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2306
2307 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2308 {
2309         u32 data2, line;
2310         u32 desc, time, count, base, data1;
2311         u32 blink1, blink2, ilink1, ilink2;
2312         u32 pc, hcmd;
2313
2314         if (priv->ucode_type == UCODE_INIT) {
2315                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2316                 if (!base)
2317                         base = priv->_agn.init_errlog_ptr;
2318         } else {
2319                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2320                 if (!base)
2321                         base = priv->_agn.inst_errlog_ptr;
2322         }
2323
2324         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2325                 IWL_ERR(priv,
2326                         "Not valid error log pointer 0x%08X for %s uCode\n",
2327                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2328                 return;
2329         }
2330
2331         count = iwl_read_targ_mem(priv, base);
2332
2333         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2334                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2335                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2336                         priv->status, count);
2337         }
2338
2339         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2340         priv->isr_stats.err_code = desc;
2341         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2342         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2343         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2344         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2345         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2346         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2347         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2348         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2349         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2350         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2351
2352         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2353                                       blink1, blink2, ilink1, ilink2);
2354
2355         IWL_ERR(priv, "Desc                                  Time       "
2356                 "data1      data2      line\n");
2357         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2358                 desc_lookup(desc), desc, time, data1, data2, line);
2359         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2360         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2361                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2362 }
2363
2364 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2365
2366 /**
2367  * iwl_print_event_log - Dump error event log to syslog
2368  *
2369  */
2370 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2371                                u32 num_events, u32 mode,
2372                                int pos, char **buf, size_t bufsz)
2373 {
2374         u32 i;
2375         u32 base;       /* SRAM byte address of event log header */
2376         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2377         u32 ptr;        /* SRAM byte address of log data */
2378         u32 ev, time, data; /* event log data */
2379         unsigned long reg_flags;
2380
2381         if (num_events == 0)
2382                 return pos;
2383
2384         if (priv->ucode_type == UCODE_INIT) {
2385                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2386                 if (!base)
2387                         base = priv->_agn.init_evtlog_ptr;
2388         } else {
2389                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2390                 if (!base)
2391                         base = priv->_agn.inst_evtlog_ptr;
2392         }
2393
2394         if (mode == 0)
2395                 event_size = 2 * sizeof(u32);
2396         else
2397                 event_size = 3 * sizeof(u32);
2398
2399         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2400
2401         /* Make sure device is powered up for SRAM reads */
2402         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2403         iwl_grab_nic_access(priv);
2404
2405         /* Set starting address; reads will auto-increment */
2406         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2407         rmb();
2408
2409         /* "time" is actually "data" for mode 0 (no timestamp).
2410         * place event id # at far right for easier visual parsing. */
2411         for (i = 0; i < num_events; i++) {
2412                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2413                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2414                 if (mode == 0) {
2415                         /* data, ev */
2416                         if (bufsz) {
2417                                 pos += scnprintf(*buf + pos, bufsz - pos,
2418                                                 "EVT_LOG:0x%08x:%04u\n",
2419                                                 time, ev);
2420                         } else {
2421                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2422                                         time, ev);
2423                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2424                                         time, ev);
2425                         }
2426                 } else {
2427                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2428                         if (bufsz) {
2429                                 pos += scnprintf(*buf + pos, bufsz - pos,
2430                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2431                                                  time, data, ev);
2432                         } else {
2433                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2434                                         time, data, ev);
2435                                 trace_iwlwifi_dev_ucode_event(priv, time,
2436                                         data, ev);
2437                         }
2438                 }
2439         }
2440
2441         /* Allow device to power down */
2442         iwl_release_nic_access(priv);
2443         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2444         return pos;
2445 }
2446
2447 /**
2448  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2449  */
2450 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2451                                     u32 num_wraps, u32 next_entry,
2452                                     u32 size, u32 mode,
2453                                     int pos, char **buf, size_t bufsz)
2454 {
2455         /*
2456          * display the newest DEFAULT_LOG_ENTRIES entries
2457          * i.e the entries just before the next ont that uCode would fill.
2458          */
2459         if (num_wraps) {
2460                 if (next_entry < size) {
2461                         pos = iwl_print_event_log(priv,
2462                                                 capacity - (size - next_entry),
2463                                                 size - next_entry, mode,
2464                                                 pos, buf, bufsz);
2465                         pos = iwl_print_event_log(priv, 0,
2466                                                   next_entry, mode,
2467                                                   pos, buf, bufsz);
2468                 } else
2469                         pos = iwl_print_event_log(priv, next_entry - size,
2470                                                   size, mode, pos, buf, bufsz);
2471         } else {
2472                 if (next_entry < size) {
2473                         pos = iwl_print_event_log(priv, 0, next_entry,
2474                                                   mode, pos, buf, bufsz);
2475                 } else {
2476                         pos = iwl_print_event_log(priv, next_entry - size,
2477                                                   size, mode, pos, buf, bufsz);
2478                 }
2479         }
2480         return pos;
2481 }
2482
2483 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2484
2485 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2486                             char **buf, bool display)
2487 {
2488         u32 base;       /* SRAM byte address of event log header */
2489         u32 capacity;   /* event log capacity in # entries */
2490         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2491         u32 num_wraps;  /* # times uCode wrapped to top of log */
2492         u32 next_entry; /* index of next entry to be written by uCode */
2493         u32 size;       /* # entries that we'll print */
2494         u32 logsize;
2495         int pos = 0;
2496         size_t bufsz = 0;
2497
2498         if (priv->ucode_type == UCODE_INIT) {
2499                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2500                 logsize = priv->_agn.init_evtlog_size;
2501                 if (!base)
2502                         base = priv->_agn.init_evtlog_ptr;
2503         } else {
2504                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2505                 logsize = priv->_agn.inst_evtlog_size;
2506                 if (!base)
2507                         base = priv->_agn.inst_evtlog_ptr;
2508         }
2509
2510         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2511                 IWL_ERR(priv,
2512                         "Invalid event log pointer 0x%08X for %s uCode\n",
2513                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2514                 return -EINVAL;
2515         }
2516
2517         /* event log header */
2518         capacity = iwl_read_targ_mem(priv, base);
2519         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2520         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2521         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2522
2523         if (capacity > logsize) {
2524                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2525                         capacity, logsize);
2526                 capacity = logsize;
2527         }
2528
2529         if (next_entry > logsize) {
2530                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2531                         next_entry, logsize);
2532                 next_entry = logsize;
2533         }
2534
2535         size = num_wraps ? capacity : next_entry;
2536
2537         /* bail out if nothing in log */
2538         if (size == 0) {
2539                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2540                 return pos;
2541         }
2542
2543         /* enable/disable bt channel inhibition */
2544         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2545
2546 #ifdef CONFIG_IWLWIFI_DEBUG
2547         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2548                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2549                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2550 #else
2551         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2552                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2553 #endif
2554         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2555                 size);
2556
2557 #ifdef CONFIG_IWLWIFI_DEBUG
2558         if (display) {
2559                 if (full_log)
2560                         bufsz = capacity * 48;
2561                 else
2562                         bufsz = size * 48;
2563                 *buf = kmalloc(bufsz, GFP_KERNEL);
2564                 if (!*buf)
2565                         return -ENOMEM;
2566         }
2567         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2568                 /*
2569                  * if uCode has wrapped back to top of log,
2570                  * start at the oldest entry,
2571                  * i.e the next one that uCode would fill.
2572                  */
2573                 if (num_wraps)
2574                         pos = iwl_print_event_log(priv, next_entry,
2575                                                 capacity - next_entry, mode,
2576                                                 pos, buf, bufsz);
2577                 /* (then/else) start at top of log */
2578                 pos = iwl_print_event_log(priv, 0,
2579                                           next_entry, mode, pos, buf, bufsz);
2580         } else
2581                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2582                                                 next_entry, size, mode,
2583                                                 pos, buf, bufsz);
2584 #else
2585         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2586                                         next_entry, size, mode,
2587                                         pos, buf, bufsz);
2588 #endif
2589         return pos;
2590 }
2591
2592 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2593 {
2594         struct iwl_ct_kill_config cmd;
2595         struct iwl_ct_kill_throttling_config adv_cmd;
2596         unsigned long flags;
2597         int ret = 0;
2598
2599         spin_lock_irqsave(&priv->lock, flags);
2600         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2601                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2602         spin_unlock_irqrestore(&priv->lock, flags);
2603         priv->thermal_throttle.ct_kill_toggle = false;
2604
2605         if (priv->cfg->base_params->support_ct_kill_exit) {
2606                 adv_cmd.critical_temperature_enter =
2607                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2608                 adv_cmd.critical_temperature_exit =
2609                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2610
2611                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2612                                        sizeof(adv_cmd), &adv_cmd);
2613                 if (ret)
2614                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2615                 else
2616                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2617                                         "succeeded, "
2618                                         "critical temperature enter is %d,"
2619                                         "exit is %d\n",
2620                                        priv->hw_params.ct_kill_threshold,
2621                                        priv->hw_params.ct_kill_exit_threshold);
2622         } else {
2623                 cmd.critical_temperature_R =
2624                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2625
2626                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2627                                        sizeof(cmd), &cmd);
2628                 if (ret)
2629                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2630                 else
2631                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2632                                         "succeeded, "
2633                                         "critical temperature is %d\n",
2634                                         priv->hw_params.ct_kill_threshold);
2635         }
2636 }
2637
2638 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2639 {
2640         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2641         struct iwl_host_cmd cmd = {
2642                 .id = CALIBRATION_CFG_CMD,
2643                 .len = sizeof(struct iwl_calib_cfg_cmd),
2644                 .data = &calib_cfg_cmd,
2645         };
2646
2647         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2648         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2649         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2650
2651         return iwl_send_cmd(priv, &cmd);
2652 }
2653
2654
2655 /**
2656  * iwl_alive_start - called after REPLY_ALIVE notification received
2657  *                   from protocol/runtime uCode (initialization uCode's
2658  *                   Alive gets handled by iwl_init_alive_start()).
2659  */
2660 static void iwl_alive_start(struct iwl_priv *priv)
2661 {
2662         int ret = 0;
2663         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2664
2665         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2666
2667         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2668          * This is a paranoid check, because we would not have gotten the
2669          * "runtime" alive if code weren't properly loaded.  */
2670         if (iwl_verify_ucode(priv)) {
2671                 /* Runtime instruction load was bad;
2672                  * take it all the way back down so we can try again */
2673                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2674                 goto restart;
2675         }
2676
2677         ret = priv->cfg->ops->lib->alive_notify(priv);
2678         if (ret) {
2679                 IWL_WARN(priv,
2680                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2681                 goto restart;
2682         }
2683
2684
2685         /* After the ALIVE response, we can send host commands to the uCode */
2686         set_bit(STATUS_ALIVE, &priv->status);
2687
2688         /* Enable watchdog to monitor the driver tx queues */
2689         iwl_setup_watchdog(priv);
2690
2691         if (iwl_is_rfkill(priv))
2692                 return;
2693
2694         /* download priority table before any calibration request */
2695         if (priv->cfg->bt_params &&
2696             priv->cfg->bt_params->advanced_bt_coexist) {
2697                 /* Configure Bluetooth device coexistence support */
2698                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2699                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2700                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2701                 priv->cfg->ops->hcmd->send_bt_config(priv);
2702                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2703                 iwlagn_send_prio_tbl(priv);
2704
2705                 /* FIXME: w/a to force change uCode BT state machine */
2706                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2707                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2708                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2709                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2710         }
2711         if (priv->hw_params.calib_rt_cfg)
2712                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2713
2714         ieee80211_wake_queues(priv->hw);
2715
2716         priv->active_rate = IWL_RATES_MASK;
2717
2718         /* Configure Tx antenna selection based on H/W config */
2719         if (priv->cfg->ops->hcmd->set_tx_ant)
2720                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2721
2722         if (iwl_is_associated_ctx(ctx)) {
2723                 struct iwl_rxon_cmd *active_rxon =
2724                                 (struct iwl_rxon_cmd *)&ctx->active;
2725                 /* apply any changes in staging */
2726                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2727                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2728         } else {
2729                 struct iwl_rxon_context *tmp;
2730                 /* Initialize our rx_config data */
2731                 for_each_context(priv, tmp)
2732                         iwl_connection_init_rx_config(priv, tmp);
2733
2734                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2735                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2736         }
2737
2738         if (priv->cfg->bt_params &&
2739             !priv->cfg->bt_params->advanced_bt_coexist) {
2740                 /* Configure Bluetooth device coexistence support */
2741                 priv->cfg->ops->hcmd->send_bt_config(priv);
2742         }
2743
2744         iwl_reset_run_time_calib(priv);
2745
2746         set_bit(STATUS_READY, &priv->status);
2747
2748         /* Configure the adapter for unassociated operation */
2749         iwlcore_commit_rxon(priv, ctx);
2750
2751         /* At this point, the NIC is initialized and operational */
2752         iwl_rf_kill_ct_config(priv);
2753
2754         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2755         wake_up_interruptible(&priv->wait_command_queue);
2756
2757         iwl_power_update_mode(priv, true);
2758         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2759
2760
2761         return;
2762
2763  restart:
2764         queue_work(priv->workqueue, &priv->restart);
2765 }
2766
2767 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2768
2769 static void __iwl_down(struct iwl_priv *priv)
2770 {
2771         unsigned long flags;
2772         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2773
2774         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2775
2776         iwl_scan_cancel_timeout(priv, 200);
2777
2778         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2779
2780         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2781          * to prevent rearm timer */
2782         del_timer_sync(&priv->watchdog);
2783
2784         iwl_clear_ucode_stations(priv, NULL);
2785         iwl_dealloc_bcast_stations(priv);
2786         iwl_clear_driver_stations(priv);
2787
2788         /* reset BT coex data */
2789         priv->bt_status = 0;
2790         if (priv->cfg->bt_params)
2791                 priv->bt_traffic_load =
2792                          priv->cfg->bt_params->bt_init_traffic_load;
2793         else
2794                 priv->bt_traffic_load = 0;
2795         priv->bt_full_concurrent = false;
2796         priv->bt_ci_compliance = 0;
2797
2798         /* Unblock any waiting calls */
2799         wake_up_interruptible_all(&priv->wait_command_queue);
2800
2801         /* Wipe out the EXIT_PENDING status bit if we are not actually
2802          * exiting the module */
2803         if (!exit_pending)
2804                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2805
2806         /* stop and reset the on-board processor */
2807         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2808
2809         /* tell the device to stop sending interrupts */
2810         spin_lock_irqsave(&priv->lock, flags);
2811         iwl_disable_interrupts(priv);
2812         spin_unlock_irqrestore(&priv->lock, flags);
2813         iwl_synchronize_irq(priv);
2814
2815         if (priv->mac80211_registered)
2816                 ieee80211_stop_queues(priv->hw);
2817
2818         /* If we have not previously called iwl_init() then
2819          * clear all bits but the RF Kill bit and return */
2820         if (!iwl_is_init(priv)) {
2821                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2822                                         STATUS_RF_KILL_HW |
2823                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2824                                         STATUS_GEO_CONFIGURED |
2825                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2826                                         STATUS_EXIT_PENDING;
2827                 goto exit;
2828         }
2829
2830         /* ...otherwise clear out all the status bits but the RF Kill
2831          * bit and continue taking the NIC down. */
2832         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2833                                 STATUS_RF_KILL_HW |
2834                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2835                                 STATUS_GEO_CONFIGURED |
2836                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2837                                 STATUS_FW_ERROR |
2838                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2839                                 STATUS_EXIT_PENDING;
2840
2841         /* device going down, Stop using ICT table */
2842         if (priv->cfg->ops->lib->isr_ops.disable)
2843                 priv->cfg->ops->lib->isr_ops.disable(priv);
2844
2845         iwlagn_txq_ctx_stop(priv);
2846         iwlagn_rxq_stop(priv);
2847
2848         /* Power-down device's busmaster DMA clocks */
2849         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2850         udelay(5);
2851
2852         /* Make sure (redundant) we've released our request to stay awake */
2853         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2854
2855         /* Stop the device, and put it in low power state */
2856         iwl_apm_stop(priv);
2857
2858  exit:
2859         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2860
2861         dev_kfree_skb(priv->beacon_skb);
2862         priv->beacon_skb = NULL;
2863
2864         /* clear out any free frames */
2865         iwl_clear_free_frames(priv);
2866 }
2867
2868 static void iwl_down(struct iwl_priv *priv)
2869 {
2870         mutex_lock(&priv->mutex);
2871         __iwl_down(priv);
2872         mutex_unlock(&priv->mutex);
2873
2874         iwl_cancel_deferred_work(priv);
2875 }
2876
2877 #define HW_READY_TIMEOUT (50)
2878
2879 static int iwl_set_hw_ready(struct iwl_priv *priv)
2880 {
2881         int ret = 0;
2882
2883         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2884                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2885
2886         /* See if we got it */
2887         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2888                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2889                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2890                                 HW_READY_TIMEOUT);
2891         if (ret != -ETIMEDOUT)
2892                 priv->hw_ready = true;
2893         else
2894                 priv->hw_ready = false;
2895
2896         IWL_DEBUG_INFO(priv, "hardware %s\n",
2897                       (priv->hw_ready == 1) ? "ready" : "not ready");
2898         return ret;
2899 }
2900
2901 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2902 {
2903         int ret = 0;
2904
2905         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2906
2907         ret = iwl_set_hw_ready(priv);
2908         if (priv->hw_ready)
2909                 return ret;
2910
2911         /* If HW is not ready, prepare the conditions to check again */
2912         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2913                         CSR_HW_IF_CONFIG_REG_PREPARE);
2914
2915         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2916                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2917                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2918
2919         /* HW should be ready by now, check again. */
2920         if (ret != -ETIMEDOUT)
2921                 iwl_set_hw_ready(priv);
2922
2923         return ret;
2924 }
2925
2926 #define MAX_HW_RESTARTS 5
2927
2928 static int __iwl_up(struct iwl_priv *priv)
2929 {
2930         struct iwl_rxon_context *ctx;
2931         int i;
2932         int ret;
2933
2934         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2935                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2936                 return -EIO;
2937         }
2938
2939         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2940                 IWL_ERR(priv, "ucode not available for device bringup\n");
2941                 return -EIO;
2942         }
2943
2944         for_each_context(priv, ctx) {
2945                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2946                 if (ret) {
2947                         iwl_dealloc_bcast_stations(priv);
2948                         return ret;
2949                 }
2950         }
2951
2952         iwl_prepare_card_hw(priv);
2953
2954         if (!priv->hw_ready) {
2955                 IWL_WARN(priv, "Exit HW not ready\n");
2956                 return -EIO;
2957         }
2958
2959         /* If platform's RF_KILL switch is NOT set to KILL */
2960         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2961                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2962         else
2963                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2964
2965         if (iwl_is_rfkill(priv)) {
2966                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2967
2968                 iwl_enable_interrupts(priv);
2969                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2970                 return 0;
2971         }
2972
2973         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2974
2975         /* must be initialised before iwl_hw_nic_init */
2976         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2977                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2978         else
2979                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2980
2981         ret = iwlagn_hw_nic_init(priv);
2982         if (ret) {
2983                 IWL_ERR(priv, "Unable to init nic\n");
2984                 return ret;
2985         }
2986
2987         /* make sure rfkill handshake bits are cleared */
2988         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2989         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2990                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2991
2992         /* clear (again), then enable host interrupts */
2993         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2994         iwl_enable_interrupts(priv);
2995
2996         /* really make sure rfkill handshake bits are cleared */
2997         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2998         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2999
3000         /* Copy original ucode data image from disk into backup cache.
3001          * This will be used to initialize the on-board processor's
3002          * data SRAM for a clean start when the runtime program first loads. */
3003         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
3004                priv->ucode_data.len);
3005
3006         for (i = 0; i < MAX_HW_RESTARTS; i++) {
3007
3008                 /* load bootstrap state machine,
3009                  * load bootstrap program into processor's memory,
3010                  * prepare to load the "initialize" uCode */
3011                 ret = priv->cfg->ops->lib->load_ucode(priv);
3012
3013                 if (ret) {
3014                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3015                                 ret);
3016                         continue;
3017                 }
3018
3019                 /* start card; "initialize" will load runtime ucode */
3020                 iwl_nic_start(priv);
3021
3022                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3023
3024                 return 0;
3025         }
3026
3027         set_bit(STATUS_EXIT_PENDING, &priv->status);
3028         __iwl_down(priv);
3029         clear_bit(STATUS_EXIT_PENDING, &priv->status);
3030
3031         /* tried to restart and config the device for as long as our
3032          * patience could withstand */
3033         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3034         return -EIO;
3035 }
3036
3037
3038 /*****************************************************************************
3039  *
3040  * Workqueue callbacks
3041  *
3042  *****************************************************************************/
3043
3044 static void iwl_bg_init_alive_start(struct work_struct *data)
3045 {
3046         struct iwl_priv *priv =
3047             container_of(data, struct iwl_priv, init_alive_start.work);
3048
3049         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3050                 return;
3051
3052         mutex_lock(&priv->mutex);
3053         priv->cfg->ops->lib->init_alive_start(priv);
3054         mutex_unlock(&priv->mutex);
3055 }
3056
3057 static void iwl_bg_alive_start(struct work_struct *data)
3058 {
3059         struct iwl_priv *priv =
3060             container_of(data, struct iwl_priv, alive_start.work);
3061
3062         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3063                 return;
3064
3065         /* enable dram interrupt */
3066         if (priv->cfg->ops->lib->isr_ops.reset)
3067                 priv->cfg->ops->lib->isr_ops.reset(priv);
3068
3069         mutex_lock(&priv->mutex);
3070         iwl_alive_start(priv);
3071         mutex_unlock(&priv->mutex);
3072 }
3073
3074 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3075 {
3076         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3077                         run_time_calib_work);
3078
3079         mutex_lock(&priv->mutex);
3080
3081         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3082             test_bit(STATUS_SCANNING, &priv->status)) {
3083                 mutex_unlock(&priv->mutex);
3084                 return;
3085         }
3086
3087         if (priv->start_calib) {
3088                 if (iwl_bt_statistics(priv)) {
3089                         iwl_chain_noise_calibration(priv,
3090                                         (void *)&priv->_agn.statistics_bt);
3091                         iwl_sensitivity_calibration(priv,
3092                                         (void *)&priv->_agn.statistics_bt);
3093                 } else {
3094                         iwl_chain_noise_calibration(priv,
3095                                         (void *)&priv->_agn.statistics);
3096                         iwl_sensitivity_calibration(priv,
3097                                         (void *)&priv->_agn.statistics);
3098                 }
3099         }
3100
3101         mutex_unlock(&priv->mutex);
3102 }
3103
3104 static void iwl_bg_restart(struct work_struct *data)
3105 {
3106         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3107
3108         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3109                 return;
3110
3111         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3112                 struct iwl_rxon_context *ctx;
3113                 bool bt_full_concurrent;
3114                 u8 bt_ci_compliance;
3115                 u8 bt_load;
3116                 u8 bt_status;
3117
3118                 mutex_lock(&priv->mutex);
3119                 for_each_context(priv, ctx)
3120                         ctx->vif = NULL;
3121                 priv->is_open = 0;
3122
3123                 /*
3124                  * __iwl_down() will clear the BT status variables,
3125                  * which is correct, but when we restart we really
3126                  * want to keep them so restore them afterwards.
3127                  *
3128                  * The restart process will later pick them up and
3129                  * re-configure the hw when we reconfigure the BT
3130                  * command.
3131                  */
3132                 bt_full_concurrent = priv->bt_full_concurrent;
3133                 bt_ci_compliance = priv->bt_ci_compliance;
3134                 bt_load = priv->bt_traffic_load;
3135                 bt_status = priv->bt_status;
3136
3137                 __iwl_down(priv);
3138
3139                 priv->bt_full_concurrent = bt_full_concurrent;
3140                 priv->bt_ci_compliance = bt_ci_compliance;
3141                 priv->bt_traffic_load = bt_load;
3142                 priv->bt_status = bt_status;
3143
3144                 mutex_unlock(&priv->mutex);
3145                 iwl_cancel_deferred_work(priv);
3146                 ieee80211_restart_hw(priv->hw);
3147         } else {
3148                 iwl_down(priv);
3149
3150                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3151                         return;
3152
3153                 mutex_lock(&priv->mutex);
3154                 __iwl_up(priv);
3155                 mutex_unlock(&priv->mutex);
3156         }
3157 }
3158
3159 static void iwl_bg_rx_replenish(struct work_struct *data)
3160 {
3161         struct iwl_priv *priv =
3162             container_of(data, struct iwl_priv, rx_replenish);
3163
3164         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3165                 return;
3166
3167         mutex_lock(&priv->mutex);
3168         iwlagn_rx_replenish(priv);
3169         mutex_unlock(&priv->mutex);
3170 }
3171
3172 /*****************************************************************************
3173  *
3174  * mac80211 entry point functions
3175  *
3176  *****************************************************************************/
3177
3178 #define UCODE_READY_TIMEOUT     (4 * HZ)
3179
3180 /*
3181  * Not a mac80211 entry point function, but it fits in with all the
3182  * other mac80211 functions grouped here.
3183  */
3184 static int iwl_mac_setup_register(struct iwl_priv *priv,
3185                                   struct iwlagn_ucode_capabilities *capa)
3186 {
3187         int ret;
3188         struct ieee80211_hw *hw = priv->hw;
3189         struct iwl_rxon_context *ctx;
3190
3191         hw->rate_control_algorithm = "iwl-agn-rs";
3192
3193         /* Tell mac80211 our characteristics */
3194         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3195                     IEEE80211_HW_AMPDU_AGGREGATION |
3196                     IEEE80211_HW_NEED_DTIM_PERIOD |
3197                     IEEE80211_HW_SPECTRUM_MGMT |
3198                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
3199
3200         hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3201
3202         if (!priv->cfg->base_params->broken_powersave)
3203                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3204                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3205
3206         if (priv->cfg->sku & IWL_SKU_N)
3207                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3208                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3209
3210         hw->sta_data_size = sizeof(struct iwl_station_priv);
3211         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3212
3213         for_each_context(priv, ctx) {
3214                 hw->wiphy->interface_modes |= ctx->interface_modes;
3215                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3216         }
3217
3218         hw->wiphy->max_remain_on_channel_duration = 1000;
3219
3220         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3221                             WIPHY_FLAG_DISABLE_BEACON_HINTS |
3222                             WIPHY_FLAG_IBSS_RSN;
3223
3224         /*
3225          * For now, disable PS by default because it affects
3226          * RX performance significantly.
3227          */
3228         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3229
3230         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3231         /* we create the 802.11 header and a zero-length SSID element */
3232         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3233
3234         /* Default value; 4 EDCA QOS priorities */
3235         hw->queues = 4;
3236
3237         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3238
3239         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3240                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3241                         &priv->bands[IEEE80211_BAND_2GHZ];
3242         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3243                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3244                         &priv->bands[IEEE80211_BAND_5GHZ];
3245
3246         iwl_leds_init(priv);
3247
3248         ret = ieee80211_register_hw(priv->hw);
3249         if (ret) {
3250                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3251                 return ret;
3252         }
3253         priv->mac80211_registered = 1;
3254
3255         return 0;
3256 }
3257
3258
3259 int iwlagn_mac_start(struct ieee80211_hw *hw)
3260 {
3261         struct iwl_priv *priv = hw->priv;
3262         int ret;
3263
3264         IWL_DEBUG_MAC80211(priv, "enter\n");
3265
3266         /* we should be verifying the device is ready to be opened */
3267         mutex_lock(&priv->mutex);
3268         ret = __iwl_up(priv);
3269         mutex_unlock(&priv->mutex);
3270
3271         if (ret)
3272                 return ret;
3273
3274         if (iwl_is_rfkill(priv))
3275                 goto out;
3276
3277         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3278
3279         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3280          * mac80211 will not be run successfully. */
3281         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3282                         test_bit(STATUS_READY, &priv->status),
3283                         UCODE_READY_TIMEOUT);
3284         if (!ret) {
3285                 if (!test_bit(STATUS_READY, &priv->status)) {
3286                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3287                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3288                         return -ETIMEDOUT;
3289                 }
3290         }
3291
3292         iwlagn_led_enable(priv);
3293
3294 out:
3295         priv->is_open = 1;
3296         IWL_DEBUG_MAC80211(priv, "leave\n");
3297         return 0;
3298 }
3299
3300 void iwlagn_mac_stop(struct ieee80211_hw *hw)
3301 {
3302         struct iwl_priv *priv = hw->priv;
3303
3304         IWL_DEBUG_MAC80211(priv, "enter\n");
3305
3306         if (!priv->is_open)
3307                 return;
3308
3309         priv->is_open = 0;
3310
3311         iwl_down(priv);
3312
3313         flush_workqueue(priv->workqueue);
3314
3315         /* User space software may expect getting rfkill changes
3316          * even if interface is down */
3317         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3318         iwl_enable_rfkill_int(priv);
3319
3320         IWL_DEBUG_MAC80211(priv, "leave\n");
3321 }
3322
3323 int iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3324 {
3325         struct iwl_priv *priv = hw->priv;
3326
3327         IWL_DEBUG_MACDUMP(priv, "enter\n");
3328
3329         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3330                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3331
3332         if (iwlagn_tx_skb(priv, skb))
3333                 dev_kfree_skb_any(skb);
3334
3335         IWL_DEBUG_MACDUMP(priv, "leave\n");
3336         return NETDEV_TX_OK;
3337 }
3338
3339 void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3340                                 struct ieee80211_vif *vif,
3341                                 struct ieee80211_key_conf *keyconf,
3342                                 struct ieee80211_sta *sta,
3343                                 u32 iv32, u16 *phase1key)
3344 {
3345         struct iwl_priv *priv = hw->priv;
3346         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3347
3348         IWL_DEBUG_MAC80211(priv, "enter\n");
3349
3350         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3351                             iv32, phase1key);
3352
3353         IWL_DEBUG_MAC80211(priv, "leave\n");
3354 }
3355
3356 int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3357                        struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3358                        struct ieee80211_key_conf *key)
3359 {
3360         struct iwl_priv *priv = hw->priv;
3361         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3362         struct iwl_rxon_context *ctx = vif_priv->ctx;
3363         int ret;
3364         u8 sta_id;
3365         bool is_default_wep_key = false;
3366
3367         IWL_DEBUG_MAC80211(priv, "enter\n");
3368
3369         if (priv->cfg->mod_params->sw_crypto) {
3370                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3371                 return -EOPNOTSUPP;
3372         }
3373
3374         /*
3375          * To support IBSS RSN, don't program group keys in IBSS, the
3376          * hardware will then not attempt to decrypt the frames.
3377          */
3378         if (vif->type == NL80211_IFTYPE_ADHOC &&
3379             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3380                 return -EOPNOTSUPP;
3381
3382         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3383         if (sta_id == IWL_INVALID_STATION)
3384                 return -EINVAL;
3385
3386         mutex_lock(&priv->mutex);
3387         iwl_scan_cancel_timeout(priv, 100);
3388
3389         /*
3390          * If we are getting WEP group key and we didn't receive any key mapping
3391          * so far, we are in legacy wep mode (group key only), otherwise we are
3392          * in 1X mode.
3393          * In legacy wep mode, we use another host command to the uCode.
3394          */
3395         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3396              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3397             !sta) {
3398                 if (cmd == SET_KEY)
3399                         is_default_wep_key = !ctx->key_mapping_keys;
3400                 else
3401                         is_default_wep_key =
3402                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3403         }
3404
3405         switch (cmd) {
3406         case SET_KEY:
3407                 if (is_default_wep_key)
3408                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3409                 else
3410                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3411                                                   key, sta_id);
3412
3413                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3414                 break;
3415         case DISABLE_KEY:
3416                 if (is_default_wep_key)
3417                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3418                 else
3419                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3420
3421                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3422                 break;
3423         default:
3424                 ret = -EINVAL;
3425         }
3426
3427         mutex_unlock(&priv->mutex);
3428         IWL_DEBUG_MAC80211(priv, "leave\n");
3429
3430         return ret;
3431 }
3432
3433 int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3434                             struct ieee80211_vif *vif,
3435                             enum ieee80211_ampdu_mlme_action action,
3436                             struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3437                             u8 buf_size)
3438 {
3439         struct iwl_priv *priv = hw->priv;
3440         int ret = -EINVAL;
3441         struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3442
3443         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3444                      sta->addr, tid);
3445
3446         if (!(priv->cfg->sku & IWL_SKU_N))
3447                 return -EACCES;
3448
3449         mutex_lock(&priv->mutex);
3450
3451         switch (action) {
3452         case IEEE80211_AMPDU_RX_START:
3453                 IWL_DEBUG_HT(priv, "start Rx\n");
3454                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3455                 break;
3456         case IEEE80211_AMPDU_RX_STOP:
3457                 IWL_DEBUG_HT(priv, "stop Rx\n");
3458                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3459                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3460                         ret = 0;
3461                 break;
3462         case IEEE80211_AMPDU_TX_START:
3463                 IWL_DEBUG_HT(priv, "start Tx\n");
3464                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3465                 if (ret == 0) {
3466                         priv->_agn.agg_tids_count++;
3467                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3468                                      priv->_agn.agg_tids_count);
3469                 }
3470                 break;
3471         case IEEE80211_AMPDU_TX_STOP:
3472                 IWL_DEBUG_HT(priv, "stop Tx\n");
3473                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3474                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3475                         priv->_agn.agg_tids_count--;
3476                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3477                                      priv->_agn.agg_tids_count);
3478                 }
3479                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3480                         ret = 0;
3481                 if (priv->cfg->ht_params &&
3482                     priv->cfg->ht_params->use_rts_for_aggregation) {
3483                         struct iwl_station_priv *sta_priv =
3484                                 (void *) sta->drv_priv;
3485                         /*
3486                          * switch off RTS/CTS if it was previously enabled
3487                          */
3488
3489                         sta_priv->lq_sta.lq.general_params.flags &=
3490                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3491                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3492                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3493                 }
3494                 break;
3495         case IEEE80211_AMPDU_TX_OPERATIONAL:
3496                 /*
3497                  * If the limit is 0, then it wasn't initialised yet,
3498                  * use the default. We can do that since we take the
3499                  * minimum below, and we don't want to go above our
3500                  * default due to hardware restrictions.
3501                  */
3502                 if (sta_priv->max_agg_bufsize == 0)
3503                         sta_priv->max_agg_bufsize =
3504                                 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3505
3506                 /*
3507                  * Even though in theory the peer could have different
3508                  * aggregation reorder buffer sizes for different sessions,
3509                  * our ucode doesn't allow for that and has a global limit
3510                  * for each station. Therefore, use the minimum of all the
3511                  * aggregation sessions and our default value.
3512                  */
3513                 sta_priv->max_agg_bufsize =
3514                         min(sta_priv->max_agg_bufsize, buf_size);
3515
3516                 if (priv->cfg->ht_params &&
3517                     priv->cfg->ht_params->use_rts_for_aggregation) {
3518                         /*
3519                          * switch to RTS/CTS if it is the prefer protection
3520                          * method for HT traffic
3521                          */
3522
3523                         sta_priv->lq_sta.lq.general_params.flags |=
3524                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3525                 }
3526
3527                 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3528                         sta_priv->max_agg_bufsize;
3529
3530                 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3531                                 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3532                 ret = 0;
3533                 break;
3534         }
3535         mutex_unlock(&priv->mutex);
3536
3537         return ret;
3538 }
3539
3540 int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3541                        struct ieee80211_vif *vif,
3542                        struct ieee80211_sta *sta)
3543 {
3544         struct iwl_priv *priv = hw->priv;
3545         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3546         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3547         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3548         int ret;
3549         u8 sta_id;
3550
3551         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3552                         sta->addr);
3553         mutex_lock(&priv->mutex);
3554         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3555                         sta->addr);
3556         sta_priv->common.sta_id = IWL_INVALID_STATION;
3557
3558         atomic_set(&sta_priv->pending_frames, 0);
3559         if (vif->type == NL80211_IFTYPE_AP)
3560                 sta_priv->client = true;
3561
3562         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3563                                      is_ap, sta, &sta_id);
3564         if (ret) {
3565                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3566                         sta->addr, ret);
3567                 /* Should we return success if return code is EEXIST ? */
3568                 mutex_unlock(&priv->mutex);
3569                 return ret;
3570         }
3571
3572         sta_priv->common.sta_id = sta_id;
3573
3574         /* Initialize rate scaling */
3575         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3576                        sta->addr);
3577         iwl_rs_rate_init(priv, sta, sta_id);
3578         mutex_unlock(&priv->mutex);
3579
3580         return 0;
3581 }
3582
3583 void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3584                                struct ieee80211_channel_switch *ch_switch)
3585 {
3586         struct iwl_priv *priv = hw->priv;
3587         const struct iwl_channel_info *ch_info;
3588         struct ieee80211_conf *conf = &hw->conf;
3589         struct ieee80211_channel *channel = ch_switch->channel;
3590         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3591         /*
3592          * MULTI-FIXME
3593          * When we add support for multiple interfaces, we need to
3594          * revisit this. The channel switch command in the device
3595          * only affects the BSS context, but what does that really
3596          * mean? And what if we get a CSA on the second interface?
3597          * This needs a lot of work.
3598          */
3599         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3600         u16 ch;
3601         unsigned long flags = 0;
3602
3603         IWL_DEBUG_MAC80211(priv, "enter\n");
3604
3605         if (iwl_is_rfkill(priv))
3606                 goto out_exit;
3607
3608         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3609             test_bit(STATUS_SCANNING, &priv->status))
3610                 goto out_exit;
3611
3612         if (!iwl_is_associated_ctx(ctx))
3613                 goto out_exit;
3614
3615         /* channel switch in progress */
3616         if (priv->switch_rxon.switch_in_progress == true)
3617                 goto out_exit;
3618
3619         mutex_lock(&priv->mutex);
3620         if (priv->cfg->ops->lib->set_channel_switch) {
3621
3622                 ch = channel->hw_value;
3623                 if (le16_to_cpu(ctx->active.channel) != ch) {
3624                         ch_info = iwl_get_channel_info(priv,
3625                                                        channel->band,
3626                                                        ch);
3627                         if (!is_channel_valid(ch_info)) {
3628                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3629                                 goto out;
3630                         }
3631                         spin_lock_irqsave(&priv->lock, flags);
3632
3633                         priv->current_ht_config.smps = conf->smps_mode;
3634
3635                         /* Configure HT40 channels */
3636                         ctx->ht.enabled = conf_is_ht(conf);
3637                         if (ctx->ht.enabled) {
3638                                 if (conf_is_ht40_minus(conf)) {
3639                                         ctx->ht.extension_chan_offset =
3640                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3641                                         ctx->ht.is_40mhz = true;
3642                                 } else if (conf_is_ht40_plus(conf)) {
3643                                         ctx->ht.extension_chan_offset =
3644                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3645                                         ctx->ht.is_40mhz = true;
3646                                 } else {
3647                                         ctx->ht.extension_chan_offset =
3648                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3649                                         ctx->ht.is_40mhz = false;
3650                                 }
3651                         } else
3652                                 ctx->ht.is_40mhz = false;
3653
3654                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3655                                 ctx->staging.flags = 0;
3656
3657                         iwl_set_rxon_channel(priv, channel, ctx);
3658                         iwl_set_rxon_ht(priv, ht_conf);
3659                         iwl_set_flags_for_band(priv, ctx, channel->band,
3660                                                ctx->vif);
3661                         spin_unlock_irqrestore(&priv->lock, flags);
3662
3663                         iwl_set_rate(priv);
3664                         /*
3665                          * at this point, staging_rxon has the
3666                          * configuration for channel switch
3667                          */
3668                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3669                                                                     ch_switch))
3670                                 priv->switch_rxon.switch_in_progress = false;
3671                 }
3672         }
3673 out:
3674         mutex_unlock(&priv->mutex);
3675 out_exit:
3676         if (!priv->switch_rxon.switch_in_progress)
3677                 ieee80211_chswitch_done(ctx->vif, false);
3678         IWL_DEBUG_MAC80211(priv, "leave\n");
3679 }
3680
3681 void iwlagn_configure_filter(struct ieee80211_hw *hw,
3682                              unsigned int changed_flags,
3683                              unsigned int *total_flags,
3684                              u64 multicast)
3685 {
3686         struct iwl_priv *priv = hw->priv;
3687         __le32 filter_or = 0, filter_nand = 0;
3688         struct iwl_rxon_context *ctx;
3689
3690 #define CHK(test, flag) do { \
3691         if (*total_flags & (test))              \
3692                 filter_or |= (flag);            \
3693         else                                    \
3694                 filter_nand |= (flag);          \
3695         } while (0)
3696
3697         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3698                         changed_flags, *total_flags);
3699
3700         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3701         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3702         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3703         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3704
3705 #undef CHK
3706
3707         mutex_lock(&priv->mutex);
3708
3709         for_each_context(priv, ctx) {
3710                 ctx->staging.filter_flags &= ~filter_nand;
3711                 ctx->staging.filter_flags |= filter_or;
3712
3713                 /*
3714                  * Not committing directly because hardware can perform a scan,
3715                  * but we'll eventually commit the filter flags change anyway.
3716                  */
3717         }
3718
3719         mutex_unlock(&priv->mutex);
3720
3721         /*
3722          * Receiving all multicast frames is always enabled by the
3723          * default flags setup in iwl_connection_init_rx_config()
3724          * since we currently do not support programming multicast
3725          * filters into the device.
3726          */
3727         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3728                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3729 }
3730
3731 void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3732 {
3733         struct iwl_priv *priv = hw->priv;
3734
3735         mutex_lock(&priv->mutex);
3736         IWL_DEBUG_MAC80211(priv, "enter\n");
3737
3738         /* do not support "flush" */
3739         if (!priv->cfg->ops->lib->txfifo_flush)
3740                 goto done;
3741
3742         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3743                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3744                 goto done;
3745         }
3746         if (iwl_is_rfkill(priv)) {
3747                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3748                 goto done;
3749         }
3750
3751         /*
3752          * mac80211 will not push any more frames for transmit
3753          * until the flush is completed
3754          */
3755         if (drop) {
3756                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3757                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3758                         IWL_ERR(priv, "flush request fail\n");
3759                         goto done;
3760                 }
3761         }
3762         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3763         iwlagn_wait_tx_queue_empty(priv);
3764 done:
3765         mutex_unlock(&priv->mutex);
3766         IWL_DEBUG_MAC80211(priv, "leave\n");
3767 }
3768
3769 static void iwlagn_disable_roc(struct iwl_priv *priv)
3770 {
3771         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3772         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3773
3774         lockdep_assert_held(&priv->mutex);
3775
3776         if (!ctx->is_active)
3777                 return;
3778
3779         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3780         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3781         iwl_set_rxon_channel(priv, chan, ctx);
3782         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3783
3784         priv->_agn.hw_roc_channel = NULL;
3785
3786         iwlcore_commit_rxon(priv, ctx);
3787
3788         ctx->is_active = false;
3789 }
3790
3791 static void iwlagn_bg_roc_done(struct work_struct *work)
3792 {
3793         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3794                                              _agn.hw_roc_work.work);
3795
3796         mutex_lock(&priv->mutex);
3797         ieee80211_remain_on_channel_expired(priv->hw);
3798         iwlagn_disable_roc(priv);
3799         mutex_unlock(&priv->mutex);
3800 }
3801
3802 #ifdef CONFIG_IWL5000
3803 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3804                                      struct ieee80211_channel *channel,
3805                                      enum nl80211_channel_type channel_type,
3806                                      int duration)
3807 {
3808         struct iwl_priv *priv = hw->priv;
3809         int err = 0;
3810
3811         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3812                 return -EOPNOTSUPP;
3813
3814         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3815                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3816                 return -EOPNOTSUPP;
3817
3818         mutex_lock(&priv->mutex);
3819
3820         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3821             test_bit(STATUS_SCAN_HW, &priv->status)) {
3822                 err = -EBUSY;
3823                 goto out;
3824         }
3825
3826         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3827         priv->_agn.hw_roc_channel = channel;
3828         priv->_agn.hw_roc_chantype = channel_type;
3829         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3830         iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3831         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3832                            msecs_to_jiffies(duration + 20));
3833
3834         msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3835         ieee80211_ready_on_channel(priv->hw);
3836
3837  out:
3838         mutex_unlock(&priv->mutex);
3839
3840         return err;
3841 }
3842
3843 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3844 {
3845         struct iwl_priv *priv = hw->priv;
3846
3847         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3848                 return -EOPNOTSUPP;
3849
3850         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3851
3852         mutex_lock(&priv->mutex);
3853         iwlagn_disable_roc(priv);
3854         mutex_unlock(&priv->mutex);
3855
3856         return 0;
3857 }
3858 #endif
3859
3860 /*****************************************************************************
3861  *
3862  * driver setup and teardown
3863  *
3864  *****************************************************************************/
3865
3866 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3867 {
3868         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3869
3870         init_waitqueue_head(&priv->wait_command_queue);
3871
3872         INIT_WORK(&priv->restart, iwl_bg_restart);
3873         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3874         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3875         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3876         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3877         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3878         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3879         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3880         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3881         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3882
3883         iwl_setup_scan_deferred_work(priv);
3884
3885         if (priv->cfg->ops->lib->setup_deferred_work)
3886                 priv->cfg->ops->lib->setup_deferred_work(priv);
3887
3888         init_timer(&priv->statistics_periodic);
3889         priv->statistics_periodic.data = (unsigned long)priv;
3890         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3891
3892         init_timer(&priv->ucode_trace);
3893         priv->ucode_trace.data = (unsigned long)priv;
3894         priv->ucode_trace.function = iwl_bg_ucode_trace;
3895
3896         init_timer(&priv->watchdog);
3897         priv->watchdog.data = (unsigned long)priv;
3898         priv->watchdog.function = iwl_bg_watchdog;
3899
3900         if (!priv->cfg->base_params->use_isr_legacy)
3901                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3902                         iwl_irq_tasklet, (unsigned long)priv);
3903         else
3904                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3905                         iwl_irq_tasklet_legacy, (unsigned long)priv);
3906 }
3907
3908 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3909 {
3910         if (priv->cfg->ops->lib->cancel_deferred_work)
3911                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3912
3913         cancel_delayed_work_sync(&priv->init_alive_start);
3914         cancel_delayed_work(&priv->alive_start);
3915         cancel_work_sync(&priv->run_time_calib_work);
3916         cancel_work_sync(&priv->beacon_update);
3917
3918         iwl_cancel_scan_deferred_work(priv);
3919
3920         cancel_work_sync(&priv->bt_full_concurrency);
3921         cancel_work_sync(&priv->bt_runtime_config);
3922
3923         del_timer_sync(&priv->statistics_periodic);
3924         del_timer_sync(&priv->ucode_trace);
3925 }
3926
3927 static void iwl_init_hw_rates(struct iwl_priv *priv,
3928                               struct ieee80211_rate *rates)
3929 {
3930         int i;
3931
3932         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3933                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3934                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3935                 rates[i].hw_value_short = i;
3936                 rates[i].flags = 0;
3937                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3938                         /*
3939                          * If CCK != 1M then set short preamble rate flag.
3940                          */
3941                         rates[i].flags |=
3942                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3943                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3944                 }
3945         }
3946 }
3947
3948 static int iwl_init_drv(struct iwl_priv *priv)
3949 {
3950         int ret;
3951
3952         spin_lock_init(&priv->sta_lock);
3953         spin_lock_init(&priv->hcmd_lock);
3954
3955         INIT_LIST_HEAD(&priv->free_frames);
3956
3957         mutex_init(&priv->mutex);
3958         mutex_init(&priv->sync_cmd_mutex);
3959
3960         priv->ieee_channels = NULL;
3961         priv->ieee_rates = NULL;
3962         priv->band = IEEE80211_BAND_2GHZ;
3963
3964         priv->iw_mode = NL80211_IFTYPE_STATION;
3965         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3966         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3967         priv->_agn.agg_tids_count = 0;
3968
3969         /* initialize force reset */
3970         priv->force_reset[IWL_RF_RESET].reset_duration =
3971                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3972         priv->force_reset[IWL_FW_RESET].reset_duration =
3973                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3974
3975         /* Choose which receivers/antennas to use */
3976         if (priv->cfg->ops->hcmd->set_rxon_chain)
3977                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3978                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3979
3980         iwl_init_scan_params(priv);
3981
3982         /* init bt coex */
3983         if (priv->cfg->bt_params &&
3984             priv->cfg->bt_params->advanced_bt_coexist) {
3985                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3986                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3987                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3988                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3989                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3990                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3991         }
3992
3993         /* Set the tx_power_user_lmt to the lowest power level
3994          * this value will get overwritten by channel max power avg
3995          * from eeprom */
3996         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3997         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3998
3999         ret = iwl_init_channel_map(priv);
4000         if (ret) {
4001                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4002                 goto err;
4003         }
4004
4005         ret = iwlcore_init_geos(priv);
4006         if (ret) {
4007                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4008                 goto err_free_channel_map;
4009         }
4010         iwl_init_hw_rates(priv, priv->ieee_rates);
4011
4012         return 0;
4013
4014 err_free_channel_map:
4015         iwl_free_channel_map(priv);
4016 err:
4017         return ret;
4018 }
4019
4020 static void iwl_uninit_drv(struct iwl_priv *priv)
4021 {
4022         iwl_calib_free_results(priv);
4023         iwlcore_free_geos(priv);
4024         iwl_free_channel_map(priv);
4025         kfree(priv->scan_cmd);
4026 }
4027
4028 #ifdef CONFIG_IWL5000
4029 struct ieee80211_ops iwlagn_hw_ops = {
4030         .tx = iwlagn_mac_tx,
4031         .start = iwlagn_mac_start,
4032         .stop = iwlagn_mac_stop,
4033         .add_interface = iwl_mac_add_interface,
4034         .remove_interface = iwl_mac_remove_interface,
4035         .change_interface = iwl_mac_change_interface,
4036         .config = iwlagn_mac_config,
4037         .configure_filter = iwlagn_configure_filter,
4038         .set_key = iwlagn_mac_set_key,
4039         .update_tkip_key = iwlagn_mac_update_tkip_key,
4040         .conf_tx = iwl_mac_conf_tx,
4041         .bss_info_changed = iwlagn_bss_info_changed,
4042         .ampdu_action = iwlagn_mac_ampdu_action,
4043         .hw_scan = iwl_mac_hw_scan,
4044         .sta_notify = iwlagn_mac_sta_notify,
4045         .sta_add = iwlagn_mac_sta_add,
4046         .sta_remove = iwl_mac_sta_remove,
4047         .channel_switch = iwlagn_mac_channel_switch,
4048         .flush = iwlagn_mac_flush,
4049         .tx_last_beacon = iwl_mac_tx_last_beacon,
4050         .remain_on_channel = iwl_mac_remain_on_channel,
4051         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
4052 };
4053 #endif
4054
4055 static void iwl_hw_detect(struct iwl_priv *priv)
4056 {
4057         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4058         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4059         priv->rev_id = priv->pci_dev->revision;
4060         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4061 }
4062
4063 static int iwl_set_hw_params(struct iwl_priv *priv)
4064 {
4065         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4066         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4067         if (priv->cfg->mod_params->amsdu_size_8K)
4068                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4069         else
4070                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4071
4072         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4073
4074         if (priv->cfg->mod_params->disable_11n)
4075                 priv->cfg->sku &= ~IWL_SKU_N;
4076
4077         /* Device-specific setup */
4078         return priv->cfg->ops->lib->set_hw_params(priv);
4079 }
4080
4081 static const u8 iwlagn_bss_ac_to_fifo[] = {
4082         IWL_TX_FIFO_VO,
4083         IWL_TX_FIFO_VI,
4084         IWL_TX_FIFO_BE,
4085         IWL_TX_FIFO_BK,
4086 };
4087
4088 static const u8 iwlagn_bss_ac_to_queue[] = {
4089         0, 1, 2, 3,
4090 };
4091
4092 static const u8 iwlagn_pan_ac_to_fifo[] = {
4093         IWL_TX_FIFO_VO_IPAN,
4094         IWL_TX_FIFO_VI_IPAN,
4095         IWL_TX_FIFO_BE_IPAN,
4096         IWL_TX_FIFO_BK_IPAN,
4097 };
4098
4099 static const u8 iwlagn_pan_ac_to_queue[] = {
4100         7, 6, 5, 4,
4101 };
4102
4103 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4104 {
4105         int err = 0, i;
4106         struct iwl_priv *priv;
4107         struct ieee80211_hw *hw;
4108         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4109         unsigned long flags;
4110         u16 pci_cmd, num_mac;
4111
4112         /************************
4113          * 1. Allocating HW data
4114          ************************/
4115
4116         /* Disabling hardware scan means that mac80211 will perform scans
4117          * "the hard way", rather than using device's scan. */
4118         if (cfg->mod_params->disable_hw_scan) {
4119                 dev_printk(KERN_DEBUG, &(pdev->dev),
4120                         "sw scan support is deprecated\n");
4121 #ifdef CONFIG_IWL5000
4122                 iwlagn_hw_ops.hw_scan = NULL;
4123 #endif
4124 #ifdef CONFIG_IWL4965
4125                 iwl4965_hw_ops.hw_scan = NULL;
4126 #endif
4127         }
4128
4129         hw = iwl_alloc_all(cfg);
4130         if (!hw) {
4131                 err = -ENOMEM;
4132                 goto out;
4133         }
4134         priv = hw->priv;
4135         /* At this point both hw and priv are allocated. */
4136
4137         /*
4138          * The default context is always valid,
4139          * more may be discovered when firmware
4140          * is loaded.
4141          */
4142         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4143
4144         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4145                 priv->contexts[i].ctxid = i;
4146
4147         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4148         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
4149         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4150         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4151         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4152         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4153         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4154         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4155         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4156         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4157         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4158                 BIT(NL80211_IFTYPE_ADHOC);
4159         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4160                 BIT(NL80211_IFTYPE_STATION);
4161         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
4162         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4163         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4164         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4165
4166         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4167         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4168         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4169         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4170         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4171         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4172         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4173         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4174         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4175         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4176         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4177         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4178                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4179 #ifdef CONFIG_IWL_P2P
4180         priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
4181                 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
4182 #endif
4183         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4184         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4185         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4186
4187         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4188
4189         SET_IEEE80211_DEV(hw, &pdev->dev);
4190
4191         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4192         priv->cfg = cfg;
4193         priv->pci_dev = pdev;
4194         priv->inta_mask = CSR_INI_SET_MASK;
4195
4196         /* is antenna coupling more than 35dB ? */
4197         priv->bt_ant_couple_ok =
4198                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4199                 true : false;
4200
4201         /* enable/disable bt channel inhibition */
4202         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4203         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
4204                        (priv->bt_ch_announce) ? "On" : "Off");
4205
4206         if (iwl_alloc_traffic_mem(priv))
4207                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4208
4209         /**************************
4210          * 2. Initializing PCI bus
4211          **************************/
4212         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4213                                 PCIE_LINK_STATE_CLKPM);
4214
4215         if (pci_enable_device(pdev)) {
4216                 err = -ENODEV;
4217                 goto out_ieee80211_free_hw;
4218         }
4219
4220         pci_set_master(pdev);
4221
4222         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4223         if (!err)
4224                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4225         if (err) {
4226                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4227                 if (!err)
4228                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4229                 /* both attempts failed: */
4230                 if (err) {
4231                         IWL_WARN(priv, "No suitable DMA available.\n");
4232                         goto out_pci_disable_device;
4233                 }
4234         }
4235
4236         err = pci_request_regions(pdev, DRV_NAME);
4237         if (err)
4238                 goto out_pci_disable_device;
4239
4240         pci_set_drvdata(pdev, priv);
4241
4242
4243         /***********************
4244          * 3. Read REV register
4245          ***********************/
4246         priv->hw_base = pci_iomap(pdev, 0, 0);
4247         if (!priv->hw_base) {
4248                 err = -ENODEV;
4249                 goto out_pci_release_regions;
4250         }
4251
4252         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4253                 (unsigned long long) pci_resource_len(pdev, 0));
4254         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4255
4256         /* these spin locks will be used in apm_ops.init and EEPROM access
4257          * we should init now
4258          */
4259         spin_lock_init(&priv->reg_lock);
4260         spin_lock_init(&priv->lock);
4261
4262         /*
4263          * stop and reset the on-board processor just in case it is in a
4264          * strange state ... like being left stranded by a primary kernel
4265          * and this is now the kdump kernel trying to start up
4266          */
4267         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4268
4269         iwl_hw_detect(priv);
4270         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4271                 priv->cfg->name, priv->hw_rev);
4272
4273         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4274          * PCI Tx retries from interfering with C3 CPU state */
4275         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4276
4277         iwl_prepare_card_hw(priv);
4278         if (!priv->hw_ready) {
4279                 IWL_WARN(priv, "Failed, HW not ready\n");
4280                 goto out_iounmap;
4281         }
4282
4283         /*****************
4284          * 4. Read EEPROM
4285          *****************/
4286         /* Read the EEPROM */
4287         err = iwl_eeprom_init(priv);
4288         if (err) {
4289                 IWL_ERR(priv, "Unable to init EEPROM\n");
4290                 goto out_iounmap;
4291         }
4292         err = iwl_eeprom_check_version(priv);
4293         if (err)
4294                 goto out_free_eeprom;
4295
4296         err = iwl_eeprom_check_sku(priv);
4297         if (err)
4298                 goto out_free_eeprom;
4299
4300         /* extract MAC Address */
4301         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4302         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4303         priv->hw->wiphy->addresses = priv->addresses;
4304         priv->hw->wiphy->n_addresses = 1;
4305         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4306         if (num_mac > 1) {
4307                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4308                        ETH_ALEN);
4309                 priv->addresses[1].addr[5]++;
4310                 priv->hw->wiphy->n_addresses++;
4311         }
4312
4313         /************************
4314          * 5. Setup HW constants
4315          ************************/
4316         if (iwl_set_hw_params(priv)) {
4317                 IWL_ERR(priv, "failed to set hw parameters\n");
4318                 goto out_free_eeprom;
4319         }
4320
4321         /*******************
4322          * 6. Setup priv
4323          *******************/
4324
4325         err = iwl_init_drv(priv);
4326         if (err)
4327                 goto out_free_eeprom;
4328         /* At this point both hw and priv are initialized. */
4329
4330         /********************
4331          * 7. Setup services
4332          ********************/
4333         spin_lock_irqsave(&priv->lock, flags);
4334         iwl_disable_interrupts(priv);
4335         spin_unlock_irqrestore(&priv->lock, flags);
4336
4337         pci_enable_msi(priv->pci_dev);
4338
4339         if (priv->cfg->ops->lib->isr_ops.alloc)
4340                 priv->cfg->ops->lib->isr_ops.alloc(priv);
4341
4342         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
4343                           IRQF_SHARED, DRV_NAME, priv);
4344         if (err) {
4345                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4346                 goto out_disable_msi;
4347         }
4348
4349         iwl_setup_deferred_work(priv);
4350         iwl_setup_rx_handlers(priv);
4351
4352         /*********************************************
4353          * 8. Enable interrupts and read RFKILL state
4354          *********************************************/
4355
4356         /* enable rfkill interrupt: hw bug w/a */
4357         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4358         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4359                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4360                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4361         }
4362
4363         iwl_enable_rfkill_int(priv);
4364
4365         /* If platform's RF_KILL switch is NOT set to KILL */
4366         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4367                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4368         else
4369                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4370
4371         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4372                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4373
4374         iwl_power_initialize(priv);
4375         iwl_tt_initialize(priv);
4376
4377         init_completion(&priv->_agn.firmware_loading_complete);
4378
4379         err = iwl_request_firmware(priv, true);
4380         if (err)
4381                 goto out_destroy_workqueue;
4382
4383         return 0;
4384
4385  out_destroy_workqueue:
4386         destroy_workqueue(priv->workqueue);
4387         priv->workqueue = NULL;
4388         free_irq(priv->pci_dev->irq, priv);
4389         if (priv->cfg->ops->lib->isr_ops.free)
4390                 priv->cfg->ops->lib->isr_ops.free(priv);
4391  out_disable_msi:
4392         pci_disable_msi(priv->pci_dev);
4393         iwl_uninit_drv(priv);
4394  out_free_eeprom:
4395         iwl_eeprom_free(priv);
4396  out_iounmap:
4397         pci_iounmap(pdev, priv->hw_base);
4398  out_pci_release_regions:
4399         pci_set_drvdata(pdev, NULL);
4400         pci_release_regions(pdev);
4401  out_pci_disable_device:
4402         pci_disable_device(pdev);
4403  out_ieee80211_free_hw:
4404         iwl_free_traffic_mem(priv);
4405         ieee80211_free_hw(priv->hw);
4406  out:
4407         return err;
4408 }
4409
4410 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4411 {
4412         struct iwl_priv *priv = pci_get_drvdata(pdev);
4413         unsigned long flags;
4414
4415         if (!priv)
4416                 return;
4417
4418         wait_for_completion(&priv->_agn.firmware_loading_complete);
4419
4420         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4421
4422         iwl_dbgfs_unregister(priv);
4423         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4424
4425         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4426          * to be called and iwl_down since we are removing the device
4427          * we need to set STATUS_EXIT_PENDING bit.
4428          */
4429         set_bit(STATUS_EXIT_PENDING, &priv->status);
4430
4431         iwl_leds_exit(priv);
4432
4433         if (priv->mac80211_registered) {
4434                 ieee80211_unregister_hw(priv->hw);
4435                 priv->mac80211_registered = 0;
4436         } else {
4437                 iwl_down(priv);
4438         }
4439
4440         /*
4441          * Make sure device is reset to low power before unloading driver.
4442          * This may be redundant with iwl_down(), but there are paths to
4443          * run iwl_down() without calling apm_ops.stop(), and there are
4444          * paths to avoid running iwl_down() at all before leaving driver.
4445          * This (inexpensive) call *makes sure* device is reset.
4446          */
4447         iwl_apm_stop(priv);
4448
4449         iwl_tt_exit(priv);
4450
4451         /* make sure we flush any pending irq or
4452          * tasklet for the driver
4453          */
4454         spin_lock_irqsave(&priv->lock, flags);
4455         iwl_disable_interrupts(priv);
4456         spin_unlock_irqrestore(&priv->lock, flags);
4457
4458         iwl_synchronize_irq(priv);
4459
4460         iwl_dealloc_ucode_pci(priv);
4461
4462         if (priv->rxq.bd)
4463                 iwlagn_rx_queue_free(priv, &priv->rxq);
4464         iwlagn_hw_txq_ctx_free(priv);
4465
4466         iwl_eeprom_free(priv);
4467
4468
4469         /*netif_stop_queue(dev); */
4470         flush_workqueue(priv->workqueue);
4471
4472         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4473          * priv->workqueue... so we can't take down the workqueue
4474          * until now... */
4475         destroy_workqueue(priv->workqueue);
4476         priv->workqueue = NULL;
4477         iwl_free_traffic_mem(priv);
4478
4479         free_irq(priv->pci_dev->irq, priv);
4480         pci_disable_msi(priv->pci_dev);
4481         pci_iounmap(pdev, priv->hw_base);
4482         pci_release_regions(pdev);
4483         pci_disable_device(pdev);
4484         pci_set_drvdata(pdev, NULL);
4485
4486         iwl_uninit_drv(priv);
4487
4488         if (priv->cfg->ops->lib->isr_ops.free)
4489                 priv->cfg->ops->lib->isr_ops.free(priv);
4490
4491         dev_kfree_skb(priv->beacon_skb);
4492
4493         ieee80211_free_hw(priv->hw);
4494 }
4495
4496
4497 /*****************************************************************************
4498  *
4499  * driver and module entry point
4500  *
4501  *****************************************************************************/
4502
4503 /* Hardware specific file defines the PCI IDs table for that hardware module */
4504 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4505 #ifdef CONFIG_IWL4965
4506         {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4507         {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4508 #endif /* CONFIG_IWL4965 */
4509 #ifdef CONFIG_IWL5000
4510 /* 5100 Series WiFi */
4511         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4512         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4513         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4514         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4515         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4516         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4517         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4518         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4519         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4520         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4521         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4522         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4523         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4524         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4525         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4526         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4527         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4528         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4529         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4530         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4531         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4532         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4533         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4534         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4535
4536 /* 5300 Series WiFi */
4537         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4538         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4539         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4540         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4541         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4542         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4543         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4544         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4545         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4546         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4547         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4548         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4549
4550 /* 5350 Series WiFi/WiMax */
4551         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4552         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4553         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4554
4555 /* 5150 Series Wifi/WiMax */
4556         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4557         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4558         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4559         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4560         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4561         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4562
4563         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4564         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4565         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4566         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4567
4568 /* 6x00 Series */
4569         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4570         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4571         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4572         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4573         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4574         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4575         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4576         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4577         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4578         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4579
4580 /* 6x05 Series */
4581         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4582         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4583         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4584         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4585         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4586         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4587         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4588
4589 /* 6x30 Series */
4590         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4591         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4592         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4593         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4594         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4595         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4596         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4597         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4598         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4599         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4600         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4601         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4602         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4603         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4604         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4605         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4606
4607 /* 6x50 WiFi/WiMax Series */
4608         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4609         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4610         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4611         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4612         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4613         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4614
4615 /* 6150 WiFi/WiMax Series */
4616         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4617         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4618         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4619         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4620         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4621         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4622
4623 /* 1000 Series WiFi */
4624         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4625         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4626         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4627         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4628         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4629         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4630         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4631         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4632         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4633         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4634         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4635         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4636
4637 /* 100 Series WiFi */
4638         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4639         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4640         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4641         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4642         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4643         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4644
4645 /* 130 Series WiFi */
4646         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4647         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4648         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4649         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4650         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4651         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4652
4653 /* 2x00 Series */
4654         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4655         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4656         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4657         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4658         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4659         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4660
4661 /* 2x30 Series */
4662         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4663         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4664         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4665         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4666         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4667         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4668
4669 /* 6x35 Series */
4670         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4671         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4672         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4673         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4674         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4675         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4676         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4677         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4678         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4679
4680 /* 200 Series */
4681         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4682         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4683         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4684         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4685         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4686         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4687
4688 /* 230 Series */
4689         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4690         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4691         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4692         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4693         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4694         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4695
4696 #endif /* CONFIG_IWL5000 */
4697
4698         {0}
4699 };
4700 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4701
4702 static struct pci_driver iwl_driver = {
4703         .name = DRV_NAME,
4704         .id_table = iwl_hw_card_ids,
4705         .probe = iwl_pci_probe,
4706         .remove = __devexit_p(iwl_pci_remove),
4707         .driver.pm = IWL_PM_OPS,
4708 };
4709
4710 static int __init iwl_init(void)
4711 {
4712
4713         int ret;
4714         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4715         pr_info(DRV_COPYRIGHT "\n");
4716
4717         ret = iwlagn_rate_control_register();
4718         if (ret) {
4719                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4720                 return ret;
4721         }
4722
4723         ret = pci_register_driver(&iwl_driver);
4724         if (ret) {
4725                 pr_err("Unable to initialize PCI module\n");
4726                 goto error_register;
4727         }
4728
4729         return ret;
4730
4731 error_register:
4732         iwlagn_rate_control_unregister();
4733         return ret;
4734 }
4735
4736 static void __exit iwl_exit(void)
4737 {
4738         pci_unregister_driver(&iwl_driver);
4739         iwlagn_rate_control_unregister();
4740 }
4741
4742 module_exit(iwl_exit);
4743 module_init(iwl_init);
4744
4745 #ifdef CONFIG_IWLWIFI_DEBUG
4746 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4747 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4748 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4749 MODULE_PARM_DESC(debug, "debug output mask");
4750 #endif
4751
4752 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4753 MODULE_PARM_DESC(swcrypto50,
4754                  "using crypto in software (default 0 [hardware]) (deprecated)");
4755 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4756 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4757 module_param_named(queues_num50,
4758                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4759 MODULE_PARM_DESC(queues_num50,
4760                  "number of hw queues in 50xx series (deprecated)");
4761 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4762 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4763 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4764 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4765 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4766 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4767 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4768                    int, S_IRUGO);
4769 MODULE_PARM_DESC(amsdu_size_8K50,
4770                  "enable 8K amsdu size in 50XX series (deprecated)");
4771 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4772                    int, S_IRUGO);
4773 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4774 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4775 MODULE_PARM_DESC(fw_restart50,
4776                  "restart firmware in case of error (deprecated)");
4777 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4778 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4779 module_param_named(
4780         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4781 MODULE_PARM_DESC(disable_hw_scan,
4782                  "disable hardware scanning (default 0) (deprecated)");
4783
4784 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4785                    S_IRUGO);
4786 MODULE_PARM_DESC(ucode_alternative,
4787                  "specify ucode alternative to use from ucode file");
4788
4789 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4790 MODULE_PARM_DESC(antenna_coupling,
4791                  "specify antenna coupling in dB (defualt: 0 dB)");
4792
4793 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4794 MODULE_PARM_DESC(bt_ch_inhibition,
4795                  "Disable BT channel inhibition (default: enable)");