drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-agn-calib.h"
  61 #include "iwl-agn.h"
  62 #include "iwl-agn-led.h"
  63
  64
  65 /******************************************************************************
  66  *
  67  * module boiler plate
  68  *
  69  ******************************************************************************/
  70
  71 /*
  72  * module name, copyright, version, etc.
  73  */
  74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  75
  76 #ifdef CONFIG_IWLWIFI_DEBUG
  77 #define VD "d"
  78 #else
  79 #define VD
  80 #endif
  81
  82 #define DRV_VERSION     IWLWIFI_VERSION VD
  83
  84
  85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86 MODULE_VERSION(DRV_VERSION);
  87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  88 MODULE_LICENSE("GPL");
  89
  90 static int iwlagn_ant_coupling;
  91 static bool iwlagn_bt_ch_announce = 1;
  92
  93 void iwl_update_chain_flags(struct iwl_priv *priv)
  94 {
  95         struct iwl_rxon_context *ctx;
  96
  97         if (priv->cfg->ops->hcmd->set_rxon_chain) {
  98                 for_each_context(priv, ctx) {
  99                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 100                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
 101                                 iwlcore_commit_rxon(priv, ctx);
 102                 }
 103         }
 104 }
 105
 106 static void iwl_clear_free_frames(struct iwl_priv *priv)
 107 {
 108         struct list_head *element;
 109
 110         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 111                        priv->frames_count);
 112
 113         while (!list_empty(&priv->free_frames)) {
 114                 element = priv->free_frames.next;
 115                 list_del(element);
 116                 kfree(list_entry(element, struct iwl_frame, list));
 117                 priv->frames_count--;
 118         }
 119
 120         if (priv->frames_count) {
 121                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 122                             priv->frames_count);
 123                 priv->frames_count = 0;
 124         }
 125 }
 126
 127 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 128 {
 129         struct iwl_frame *frame;
 130         struct list_head *element;
 131         if (list_empty(&priv->free_frames)) {
 132                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 133                 if (!frame) {
 134                         IWL_ERR(priv, "Could not allocate frame!\n");
 135                         return NULL;
 136                 }
 137
 138                 priv->frames_count++;
 139                 return frame;
 140         }
 141
 142         element = priv->free_frames.next;
 143         list_del(element);
 144         return list_entry(element, struct iwl_frame, list);
 145 }
 146
 147 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 148 {
 149         memset(frame, 0, sizeof(*frame));
 150         list_add(&frame->list, &priv->free_frames);
 151 }
 152
 153 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 154                                  struct ieee80211_hdr *hdr,
 155                                  int left)
 156 {
 157         lockdep_assert_held(&priv->mutex);
 158
 159         if (!priv->beacon_skb)
 160                 return 0;
 161
 162         if (priv->beacon_skb->len > left)
 163                 return 0;
 164
 165         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
 166
 167         return priv->beacon_skb->len;
 168 }
 169
 170 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 171 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 172                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 173                                u8 *beacon, u32 frame_size)
 174 {
 175         u16 tim_idx;
 176         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 177
 178         /*
 179          * The index is relative to frame start but we start looking at the
 180          * variable-length part of the beacon.
 181          */
 182         tim_idx = mgmt->u.beacon.variable - beacon;
 183
 184         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 185         while ((tim_idx < (frame_size - 2)) &&
 186                         (beacon[tim_idx] != WLAN_EID_TIM))
 187                 tim_idx += beacon[tim_idx+1] + 2;
 188
 189         /* If TIM field was found, set variables */
 190         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 191                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 192                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 193         } else
 194                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 195 }
 196
 197 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 198                                        struct iwl_frame *frame)
 199 {
 200         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 201         u32 frame_size;
 202         u32 rate_flags;
 203         u32 rate;
 204         /*
 205          * We have to set up the TX command, the TX Beacon command, and the
 206          * beacon contents.
 207          */
 208
 209         lockdep_assert_held(&priv->mutex);
 210
 211         if (!priv->beacon_ctx) {
 212                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 213                 return 0;
 214         }
 215
 216         /* Initialize memory */
 217         tx_beacon_cmd = &frame->u.beacon;
 218         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 219
 220         /* Set up TX beacon contents */
 221         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 222                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 223         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 224                 return 0;
 225         if (!frame_size)
 226                 return 0;
 227
 228         /* Set up TX command fields */
 229         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 230         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 231         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 232         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 233                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 234
 235         /* Set up TX beacon command fields */
 236         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 237                            frame_size);
 238
 239         /* Set up packet rate and flags */
 240         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 241         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 242                                               priv->hw_params.valid_tx_ant);
 243         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 244         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 245                 rate_flags |= RATE_MCS_CCK_MSK;
 246         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 247                         rate_flags);
 248
 249         return sizeof(*tx_beacon_cmd) + frame_size;
 250 }
 251
 252 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
 253 {
 254         struct iwl_frame *frame;
 255         unsigned int frame_size;
 256         int rc;
 257
 258         frame = iwl_get_free_frame(priv);
 259         if (!frame) {
 260                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 261                           "command.\n");
 262                 return -ENOMEM;
 263         }
 264
 265         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 266         if (!frame_size) {
 267                 IWL_ERR(priv, "Error configuring the beacon command\n");
 268                 iwl_free_frame(priv, frame);
 269                 return -EINVAL;
 270         }
 271
 272         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 273                               &frame->u.cmd[0]);
 274
 275         iwl_free_frame(priv, frame);
 276
 277         return rc;
 278 }
 279
 280 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 281 {
 282         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 283
 284         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 285         if (sizeof(dma_addr_t) > sizeof(u32))
 286                 addr |=
 287                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 288
 289         return addr;
 290 }
 291
 292 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 293 {
 294         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 295
 296         return le16_to_cpu(tb->hi_n_len) >> 4;
 297 }
 298
 299 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 300                                   dma_addr_t addr, u16 len)
 301 {
 302         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 303         u16 hi_n_len = len << 4;
 304
 305         put_unaligned_le32(addr, &tb->lo);
 306         if (sizeof(dma_addr_t) > sizeof(u32))
 307                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 308
 309         tb->hi_n_len = cpu_to_le16(hi_n_len);
 310
 311         tfd->num_tbs = idx + 1;
 312 }
 313
 314 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 315 {
 316         return tfd->num_tbs & 0x1f;
 317 }
 318
 319 /**
 320  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 321  * @priv - driver private data
 322  * @txq - tx queue
 323  *
 324  * Does NOT advance any TFD circular buffer read/write indexes
 325  * Does NOT free the TFD itself (which is within circular buffer)
 326  */
 327 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 328 {
 329         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 330         struct iwl_tfd *tfd;
 331         struct pci_dev *dev = priv->pci_dev;
 332         int index = txq->q.read_ptr;
 333         int i;
 334         int num_tbs;
 335
 336         tfd = &tfd_tmp[index];
 337
 338         /* Sanity check on number of chunks */
 339         num_tbs = iwl_tfd_get_num_tbs(tfd);
 340
 341         if (num_tbs >= IWL_NUM_OF_TBS) {
 342                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 343                 /* @todo issue fatal error, it is quite serious situation */
 344                 return;
 345         }
 346
 347         /* Unmap tx_cmd */
 348         if (num_tbs)
 349                 pci_unmap_single(dev,
 350                                 dma_unmap_addr(&txq->meta[index], mapping),
 351                                 dma_unmap_len(&txq->meta[index], len),
 352                                 PCI_DMA_BIDIRECTIONAL);
 353
 354         /* Unmap chunks, if any. */
 355         for (i = 1; i < num_tbs; i++)
 356                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 357                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 358
 359         /* free SKB */
 360         if (txq->txb) {
 361                 struct sk_buff *skb;
 362
 363                 skb = txq->txb[txq->q.read_ptr].skb;
 364
 365                 /* can be called from irqs-disabled context */
 366                 if (skb) {
 367                         dev_kfree_skb_any(skb);
 368                         txq->txb[txq->q.read_ptr].skb = NULL;
 369                 }
 370         }
 371 }
 372
 373 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 374                                  struct iwl_tx_queue *txq,
 375                                  dma_addr_t addr, u16 len,
 376                                  u8 reset, u8 pad)
 377 {
 378         struct iwl_queue *q;
 379         struct iwl_tfd *tfd, *tfd_tmp;
 380         u32 num_tbs;
 381
 382         q = &txq->q;
 383         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 384         tfd = &tfd_tmp[q->write_ptr];
 385
 386         if (reset)
 387                 memset(tfd, 0, sizeof(*tfd));
 388
 389         num_tbs = iwl_tfd_get_num_tbs(tfd);
 390
 391         /* Each TFD can point to a maximum 20 Tx buffers */
 392         if (num_tbs >= IWL_NUM_OF_TBS) {
 393                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 394                           IWL_NUM_OF_TBS);
 395                 return -EINVAL;
 396         }
 397
 398         BUG_ON(addr & ~DMA_BIT_MASK(36));
 399         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 400                 IWL_ERR(priv, "Unaligned address = %llx\n",
 401                           (unsigned long long)addr);
 402
 403         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 404
 405         return 0;
 406 }
 407
 408 /*
 409  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 410  * given Tx queue, and enable the DMA channel used for that queue.
 411  *
 412  * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 413  * channels supported in hardware.
 414  */
 415 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 416                          struct iwl_tx_queue *txq)
 417 {
 418         int txq_id = txq->q.id;
 419
 420         /* Circular buffer (TFD queue in DRAM) physical base address */
 421         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 422                              txq->q.dma_addr >> 8);
 423
 424         return 0;
 425 }
 426
 427 static void iwl_bg_beacon_update(struct work_struct *work)
 428 {
 429         struct iwl_priv *priv =
 430                 container_of(work, struct iwl_priv, beacon_update);
 431         struct sk_buff *beacon;
 432
 433         mutex_lock(&priv->mutex);
 434         if (!priv->beacon_ctx) {
 435                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 436                 goto out;
 437         }
 438
 439         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 440                 /*
 441                  * The ucode will send beacon notifications even in
 442                  * IBSS mode, but we don't want to process them. But
 443                  * we need to defer the type check to here due to
 444                  * requiring locking around the beacon_ctx access.
 445                  */
 446                 goto out;
 447         }
 448
 449         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 450         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 451         if (!beacon) {
 452                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
 453                 goto out;
 454         }
 455
 456         /* new beacon skb is allocated every time; dispose previous.*/
 457         dev_kfree_skb(priv->beacon_skb);
 458
 459         priv->beacon_skb = beacon;
 460
 461         iwlagn_send_beacon_cmd(priv);
 462  out:
 463         mutex_unlock(&priv->mutex);
 464 }
 465
 466 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 467 {
 468         struct iwl_priv *priv =
 469                 container_of(work, struct iwl_priv, bt_runtime_config);
 470
 471         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 472                 return;
 473
 474         /* dont send host command if rf-kill is on */
 475         if (!iwl_is_ready_rf(priv))
 476                 return;
 477         priv->cfg->ops->hcmd->send_bt_config(priv);
 478 }
 479
 480 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 481 {
 482         struct iwl_priv *priv =
 483                 container_of(work, struct iwl_priv, bt_full_concurrency);
 484         struct iwl_rxon_context *ctx;
 485
 486         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 487                 return;
 488
 489         /* dont send host command if rf-kill is on */
 490         if (!iwl_is_ready_rf(priv))
 491                 return;
 492
 493         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 494                        priv->bt_full_concurrent ?
 495                        "full concurrency" : "3-wire");
 496
 497         /*
 498          * LQ & RXON updated cmds must be sent before BT Config cmd
 499          * to avoid 3-wire collisions
 500          */
 501         mutex_lock(&priv->mutex);
 502         for_each_context(priv, ctx) {
 503                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 504                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 505                 iwlcore_commit_rxon(priv, ctx);
 506         }
 507         mutex_unlock(&priv->mutex);
 508
 509         priv->cfg->ops->hcmd->send_bt_config(priv);
 510 }
 511
 512 /**
 513  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 514  *
 515  * This callback is provided in order to send a statistics request.
 516  *
 517  * This timer function is continually reset to execute within
 518  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 519  * was received.  We need to ensure we receive the statistics in order
 520  * to update the temperature used for calibrating the TXPOWER.
 521  */
 522 static void iwl_bg_statistics_periodic(unsigned long data)
 523 {
 524         struct iwl_priv *priv = (struct iwl_priv *)data;
 525
 526         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 527                 return;
 528
 529         /* dont send host command if rf-kill is on */
 530         if (!iwl_is_ready_rf(priv))
 531                 return;
 532
 533         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 534 }
 535
 536
 537 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 538                                         u32 start_idx, u32 num_events,
 539                                         u32 mode)
 540 {
 541         u32 i;
 542         u32 ptr;        /* SRAM byte address of log data */
 543         u32 ev, time, data; /* event log data */
 544         unsigned long reg_flags;
 545
 546         if (mode == 0)
 547                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 548         else
 549                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 550
 551         /* Make sure device is powered up for SRAM reads */
 552         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 553         if (iwl_grab_nic_access(priv)) {
 554                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 555                 return;
 556         }
 557
 558         /* Set starting address; reads will auto-increment */
 559         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 560         rmb();
 561
 562         /*
 563          * "time" is actually "data" for mode 0 (no timestamp).
 564          * place event id # at far right for easier visual parsing.
 565          */
 566         for (i = 0; i < num_events; i++) {
 567                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 568                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 569                 if (mode == 0) {
 570                         trace_iwlwifi_dev_ucode_cont_event(priv,
 571                                                         0, time, ev);
 572                 } else {
 573                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 574                         trace_iwlwifi_dev_ucode_cont_event(priv,
 575                                                 time, data, ev);
 576                 }
 577         }
 578         /* Allow device to power down */
 579         iwl_release_nic_access(priv);
 580         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 581 }
 582
 583 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 584 {
 585         u32 capacity;   /* event log capacity in # entries */
 586         u32 base;       /* SRAM byte address of event log header */
 587         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 588         u32 num_wraps;  /* # times uCode wrapped to top of log */
 589         u32 next_entry; /* index of next entry to be written by uCode */
 590
 591         if (priv->ucode_type == UCODE_INIT)
 592                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 593         else
 594                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 595         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 596                 capacity = iwl_read_targ_mem(priv, base);
 597                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 598                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 599                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 600         } else
 601                 return;
 602
 603         if (num_wraps == priv->event_log.num_wraps) {
 604                 iwl_print_cont_event_trace(priv,
 605                                        base, priv->event_log.next_entry,
 606                                        next_entry - priv->event_log.next_entry,
 607                                        mode);
 608                 priv->event_log.non_wraps_count++;
 609         } else {
 610                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 611                         priv->event_log.wraps_more_count++;
 612                 else
 613                         priv->event_log.wraps_once_count++;
 614                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 615                                 num_wraps - priv->event_log.num_wraps,
 616                                 next_entry, priv->event_log.next_entry);
 617                 if (next_entry < priv->event_log.next_entry) {
 618                         iwl_print_cont_event_trace(priv, base,
 619                                priv->event_log.next_entry,
 620                                capacity - priv->event_log.next_entry,
 621                                mode);
 622
 623                         iwl_print_cont_event_trace(priv, base, 0,
 624                                 next_entry, mode);
 625                 } else {
 626                         iwl_print_cont_event_trace(priv, base,
 627                                next_entry, capacity - next_entry,
 628                                mode);
 629
 630                         iwl_print_cont_event_trace(priv, base, 0,
 631                                 next_entry, mode);
 632                 }
 633         }
 634         priv->event_log.num_wraps = num_wraps;
 635         priv->event_log.next_entry = next_entry;
 636 }
 637
 638 /**
 639  * iwl_bg_ucode_trace - Timer callback to log ucode event
 640  *
 641  * The timer is continually set to execute every
 642  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 643  * this function is to perform continuous uCode event logging operation
 644  * if enabled
 645  */
 646 static void iwl_bg_ucode_trace(unsigned long data)
 647 {
 648         struct iwl_priv *priv = (struct iwl_priv *)data;
 649
 650         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 651                 return;
 652
 653         if (priv->event_log.ucode_trace) {
 654                 iwl_continuous_event_trace(priv);
 655                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 656                 mod_timer(&priv->ucode_trace,
 657                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 658         }
 659 }
 660
 661 static void iwl_bg_tx_flush(struct work_struct *work)
 662 {
 663         struct iwl_priv *priv =
 664                 container_of(work, struct iwl_priv, tx_flush);
 665
 666         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 667                 return;
 668
 669         /* do nothing if rf-kill is on */
 670         if (!iwl_is_ready_rf(priv))
 671                 return;
 672
 673         if (priv->cfg->ops->lib->txfifo_flush) {
 674                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 675                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 676         }
 677 }
 678
 679 /**
 680  * iwl_rx_handle - Main entry function for receiving responses from uCode
 681  *
 682  * Uses the priv->rx_handlers callback function array to invoke
 683  * the appropriate handlers, including command responses,
 684  * frame-received notifications, and other notifications.
 685  */
 686 static void iwl_rx_handle(struct iwl_priv *priv)
 687 {
 688         struct iwl_rx_mem_buffer *rxb;
 689         struct iwl_rx_packet *pkt;
 690         struct iwl_rx_queue *rxq = &priv->rxq;
 691         u32 r, i;
 692         int reclaim;
 693         unsigned long flags;
 694         u8 fill_rx = 0;
 695         u32 count = 8;
 696         int total_empty;
 697
 698         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 699          * buffer that the driver may process (last buffer filled by ucode). */
 700         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 701         i = rxq->read;
 702
 703         /* Rx interrupt, but nothing sent from uCode */
 704         if (i == r)
 705                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
 706
 707         /* calculate total frames need to be restock after handling RX */
 708         total_empty = r - rxq->write_actual;
 709         if (total_empty < 0)
 710                 total_empty += RX_QUEUE_SIZE;
 711
 712         if (total_empty > (RX_QUEUE_SIZE / 2))
 713                 fill_rx = 1;
 714
 715         while (i != r) {
 716                 int len;
 717
 718                 rxb = rxq->queue[i];
 719
 720                 /* If an RXB doesn't have a Rx queue slot associated with it,
 721                  * then a bug has been introduced in the queue refilling
 722                  * routines -- catch it here */
 723                 BUG_ON(rxb == NULL);
 724
 725                 rxq->queue[i] = NULL;
 726
 727                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
 728                                PAGE_SIZE << priv->hw_params.rx_page_order,
 729                                PCI_DMA_FROMDEVICE);
 730                 pkt = rxb_addr(rxb);
 731
 732                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 733                 len += sizeof(u32); /* account for status word */
 734                 trace_iwlwifi_dev_rx(priv, pkt, len);
 735
 736                 /* Reclaim a command buffer only if this packet is a response
 737                  *   to a (driver-originated) command.
 738                  * If the packet (e.g. Rx frame) originated from uCode,
 739                  *   there is no command buffer to reclaim.
 740                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 741                  *   but apparently a few don't get set; catch them here. */
 742                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 743                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 744                         (pkt->hdr.cmd != REPLY_RX) &&
 745                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 746                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 747                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 748                         (pkt->hdr.cmd != REPLY_TX);
 749
 750                 /*
 751                  * Do the notification wait before RX handlers so
 752                  * even if the RX handler consumes the RXB we have
 753                  * access to it in the notification wait entry.
 754                  */
 755                 if (!list_empty(&priv->_agn.notif_waits)) {
 756                         struct iwl_notification_wait *w;
 757
 758                         spin_lock(&priv->_agn.notif_wait_lock);
 759                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
 760                                 if (w->cmd == pkt->hdr.cmd) {
 761                                         w->triggered = true;
 762                                         if (w->fn)
 763                                                 w->fn(priv, pkt);
 764                                 }
 765                         }
 766                         spin_unlock(&priv->_agn.notif_wait_lock);
 767
 768                         wake_up_all(&priv->_agn.notif_waitq);
 769                 }
 770
 771                 /* Based on type of command response or notification,
 772                  *   handle those that need handling via function in
 773                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
 774                 if (priv->rx_handlers[pkt->hdr.cmd]) {
 775                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
 776                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 777                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
 778                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
 779                 } else {
 780                         /* No handling needed */
 781                         IWL_DEBUG_RX(priv,
 782                                 "r %d i %d No handler needed for %s, 0x%02x\n",
 783                                 r, i, get_cmd_string(pkt->hdr.cmd),
 784                                 pkt->hdr.cmd);
 785                 }
 786
 787                 /*
 788                  * XXX: After here, we should always check rxb->page
 789                  * against NULL before touching it or its virtual
 790                  * memory (pkt). Because some rx_handler might have
 791                  * already taken or freed the pages.
 792                  */
 793
 794                 if (reclaim) {
 795                         /* Invoke any callbacks, transfer the buffer to caller,
 796                          * and fire off the (possibly) blocking iwl_send_cmd()
 797                          * as we reclaim the driver command queue */
 798                         if (rxb->page)
 799                                 iwl_tx_cmd_complete(priv, rxb);
 800                         else
 801                                 IWL_WARN(priv, "Claim null rxb?\n");
 802                 }
 803
 804                 /* Reuse the page if possible. For notification packets and
 805                  * SKBs that fail to Rx correctly, add them back into the
 806                  * rx_free list for reuse later. */
 807                 spin_lock_irqsave(&rxq->lock, flags);
 808                 if (rxb->page != NULL) {
 809                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
 810                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
 811                                 PCI_DMA_FROMDEVICE);
 812                         list_add_tail(&rxb->list, &rxq->rx_free);
 813                         rxq->free_count++;
 814                 } else
 815                         list_add_tail(&rxb->list, &rxq->rx_used);
 816
 817                 spin_unlock_irqrestore(&rxq->lock, flags);
 818
 819                 i = (i + 1) & RX_QUEUE_MASK;
 820                 /* If there are a lot of unused frames,
 821                  * restock the Rx queue so ucode wont assert. */
 822                 if (fill_rx) {
 823                         count++;
 824                         if (count >= 8) {
 825                                 rxq->read = i;
 826                                 iwlagn_rx_replenish_now(priv);
 827                                 count = 0;
 828                         }
 829                 }
 830         }
 831
 832         /* Backtrack one entry */
 833         rxq->read = i;
 834         if (fill_rx)
 835                 iwlagn_rx_replenish_now(priv);
 836         else
 837                 iwlagn_rx_queue_restock(priv);
 838 }
 839
 840 /* call this function to flush any scheduled tasklet */
 841 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
 842 {
 843         /* wait to make sure we flush pending tasklet*/
 844         synchronize_irq(priv->pci_dev->irq);
 845         tasklet_kill(&priv->irq_tasklet);
 846 }
 847
 848 /* tasklet for iwlagn interrupt */
 849 static void iwl_irq_tasklet(struct iwl_priv *priv)
 850 {
 851         u32 inta = 0;
 852         u32 handled = 0;
 853         unsigned long flags;
 854         u32 i;
 855 #ifdef CONFIG_IWLWIFI_DEBUG
 856         u32 inta_mask;
 857 #endif
 858
 859         spin_lock_irqsave(&priv->lock, flags);
 860
 861         /* Ack/clear/reset pending uCode interrupts.
 862          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 863          */
 864         /* There is a hardware bug in the interrupt mask function that some
 865          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 866          * they are disabled in the CSR_INT_MASK register. Furthermore the
 867          * ICT interrupt handling mechanism has another bug that might cause
 868          * these unmasked interrupts fail to be detected. We workaround the
 869          * hardware bugs here by ACKing all the possible interrupts so that
 870          * interrupt coalescing can still be achieved.
 871          */
 872         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
 873
 874         inta = priv->_agn.inta;
 875
 876 #ifdef CONFIG_IWLWIFI_DEBUG
 877         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
 878                 /* just for debug */
 879                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
 880                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
 881                                 inta, inta_mask);
 882         }
 883 #endif
 884
 885         spin_unlock_irqrestore(&priv->lock, flags);
 886
 887         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
 888         priv->_agn.inta = 0;
 889
 890         /* Now service all interrupt bits discovered above. */
 891         if (inta & CSR_INT_BIT_HW_ERR) {
 892                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
 893
 894                 /* Tell the device to stop sending interrupts */
 895                 iwl_disable_interrupts(priv);
 896
 897                 priv->isr_stats.hw++;
 898                 iwl_irq_handle_error(priv);
 899
 900                 handled |= CSR_INT_BIT_HW_ERR;
 901
 902                 return;
 903         }
 904
 905 #ifdef CONFIG_IWLWIFI_DEBUG
 906         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
 907                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 908                 if (inta & CSR_INT_BIT_SCD) {
 909                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
 910                                       "the frame/frames.\n");
 911                         priv->isr_stats.sch++;
 912                 }
 913
 914                 /* Alive notification via Rx interrupt will do the real work */
 915                 if (inta & CSR_INT_BIT_ALIVE) {
 916                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
 917                         priv->isr_stats.alive++;
 918                 }
 919         }
 920 #endif
 921         /* Safely ignore these bits for debug checks below */
 922         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 923
 924         /* HW RF KILL switch toggled */
 925         if (inta & CSR_INT_BIT_RF_KILL) {
 926                 int hw_rf_kill = 0;
 927                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
 928                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
 929                         hw_rf_kill = 1;
 930
 931                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
 932                                 hw_rf_kill ? "disable radio" : "enable radio");
 933
 934                 priv->isr_stats.rfkill++;
 935
 936                 /* driver only loads ucode once setting the interface up.
 937                  * the driver allows loading the ucode even if the radio
 938                  * is killed. Hence update the killswitch state here. The
 939                  * rfkill handler will care about restarting if needed.
 940                  */
 941                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
 942                         if (hw_rf_kill)
 943                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 944                         else
 945                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 946                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
 947                 }
 948
 949                 handled |= CSR_INT_BIT_RF_KILL;
 950         }
 951
 952         /* Chip got too hot and stopped itself */
 953         if (inta & CSR_INT_BIT_CT_KILL) {
 954                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
 955                 priv->isr_stats.ctkill++;
 956                 handled |= CSR_INT_BIT_CT_KILL;
 957         }
 958
 959         /* Error detected by uCode */
 960         if (inta & CSR_INT_BIT_SW_ERR) {
 961                 IWL_ERR(priv, "Microcode SW error detected. "
 962                         " Restarting 0x%X.\n", inta);
 963                 priv->isr_stats.sw++;
 964                 iwl_irq_handle_error(priv);
 965                 handled |= CSR_INT_BIT_SW_ERR;
 966         }
 967
 968         /* uCode wakes up after power-down sleep */
 969         if (inta & CSR_INT_BIT_WAKEUP) {
 970                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
 971                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
 972                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
 973                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
 974
 975                 priv->isr_stats.wakeup++;
 976
 977                 handled |= CSR_INT_BIT_WAKEUP;
 978         }
 979
 980         /* All uCode command responses, including Tx command responses,
 981          * Rx "responses" (frame-received notification), and other
 982          * notifications from uCode come through here*/
 983         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
 984                         CSR_INT_BIT_RX_PERIODIC)) {
 985                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
 986                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
 987                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
 988                         iwl_write32(priv, CSR_FH_INT_STATUS,
 989                                         CSR_FH_INT_RX_MASK);
 990                 }
 991                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
 992                         handled |= CSR_INT_BIT_RX_PERIODIC;
 993                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
 994                 }
 995                 /* Sending RX interrupt require many steps to be done in the
 996                  * the device:
 997                  * 1- write interrupt to current index in ICT table.
 998                  * 2- dma RX frame.
 999                  * 3- update RX shared data to indicate last write index.
1000                  * 4- send interrupt.
1001                  * This could lead to RX race, driver could receive RX interrupt
1002                  * but the shared data changes does not reflect this;
1003                  * periodic interrupt will detect any dangling Rx activity.
1004                  */
1005
1006                 /* Disable periodic interrupt; we use it as just a one-shot. */
1007                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1008                             CSR_INT_PERIODIC_DIS);
1009                 iwl_rx_handle(priv);
1010
1011                 /*
1012                  * Enable periodic interrupt in 8 msec only if we received
1013                  * real RX interrupt (instead of just periodic int), to catch
1014                  * any dangling Rx interrupt.  If it was just the periodic
1015                  * interrupt, there was no dangling Rx activity, and no need
1016                  * to extend the periodic interrupt; one-shot is enough.
1017                  */
1018                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1019                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1020                                     CSR_INT_PERIODIC_ENA);
1021
1022                 priv->isr_stats.rx++;
1023         }
1024
1025         /* This "Tx" DMA channel is used only for loading uCode */
1026         if (inta & CSR_INT_BIT_FH_TX) {
1027                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1028                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1029                 priv->isr_stats.tx++;
1030                 handled |= CSR_INT_BIT_FH_TX;
1031                 /* Wake up uCode load routine, now that load is complete */
1032                 priv->ucode_write_complete = 1;
1033                 wake_up_interruptible(&priv->wait_command_queue);
1034         }
1035
1036         if (inta & ~handled) {
1037                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1038                 priv->isr_stats.unhandled++;
1039         }
1040
1041         if (inta & ~(priv->inta_mask)) {
1042                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1043                          inta & ~priv->inta_mask);
1044         }
1045
1046         /* Re-enable all interrupts */
1047         /* only Re-enable if disabled by irq */
1048         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1049                 iwl_enable_interrupts(priv);
1050         /* Re-enable RF_KILL if it occurred */
1051         else if (handled & CSR_INT_BIT_RF_KILL)
1052                 iwl_enable_rfkill_int(priv);
1053 }
1054
1055 /*****************************************************************************
1056  *
1057  * sysfs attributes
1058  *
1059  *****************************************************************************/
1060
1061 #ifdef CONFIG_IWLWIFI_DEBUG
1062
1063 /*
1064  * The following adds a new attribute to the sysfs representation
1065  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1066  * used for controlling the debug level.
1067  *
1068  * See the level definitions in iwl for details.
1069  *
1070  * The debug_level being managed using sysfs below is a per device debug
1071  * level that is used instead of the global debug level if it (the per
1072  * device debug level) is set.
1073  */
1074 static ssize_t show_debug_level(struct device *d,
1075                                 struct device_attribute *attr, char *buf)
1076 {
1077         struct iwl_priv *priv = dev_get_drvdata(d);
1078         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1079 }
1080 static ssize_t store_debug_level(struct device *d,
1081                                 struct device_attribute *attr,
1082                                  const char *buf, size_t count)
1083 {
1084         struct iwl_priv *priv = dev_get_drvdata(d);
1085         unsigned long val;
1086         int ret;
1087
1088         ret = strict_strtoul(buf, 0, &val);
1089         if (ret)
1090                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1091         else {
1092                 priv->debug_level = val;
1093                 if (iwl_alloc_traffic_mem(priv))
1094                         IWL_ERR(priv,
1095                                 "Not enough memory to generate traffic log\n");
1096         }
1097         return strnlen(buf, count);
1098 }
1099
1100 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1101                         show_debug_level, store_debug_level);
1102
1103
1104 #endif /* CONFIG_IWLWIFI_DEBUG */
1105
1106
1107 static ssize_t show_temperature(struct device *d,
1108                                 struct device_attribute *attr, char *buf)
1109 {
1110         struct iwl_priv *priv = dev_get_drvdata(d);
1111
1112         if (!iwl_is_alive(priv))
1113                 return -EAGAIN;
1114
1115         return sprintf(buf, "%d\n", priv->temperature);
1116 }
1117
1118 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1119
1120 static ssize_t show_tx_power(struct device *d,
1121                              struct device_attribute *attr, char *buf)
1122 {
1123         struct iwl_priv *priv = dev_get_drvdata(d);
1124
1125         if (!iwl_is_ready_rf(priv))
1126                 return sprintf(buf, "off\n");
1127         else
1128                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1129 }
1130
1131 static ssize_t store_tx_power(struct device *d,
1132                               struct device_attribute *attr,
1133                               const char *buf, size_t count)
1134 {
1135         struct iwl_priv *priv = dev_get_drvdata(d);
1136         unsigned long val;
1137         int ret;
1138
1139         ret = strict_strtoul(buf, 10, &val);
1140         if (ret)
1141                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1142         else {
1143                 ret = iwl_set_tx_power(priv, val, false);
1144                 if (ret)
1145                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1146                                 ret);
1147                 else
1148                         ret = count;
1149         }
1150         return ret;
1151 }
1152
1153 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1154
1155 static struct attribute *iwl_sysfs_entries[] = {
1156         &dev_attr_temperature.attr,
1157         &dev_attr_tx_power.attr,
1158 #ifdef CONFIG_IWLWIFI_DEBUG
1159         &dev_attr_debug_level.attr,
1160 #endif
1161         NULL
1162 };
1163
1164 static struct attribute_group iwl_attribute_group = {
1165         .name = NULL,           /* put in device directory */
1166         .attrs = iwl_sysfs_entries,
1167 };
1168
1169 /******************************************************************************
1170  *
1171  * uCode download functions
1172  *
1173  ******************************************************************************/
1174
1175 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1176 {
1177         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1178         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1179         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1180         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1181         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1182         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1183 }
1184
1185 static void iwl_nic_start(struct iwl_priv *priv)
1186 {
1187         /* Remove all resets to allow NIC to operate */
1188         iwl_write32(priv, CSR_RESET, 0);
1189 }
1190
1191 struct iwlagn_ucode_capabilities {
1192         u32 max_probe_length;
1193         u32 standard_phy_calibration_size;
1194         bool pan;
1195 };
1196
1197 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1198 static int iwl_mac_setup_register(struct iwl_priv *priv,
1199                                   struct iwlagn_ucode_capabilities *capa);
1200
1201 #define UCODE_EXPERIMENTAL_INDEX        100
1202 #define UCODE_EXPERIMENTAL_TAG          "exp"
1203
1204 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1205 {
1206         const char *name_pre = priv->cfg->fw_name_pre;
1207         char tag[8];
1208
1209         if (first) {
1210 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1211                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1212                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1213         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1214 #endif
1215                 priv->fw_index = priv->cfg->ucode_api_max;
1216                 sprintf(tag, "%d", priv->fw_index);
1217         } else {
1218                 priv->fw_index--;
1219                 sprintf(tag, "%d", priv->fw_index);
1220         }
1221
1222         if (priv->fw_index < priv->cfg->ucode_api_min) {
1223                 IWL_ERR(priv, "no suitable firmware found!\n");
1224                 return -ENOENT;
1225         }
1226
1227         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1228
1229         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1230                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1231                                 ? "EXPERIMENTAL " : "",
1232                        priv->firmware_name);
1233
1234         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1235                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1236                                        iwl_ucode_callback);
1237 }
1238
1239 struct iwlagn_firmware_pieces {
1240         const void *inst, *data, *init, *init_data, *boot;
1241         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1242
1243         u32 build;
1244
1245         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1246         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1247 };
1248
1249 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1250                                        const struct firmware *ucode_raw,
1251                                        struct iwlagn_firmware_pieces *pieces)
1252 {
1253         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1254         u32 api_ver, hdr_size;
1255         const u8 *src;
1256
1257         priv->ucode_ver = le32_to_cpu(ucode->ver);
1258         api_ver = IWL_UCODE_API(priv->ucode_ver);
1259
1260         switch (api_ver) {
1261         default:
1262                 hdr_size = 28;
1263                 if (ucode_raw->size < hdr_size) {
1264                         IWL_ERR(priv, "File size too small!\n");
1265                         return -EINVAL;
1266                 }
1267                 pieces->build = le32_to_cpu(ucode->u.v2.build);
1268                 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1269                 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1270                 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1271                 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1272                 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1273                 src = ucode->u.v2.data;
1274                 break;
1275         case 0:
1276         case 1:
1277         case 2:
1278                 hdr_size = 24;
1279                 if (ucode_raw->size < hdr_size) {
1280                         IWL_ERR(priv, "File size too small!\n");
1281                         return -EINVAL;
1282                 }
1283                 pieces->build = 0;
1284                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1285                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1286                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1287                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1288                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1289                 src = ucode->u.v1.data;
1290                 break;
1291         }
1292
1293         /* Verify size of file vs. image size info in file's header */
1294         if (ucode_raw->size != hdr_size + pieces->inst_size +
1295                                 pieces->data_size + pieces->init_size +
1296                                 pieces->init_data_size + pieces->boot_size) {
1297
1298                 IWL_ERR(priv,
1299                         "uCode file size %d does not match expected size\n",
1300                         (int)ucode_raw->size);
1301                 return -EINVAL;
1302         }
1303
1304         pieces->inst = src;
1305         src += pieces->inst_size;
1306         pieces->data = src;
1307         src += pieces->data_size;
1308         pieces->init = src;
1309         src += pieces->init_size;
1310         pieces->init_data = src;
1311         src += pieces->init_data_size;
1312         pieces->boot = src;
1313         src += pieces->boot_size;
1314
1315         return 0;
1316 }
1317
1318 static int iwlagn_wanted_ucode_alternative = 1;
1319
1320 static int iwlagn_load_firmware(struct iwl_priv *priv,
1321                                 const struct firmware *ucode_raw,
1322                                 struct iwlagn_firmware_pieces *pieces,
1323                                 struct iwlagn_ucode_capabilities *capa)
1324 {
1325         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1326         struct iwl_ucode_tlv *tlv;
1327         size_t len = ucode_raw->size;
1328         const u8 *data;
1329         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1330         u64 alternatives;
1331         u32 tlv_len;
1332         enum iwl_ucode_tlv_type tlv_type;
1333         const u8 *tlv_data;
1334
1335         if (len < sizeof(*ucode)) {
1336                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1337                 return -EINVAL;
1338         }
1339
1340         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1341                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1342                         le32_to_cpu(ucode->magic));
1343                 return -EINVAL;
1344         }
1345
1346         /*
1347          * Check which alternatives are present, and "downgrade"
1348          * when the chosen alternative is not present, warning
1349          * the user when that happens. Some files may not have
1350          * any alternatives, so don't warn in that case.
1351          */
1352         alternatives = le64_to_cpu(ucode->alternatives);
1353         tmp = wanted_alternative;
1354         if (wanted_alternative > 63)
1355                 wanted_alternative = 63;
1356         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1357                 wanted_alternative--;
1358         if (wanted_alternative && wanted_alternative != tmp)
1359                 IWL_WARN(priv,
1360                          "uCode alternative %d not available, choosing %d\n",
1361                          tmp, wanted_alternative);
1362
1363         priv->ucode_ver = le32_to_cpu(ucode->ver);
1364         pieces->build = le32_to_cpu(ucode->build);
1365         data = ucode->data;
1366
1367         len -= sizeof(*ucode);
1368
1369         while (len >= sizeof(*tlv)) {
1370                 u16 tlv_alt;
1371
1372                 len -= sizeof(*tlv);
1373                 tlv = (void *)data;
1374
1375                 tlv_len = le32_to_cpu(tlv->length);
1376                 tlv_type = le16_to_cpu(tlv->type);
1377                 tlv_alt = le16_to_cpu(tlv->alternative);
1378                 tlv_data = tlv->data;
1379
1380                 if (len < tlv_len) {
1381                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1382                                 len, tlv_len);
1383                         return -EINVAL;
1384                 }
1385                 len -= ALIGN(tlv_len, 4);
1386                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1387
1388                 /*
1389                  * Alternative 0 is always valid.
1390                  *
1391                  * Skip alternative TLVs that are not selected.
1392                  */
1393                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1394                         continue;
1395
1396                 switch (tlv_type) {
1397                 case IWL_UCODE_TLV_INST:
1398                         pieces->inst = tlv_data;
1399                         pieces->inst_size = tlv_len;
1400                         break;
1401                 case IWL_UCODE_TLV_DATA:
1402                         pieces->data = tlv_data;
1403                         pieces->data_size = tlv_len;
1404                         break;
1405                 case IWL_UCODE_TLV_INIT:
1406                         pieces->init = tlv_data;
1407                         pieces->init_size = tlv_len;
1408                         break;
1409                 case IWL_UCODE_TLV_INIT_DATA:
1410                         pieces->init_data = tlv_data;
1411                         pieces->init_data_size = tlv_len;
1412                         break;
1413                 case IWL_UCODE_TLV_BOOT:
1414                         pieces->boot = tlv_data;
1415                         pieces->boot_size = tlv_len;
1416                         break;
1417                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1418                         if (tlv_len != sizeof(u32))
1419                                 goto invalid_tlv_len;
1420                         capa->max_probe_length =
1421                                         le32_to_cpup((__le32 *)tlv_data);
1422                         break;
1423                 case IWL_UCODE_TLV_PAN:
1424                         if (tlv_len)
1425                                 goto invalid_tlv_len;
1426                         capa->pan = true;
1427                         break;
1428                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1429                         if (tlv_len != sizeof(u32))
1430                                 goto invalid_tlv_len;
1431                         pieces->init_evtlog_ptr =
1432                                         le32_to_cpup((__le32 *)tlv_data);
1433                         break;
1434                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1435                         if (tlv_len != sizeof(u32))
1436                                 goto invalid_tlv_len;
1437                         pieces->init_evtlog_size =
1438                                         le32_to_cpup((__le32 *)tlv_data);
1439                         break;
1440                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1441                         if (tlv_len != sizeof(u32))
1442                                 goto invalid_tlv_len;
1443                         pieces->init_errlog_ptr =
1444                                         le32_to_cpup((__le32 *)tlv_data);
1445                         break;
1446                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1447                         if (tlv_len != sizeof(u32))
1448                                 goto invalid_tlv_len;
1449                         pieces->inst_evtlog_ptr =
1450                                         le32_to_cpup((__le32 *)tlv_data);
1451                         break;
1452                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1453                         if (tlv_len != sizeof(u32))
1454                                 goto invalid_tlv_len;
1455                         pieces->inst_evtlog_size =
1456                                         le32_to_cpup((__le32 *)tlv_data);
1457                         break;
1458                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1459                         if (tlv_len != sizeof(u32))
1460                                 goto invalid_tlv_len;
1461                         pieces->inst_errlog_ptr =
1462                                         le32_to_cpup((__le32 *)tlv_data);
1463                         break;
1464                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1465                         if (tlv_len)
1466                                 goto invalid_tlv_len;
1467                         priv->enhance_sensitivity_table = true;
1468                         break;
1469                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1470                         if (tlv_len != sizeof(u32))
1471                                 goto invalid_tlv_len;
1472                         capa->standard_phy_calibration_size =
1473                                         le32_to_cpup((__le32 *)tlv_data);
1474                         break;
1475                 default:
1476                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1477                         break;
1478                 }
1479         }
1480
1481         if (len) {
1482                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1483                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1484                 return -EINVAL;
1485         }
1486
1487         return 0;
1488
1489  invalid_tlv_len:
1490         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1491         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1492
1493         return -EINVAL;
1494 }
1495
1496 /**
1497  * iwl_ucode_callback - callback when firmware was loaded
1498  *
1499  * If loaded successfully, copies the firmware into buffers
1500  * for the card to fetch (via DMA).
1501  */
1502 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1503 {
1504         struct iwl_priv *priv = context;
1505         struct iwl_ucode_header *ucode;
1506         int err;
1507         struct iwlagn_firmware_pieces pieces;
1508         const unsigned int api_max = priv->cfg->ucode_api_max;
1509         const unsigned int api_min = priv->cfg->ucode_api_min;
1510         u32 api_ver;
1511         char buildstr[25];
1512         u32 build;
1513         struct iwlagn_ucode_capabilities ucode_capa = {
1514                 .max_probe_length = 200,
1515                 .standard_phy_calibration_size =
1516                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1517         };
1518
1519         memset(&pieces, 0, sizeof(pieces));
1520
1521         if (!ucode_raw) {
1522                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1523                         IWL_ERR(priv,
1524                                 "request for firmware file '%s' failed.\n",
1525                                 priv->firmware_name);
1526                 goto try_again;
1527         }
1528
1529         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1530                        priv->firmware_name, ucode_raw->size);
1531
1532         /* Make sure that we got at least the API version number */
1533         if (ucode_raw->size < 4) {
1534                 IWL_ERR(priv, "File size way too small!\n");
1535                 goto try_again;
1536         }
1537
1538         /* Data from ucode file:  header followed by uCode images */
1539         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1540
1541         if (ucode->ver)
1542                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1543         else
1544                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1545                                            &ucode_capa);
1546
1547         if (err)
1548                 goto try_again;
1549
1550         api_ver = IWL_UCODE_API(priv->ucode_ver);
1551         build = pieces.build;
1552
1553         /*
1554          * api_ver should match the api version forming part of the
1555          * firmware filename ... but we don't check for that and only rely
1556          * on the API version read from firmware header from here on forward
1557          */
1558         /* no api version check required for experimental uCode */
1559         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1560                 if (api_ver < api_min || api_ver > api_max) {
1561                         IWL_ERR(priv,
1562                                 "Driver unable to support your firmware API. "
1563                                 "Driver supports v%u, firmware is v%u.\n",
1564                                 api_max, api_ver);
1565                         goto try_again;
1566                 }
1567
1568                 if (api_ver != api_max)
1569                         IWL_ERR(priv,
1570                                 "Firmware has old API version. Expected v%u, "
1571                                 "got v%u. New firmware can be obtained "
1572                                 "from http://www.intellinuxwireless.org.\n",
1573                                 api_max, api_ver);
1574         }
1575
1576         if (build)
1577                 sprintf(buildstr, " build %u%s", build,
1578                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1579                                 ? " (EXP)" : "");
1580         else
1581                 buildstr[0] = '\0';
1582
1583         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1584                  IWL_UCODE_MAJOR(priv->ucode_ver),
1585                  IWL_UCODE_MINOR(priv->ucode_ver),
1586                  IWL_UCODE_API(priv->ucode_ver),
1587                  IWL_UCODE_SERIAL(priv->ucode_ver),
1588                  buildstr);
1589
1590         snprintf(priv->hw->wiphy->fw_version,
1591                  sizeof(priv->hw->wiphy->fw_version),
1592                  "%u.%u.%u.%u%s",
1593                  IWL_UCODE_MAJOR(priv->ucode_ver),
1594                  IWL_UCODE_MINOR(priv->ucode_ver),
1595                  IWL_UCODE_API(priv->ucode_ver),
1596                  IWL_UCODE_SERIAL(priv->ucode_ver),
1597                  buildstr);
1598
1599         /*
1600          * For any of the failures below (before allocating pci memory)
1601          * we will try to load a version with a smaller API -- maybe the
1602          * user just got a corrupted version of the latest API.
1603          */
1604
1605         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1606                        priv->ucode_ver);
1607         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1608                        pieces.inst_size);
1609         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1610                        pieces.data_size);
1611         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1612                        pieces.init_size);
1613         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1614                        pieces.init_data_size);
1615         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
1616                        pieces.boot_size);
1617
1618         /* Verify that uCode images will fit in card's SRAM */
1619         if (pieces.inst_size > priv->hw_params.max_inst_size) {
1620                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1621                         pieces.inst_size);
1622                 goto try_again;
1623         }
1624
1625         if (pieces.data_size > priv->hw_params.max_data_size) {
1626                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1627                         pieces.data_size);
1628                 goto try_again;
1629         }
1630
1631         if (pieces.init_size > priv->hw_params.max_inst_size) {
1632                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1633                         pieces.init_size);
1634                 goto try_again;
1635         }
1636
1637         if (pieces.init_data_size > priv->hw_params.max_data_size) {
1638                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1639                         pieces.init_data_size);
1640                 goto try_again;
1641         }
1642
1643         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
1644                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
1645                         pieces.boot_size);
1646                 goto try_again;
1647         }
1648
1649         /* Allocate ucode buffers for card's bus-master loading ... */
1650
1651         /* Runtime instructions and 2 copies of data:
1652          * 1) unmodified from disk
1653          * 2) backup cache for save/restore during power-downs */
1654         priv->ucode_code.len = pieces.inst_size;
1655         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1656
1657         priv->ucode_data.len = pieces.data_size;
1658         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1659
1660         priv->ucode_data_backup.len = pieces.data_size;
1661         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1662
1663         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1664             !priv->ucode_data_backup.v_addr)
1665                 goto err_pci_alloc;
1666
1667         /* Initialization instructions and data */
1668         if (pieces.init_size && pieces.init_data_size) {
1669                 priv->ucode_init.len = pieces.init_size;
1670                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1671
1672                 priv->ucode_init_data.len = pieces.init_data_size;
1673                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1674
1675                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1676                         goto err_pci_alloc;
1677         }
1678
1679         /* Bootstrap (instructions only, no data) */
1680         if (pieces.boot_size) {
1681                 priv->ucode_boot.len = pieces.boot_size;
1682                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
1683
1684                 if (!priv->ucode_boot.v_addr)
1685                         goto err_pci_alloc;
1686         }
1687
1688         /* Now that we can no longer fail, copy information */
1689
1690         /*
1691          * The (size - 16) / 12 formula is based on the information recorded
1692          * for each event, which is of mode 1 (including timestamp) for all
1693          * new microcodes that include this information.
1694          */
1695         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1696         if (pieces.init_evtlog_size)
1697                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1698         else
1699                 priv->_agn.init_evtlog_size =
1700                         priv->cfg->base_params->max_event_log_size;
1701         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1702         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1703         if (pieces.inst_evtlog_size)
1704                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1705         else
1706                 priv->_agn.inst_evtlog_size =
1707                         priv->cfg->base_params->max_event_log_size;
1708         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1709
1710         if (ucode_capa.pan) {
1711                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1712                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1713         } else
1714                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1715
1716         /* Copy images into buffers for card's bus-master reads ... */
1717
1718         /* Runtime instructions (first block of data in file) */
1719         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1720                         pieces.inst_size);
1721         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1722
1723         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1724                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1725
1726         /*
1727          * Runtime data
1728          * NOTE:  Copy into backup buffer will be done in iwl_up()
1729          */
1730         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1731                         pieces.data_size);
1732         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1733         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
1734
1735         /* Initialization instructions */
1736         if (pieces.init_size) {
1737                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1738                                 pieces.init_size);
1739                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
1740         }
1741
1742         /* Initialization data */
1743         if (pieces.init_data_size) {
1744                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1745                                pieces.init_data_size);
1746                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1747                        pieces.init_data_size);
1748         }
1749
1750         /* Bootstrap instructions */
1751         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
1752                         pieces.boot_size);
1753         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
1754
1755         /*
1756          * figure out the offset of chain noise reset and gain commands
1757          * base on the size of standard phy calibration commands table size
1758          */
1759         if (ucode_capa.standard_phy_calibration_size >
1760             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1761                 ucode_capa.standard_phy_calibration_size =
1762                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1763
1764         priv->_agn.phy_calib_chain_noise_reset_cmd =
1765                 ucode_capa.standard_phy_calibration_size;
1766         priv->_agn.phy_calib_chain_noise_gain_cmd =
1767                 ucode_capa.standard_phy_calibration_size + 1;
1768
1769         /**************************************************
1770          * This is still part of probe() in a sense...
1771          *
1772          * 9. Setup and register with mac80211 and debugfs
1773          **************************************************/
1774         err = iwl_mac_setup_register(priv, &ucode_capa);
1775         if (err)
1776                 goto out_unbind;
1777
1778         err = iwl_dbgfs_register(priv, DRV_NAME);
1779         if (err)
1780                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1781
1782         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1783                                         &iwl_attribute_group);
1784         if (err) {
1785                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1786                 goto out_unbind;
1787         }
1788
1789         /* We have our copies now, allow OS release its copies */
1790         release_firmware(ucode_raw);
1791         complete(&priv->_agn.firmware_loading_complete);
1792         return;
1793
1794  try_again:
1795         /* try next, if any */
1796         if (iwl_request_firmware(priv, false))
1797                 goto out_unbind;
1798         release_firmware(ucode_raw);
1799         return;
1800
1801  err_pci_alloc:
1802         IWL_ERR(priv, "failed to allocate pci memory\n");
1803         iwl_dealloc_ucode_pci(priv);
1804  out_unbind:
1805         complete(&priv->_agn.firmware_loading_complete);
1806         device_release_driver(&priv->pci_dev->dev);
1807         release_firmware(ucode_raw);
1808 }
1809
1810 static const char *desc_lookup_text[] = {
1811         "OK",
1812         "FAIL",
1813         "BAD_PARAM",
1814         "BAD_CHECKSUM",
1815         "NMI_INTERRUPT_WDG",
1816         "SYSASSERT",
1817         "FATAL_ERROR",
1818         "BAD_COMMAND",
1819         "HW_ERROR_TUNE_LOCK",
1820         "HW_ERROR_TEMPERATURE",
1821         "ILLEGAL_CHAN_FREQ",
1822         "VCC_NOT_STABLE",
1823         "FH_ERROR",
1824         "NMI_INTERRUPT_HOST",
1825         "NMI_INTERRUPT_ACTION_PT",
1826         "NMI_INTERRUPT_UNKNOWN",
1827         "UCODE_VERSION_MISMATCH",
1828         "HW_ERROR_ABS_LOCK",
1829         "HW_ERROR_CAL_LOCK_FAIL",
1830         "NMI_INTERRUPT_INST_ACTION_PT",
1831         "NMI_INTERRUPT_DATA_ACTION_PT",
1832         "NMI_TRM_HW_ER",
1833         "NMI_INTERRUPT_TRM",
1834         "NMI_INTERRUPT_BREAK_POINT"
1835         "DEBUG_0",
1836         "DEBUG_1",
1837         "DEBUG_2",
1838         "DEBUG_3",
1839 };
1840
1841 static struct { char *name; u8 num; } advanced_lookup[] = {
1842         { "NMI_INTERRUPT_WDG", 0x34 },
1843         { "SYSASSERT", 0x35 },
1844         { "UCODE_VERSION_MISMATCH", 0x37 },
1845         { "BAD_COMMAND", 0x38 },
1846         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1847         { "FATAL_ERROR", 0x3D },
1848         { "NMI_TRM_HW_ERR", 0x46 },
1849         { "NMI_INTERRUPT_TRM", 0x4C },
1850         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1851         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1852         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1853         { "NMI_INTERRUPT_HOST", 0x66 },
1854         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1855         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1856         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1857         { "ADVANCED_SYSASSERT", 0 },
1858 };
1859
1860 static const char *desc_lookup(u32 num)
1861 {
1862         int i;
1863         int max = ARRAY_SIZE(desc_lookup_text);
1864
1865         if (num < max)
1866                 return desc_lookup_text[num];
1867
1868         max = ARRAY_SIZE(advanced_lookup) - 1;
1869         for (i = 0; i < max; i++) {
1870                 if (advanced_lookup[i].num == num)
1871                         break;;
1872         }
1873         return advanced_lookup[i].name;
1874 }
1875
1876 #define ERROR_START_OFFSET  (1 * sizeof(u32))
1877 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
1878
1879 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1880 {
1881         u32 data2, line;
1882         u32 desc, time, count, base, data1;
1883         u32 blink1, blink2, ilink1, ilink2;
1884         u32 pc, hcmd;
1885
1886         if (priv->ucode_type == UCODE_INIT) {
1887                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1888                 if (!base)
1889                         base = priv->_agn.init_errlog_ptr;
1890         } else {
1891                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1892                 if (!base)
1893                         base = priv->_agn.inst_errlog_ptr;
1894         }
1895
1896         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1897                 IWL_ERR(priv,
1898                         "Not valid error log pointer 0x%08X for %s uCode\n",
1899                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
1900                 return;
1901         }
1902
1903         count = iwl_read_targ_mem(priv, base);
1904
1905         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1906                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1907                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1908                         priv->status, count);
1909         }
1910
1911         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1912         priv->isr_stats.err_code = desc;
1913         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
1914         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1915         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1916         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1917         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1918         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1919         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1920         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1921         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1922         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
1923
1924         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1925                                       blink1, blink2, ilink1, ilink2);
1926
1927         IWL_ERR(priv, "Desc                                  Time       "
1928                 "data1      data2      line\n");
1929         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1930                 desc_lookup(desc), desc, time, data1, data2, line);
1931         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
1932         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1933                 pc, blink1, blink2, ilink1, ilink2, hcmd);
1934 }
1935
1936 #define EVENT_START_OFFSET  (4 * sizeof(u32))
1937
1938 /**
1939  * iwl_print_event_log - Dump error event log to syslog
1940  *
1941  */
1942 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1943                                u32 num_events, u32 mode,
1944                                int pos, char **buf, size_t bufsz)
1945 {
1946         u32 i;
1947         u32 base;       /* SRAM byte address of event log header */
1948         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1949         u32 ptr;        /* SRAM byte address of log data */
1950         u32 ev, time, data; /* event log data */
1951         unsigned long reg_flags;
1952
1953         if (num_events == 0)
1954                 return pos;
1955
1956         if (priv->ucode_type == UCODE_INIT) {
1957                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1958                 if (!base)
1959                         base = priv->_agn.init_evtlog_ptr;
1960         } else {
1961                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1962                 if (!base)
1963                         base = priv->_agn.inst_evtlog_ptr;
1964         }
1965
1966         if (mode == 0)
1967                 event_size = 2 * sizeof(u32);
1968         else
1969                 event_size = 3 * sizeof(u32);
1970
1971         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1972
1973         /* Make sure device is powered up for SRAM reads */
1974         spin_lock_irqsave(&priv->reg_lock, reg_flags);
1975         iwl_grab_nic_access(priv);
1976
1977         /* Set starting address; reads will auto-increment */
1978         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1979         rmb();
1980
1981         /* "time" is actually "data" for mode 0 (no timestamp).
1982         * place event id # at far right for easier visual parsing. */
1983         for (i = 0; i < num_events; i++) {
1984                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1985                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1986                 if (mode == 0) {
1987                         /* data, ev */
1988                         if (bufsz) {
1989                                 pos += scnprintf(*buf + pos, bufsz - pos,
1990                                                 "EVT_LOG:0x%08x:%04u\n",
1991                                                 time, ev);
1992                         } else {
1993                                 trace_iwlwifi_dev_ucode_event(priv, 0,
1994                                         time, ev);
1995                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1996                                         time, ev);
1997                         }
1998                 } else {
1999                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2000                         if (bufsz) {
2001                                 pos += scnprintf(*buf + pos, bufsz - pos,
2002                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2003                                                  time, data, ev);
2004                         } else {
2005                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2006                                         time, data, ev);
2007                                 trace_iwlwifi_dev_ucode_event(priv, time,
2008                                         data, ev);
2009                         }
2010                 }
2011         }
2012
2013         /* Allow device to power down */
2014         iwl_release_nic_access(priv);
2015         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2016         return pos;
2017 }
2018
2019 /**
2020  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2021  */
2022 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2023                                     u32 num_wraps, u32 next_entry,
2024                                     u32 size, u32 mode,
2025                                     int pos, char **buf, size_t bufsz)
2026 {
2027         /*
2028          * display the newest DEFAULT_LOG_ENTRIES entries
2029          * i.e the entries just before the next ont that uCode would fill.
2030          */
2031         if (num_wraps) {
2032                 if (next_entry < size) {
2033                         pos = iwl_print_event_log(priv,
2034                                                 capacity - (size - next_entry),
2035                                                 size - next_entry, mode,
2036                                                 pos, buf, bufsz);
2037                         pos = iwl_print_event_log(priv, 0,
2038                                                   next_entry, mode,
2039                                                   pos, buf, bufsz);
2040                 } else
2041                         pos = iwl_print_event_log(priv, next_entry - size,
2042                                                   size, mode, pos, buf, bufsz);
2043         } else {
2044                 if (next_entry < size) {
2045                         pos = iwl_print_event_log(priv, 0, next_entry,
2046                                                   mode, pos, buf, bufsz);
2047                 } else {
2048                         pos = iwl_print_event_log(priv, next_entry - size,
2049                                                   size, mode, pos, buf, bufsz);
2050                 }
2051         }
2052         return pos;
2053 }
2054
2055 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2056
2057 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2058                             char **buf, bool display)
2059 {
2060         u32 base;       /* SRAM byte address of event log header */
2061         u32 capacity;   /* event log capacity in # entries */
2062         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2063         u32 num_wraps;  /* # times uCode wrapped to top of log */
2064         u32 next_entry; /* index of next entry to be written by uCode */
2065         u32 size;       /* # entries that we'll print */
2066         u32 logsize;
2067         int pos = 0;
2068         size_t bufsz = 0;
2069
2070         if (priv->ucode_type == UCODE_INIT) {
2071                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2072                 logsize = priv->_agn.init_evtlog_size;
2073                 if (!base)
2074                         base = priv->_agn.init_evtlog_ptr;
2075         } else {
2076                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2077                 logsize = priv->_agn.inst_evtlog_size;
2078                 if (!base)
2079                         base = priv->_agn.inst_evtlog_ptr;
2080         }
2081
2082         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2083                 IWL_ERR(priv,
2084                         "Invalid event log pointer 0x%08X for %s uCode\n",
2085                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2086                 return -EINVAL;
2087         }
2088
2089         /* event log header */
2090         capacity = iwl_read_targ_mem(priv, base);
2091         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2092         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2093         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2094
2095         if (capacity > logsize) {
2096                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2097                         capacity, logsize);
2098                 capacity = logsize;
2099         }
2100
2101         if (next_entry > logsize) {
2102                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2103                         next_entry, logsize);
2104                 next_entry = logsize;
2105         }
2106
2107         size = num_wraps ? capacity : next_entry;
2108
2109         /* bail out if nothing in log */
2110         if (size == 0) {
2111                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2112                 return pos;
2113         }
2114
2115         /* enable/disable bt channel inhibition */
2116         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2117
2118 #ifdef CONFIG_IWLWIFI_DEBUG
2119         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2120                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2121                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2122 #else
2123         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2124                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2125 #endif
2126         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2127                 size);
2128
2129 #ifdef CONFIG_IWLWIFI_DEBUG
2130         if (display) {
2131                 if (full_log)
2132                         bufsz = capacity * 48;
2133                 else
2134                         bufsz = size * 48;
2135                 *buf = kmalloc(bufsz, GFP_KERNEL);
2136                 if (!*buf)
2137                         return -ENOMEM;
2138         }
2139         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2140                 /*
2141                  * if uCode has wrapped back to top of log,
2142                  * start at the oldest entry,
2143                  * i.e the next one that uCode would fill.
2144                  */
2145                 if (num_wraps)
2146                         pos = iwl_print_event_log(priv, next_entry,
2147                                                 capacity - next_entry, mode,
2148                                                 pos, buf, bufsz);
2149                 /* (then/else) start at top of log */
2150                 pos = iwl_print_event_log(priv, 0,
2151                                           next_entry, mode, pos, buf, bufsz);
2152         } else
2153                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2154                                                 next_entry, size, mode,
2155                                                 pos, buf, bufsz);
2156 #else
2157         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2158                                         next_entry, size, mode,
2159                                         pos, buf, bufsz);
2160 #endif
2161         return pos;
2162 }
2163
2164 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2165 {
2166         struct iwl_ct_kill_config cmd;
2167         struct iwl_ct_kill_throttling_config adv_cmd;
2168         unsigned long flags;
2169         int ret = 0;
2170
2171         spin_lock_irqsave(&priv->lock, flags);
2172         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2173                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2174         spin_unlock_irqrestore(&priv->lock, flags);
2175         priv->thermal_throttle.ct_kill_toggle = false;
2176
2177         if (priv->cfg->base_params->support_ct_kill_exit) {
2178                 adv_cmd.critical_temperature_enter =
2179                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2180                 adv_cmd.critical_temperature_exit =
2181                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2182
2183                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2184                                        sizeof(adv_cmd), &adv_cmd);
2185                 if (ret)
2186                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2187                 else
2188                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2189                                         "succeeded, "
2190                                         "critical temperature enter is %d,"
2191                                         "exit is %d\n",
2192                                        priv->hw_params.ct_kill_threshold,
2193                                        priv->hw_params.ct_kill_exit_threshold);
2194         } else {
2195                 cmd.critical_temperature_R =
2196                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2197
2198                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2199                                        sizeof(cmd), &cmd);
2200                 if (ret)
2201                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2202                 else
2203                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2204                                         "succeeded, "
2205                                         "critical temperature is %d\n",
2206                                         priv->hw_params.ct_kill_threshold);
2207         }
2208 }
2209
2210 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2211 {
2212         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2213         struct iwl_host_cmd cmd = {
2214                 .id = CALIBRATION_CFG_CMD,
2215                 .len = sizeof(struct iwl_calib_cfg_cmd),
2216                 .data = &calib_cfg_cmd,
2217         };
2218
2219         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2220         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2221         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2222
2223         return iwl_send_cmd(priv, &cmd);
2224 }
2225
2226
2227 /**
2228  * iwl_alive_start - called after REPLY_ALIVE notification received
2229  *                   from protocol/runtime uCode (initialization uCode's
2230  *                   Alive gets handled by iwl_init_alive_start()).
2231  */
2232 static void iwl_alive_start(struct iwl_priv *priv)
2233 {
2234         int ret = 0;
2235         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2236
2237         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2238
2239         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2240          * This is a paranoid check, because we would not have gotten the
2241          * "runtime" alive if code weren't properly loaded.  */
2242         if (iwl_verify_ucode(priv)) {
2243                 /* Runtime instruction load was bad;
2244                  * take it all the way back down so we can try again */
2245                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2246                 goto restart;
2247         }
2248
2249         ret = priv->cfg->ops->lib->alive_notify(priv);
2250         if (ret) {
2251                 IWL_WARN(priv,
2252                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2253                 goto restart;
2254         }
2255
2256
2257         /* After the ALIVE response, we can send host commands to the uCode */
2258         set_bit(STATUS_ALIVE, &priv->status);
2259
2260         /* Enable watchdog to monitor the driver tx queues */
2261         iwl_setup_watchdog(priv);
2262
2263         if (iwl_is_rfkill(priv))
2264                 return;
2265
2266         /* download priority table before any calibration request */
2267         if (priv->cfg->bt_params &&
2268             priv->cfg->bt_params->advanced_bt_coexist) {
2269                 /* Configure Bluetooth device coexistence support */
2270                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2271                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2272                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2273                 priv->cfg->ops->hcmd->send_bt_config(priv);
2274                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2275                 iwlagn_send_prio_tbl(priv);
2276
2277                 /* FIXME: w/a to force change uCode BT state machine */
2278                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2279                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2280                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2281                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2282         }
2283         if (priv->hw_params.calib_rt_cfg)
2284                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2285
2286         ieee80211_wake_queues(priv->hw);
2287
2288         priv->active_rate = IWL_RATES_MASK;
2289
2290         /* Configure Tx antenna selection based on H/W config */
2291         if (priv->cfg->ops->hcmd->set_tx_ant)
2292                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2293
2294         if (iwl_is_associated_ctx(ctx)) {
2295                 struct iwl_rxon_cmd *active_rxon =
2296                                 (struct iwl_rxon_cmd *)&ctx->active;
2297                 /* apply any changes in staging */
2298                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2299                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2300         } else {
2301                 struct iwl_rxon_context *tmp;
2302                 /* Initialize our rx_config data */
2303                 for_each_context(priv, tmp)
2304                         iwl_connection_init_rx_config(priv, tmp);
2305
2306                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2307                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2308         }
2309
2310         if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2311             !priv->cfg->bt_params->advanced_bt_coexist)) {
2312                 /*
2313                  * default is 2-wire BT coexexistence support
2314                  */
2315                 priv->cfg->ops->hcmd->send_bt_config(priv);
2316         }
2317
2318         iwl_reset_run_time_calib(priv);
2319
2320         set_bit(STATUS_READY, &priv->status);
2321
2322         /* Configure the adapter for unassociated operation */
2323         iwlcore_commit_rxon(priv, ctx);
2324
2325         /* At this point, the NIC is initialized and operational */
2326         iwl_rf_kill_ct_config(priv);
2327
2328         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2329         wake_up_interruptible(&priv->wait_command_queue);
2330
2331         iwl_power_update_mode(priv, true);
2332         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2333
2334
2335         return;
2336
2337  restart:
2338         queue_work(priv->workqueue, &priv->restart);
2339 }
2340
2341 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2342
2343 static void __iwl_down(struct iwl_priv *priv)
2344 {
2345         unsigned long flags;
2346         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2347
2348         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2349
2350         iwl_scan_cancel_timeout(priv, 200);
2351
2352         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2353
2354         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2355          * to prevent rearm timer */
2356         del_timer_sync(&priv->watchdog);
2357
2358         iwl_clear_ucode_stations(priv, NULL);
2359         iwl_dealloc_bcast_stations(priv);
2360         iwl_clear_driver_stations(priv);
2361
2362         /* reset BT coex data */
2363         priv->bt_status = 0;
2364         if (priv->cfg->bt_params)
2365                 priv->bt_traffic_load =
2366                          priv->cfg->bt_params->bt_init_traffic_load;
2367         else
2368                 priv->bt_traffic_load = 0;
2369         priv->bt_full_concurrent = false;
2370         priv->bt_ci_compliance = 0;
2371
2372         /* Unblock any waiting calls */
2373         wake_up_interruptible_all(&priv->wait_command_queue);
2374
2375         /* Wipe out the EXIT_PENDING status bit if we are not actually
2376          * exiting the module */
2377         if (!exit_pending)
2378                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2379
2380         /* stop and reset the on-board processor */
2381         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2382
2383         /* tell the device to stop sending interrupts */
2384         spin_lock_irqsave(&priv->lock, flags);
2385         iwl_disable_interrupts(priv);
2386         spin_unlock_irqrestore(&priv->lock, flags);
2387         iwl_synchronize_irq(priv);
2388
2389         if (priv->mac80211_registered)
2390                 ieee80211_stop_queues(priv->hw);
2391
2392         /* If we have not previously called iwl_init() then
2393          * clear all bits but the RF Kill bit and return */
2394         if (!iwl_is_init(priv)) {
2395                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2396                                         STATUS_RF_KILL_HW |
2397                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2398                                         STATUS_GEO_CONFIGURED |
2399                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2400                                         STATUS_EXIT_PENDING;
2401                 goto exit;
2402         }
2403
2404         /* ...otherwise clear out all the status bits but the RF Kill
2405          * bit and continue taking the NIC down. */
2406         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2407                                 STATUS_RF_KILL_HW |
2408                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2409                                 STATUS_GEO_CONFIGURED |
2410                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2411                                 STATUS_FW_ERROR |
2412                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2413                                 STATUS_EXIT_PENDING;
2414
2415         /* device going down, Stop using ICT table */
2416         if (priv->cfg->ops->lib->isr_ops.disable)
2417                 priv->cfg->ops->lib->isr_ops.disable(priv);
2418
2419         iwlagn_txq_ctx_stop(priv);
2420         iwlagn_rxq_stop(priv);
2421
2422         /* Power-down device's busmaster DMA clocks */
2423         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2424         udelay(5);
2425
2426         /* Make sure (redundant) we've released our request to stay awake */
2427         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2428
2429         /* Stop the device, and put it in low power state */
2430         iwl_apm_stop(priv);
2431
2432  exit:
2433         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2434
2435         dev_kfree_skb(priv->beacon_skb);
2436         priv->beacon_skb = NULL;
2437
2438         /* clear out any free frames */
2439         iwl_clear_free_frames(priv);
2440 }
2441
2442 static void iwl_down(struct iwl_priv *priv)
2443 {
2444         mutex_lock(&priv->mutex);
2445         __iwl_down(priv);
2446         mutex_unlock(&priv->mutex);
2447
2448         iwl_cancel_deferred_work(priv);
2449 }
2450
2451 #define HW_READY_TIMEOUT (50)
2452
2453 static int iwl_set_hw_ready(struct iwl_priv *priv)
2454 {
2455         int ret = 0;
2456
2457         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2458                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2459
2460         /* See if we got it */
2461         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2462                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2463                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2464                                 HW_READY_TIMEOUT);
2465         if (ret != -ETIMEDOUT)
2466                 priv->hw_ready = true;
2467         else
2468                 priv->hw_ready = false;
2469
2470         IWL_DEBUG_INFO(priv, "hardware %s\n",
2471                       (priv->hw_ready == 1) ? "ready" : "not ready");
2472         return ret;
2473 }
2474
2475 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2476 {
2477         int ret = 0;
2478
2479         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2480
2481         ret = iwl_set_hw_ready(priv);
2482         if (priv->hw_ready)
2483                 return ret;
2484
2485         /* If HW is not ready, prepare the conditions to check again */
2486         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2487                         CSR_HW_IF_CONFIG_REG_PREPARE);
2488
2489         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2490                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2491                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2492
2493         /* HW should be ready by now, check again. */
2494         if (ret != -ETIMEDOUT)
2495                 iwl_set_hw_ready(priv);
2496
2497         return ret;
2498 }
2499
2500 #define MAX_HW_RESTARTS 5
2501
2502 static int __iwl_up(struct iwl_priv *priv)
2503 {
2504         struct iwl_rxon_context *ctx;
2505         int i;
2506         int ret;
2507
2508         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2509                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2510                 return -EIO;
2511         }
2512
2513         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2514                 IWL_ERR(priv, "ucode not available for device bringup\n");
2515                 return -EIO;
2516         }
2517
2518         for_each_context(priv, ctx) {
2519                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2520                 if (ret) {
2521                         iwl_dealloc_bcast_stations(priv);
2522                         return ret;
2523                 }
2524         }
2525
2526         iwl_prepare_card_hw(priv);
2527
2528         if (!priv->hw_ready) {
2529                 IWL_WARN(priv, "Exit HW not ready\n");
2530                 return -EIO;
2531         }
2532
2533         /* If platform's RF_KILL switch is NOT set to KILL */
2534         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2535                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2536         else
2537                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2538
2539         if (iwl_is_rfkill(priv)) {
2540                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2541
2542                 iwl_enable_interrupts(priv);
2543                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2544                 return 0;
2545         }
2546
2547         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2548
2549         /* must be initialised before iwl_hw_nic_init */
2550         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2551                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2552         else
2553                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2554
2555         ret = iwlagn_hw_nic_init(priv);
2556         if (ret) {
2557                 IWL_ERR(priv, "Unable to init nic\n");
2558                 return ret;
2559         }
2560
2561         /* make sure rfkill handshake bits are cleared */
2562         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2563         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2564                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2565
2566         /* clear (again), then enable host interrupts */
2567         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2568         iwl_enable_interrupts(priv);
2569
2570         /* really make sure rfkill handshake bits are cleared */
2571         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2572         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2573
2574         /* Copy original ucode data image from disk into backup cache.
2575          * This will be used to initialize the on-board processor's
2576          * data SRAM for a clean start when the runtime program first loads. */
2577         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2578                priv->ucode_data.len);
2579
2580         for (i = 0; i < MAX_HW_RESTARTS; i++) {
2581
2582                 /* load bootstrap state machine,
2583                  * load bootstrap program into processor's memory,
2584                  * prepare to load the "initialize" uCode */
2585                 ret = priv->cfg->ops->lib->load_ucode(priv);
2586
2587                 if (ret) {
2588                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2589                                 ret);
2590                         continue;
2591                 }
2592
2593                 /* start card; "initialize" will load runtime ucode */
2594                 iwl_nic_start(priv);
2595
2596                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2597
2598                 return 0;
2599         }
2600
2601         set_bit(STATUS_EXIT_PENDING, &priv->status);
2602         __iwl_down(priv);
2603         clear_bit(STATUS_EXIT_PENDING, &priv->status);
2604
2605         /* tried to restart and config the device for as long as our
2606          * patience could withstand */
2607         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2608         return -EIO;
2609 }
2610
2611
2612 /*****************************************************************************
2613  *
2614  * Workqueue callbacks
2615  *
2616  *****************************************************************************/
2617
2618 static void iwl_bg_init_alive_start(struct work_struct *data)
2619 {
2620         struct iwl_priv *priv =
2621             container_of(data, struct iwl_priv, init_alive_start.work);
2622
2623         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2624                 return;
2625
2626         mutex_lock(&priv->mutex);
2627         priv->cfg->ops->lib->init_alive_start(priv);
2628         mutex_unlock(&priv->mutex);
2629 }
2630
2631 static void iwl_bg_alive_start(struct work_struct *data)
2632 {
2633         struct iwl_priv *priv =
2634             container_of(data, struct iwl_priv, alive_start.work);
2635
2636         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2637                 return;
2638
2639         /* enable dram interrupt */
2640         if (priv->cfg->ops->lib->isr_ops.reset)
2641                 priv->cfg->ops->lib->isr_ops.reset(priv);
2642
2643         mutex_lock(&priv->mutex);
2644         iwl_alive_start(priv);
2645         mutex_unlock(&priv->mutex);
2646 }
2647
2648 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2649 {
2650         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2651                         run_time_calib_work);
2652
2653         mutex_lock(&priv->mutex);
2654
2655         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2656             test_bit(STATUS_SCANNING, &priv->status)) {
2657                 mutex_unlock(&priv->mutex);
2658                 return;
2659         }
2660
2661         if (priv->start_calib) {
2662                 if (iwl_bt_statistics(priv)) {
2663                         iwl_chain_noise_calibration(priv,
2664                                         (void *)&priv->_agn.statistics_bt);
2665                         iwl_sensitivity_calibration(priv,
2666                                         (void *)&priv->_agn.statistics_bt);
2667                 } else {
2668                         iwl_chain_noise_calibration(priv,
2669                                         (void *)&priv->_agn.statistics);
2670                         iwl_sensitivity_calibration(priv,
2671                                         (void *)&priv->_agn.statistics);
2672                 }
2673         }
2674
2675         mutex_unlock(&priv->mutex);
2676 }
2677
2678 static void iwl_bg_restart(struct work_struct *data)
2679 {
2680         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2681
2682         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2683                 return;
2684
2685         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2686                 struct iwl_rxon_context *ctx;
2687                 bool bt_full_concurrent;
2688                 u8 bt_ci_compliance;
2689                 u8 bt_load;
2690                 u8 bt_status;
2691
2692                 mutex_lock(&priv->mutex);
2693                 for_each_context(priv, ctx)
2694                         ctx->vif = NULL;
2695                 priv->is_open = 0;
2696
2697                 /*
2698                  * __iwl_down() will clear the BT status variables,
2699                  * which is correct, but when we restart we really
2700                  * want to keep them so restore them afterwards.
2701                  *
2702                  * The restart process will later pick them up and
2703                  * re-configure the hw when we reconfigure the BT
2704                  * command.
2705                  */
2706                 bt_full_concurrent = priv->bt_full_concurrent;
2707                 bt_ci_compliance = priv->bt_ci_compliance;
2708                 bt_load = priv->bt_traffic_load;
2709                 bt_status = priv->bt_status;
2710
2711                 __iwl_down(priv);
2712
2713                 priv->bt_full_concurrent = bt_full_concurrent;
2714                 priv->bt_ci_compliance = bt_ci_compliance;
2715                 priv->bt_traffic_load = bt_load;
2716                 priv->bt_status = bt_status;
2717
2718                 mutex_unlock(&priv->mutex);
2719                 iwl_cancel_deferred_work(priv);
2720                 ieee80211_restart_hw(priv->hw);
2721         } else {
2722                 iwl_down(priv);
2723
2724                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2725                         return;
2726
2727                 mutex_lock(&priv->mutex);
2728                 __iwl_up(priv);
2729                 mutex_unlock(&priv->mutex);
2730         }
2731 }
2732
2733 static void iwl_bg_rx_replenish(struct work_struct *data)
2734 {
2735         struct iwl_priv *priv =
2736             container_of(data, struct iwl_priv, rx_replenish);
2737
2738         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2739                 return;
2740
2741         mutex_lock(&priv->mutex);
2742         iwlagn_rx_replenish(priv);
2743         mutex_unlock(&priv->mutex);
2744 }
2745
2746 static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2747                                  struct ieee80211_channel *chan,
2748                                  enum nl80211_channel_type channel_type,
2749                                  unsigned int wait)
2750 {
2751         struct iwl_priv *priv = hw->priv;
2752         int ret;
2753
2754         /* Not supported if we don't have PAN */
2755         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2756                 ret = -EOPNOTSUPP;
2757                 goto free;
2758         }
2759
2760         /* Not supported on pre-P2P firmware */
2761         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2762                                         BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2763                 ret = -EOPNOTSUPP;
2764                 goto free;
2765         }
2766
2767         mutex_lock(&priv->mutex);
2768
2769         if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2770                 /*
2771                  * If the PAN context is free, use the normal
2772                  * way of doing remain-on-channel offload + TX.
2773                  */
2774                 ret = 1;
2775                 goto out;
2776         }
2777
2778         /* TODO: queue up if scanning? */
2779         if (test_bit(STATUS_SCANNING, &priv->status) ||
2780             priv->_agn.offchan_tx_skb) {
2781                 ret = -EBUSY;
2782                 goto out;
2783         }
2784
2785         /*
2786          * max_scan_ie_len doesn't include the blank SSID or the header,
2787          * so need to add that again here.
2788          */
2789         if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2790                 ret = -ENOBUFS;
2791                 goto out;
2792         }
2793
2794         priv->_agn.offchan_tx_skb = skb;
2795         priv->_agn.offchan_tx_timeout = wait;
2796         priv->_agn.offchan_tx_chan = chan;
2797
2798         ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2799                                 IWL_SCAN_OFFCH_TX, chan->band);
2800         if (ret)
2801                 priv->_agn.offchan_tx_skb = NULL;
2802  out:
2803         mutex_unlock(&priv->mutex);
2804  free:
2805         if (ret < 0)
2806                 kfree_skb(skb);
2807
2808         return ret;
2809 }
2810
2811 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2812 {
2813         struct iwl_priv *priv = hw->priv;
2814         int ret;
2815
2816         mutex_lock(&priv->mutex);
2817
2818         if (!priv->_agn.offchan_tx_skb)
2819                 return -EINVAL;
2820
2821         priv->_agn.offchan_tx_skb = NULL;
2822
2823         ret = iwl_scan_cancel_timeout(priv, 200);
2824         if (ret)
2825                 ret = -EIO;
2826         mutex_unlock(&priv->mutex);
2827
2828         return ret;
2829 }
2830
2831 /*****************************************************************************
2832  *
2833  * mac80211 entry point functions
2834  *
2835  *****************************************************************************/
2836
2837 #define UCODE_READY_TIMEOUT     (4 * HZ)
2838
2839 /*
2840  * Not a mac80211 entry point function, but it fits in with all the
2841  * other mac80211 functions grouped here.
2842  */
2843 static int iwl_mac_setup_register(struct iwl_priv *priv,
2844                                   struct iwlagn_ucode_capabilities *capa)
2845 {
2846         int ret;
2847         struct ieee80211_hw *hw = priv->hw;
2848         struct iwl_rxon_context *ctx;
2849
2850         hw->rate_control_algorithm = "iwl-agn-rs";
2851
2852         /* Tell mac80211 our characteristics */
2853         hw->flags = IEEE80211_HW_SIGNAL_DBM |
2854                     IEEE80211_HW_AMPDU_AGGREGATION |
2855                     IEEE80211_HW_NEED_DTIM_PERIOD |
2856                     IEEE80211_HW_SPECTRUM_MGMT |
2857                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2858
2859         hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2860
2861         if (!priv->cfg->base_params->broken_powersave)
2862                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2863                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2864
2865         if (priv->cfg->sku & IWL_SKU_N)
2866                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2867                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2868
2869         hw->sta_data_size = sizeof(struct iwl_station_priv);
2870         hw->vif_data_size = sizeof(struct iwl_vif_priv);
2871
2872         for_each_context(priv, ctx) {
2873                 hw->wiphy->interface_modes |= ctx->interface_modes;
2874                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2875         }
2876
2877         hw->wiphy->max_remain_on_channel_duration = 1000;
2878
2879         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2880                             WIPHY_FLAG_DISABLE_BEACON_HINTS |
2881                             WIPHY_FLAG_IBSS_RSN;
2882
2883         /*
2884          * For now, disable PS by default because it affects
2885          * RX performance significantly.
2886          */
2887         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2888
2889         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2890         /* we create the 802.11 header and a zero-length SSID element */
2891         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
2892
2893         /* Default value; 4 EDCA QOS priorities */
2894         hw->queues = 4;
2895
2896         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2897
2898         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2899                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2900                         &priv->bands[IEEE80211_BAND_2GHZ];
2901         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2902                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2903                         &priv->bands[IEEE80211_BAND_5GHZ];
2904
2905         iwl_leds_init(priv);
2906
2907         ret = ieee80211_register_hw(priv->hw);
2908         if (ret) {
2909                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2910                 return ret;
2911         }
2912         priv->mac80211_registered = 1;
2913
2914         return 0;
2915 }
2916
2917
2918 int iwlagn_mac_start(struct ieee80211_hw *hw)
2919 {
2920         struct iwl_priv *priv = hw->priv;
2921         int ret;
2922
2923         IWL_DEBUG_MAC80211(priv, "enter\n");
2924
2925         /* we should be verifying the device is ready to be opened */
2926         mutex_lock(&priv->mutex);
2927         ret = __iwl_up(priv);
2928         mutex_unlock(&priv->mutex);
2929
2930         if (ret)
2931                 return ret;
2932
2933         if (iwl_is_rfkill(priv))
2934                 goto out;
2935
2936         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2937
2938         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2939          * mac80211 will not be run successfully. */
2940         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2941                         test_bit(STATUS_READY, &priv->status),
2942                         UCODE_READY_TIMEOUT);
2943         if (!ret) {
2944                 if (!test_bit(STATUS_READY, &priv->status)) {
2945                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2946                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2947                         return -ETIMEDOUT;
2948                 }
2949         }
2950
2951         iwlagn_led_enable(priv);
2952
2953 out:
2954         priv->is_open = 1;
2955         IWL_DEBUG_MAC80211(priv, "leave\n");
2956         return 0;
2957 }
2958
2959 void iwlagn_mac_stop(struct ieee80211_hw *hw)
2960 {
2961         struct iwl_priv *priv = hw->priv;
2962
2963         IWL_DEBUG_MAC80211(priv, "enter\n");
2964
2965         if (!priv->is_open)
2966                 return;
2967
2968         priv->is_open = 0;
2969
2970         iwl_down(priv);
2971
2972         flush_workqueue(priv->workqueue);
2973
2974         /* User space software may expect getting rfkill changes
2975          * even if interface is down */
2976         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2977         iwl_enable_rfkill_int(priv);
2978
2979         IWL_DEBUG_MAC80211(priv, "leave\n");
2980 }
2981
2982 void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2983 {
2984         struct iwl_priv *priv = hw->priv;
2985
2986         IWL_DEBUG_MACDUMP(priv, "enter\n");
2987
2988         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2989                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2990
2991         if (iwlagn_tx_skb(priv, skb))
2992                 dev_kfree_skb_any(skb);
2993
2994         IWL_DEBUG_MACDUMP(priv, "leave\n");
2995 }
2996
2997 void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
2998                                 struct ieee80211_vif *vif,
2999                                 struct ieee80211_key_conf *keyconf,
3000                                 struct ieee80211_sta *sta,
3001                                 u32 iv32, u16 *phase1key)
3002 {
3003         struct iwl_priv *priv = hw->priv;
3004         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3005
3006         IWL_DEBUG_MAC80211(priv, "enter\n");
3007
3008         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3009                             iv32, phase1key);
3010
3011         IWL_DEBUG_MAC80211(priv, "leave\n");
3012 }
3013
3014 int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3015                        struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3016                        struct ieee80211_key_conf *key)
3017 {
3018         struct iwl_priv *priv = hw->priv;
3019         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3020         struct iwl_rxon_context *ctx = vif_priv->ctx;
3021         int ret;
3022         u8 sta_id;
3023         bool is_default_wep_key = false;
3024
3025         IWL_DEBUG_MAC80211(priv, "enter\n");
3026
3027         if (priv->cfg->mod_params->sw_crypto) {
3028                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3029                 return -EOPNOTSUPP;
3030         }
3031
3032         /*
3033          * To support IBSS RSN, don't program group keys in IBSS, the
3034          * hardware will then not attempt to decrypt the frames.
3035          */
3036         if (vif->type == NL80211_IFTYPE_ADHOC &&
3037             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3038                 return -EOPNOTSUPP;
3039
3040         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3041         if (sta_id == IWL_INVALID_STATION)
3042                 return -EINVAL;
3043
3044         mutex_lock(&priv->mutex);
3045         iwl_scan_cancel_timeout(priv, 100);
3046
3047         /*
3048          * If we are getting WEP group key and we didn't receive any key mapping
3049          * so far, we are in legacy wep mode (group key only), otherwise we are
3050          * in 1X mode.
3051          * In legacy wep mode, we use another host command to the uCode.
3052          */
3053         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3054              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3055             !sta) {
3056                 if (cmd == SET_KEY)
3057                         is_default_wep_key = !ctx->key_mapping_keys;
3058                 else
3059                         is_default_wep_key =
3060                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3061         }
3062
3063         switch (cmd) {
3064         case SET_KEY:
3065                 if (is_default_wep_key)
3066                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3067                 else
3068                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3069                                                   key, sta_id);
3070
3071                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3072                 break;
3073         case DISABLE_KEY:
3074                 if (is_default_wep_key)
3075                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3076                 else
3077                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3078
3079                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3080                 break;
3081         default:
3082                 ret = -EINVAL;
3083         }
3084
3085         mutex_unlock(&priv->mutex);
3086         IWL_DEBUG_MAC80211(priv, "leave\n");
3087
3088         return ret;
3089 }
3090
3091 int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3092                             struct ieee80211_vif *vif,
3093                             enum ieee80211_ampdu_mlme_action action,
3094                             struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3095                             u8 buf_size)
3096 {
3097         struct iwl_priv *priv = hw->priv;
3098         int ret = -EINVAL;
3099         struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3100
3101         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3102                      sta->addr, tid);
3103
3104         if (!(priv->cfg->sku & IWL_SKU_N))
3105                 return -EACCES;
3106
3107         mutex_lock(&priv->mutex);
3108
3109         switch (action) {
3110         case IEEE80211_AMPDU_RX_START:
3111                 IWL_DEBUG_HT(priv, "start Rx\n");
3112                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3113                 break;
3114         case IEEE80211_AMPDU_RX_STOP:
3115                 IWL_DEBUG_HT(priv, "stop Rx\n");
3116                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3117                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3118                         ret = 0;
3119                 break;
3120         case IEEE80211_AMPDU_TX_START:
3121                 IWL_DEBUG_HT(priv, "start Tx\n");
3122                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3123                 if (ret == 0) {
3124                         priv->_agn.agg_tids_count++;
3125                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3126                                      priv->_agn.agg_tids_count);
3127                 }
3128                 break;
3129         case IEEE80211_AMPDU_TX_STOP:
3130                 IWL_DEBUG_HT(priv, "stop Tx\n");
3131                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3132                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3133                         priv->_agn.agg_tids_count--;
3134                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3135                                      priv->_agn.agg_tids_count);
3136                 }
3137                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3138                         ret = 0;
3139                 if (priv->cfg->ht_params &&
3140                     priv->cfg->ht_params->use_rts_for_aggregation) {
3141                         struct iwl_station_priv *sta_priv =
3142                                 (void *) sta->drv_priv;
3143                         /*
3144                          * switch off RTS/CTS if it was previously enabled
3145                          */
3146
3147                         sta_priv->lq_sta.lq.general_params.flags &=
3148                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3149                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3150                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3151                 }
3152                 break;
3153         case IEEE80211_AMPDU_TX_OPERATIONAL:
3154                 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
3155
3156                 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
3157
3158                 /*
3159                  * If the limit is 0, then it wasn't initialised yet,
3160                  * use the default. We can do that since we take the
3161                  * minimum below, and we don't want to go above our
3162                  * default due to hardware restrictions.
3163                  */
3164                 if (sta_priv->max_agg_bufsize == 0)
3165                         sta_priv->max_agg_bufsize =
3166                                 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3167
3168                 /*
3169                  * Even though in theory the peer could have different
3170                  * aggregation reorder buffer sizes for different sessions,
3171                  * our ucode doesn't allow for that and has a global limit
3172                  * for each station. Therefore, use the minimum of all the
3173                  * aggregation sessions and our default value.
3174                  */
3175                 sta_priv->max_agg_bufsize =
3176                         min(sta_priv->max_agg_bufsize, buf_size);
3177
3178                 if (priv->cfg->ht_params &&
3179                     priv->cfg->ht_params->use_rts_for_aggregation) {
3180                         /*
3181                          * switch to RTS/CTS if it is the prefer protection
3182                          * method for HT traffic
3183                          */
3184
3185                         sta_priv->lq_sta.lq.general_params.flags |=
3186                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3187                 }
3188
3189                 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3190                         sta_priv->max_agg_bufsize;
3191
3192                 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3193                                 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3194                 ret = 0;
3195                 break;
3196         }
3197         mutex_unlock(&priv->mutex);
3198
3199         return ret;
3200 }
3201
3202 int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3203                        struct ieee80211_vif *vif,
3204                        struct ieee80211_sta *sta)
3205 {
3206         struct iwl_priv *priv = hw->priv;
3207         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3208         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3209         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3210         int ret;
3211         u8 sta_id;
3212
3213         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3214                         sta->addr);
3215         mutex_lock(&priv->mutex);
3216         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3217                         sta->addr);
3218         sta_priv->common.sta_id = IWL_INVALID_STATION;
3219
3220         atomic_set(&sta_priv->pending_frames, 0);
3221         if (vif->type == NL80211_IFTYPE_AP)
3222                 sta_priv->client = true;
3223
3224         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3225                                      is_ap, sta, &sta_id);
3226         if (ret) {
3227                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3228                         sta->addr, ret);
3229                 /* Should we return success if return code is EEXIST ? */
3230                 mutex_unlock(&priv->mutex);
3231                 return ret;
3232         }
3233
3234         sta_priv->common.sta_id = sta_id;
3235
3236         /* Initialize rate scaling */
3237         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3238                        sta->addr);
3239         iwl_rs_rate_init(priv, sta, sta_id);
3240         mutex_unlock(&priv->mutex);
3241
3242         return 0;
3243 }
3244
3245 void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3246                                struct ieee80211_channel_switch *ch_switch)
3247 {
3248         struct iwl_priv *priv = hw->priv;
3249         const struct iwl_channel_info *ch_info;
3250         struct ieee80211_conf *conf = &hw->conf;
3251         struct ieee80211_channel *channel = ch_switch->channel;
3252         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3253         /*
3254          * MULTI-FIXME
3255          * When we add support for multiple interfaces, we need to
3256          * revisit this. The channel switch command in the device
3257          * only affects the BSS context, but what does that really
3258          * mean? And what if we get a CSA on the second interface?
3259          * This needs a lot of work.
3260          */
3261         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3262         u16 ch;
3263         unsigned long flags = 0;
3264
3265         IWL_DEBUG_MAC80211(priv, "enter\n");
3266
3267         if (iwl_is_rfkill(priv))
3268                 goto out_exit;
3269
3270         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3271             test_bit(STATUS_SCANNING, &priv->status))
3272                 goto out_exit;
3273
3274         if (!iwl_is_associated_ctx(ctx))
3275                 goto out_exit;
3276
3277         /* channel switch in progress */
3278         if (priv->switch_rxon.switch_in_progress == true)
3279                 goto out_exit;
3280
3281         mutex_lock(&priv->mutex);
3282         if (priv->cfg->ops->lib->set_channel_switch) {
3283
3284                 ch = channel->hw_value;
3285                 if (le16_to_cpu(ctx->active.channel) != ch) {
3286                         ch_info = iwl_get_channel_info(priv,
3287                                                        channel->band,
3288                                                        ch);
3289                         if (!is_channel_valid(ch_info)) {
3290                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3291                                 goto out;
3292                         }
3293                         spin_lock_irqsave(&priv->lock, flags);
3294
3295                         priv->current_ht_config.smps = conf->smps_mode;
3296
3297                         /* Configure HT40 channels */
3298                         ctx->ht.enabled = conf_is_ht(conf);
3299                         if (ctx->ht.enabled) {
3300                                 if (conf_is_ht40_minus(conf)) {
3301                                         ctx->ht.extension_chan_offset =
3302                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3303                                         ctx->ht.is_40mhz = true;
3304                                 } else if (conf_is_ht40_plus(conf)) {
3305                                         ctx->ht.extension_chan_offset =
3306                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3307                                         ctx->ht.is_40mhz = true;
3308                                 } else {
3309                                         ctx->ht.extension_chan_offset =
3310                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3311                                         ctx->ht.is_40mhz = false;
3312                                 }
3313                         } else
3314                                 ctx->ht.is_40mhz = false;
3315
3316                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3317                                 ctx->staging.flags = 0;
3318
3319                         iwl_set_rxon_channel(priv, channel, ctx);
3320                         iwl_set_rxon_ht(priv, ht_conf);
3321                         iwl_set_flags_for_band(priv, ctx, channel->band,
3322                                                ctx->vif);
3323                         spin_unlock_irqrestore(&priv->lock, flags);
3324
3325                         iwl_set_rate(priv);
3326                         /*
3327                          * at this point, staging_rxon has the
3328                          * configuration for channel switch
3329                          */
3330                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3331                                                                     ch_switch))
3332                                 priv->switch_rxon.switch_in_progress = false;
3333                 }
3334         }
3335 out:
3336         mutex_unlock(&priv->mutex);
3337 out_exit:
3338         if (!priv->switch_rxon.switch_in_progress)
3339                 ieee80211_chswitch_done(ctx->vif, false);
3340         IWL_DEBUG_MAC80211(priv, "leave\n");
3341 }
3342
3343 void iwlagn_configure_filter(struct ieee80211_hw *hw,
3344                              unsigned int changed_flags,
3345                              unsigned int *total_flags,
3346                              u64 multicast)
3347 {
3348         struct iwl_priv *priv = hw->priv;
3349         __le32 filter_or = 0, filter_nand = 0;
3350         struct iwl_rxon_context *ctx;
3351
3352 #define CHK(test, flag) do { \
3353         if (*total_flags & (test))              \
3354                 filter_or |= (flag);            \
3355         else                                    \
3356                 filter_nand |= (flag);          \
3357         } while (0)
3358
3359         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3360                         changed_flags, *total_flags);
3361
3362         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3363         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3364         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3365         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3366
3367 #undef CHK
3368
3369         mutex_lock(&priv->mutex);
3370
3371         for_each_context(priv, ctx) {
3372                 ctx->staging.filter_flags &= ~filter_nand;
3373                 ctx->staging.filter_flags |= filter_or;
3374
3375                 /*
3376                  * Not committing directly because hardware can perform a scan,
3377                  * but we'll eventually commit the filter flags change anyway.
3378                  */
3379         }
3380
3381         mutex_unlock(&priv->mutex);
3382
3383         /*
3384          * Receiving all multicast frames is always enabled by the
3385          * default flags setup in iwl_connection_init_rx_config()
3386          * since we currently do not support programming multicast
3387          * filters into the device.
3388          */
3389         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3390                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3391 }
3392
3393 void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3394 {
3395         struct iwl_priv *priv = hw->priv;
3396
3397         mutex_lock(&priv->mutex);
3398         IWL_DEBUG_MAC80211(priv, "enter\n");
3399
3400         /* do not support "flush" */
3401         if (!priv->cfg->ops->lib->txfifo_flush)
3402                 goto done;
3403
3404         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3405                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3406                 goto done;
3407         }
3408         if (iwl_is_rfkill(priv)) {
3409                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3410                 goto done;
3411         }
3412
3413         /*
3414          * mac80211 will not push any more frames for transmit
3415          * until the flush is completed
3416          */
3417         if (drop) {
3418                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3419                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3420                         IWL_ERR(priv, "flush request fail\n");
3421                         goto done;
3422                 }
3423         }
3424         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3425         iwlagn_wait_tx_queue_empty(priv);
3426 done:
3427         mutex_unlock(&priv->mutex);
3428         IWL_DEBUG_MAC80211(priv, "leave\n");
3429 }
3430
3431 static void iwlagn_disable_roc(struct iwl_priv *priv)
3432 {
3433         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3434         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3435
3436         lockdep_assert_held(&priv->mutex);
3437
3438         if (!ctx->is_active)
3439                 return;
3440
3441         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3442         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3443         iwl_set_rxon_channel(priv, chan, ctx);
3444         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3445
3446         priv->_agn.hw_roc_channel = NULL;
3447
3448         iwlcore_commit_rxon(priv, ctx);
3449
3450         ctx->is_active = false;
3451 }
3452
3453 static void iwlagn_bg_roc_done(struct work_struct *work)
3454 {
3455         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3456                                              _agn.hw_roc_work.work);
3457
3458         mutex_lock(&priv->mutex);
3459         ieee80211_remain_on_channel_expired(priv->hw);
3460         iwlagn_disable_roc(priv);
3461         mutex_unlock(&priv->mutex);
3462 }
3463
3464 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3465                                      struct ieee80211_channel *channel,
3466                                      enum nl80211_channel_type channel_type,
3467                                      int duration)
3468 {
3469         struct iwl_priv *priv = hw->priv;
3470         int err = 0;
3471
3472         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3473                 return -EOPNOTSUPP;
3474
3475         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3476                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3477                 return -EOPNOTSUPP;
3478
3479         mutex_lock(&priv->mutex);
3480
3481         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3482             test_bit(STATUS_SCAN_HW, &priv->status)) {
3483                 err = -EBUSY;
3484                 goto out;
3485         }
3486
3487         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3488         priv->_agn.hw_roc_channel = channel;
3489         priv->_agn.hw_roc_chantype = channel_type;
3490         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3491         iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3492         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3493                            msecs_to_jiffies(duration + 20));
3494
3495         msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3496         ieee80211_ready_on_channel(priv->hw);
3497
3498  out:
3499         mutex_unlock(&priv->mutex);
3500
3501         return err;
3502 }
3503
3504 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3505 {
3506         struct iwl_priv *priv = hw->priv;
3507
3508         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3509                 return -EOPNOTSUPP;
3510
3511         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3512
3513         mutex_lock(&priv->mutex);
3514         iwlagn_disable_roc(priv);
3515         mutex_unlock(&priv->mutex);
3516
3517         return 0;
3518 }
3519
3520 /*****************************************************************************
3521  *
3522  * driver setup and teardown
3523  *
3524  *****************************************************************************/
3525
3526 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3527 {
3528         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3529
3530         init_waitqueue_head(&priv->wait_command_queue);
3531
3532         INIT_WORK(&priv->restart, iwl_bg_restart);
3533         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3534         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3535         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3536         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3537         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3538         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3539         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3540         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3541         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3542
3543         iwl_setup_scan_deferred_work(priv);
3544
3545         if (priv->cfg->ops->lib->setup_deferred_work)
3546                 priv->cfg->ops->lib->setup_deferred_work(priv);
3547
3548         init_timer(&priv->statistics_periodic);
3549         priv->statistics_periodic.data = (unsigned long)priv;
3550         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3551
3552         init_timer(&priv->ucode_trace);
3553         priv->ucode_trace.data = (unsigned long)priv;
3554         priv->ucode_trace.function = iwl_bg_ucode_trace;
3555
3556         init_timer(&priv->watchdog);
3557         priv->watchdog.data = (unsigned long)priv;
3558         priv->watchdog.function = iwl_bg_watchdog;
3559
3560         tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3561                 iwl_irq_tasklet, (unsigned long)priv);
3562 }
3563
3564 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3565 {
3566         if (priv->cfg->ops->lib->cancel_deferred_work)
3567                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3568
3569         cancel_delayed_work_sync(&priv->init_alive_start);
3570         cancel_delayed_work(&priv->alive_start);
3571         cancel_work_sync(&priv->run_time_calib_work);
3572         cancel_work_sync(&priv->beacon_update);
3573
3574         iwl_cancel_scan_deferred_work(priv);
3575
3576         cancel_work_sync(&priv->bt_full_concurrency);
3577         cancel_work_sync(&priv->bt_runtime_config);
3578
3579         del_timer_sync(&priv->statistics_periodic);
3580         del_timer_sync(&priv->ucode_trace);
3581 }
3582
3583 static void iwl_init_hw_rates(struct iwl_priv *priv,
3584                               struct ieee80211_rate *rates)
3585 {
3586         int i;
3587
3588         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3589                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3590                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3591                 rates[i].hw_value_short = i;
3592                 rates[i].flags = 0;
3593                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3594                         /*
3595                          * If CCK != 1M then set short preamble rate flag.
3596                          */
3597                         rates[i].flags |=
3598                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3599                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3600                 }
3601         }
3602 }
3603
3604 static int iwl_init_drv(struct iwl_priv *priv)
3605 {
3606         int ret;
3607
3608         spin_lock_init(&priv->sta_lock);
3609         spin_lock_init(&priv->hcmd_lock);
3610
3611         INIT_LIST_HEAD(&priv->free_frames);
3612
3613         mutex_init(&priv->mutex);
3614         mutex_init(&priv->sync_cmd_mutex);
3615
3616         priv->ieee_channels = NULL;
3617         priv->ieee_rates = NULL;
3618         priv->band = IEEE80211_BAND_2GHZ;
3619
3620         priv->iw_mode = NL80211_IFTYPE_STATION;
3621         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3622         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3623         priv->_agn.agg_tids_count = 0;
3624
3625         /* initialize force reset */
3626         priv->force_reset[IWL_RF_RESET].reset_duration =
3627                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3628         priv->force_reset[IWL_FW_RESET].reset_duration =
3629                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3630
3631         priv->rx_statistics_jiffies = jiffies;
3632
3633         /* Choose which receivers/antennas to use */
3634         if (priv->cfg->ops->hcmd->set_rxon_chain)
3635                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3636                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3637
3638         iwl_init_scan_params(priv);
3639
3640         /* init bt coex */
3641         if (priv->cfg->bt_params &&
3642             priv->cfg->bt_params->advanced_bt_coexist) {
3643                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3644                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3645                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3646                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3647                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3648                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3649         }
3650
3651         /* Set the tx_power_user_lmt to the lowest power level
3652          * this value will get overwritten by channel max power avg
3653          * from eeprom */
3654         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3655         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3656
3657         ret = iwl_init_channel_map(priv);
3658         if (ret) {
3659                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3660                 goto err;
3661         }
3662
3663         ret = iwlcore_init_geos(priv);
3664         if (ret) {
3665                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3666                 goto err_free_channel_map;
3667         }
3668         iwl_init_hw_rates(priv, priv->ieee_rates);
3669
3670         return 0;
3671
3672 err_free_channel_map:
3673         iwl_free_channel_map(priv);
3674 err:
3675         return ret;
3676 }
3677
3678 static void iwl_uninit_drv(struct iwl_priv *priv)
3679 {
3680         iwl_calib_free_results(priv);
3681         iwlcore_free_geos(priv);
3682         iwl_free_channel_map(priv);
3683         kfree(priv->scan_cmd);
3684 }
3685
3686 struct ieee80211_ops iwlagn_hw_ops = {
3687         .tx = iwlagn_mac_tx,
3688         .start = iwlagn_mac_start,
3689         .stop = iwlagn_mac_stop,
3690         .add_interface = iwl_mac_add_interface,
3691         .remove_interface = iwl_mac_remove_interface,
3692         .change_interface = iwl_mac_change_interface,
3693         .config = iwlagn_mac_config,
3694         .configure_filter = iwlagn_configure_filter,
3695         .set_key = iwlagn_mac_set_key,
3696         .update_tkip_key = iwlagn_mac_update_tkip_key,
3697         .conf_tx = iwl_mac_conf_tx,
3698         .bss_info_changed = iwlagn_bss_info_changed,
3699         .ampdu_action = iwlagn_mac_ampdu_action,
3700         .hw_scan = iwl_mac_hw_scan,
3701         .sta_notify = iwlagn_mac_sta_notify,
3702         .sta_add = iwlagn_mac_sta_add,
3703         .sta_remove = iwl_mac_sta_remove,
3704         .channel_switch = iwlagn_mac_channel_switch,
3705         .flush = iwlagn_mac_flush,
3706         .tx_last_beacon = iwl_mac_tx_last_beacon,
3707         .remain_on_channel = iwl_mac_remain_on_channel,
3708         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3709         .offchannel_tx = iwl_mac_offchannel_tx,
3710         .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3711 };
3712
3713 static void iwl_hw_detect(struct iwl_priv *priv)
3714 {
3715         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
3716         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
3717         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
3718         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3719 }
3720
3721 static int iwl_set_hw_params(struct iwl_priv *priv)
3722 {
3723         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3724         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3725         if (priv->cfg->mod_params->amsdu_size_8K)
3726                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3727         else
3728                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3729
3730         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3731
3732         if (priv->cfg->mod_params->disable_11n)
3733                 priv->cfg->sku &= ~IWL_SKU_N;
3734
3735         /* Device-specific setup */
3736         return priv->cfg->ops->lib->set_hw_params(priv);
3737 }
3738
3739 static const u8 iwlagn_bss_ac_to_fifo[] = {
3740         IWL_TX_FIFO_VO,
3741         IWL_TX_FIFO_VI,
3742         IWL_TX_FIFO_BE,
3743         IWL_TX_FIFO_BK,
3744 };
3745
3746 static const u8 iwlagn_bss_ac_to_queue[] = {
3747         0, 1, 2, 3,
3748 };
3749
3750 static const u8 iwlagn_pan_ac_to_fifo[] = {
3751         IWL_TX_FIFO_VO_IPAN,
3752         IWL_TX_FIFO_VI_IPAN,
3753         IWL_TX_FIFO_BE_IPAN,
3754         IWL_TX_FIFO_BK_IPAN,
3755 };
3756
3757 static const u8 iwlagn_pan_ac_to_queue[] = {
3758         7, 6, 5, 4,
3759 };
3760
3761 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3762 {
3763         int err = 0, i;
3764         struct iwl_priv *priv;
3765         struct ieee80211_hw *hw;
3766         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3767         unsigned long flags;
3768         u16 pci_cmd, num_mac;
3769
3770         /************************
3771          * 1. Allocating HW data
3772          ************************/
3773
3774         hw = iwl_alloc_all(cfg);
3775         if (!hw) {
3776                 err = -ENOMEM;
3777                 goto out;
3778         }
3779         priv = hw->priv;
3780         /* At this point both hw and priv are allocated. */
3781
3782         /*
3783          * The default context is always valid,
3784          * more may be discovered when firmware
3785          * is loaded.
3786          */
3787         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3788
3789         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3790                 priv->contexts[i].ctxid = i;
3791
3792         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3793         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3794         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3795         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3796         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
3797         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
3798         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
3799         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
3800         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3801         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
3802         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3803                 BIT(NL80211_IFTYPE_ADHOC);
3804         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3805                 BIT(NL80211_IFTYPE_STATION);
3806         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
3807         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3808         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3809         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
3810
3811         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3812         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
3813         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
3814         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3815         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3816         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3817         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3818         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
3819         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3820         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3821         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
3822         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3823                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
3824 #ifdef CONFIG_IWL_P2P
3825         priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3826                 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3827 #endif
3828         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3829         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3830         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
3831
3832         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
3833
3834         SET_IEEE80211_DEV(hw, &pdev->dev);
3835
3836         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3837         priv->cfg = cfg;
3838         priv->pci_dev = pdev;
3839         priv->inta_mask = CSR_INI_SET_MASK;
3840
3841         /* is antenna coupling more than 35dB ? */
3842         priv->bt_ant_couple_ok =
3843                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3844                 true : false;
3845
3846         /* enable/disable bt channel inhibition */
3847         priv->bt_ch_announce = iwlagn_bt_ch_announce;
3848         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3849                        (priv->bt_ch_announce) ? "On" : "Off");
3850
3851         if (iwl_alloc_traffic_mem(priv))
3852                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3853
3854         /**************************
3855          * 2. Initializing PCI bus
3856          **************************/
3857         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3858                                 PCIE_LINK_STATE_CLKPM);
3859
3860         if (pci_enable_device(pdev)) {
3861                 err = -ENODEV;
3862                 goto out_ieee80211_free_hw;
3863         }
3864
3865         pci_set_master(pdev);
3866
3867         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3868         if (!err)
3869                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3870         if (err) {
3871                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3872                 if (!err)
3873                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3874                 /* both attempts failed: */
3875                 if (err) {
3876                         IWL_WARN(priv, "No suitable DMA available.\n");
3877                         goto out_pci_disable_device;
3878                 }
3879         }
3880
3881         err = pci_request_regions(pdev, DRV_NAME);
3882         if (err)
3883                 goto out_pci_disable_device;
3884
3885         pci_set_drvdata(pdev, priv);
3886
3887
3888         /***********************
3889          * 3. Read REV register
3890          ***********************/
3891         priv->hw_base = pci_iomap(pdev, 0, 0);
3892         if (!priv->hw_base) {
3893                 err = -ENODEV;
3894                 goto out_pci_release_regions;
3895         }
3896
3897         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3898                 (unsigned long long) pci_resource_len(pdev, 0));
3899         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3900
3901         /* these spin locks will be used in apm_ops.init and EEPROM access
3902          * we should init now
3903          */
3904         spin_lock_init(&priv->reg_lock);
3905         spin_lock_init(&priv->lock);
3906
3907         /*
3908          * stop and reset the on-board processor just in case it is in a
3909          * strange state ... like being left stranded by a primary kernel
3910          * and this is now the kdump kernel trying to start up
3911          */
3912         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3913
3914         iwl_hw_detect(priv);
3915         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3916                 priv->cfg->name, priv->hw_rev);
3917
3918         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3919          * PCI Tx retries from interfering with C3 CPU state */
3920         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3921
3922         iwl_prepare_card_hw(priv);
3923         if (!priv->hw_ready) {
3924                 IWL_WARN(priv, "Failed, HW not ready\n");
3925                 goto out_iounmap;
3926         }
3927
3928         /*****************
3929          * 4. Read EEPROM
3930          *****************/
3931         /* Read the EEPROM */
3932         err = iwl_eeprom_init(priv);
3933         if (err) {
3934                 IWL_ERR(priv, "Unable to init EEPROM\n");
3935                 goto out_iounmap;
3936         }
3937         err = iwl_eeprom_check_version(priv);
3938         if (err)
3939                 goto out_free_eeprom;
3940
3941         err = iwl_eeprom_check_sku(priv);
3942         if (err)
3943                 goto out_free_eeprom;
3944
3945         /* extract MAC Address */
3946         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3947         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3948         priv->hw->wiphy->addresses = priv->addresses;
3949         priv->hw->wiphy->n_addresses = 1;
3950         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3951         if (num_mac > 1) {
3952                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3953                        ETH_ALEN);
3954                 priv->addresses[1].addr[5]++;
3955                 priv->hw->wiphy->n_addresses++;
3956         }
3957
3958         /************************
3959          * 5. Setup HW constants
3960          ************************/
3961         if (iwl_set_hw_params(priv)) {
3962                 IWL_ERR(priv, "failed to set hw parameters\n");
3963                 goto out_free_eeprom;
3964         }
3965
3966         /*******************
3967          * 6. Setup priv
3968          *******************/
3969
3970         err = iwl_init_drv(priv);
3971         if (err)
3972                 goto out_free_eeprom;
3973         /* At this point both hw and priv are initialized. */
3974
3975         /********************
3976          * 7. Setup services
3977          ********************/
3978         spin_lock_irqsave(&priv->lock, flags);
3979         iwl_disable_interrupts(priv);
3980         spin_unlock_irqrestore(&priv->lock, flags);
3981
3982         pci_enable_msi(priv->pci_dev);
3983
3984         if (priv->cfg->ops->lib->isr_ops.alloc)
3985                 priv->cfg->ops->lib->isr_ops.alloc(priv);
3986
3987         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
3988                           IRQF_SHARED, DRV_NAME, priv);
3989         if (err) {
3990                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3991                 goto out_disable_msi;
3992         }
3993
3994         iwl_setup_deferred_work(priv);
3995         iwl_setup_rx_handlers(priv);
3996
3997         /*********************************************
3998          * 8. Enable interrupts and read RFKILL state
3999          *********************************************/
4000
4001         /* enable rfkill interrupt: hw bug w/a */
4002         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4003         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4004                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4005                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4006         }
4007
4008         iwl_enable_rfkill_int(priv);
4009
4010         /* If platform's RF_KILL switch is NOT set to KILL */
4011         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4012                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4013         else
4014                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4015
4016         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4017                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4018
4019         iwl_power_initialize(priv);
4020         iwl_tt_initialize(priv);
4021
4022         init_completion(&priv->_agn.firmware_loading_complete);
4023
4024         err = iwl_request_firmware(priv, true);
4025         if (err)
4026                 goto out_destroy_workqueue;
4027
4028         return 0;
4029
4030  out_destroy_workqueue:
4031         destroy_workqueue(priv->workqueue);
4032         priv->workqueue = NULL;
4033         free_irq(priv->pci_dev->irq, priv);
4034         if (priv->cfg->ops->lib->isr_ops.free)
4035                 priv->cfg->ops->lib->isr_ops.free(priv);
4036  out_disable_msi:
4037         pci_disable_msi(priv->pci_dev);
4038         iwl_uninit_drv(priv);
4039  out_free_eeprom:
4040         iwl_eeprom_free(priv);
4041  out_iounmap:
4042         pci_iounmap(pdev, priv->hw_base);
4043  out_pci_release_regions:
4044         pci_set_drvdata(pdev, NULL);
4045         pci_release_regions(pdev);
4046  out_pci_disable_device:
4047         pci_disable_device(pdev);
4048  out_ieee80211_free_hw:
4049         iwl_free_traffic_mem(priv);
4050         ieee80211_free_hw(priv->hw);
4051  out:
4052         return err;
4053 }
4054
4055 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4056 {
4057         struct iwl_priv *priv = pci_get_drvdata(pdev);
4058         unsigned long flags;
4059
4060         if (!priv)
4061                 return;
4062
4063         wait_for_completion(&priv->_agn.firmware_loading_complete);
4064
4065         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4066
4067         iwl_dbgfs_unregister(priv);
4068         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4069
4070         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4071          * to be called and iwl_down since we are removing the device
4072          * we need to set STATUS_EXIT_PENDING bit.
4073          */
4074         set_bit(STATUS_EXIT_PENDING, &priv->status);
4075
4076         iwl_leds_exit(priv);
4077
4078         if (priv->mac80211_registered) {
4079                 ieee80211_unregister_hw(priv->hw);
4080                 priv->mac80211_registered = 0;
4081         } else {
4082                 iwl_down(priv);
4083         }
4084
4085         /*
4086          * Make sure device is reset to low power before unloading driver.
4087          * This may be redundant with iwl_down(), but there are paths to
4088          * run iwl_down() without calling apm_ops.stop(), and there are
4089          * paths to avoid running iwl_down() at all before leaving driver.
4090          * This (inexpensive) call *makes sure* device is reset.
4091          */
4092         iwl_apm_stop(priv);
4093
4094         iwl_tt_exit(priv);
4095
4096         /* make sure we flush any pending irq or
4097          * tasklet for the driver
4098          */
4099         spin_lock_irqsave(&priv->lock, flags);
4100         iwl_disable_interrupts(priv);
4101         spin_unlock_irqrestore(&priv->lock, flags);
4102
4103         iwl_synchronize_irq(priv);
4104
4105         iwl_dealloc_ucode_pci(priv);
4106
4107         if (priv->rxq.bd)
4108                 iwlagn_rx_queue_free(priv, &priv->rxq);
4109         iwlagn_hw_txq_ctx_free(priv);
4110
4111         iwl_eeprom_free(priv);
4112
4113
4114         /*netif_stop_queue(dev); */
4115         flush_workqueue(priv->workqueue);
4116
4117         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4118          * priv->workqueue... so we can't take down the workqueue
4119          * until now... */
4120         destroy_workqueue(priv->workqueue);
4121         priv->workqueue = NULL;
4122         iwl_free_traffic_mem(priv);
4123
4124         free_irq(priv->pci_dev->irq, priv);
4125         pci_disable_msi(priv->pci_dev);
4126         pci_iounmap(pdev, priv->hw_base);
4127         pci_release_regions(pdev);
4128         pci_disable_device(pdev);
4129         pci_set_drvdata(pdev, NULL);
4130
4131         iwl_uninit_drv(priv);
4132
4133         if (priv->cfg->ops->lib->isr_ops.free)
4134                 priv->cfg->ops->lib->isr_ops.free(priv);
4135
4136         dev_kfree_skb(priv->beacon_skb);
4137
4138         ieee80211_free_hw(priv->hw);
4139 }
4140
4141
4142 /*****************************************************************************
4143  *
4144  * driver and module entry point
4145  *
4146  *****************************************************************************/
4147
4148 /* Hardware specific file defines the PCI IDs table for that hardware module */
4149 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4150         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4151         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4152         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4153         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4154         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4155         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4156         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4157         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4158         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4159         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4160         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4161         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4162         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4163         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4164         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4165         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4166         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4167         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4168         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4169         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4170         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4171         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4172         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4173         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4174
4175 /* 5300 Series WiFi */
4176         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4177         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4178         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4179         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4180         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4181         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4182         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4183         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4184         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4185         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4186         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4187         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4188
4189 /* 5350 Series WiFi/WiMax */
4190         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4191         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4192         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4193
4194 /* 5150 Series Wifi/WiMax */
4195         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4196         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4197         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4198         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4199         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4200         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4201
4202         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4203         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4204         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4205         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4206
4207 /* 6x00 Series */
4208         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4209         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4210         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4211         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4212         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4213         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4214         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4215         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4216         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4217         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4218
4219 /* 6x05 Series */
4220         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4221         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4222         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4223         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4224         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4225         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4226         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4227
4228 /* 6x30 Series */
4229         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4230         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4231         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4232         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4233         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4234         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4235         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4236         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4237         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4238         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4239         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4240         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4241         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4242         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4243         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4244         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4245
4246 /* 6x50 WiFi/WiMax Series */
4247         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4248         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4249         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4250         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4251         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4252         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4253
4254 /* 6150 WiFi/WiMax Series */
4255         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4256         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4257         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4258         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4259         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4260         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4261
4262 /* 1000 Series WiFi */
4263         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4264         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4265         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4266         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4267         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4268         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4269         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4270         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4271         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4272         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4273         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4274         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4275
4276 /* 100 Series WiFi */
4277         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4278         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4279         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4280         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4281         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4282         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4283
4284 /* 130 Series WiFi */
4285         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4286         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4287         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4288         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4289         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4290         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4291
4292 /* 2x00 Series */
4293         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4294         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4295         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4296         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4297         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4298         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4299
4300 /* 2x30 Series */
4301         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4302         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4303         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4304         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4305         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4306         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4307
4308 /* 6x35 Series */
4309         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4310         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4311         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4312         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4313         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4314         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4315         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4316         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4317         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4318
4319 /* 200 Series */
4320         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4321         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4322         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4323         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4324         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4325         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4326
4327 /* 230 Series */
4328         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4329         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4330         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4331         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4332         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4333         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4334
4335         {0}
4336 };
4337 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4338
4339 static struct pci_driver iwl_driver = {
4340         .name = DRV_NAME,
4341         .id_table = iwl_hw_card_ids,
4342         .probe = iwl_pci_probe,
4343         .remove = __devexit_p(iwl_pci_remove),
4344         .driver.pm = IWL_PM_OPS,
4345 };
4346
4347 static int __init iwl_init(void)
4348 {
4349
4350         int ret;
4351         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4352         pr_info(DRV_COPYRIGHT "\n");
4353
4354         ret = iwlagn_rate_control_register();
4355         if (ret) {
4356                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4357                 return ret;
4358         }
4359
4360         ret = pci_register_driver(&iwl_driver);
4361         if (ret) {
4362                 pr_err("Unable to initialize PCI module\n");
4363                 goto error_register;
4364         }
4365
4366         return ret;
4367
4368 error_register:
4369         iwlagn_rate_control_unregister();
4370         return ret;
4371 }
4372
4373 static void __exit iwl_exit(void)
4374 {
4375         pci_unregister_driver(&iwl_driver);
4376         iwlagn_rate_control_unregister();
4377 }
4378
4379 module_exit(iwl_exit);
4380 module_init(iwl_init);
4381
4382 #ifdef CONFIG_IWLWIFI_DEBUG
4383 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4384 MODULE_PARM_DESC(debug, "debug output mask");
4385 #endif
4386
4387 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4388 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4389 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4390 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4391 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4392 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4393 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4394                    int, S_IRUGO);
4395 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4396 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4397 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4398
4399 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4400                    S_IRUGO);
4401 MODULE_PARM_DESC(ucode_alternative,
4402                  "specify ucode alternative to use from ucode file");
4403
4404 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4405 MODULE_PARM_DESC(antenna_coupling,
4406                  "specify antenna coupling in dB (defualt: 0 dB)");
4407
4408 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4409 MODULE_PARM_DESC(bt_ch_inhibition,
4410                  "Disable BT channel inhibition (default: enable)");
4411
4412 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4413 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4414
4415 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4416 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");