drivers/net/wireless/iwlwifi/iwl-agn-ucode.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/init.h>
  33 #include <linux/sched.h>
  34
  35 #include "iwl-dev.h"
  36 #include "iwl-core.h"
  37 #include "iwl-io.h"
  38 #include "iwl-helpers.h"
  39 #include "iwl-agn-hw.h"
  40 #include "iwl-agn.h"
  41 #include "iwl-agn-calib.h"
  42
  43 #define IWL_AC_UNSET -1
  44
  45 struct queue_to_fifo_ac {
  46         s8 fifo, ac;
  47 };
  48
  49 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
  50         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
  51         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
  52         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
  53         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
  54         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
  55         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
  56         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
  57         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
  58         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
  59         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
  60 };
  61
  62 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
  63         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
  64         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
  65         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
  66         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
  67         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
  68         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
  69         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
  70         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
  71         { IWL_TX_FIFO_BE_IPAN, 2, },
  72         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
  73 };
  74
  75 static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
  76         {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
  77          0, COEX_UNASSOC_IDLE_FLAGS},
  78         {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
  79          0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
  80         {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
  81          0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
  82         {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
  83          0, COEX_CALIBRATION_FLAGS},
  84         {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
  85          0, COEX_PERIODIC_CALIBRATION_FLAGS},
  86         {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
  87          0, COEX_CONNECTION_ESTAB_FLAGS},
  88         {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
  89          0, COEX_ASSOCIATED_IDLE_FLAGS},
  90         {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
  91          0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
  92         {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
  93          0, COEX_ASSOC_AUTO_SCAN_FLAGS},
  94         {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
  95          0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
  96         {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
  97         {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
  98         {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
  99          0, COEX_STAND_ALONE_DEBUG_FLAGS},
 100         {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
 101          0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
 102         {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
 103         {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
 104 };
 105
 106 /*
 107  * ucode
 108  */
 109 static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
 110                                 struct fw_desc *image, u32 dst_addr)
 111 {
 112         dma_addr_t phy_addr = image->p_addr;
 113         u32 byte_cnt = image->len;
 114         int ret;
 115
 116         priv->ucode_write_complete = 0;
 117
 118         iwl_write_direct32(priv,
 119                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 120                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 121
 122         iwl_write_direct32(priv,
 123                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 124
 125         iwl_write_direct32(priv,
 126                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 127                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 128
 129         iwl_write_direct32(priv,
 130                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 131                 (iwl_get_dma_hi_addr(phy_addr)
 132                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 133
 134         iwl_write_direct32(priv,
 135                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 136                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 137                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 138                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 139
 140         iwl_write_direct32(priv,
 141                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 142                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 143                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 144                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 145
 146         IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name);
 147         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 148                                         priv->ucode_write_complete, 5 * HZ);
 149         if (ret == -ERESTARTSYS) {
 150                 IWL_ERR(priv, "Could not load the %s uCode section due "
 151                         "to interrupt\n", name);
 152                 return ret;
 153         }
 154         if (!ret) {
 155                 IWL_ERR(priv, "Could not load the %s uCode section\n",
 156                         name);
 157                 return -ETIMEDOUT;
 158         }
 159
 160         return 0;
 161 }
 162
 163 static int iwlagn_load_given_ucode(struct iwl_priv *priv,
 164                                    struct fw_img *image)
 165 {
 166         int ret = 0;
 167
 168         ret = iwlagn_load_section(priv, "INST", &image->code,
 169                                    IWLAGN_RTC_INST_LOWER_BOUND);
 170         if (ret)
 171                 return ret;
 172
 173         return iwlagn_load_section(priv, "DATA", &image->data,
 174                                     IWLAGN_RTC_DATA_LOWER_BOUND);
 175 }
 176
 177 /*
 178  *  Calibration
 179  */
 180 static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
 181 {
 182         struct iwl_calib_xtal_freq_cmd cmd;
 183         __le16 *xtal_calib =
 184                 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
 185
 186         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
 187         cmd.hdr.first_group = 0;
 188         cmd.hdr.groups_num = 1;
 189         cmd.hdr.data_valid = 1;
 190         cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
 191         cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
 192         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
 193                              (u8 *)&cmd, sizeof(cmd));
 194 }
 195
 196 static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
 197 {
 198         struct iwl_calib_temperature_offset_cmd cmd;
 199         __le16 *offset_calib =
 200                 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_TEMPERATURE);
 201         cmd.hdr.op_code = IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD;
 202         cmd.hdr.first_group = 0;
 203         cmd.hdr.groups_num = 1;
 204         cmd.hdr.data_valid = 1;
 205         cmd.radio_sensor_offset = le16_to_cpu(offset_calib[1]);
 206         if (!(cmd.radio_sensor_offset))
 207                 cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
 208         cmd.reserved = 0;
 209         IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
 210                         cmd.radio_sensor_offset);
 211         return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
 212                              (u8 *)&cmd, sizeof(cmd));
 213 }
 214
 215 static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
 216 {
 217         struct iwl_calib_cfg_cmd calib_cfg_cmd;
 218         struct iwl_host_cmd cmd = {
 219                 .id = CALIBRATION_CFG_CMD,
 220                 .len = { sizeof(struct iwl_calib_cfg_cmd), },
 221                 .data = { &calib_cfg_cmd, },
 222         };
 223
 224         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 225         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 226         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 227         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 228         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 229
 230         return iwl_send_cmd(priv, &cmd);
 231 }
 232
 233 void iwlagn_rx_calib_result(struct iwl_priv *priv,
 234                              struct iwl_rx_mem_buffer *rxb)
 235 {
 236         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 237         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
 238         int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 239         int index;
 240
 241         /* reduce the size of the length field itself */
 242         len -= 4;
 243
 244         /* Define the order in which the results will be sent to the runtime
 245          * uCode. iwl_send_calib_results sends them in a row according to
 246          * their index. We sort them here
 247          */
 248         switch (hdr->op_code) {
 249         case IWL_PHY_CALIBRATE_DC_CMD:
 250                 index = IWL_CALIB_DC;
 251                 break;
 252         case IWL_PHY_CALIBRATE_LO_CMD:
 253                 index = IWL_CALIB_LO;
 254                 break;
 255         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
 256                 index = IWL_CALIB_TX_IQ;
 257                 break;
 258         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 259                 index = IWL_CALIB_TX_IQ_PERD;
 260                 break;
 261         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
 262                 index = IWL_CALIB_BASE_BAND;
 263                 break;
 264         default:
 265                 IWL_ERR(priv, "Unknown calibration notification %d\n",
 266                           hdr->op_code);
 267                 return;
 268         }
 269         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 270 }
 271
 272 int iwlagn_init_alive_start(struct iwl_priv *priv)
 273 {
 274         int ret;
 275
 276         if (priv->cfg->bt_params &&
 277             priv->cfg->bt_params->advanced_bt_coexist) {
 278                 /*
 279                  * Tell uCode we are ready to perform calibration
 280                  * need to perform this before any calibration
 281                  * no need to close the envlope since we are going
 282                  * to load the runtime uCode later.
 283                  */
 284                 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
 285                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
 286                 if (ret)
 287                         return ret;
 288
 289         }
 290
 291         ret = iwlagn_send_calib_cfg(priv);
 292         if (ret)
 293                 return ret;
 294
 295         /**
 296          * temperature offset calibration is only needed for runtime ucode,
 297          * so prepare the value now.
 298          */
 299         if (priv->cfg->need_temp_offset_calib)
 300                 return iwlagn_set_temperature_offset_calib(priv);
 301
 302         return 0;
 303 }
 304
 305 static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
 306 {
 307         struct iwl_wimax_coex_cmd coex_cmd;
 308
 309         if (priv->cfg->base_params->support_wimax_coexist) {
 310                 /* UnMask wake up src at associated sleep */
 311                 coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
 312
 313                 /* UnMask wake up src at unassociated sleep */
 314                 coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
 315                 memcpy(coex_cmd.sta_prio, cu_priorities,
 316                         sizeof(struct iwl_wimax_coex_event_entry) *
 317                          COEX_NUM_OF_EVENTS);
 318
 319                 /* enabling the coexistence feature */
 320                 coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
 321
 322                 /* enabling the priorities tables */
 323                 coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
 324         } else {
 325                 /* coexistence is disabled */
 326                 memset(&coex_cmd, 0, sizeof(coex_cmd));
 327         }
 328         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
 329                                 sizeof(coex_cmd), &coex_cmd);
 330 }
 331
 332 static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
 333         ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 334                 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 335         ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 336                 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 337         ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 338                 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 339         ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 340                 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 341         ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 342                 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 343         ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 344                 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 345         ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 346                 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 347         ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 348                 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 349         ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 350                 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 351         0, 0, 0, 0, 0, 0, 0
 352 };
 353
 354 void iwlagn_send_prio_tbl(struct iwl_priv *priv)
 355 {
 356         struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
 357
 358         memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
 359                 sizeof(iwlagn_bt_prio_tbl));
 360         if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PRIO_TABLE,
 361                                 sizeof(prio_tbl_cmd), &prio_tbl_cmd))
 362                 IWL_ERR(priv, "failed to send BT prio tbl command\n");
 363 }
 364
 365 int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
 366 {
 367         struct iwl_bt_coex_prot_env_cmd env_cmd;
 368         int ret;
 369
 370         env_cmd.action = action;
 371         env_cmd.type = type;
 372         ret = iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PROT_ENV,
 373                                sizeof(env_cmd), &env_cmd);
 374         if (ret)
 375                 IWL_ERR(priv, "failed to send BT env command\n");
 376         return ret;
 377 }
 378
 379
 380 static int iwlagn_alive_notify(struct iwl_priv *priv)
 381 {
 382         const struct queue_to_fifo_ac *queue_to_fifo;
 383         struct iwl_rxon_context *ctx;
 384         u32 a;
 385         unsigned long flags;
 386         int i, chan;
 387         u32 reg_val;
 388         int ret;
 389
 390         spin_lock_irqsave(&priv->lock, flags);
 391
 392         priv->scd_base_addr = iwl_read_prph(priv, IWLAGN_SCD_SRAM_BASE_ADDR);
 393         a = priv->scd_base_addr + IWLAGN_SCD_CONTEXT_DATA_OFFSET;
 394         for (; a < priv->scd_base_addr + IWLAGN_SCD_TX_STTS_BITMAP_OFFSET;
 395                 a += 4)
 396                 iwl_write_targ_mem(priv, a, 0);
 397         for (; a < priv->scd_base_addr + IWLAGN_SCD_TRANSLATE_TBL_OFFSET;
 398                 a += 4)
 399                 iwl_write_targ_mem(priv, a, 0);
 400         for (; a < priv->scd_base_addr +
 401                IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
 402                 iwl_write_targ_mem(priv, a, 0);
 403
 404         iwl_write_prph(priv, IWLAGN_SCD_DRAM_BASE_ADDR,
 405                        priv->scd_bc_tbls.dma >> 10);
 406
 407         /* Enable DMA channel */
 408         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
 409                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 410                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 411                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 412
 413         /* Update FH chicken bits */
 414         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 415         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 416                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 417
 418         iwl_write_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL,
 419                 IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv));
 420         iwl_write_prph(priv, IWLAGN_SCD_AGGR_SEL, 0);
 421
 422         /* initiate the queues */
 423         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 424                 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(i), 0);
 425                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 426                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 427                                 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 428                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 429                                 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i) +
 430                                 sizeof(u32),
 431                                 ((SCD_WIN_SIZE <<
 432                                 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 433                                 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 434                                 ((SCD_FRAME_LIMIT <<
 435                                 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 436                                 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 437         }
 438
 439         iwl_write_prph(priv, IWLAGN_SCD_INTERRUPT_MASK,
 440                         IWL_MASK(0, priv->hw_params.max_txq_num));
 441
 442         /* Activate all Tx DMA/FIFO channels */
 443         iwlagn_txq_set_sched(priv, IWL_MASK(0, 7));
 444
 445         /* map queues to FIFOs */
 446         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
 447                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
 448         else
 449                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
 450
 451         iwlagn_set_wr_ptrs(priv, priv->cmd_queue, 0);
 452
 453         /* make sure all queue are not stopped */
 454         memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
 455         for (i = 0; i < 4; i++)
 456                 atomic_set(&priv->queue_stop_count[i], 0);
 457         for_each_context(priv, ctx)
 458                 ctx->last_tx_rejected = false;
 459
 460         /* reset to 0 to enable all the queue first */
 461         priv->txq_ctx_active_msk = 0;
 462
 463         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) != 10);
 464         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) != 10);
 465
 466         for (i = 0; i < 10; i++) {
 467                 int fifo = queue_to_fifo[i].fifo;
 468                 int ac = queue_to_fifo[i].ac;
 469
 470                 iwl_txq_ctx_activate(priv, i);
 471
 472                 if (fifo == IWL_TX_FIFO_UNUSED)
 473                         continue;
 474
 475                 if (ac != IWL_AC_UNSET)
 476                         iwl_set_swq_id(&priv->txq[i], ac, i);
 477                 iwlagn_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
 478         }
 479
 480         spin_unlock_irqrestore(&priv->lock, flags);
 481
 482         /* Enable L1-Active */
 483         iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG,
 484                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 485
 486         ret = iwlagn_send_wimax_coex(priv);
 487         if (ret)
 488                 return ret;
 489
 490         ret = iwlagn_set_Xtal_calib(priv);
 491         if (ret)
 492                 return ret;
 493
 494         return iwl_send_calib_results(priv);
 495 }
 496
 497
 498 /**
 499  * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
 500  *   using sample data 100 bytes apart.  If these sample points are good,
 501  *   it's a pretty good bet that everything between them is good, too.
 502  */
 503 static int iwlcore_verify_inst_sparse(struct iwl_priv *priv,
 504                                       struct fw_desc *fw_desc)
 505 {
 506         __le32 *image = (__le32 *)fw_desc->v_addr;
 507         u32 len = fw_desc->len;
 508         u32 val;
 509         u32 i;
 510
 511         IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
 512
 513         for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
 514                 /* read data comes through single port, auto-incr addr */
 515                 /* NOTE: Use the debugless read so we don't flood kernel log
 516                  * if IWL_DL_IO is set */
 517                 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
 518                         i + IWLAGN_RTC_INST_LOWER_BOUND);
 519                 val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
 520                 if (val != le32_to_cpu(*image))
 521                         return -EIO;
 522         }
 523
 524         return 0;
 525 }
 526
 527 static void iwl_print_mismatch_inst(struct iwl_priv *priv,
 528                                     struct fw_desc *fw_desc)
 529 {
 530         __le32 *image = (__le32 *)fw_desc->v_addr;
 531         u32 len = fw_desc->len;
 532         u32 val;
 533         u32 offs;
 534         int errors = 0;
 535
 536         IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
 537
 538         iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
 539                            IWLAGN_RTC_INST_LOWER_BOUND);
 540
 541         for (offs = 0;
 542              offs < len && errors < 20;
 543              offs += sizeof(u32), image++) {
 544                 /* read data comes through single port, auto-incr addr */
 545                 val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
 546                 if (val != le32_to_cpu(*image)) {
 547                         IWL_ERR(priv, "uCode INST section at "
 548                                 "offset 0x%x, is 0x%x, s/b 0x%x\n",
 549                                 offs, val, le32_to_cpu(*image));
 550                         errors++;
 551                 }
 552         }
 553 }
 554
 555 /**
 556  * iwl_verify_ucode - determine which instruction image is in SRAM,
 557  *    and verify its contents
 558  */
 559 static int iwl_verify_ucode(struct iwl_priv *priv, struct fw_img *img)
 560 {
 561         if (!iwlcore_verify_inst_sparse(priv, &img->code)) {
 562                 IWL_DEBUG_INFO(priv, "uCode is good in inst SRAM\n");
 563                 return 0;
 564         }
 565
 566         IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
 567
 568         iwl_print_mismatch_inst(priv, &img->code);
 569         return -EIO;
 570 }
 571
 572 struct iwlagn_alive_data {
 573         bool valid;
 574         u8 subtype;
 575 };
 576
 577 static void iwlagn_alive_fn(struct iwl_priv *priv,
 578                             struct iwl_rx_packet *pkt,
 579                             void *data)
 580 {
 581         struct iwlagn_alive_data *alive_data = data;
 582         struct iwl_alive_resp *palive;
 583
 584         palive = &pkt->u.alive_frame;
 585
 586         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
 587                        "0x%01X 0x%01X\n",
 588                        palive->is_valid, palive->ver_type,
 589                        palive->ver_subtype);
 590
 591         priv->device_pointers.error_event_table =
 592                 le32_to_cpu(palive->error_event_table_ptr);
 593         priv->device_pointers.log_event_table =
 594                 le32_to_cpu(palive->log_event_table_ptr);
 595
 596         alive_data->subtype = palive->ver_subtype;
 597         alive_data->valid = palive->is_valid == UCODE_VALID_OK;
 598 }
 599
 600 #define UCODE_ALIVE_TIMEOUT     HZ
 601 #define UCODE_CALIB_TIMEOUT     (2*HZ)
 602
 603 int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
 604                                  struct fw_img *image,
 605                                  int subtype, int alternate_subtype)
 606 {
 607         struct iwl_notification_wait alive_wait;
 608         struct iwlagn_alive_data alive_data;
 609         int ret;
 610         enum iwlagn_ucode_subtype old_type;
 611
 612         ret = iwlagn_start_device(priv);
 613         if (ret)
 614                 return ret;
 615
 616         iwlagn_init_notification_wait(priv, &alive_wait, REPLY_ALIVE,
 617                                       iwlagn_alive_fn, &alive_data);
 618
 619         old_type = priv->ucode_type;
 620         priv->ucode_type = subtype;
 621
 622         ret = iwlagn_load_given_ucode(priv, image);
 623         if (ret) {
 624                 priv->ucode_type = old_type;
 625                 iwlagn_remove_notification(priv, &alive_wait);
 626                 return ret;
 627         }
 628
 629         /* Remove all resets to allow NIC to operate */
 630         iwl_write32(priv, CSR_RESET, 0);
 631
 632         /*
 633          * Some things may run in the background now, but we
 634          * just wait for the ALIVE notification here.
 635          */
 636         ret = iwlagn_wait_notification(priv, &alive_wait, UCODE_ALIVE_TIMEOUT);
 637         if (ret) {
 638                 priv->ucode_type = old_type;
 639                 return ret;
 640         }
 641
 642         if (!alive_data.valid) {
 643                 IWL_ERR(priv, "Loaded ucode is not valid!\n");
 644                 priv->ucode_type = old_type;
 645                 return -EIO;
 646         }
 647
 648         if (alive_data.subtype != subtype &&
 649             alive_data.subtype != alternate_subtype) {
 650                 IWL_ERR(priv,
 651                         "Loaded ucode is not expected type (got %d, expected %d)!\n",
 652                         alive_data.subtype, subtype);
 653                 priv->ucode_type = old_type;
 654                 return -EIO;
 655         }
 656
 657         ret = iwl_verify_ucode(priv, image);
 658         if (ret) {
 659                 priv->ucode_type = old_type;
 660                 return ret;
 661         }
 662
 663         /* delay a bit to give rfkill time to run */
 664         msleep(5);
 665
 666         ret = iwlagn_alive_notify(priv);
 667         if (ret) {
 668                 IWL_WARN(priv,
 669                         "Could not complete ALIVE transition: %d\n", ret);
 670                 priv->ucode_type = old_type;
 671                 return ret;
 672         }
 673
 674         return 0;
 675 }
 676
 677 int iwlagn_run_init_ucode(struct iwl_priv *priv)
 678 {
 679         struct iwl_notification_wait calib_wait;
 680         int ret;
 681
 682         lockdep_assert_held(&priv->mutex);
 683
 684         /* No init ucode required? Curious, but maybe ok */
 685         if (!priv->ucode_init.code.len)
 686                 return 0;
 687
 688         if (priv->ucode_type != UCODE_SUBTYPE_NONE_LOADED)
 689                 return 0;
 690
 691         iwlagn_init_notification_wait(priv, &calib_wait,
 692                                       CALIBRATION_COMPLETE_NOTIFICATION,
 693                                       NULL, NULL);
 694
 695         /* Will also start the device */
 696         ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
 697                                            UCODE_SUBTYPE_INIT, -1);
 698         if (ret)
 699                 goto error;
 700
 701         ret = iwlagn_init_alive_start(priv);
 702         if (ret)
 703                 goto error;
 704
 705         /*
 706          * Some things may run in the background now, but we
 707          * just wait for the calibration complete notification.
 708          */
 709         ret = iwlagn_wait_notification(priv, &calib_wait, UCODE_CALIB_TIMEOUT);
 710
 711         goto out;
 712
 713  error:
 714         iwlagn_remove_notification(priv, &calib_wait);
 715  out:
 716         /* Whatever happened, stop the device */
 717         iwlagn_stop_device(priv);
 718         return ret;
 719 }