drivers/net/wireless/iwlwifi/iwl-agn-lib.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/etherdevice.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/init.h>
  33 #include <linux/sched.h>
  34
  35 #include "iwl-dev.h"
  36 #include "iwl-core.h"
  37 #include "iwl-io.h"
  38 #include "iwl-helpers.h"
  39 #include "iwl-agn-hw.h"
  40 #include "iwl-agn.h"
  41 #include "iwl-sta.h"
  42
  43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
  44 {
  45         return le32_to_cpup((__le32 *)&tx_resp->status +
  46                             tx_resp->frame_count) & MAX_SN;
  47 }
  48
  49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
  50 {
  51         status &= TX_STATUS_MSK;
  52
  53         switch (status) {
  54         case TX_STATUS_POSTPONE_DELAY:
  55                 priv->_agn.reply_tx_stats.pp_delay++;
  56                 break;
  57         case TX_STATUS_POSTPONE_FEW_BYTES:
  58                 priv->_agn.reply_tx_stats.pp_few_bytes++;
  59                 break;
  60         case TX_STATUS_POSTPONE_BT_PRIO:
  61                 priv->_agn.reply_tx_stats.pp_bt_prio++;
  62                 break;
  63         case TX_STATUS_POSTPONE_QUIET_PERIOD:
  64                 priv->_agn.reply_tx_stats.pp_quiet_period++;
  65                 break;
  66         case TX_STATUS_POSTPONE_CALC_TTAK:
  67                 priv->_agn.reply_tx_stats.pp_calc_ttak++;
  68                 break;
  69         case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
  70                 priv->_agn.reply_tx_stats.int_crossed_retry++;
  71                 break;
  72         case TX_STATUS_FAIL_SHORT_LIMIT:
  73                 priv->_agn.reply_tx_stats.short_limit++;
  74                 break;
  75         case TX_STATUS_FAIL_LONG_LIMIT:
  76                 priv->_agn.reply_tx_stats.long_limit++;
  77                 break;
  78         case TX_STATUS_FAIL_FIFO_UNDERRUN:
  79                 priv->_agn.reply_tx_stats.fifo_underrun++;
  80                 break;
  81         case TX_STATUS_FAIL_DRAIN_FLOW:
  82                 priv->_agn.reply_tx_stats.drain_flow++;
  83                 break;
  84         case TX_STATUS_FAIL_RFKILL_FLUSH:
  85                 priv->_agn.reply_tx_stats.rfkill_flush++;
  86                 break;
  87         case TX_STATUS_FAIL_LIFE_EXPIRE:
  88                 priv->_agn.reply_tx_stats.life_expire++;
  89                 break;
  90         case TX_STATUS_FAIL_DEST_PS:
  91                 priv->_agn.reply_tx_stats.dest_ps++;
  92                 break;
  93         case TX_STATUS_FAIL_HOST_ABORTED:
  94                 priv->_agn.reply_tx_stats.host_abort++;
  95                 break;
  96         case TX_STATUS_FAIL_BT_RETRY:
  97                 priv->_agn.reply_tx_stats.bt_retry++;
  98                 break;
  99         case TX_STATUS_FAIL_STA_INVALID:
 100                 priv->_agn.reply_tx_stats.sta_invalid++;
 101                 break;
 102         case TX_STATUS_FAIL_FRAG_DROPPED:
 103                 priv->_agn.reply_tx_stats.frag_drop++;
 104                 break;
 105         case TX_STATUS_FAIL_TID_DISABLE:
 106                 priv->_agn.reply_tx_stats.tid_disable++;
 107                 break;
 108         case TX_STATUS_FAIL_FIFO_FLUSHED:
 109                 priv->_agn.reply_tx_stats.fifo_flush++;
 110                 break;
 111         case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
 112                 priv->_agn.reply_tx_stats.insuff_cf_poll++;
 113                 break;
 114         case TX_STATUS_FAIL_PASSIVE_NO_RX:
 115                 priv->_agn.reply_tx_stats.fail_hw_drop++;
 116                 break;
 117         case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
 118                 priv->_agn.reply_tx_stats.sta_color_mismatch++;
 119                 break;
 120         default:
 121                 priv->_agn.reply_tx_stats.unknown++;
 122                 break;
 123         }
 124 }
 125
 126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
 127 {
 128         status &= AGG_TX_STATUS_MSK;
 129
 130         switch (status) {
 131         case AGG_TX_STATE_UNDERRUN_MSK:
 132                 priv->_agn.reply_agg_tx_stats.underrun++;
 133                 break;
 134         case AGG_TX_STATE_BT_PRIO_MSK:
 135                 priv->_agn.reply_agg_tx_stats.bt_prio++;
 136                 break;
 137         case AGG_TX_STATE_FEW_BYTES_MSK:
 138                 priv->_agn.reply_agg_tx_stats.few_bytes++;
 139                 break;
 140         case AGG_TX_STATE_ABORT_MSK:
 141                 priv->_agn.reply_agg_tx_stats.abort++;
 142                 break;
 143         case AGG_TX_STATE_LAST_SENT_TTL_MSK:
 144                 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
 145                 break;
 146         case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
 147                 priv->_agn.reply_agg_tx_stats.last_sent_try++;
 148                 break;
 149         case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
 150                 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
 151                 break;
 152         case AGG_TX_STATE_SCD_QUERY_MSK:
 153                 priv->_agn.reply_agg_tx_stats.scd_query++;
 154                 break;
 155         case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
 156                 priv->_agn.reply_agg_tx_stats.bad_crc32++;
 157                 break;
 158         case AGG_TX_STATE_RESPONSE_MSK:
 159                 priv->_agn.reply_agg_tx_stats.response++;
 160                 break;
 161         case AGG_TX_STATE_DUMP_TX_MSK:
 162                 priv->_agn.reply_agg_tx_stats.dump_tx++;
 163                 break;
 164         case AGG_TX_STATE_DELAY_TX_MSK:
 165                 priv->_agn.reply_agg_tx_stats.delay_tx++;
 166                 break;
 167         default:
 168                 priv->_agn.reply_agg_tx_stats.unknown++;
 169                 break;
 170         }
 171 }
 172
 173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
 174                                  struct ieee80211_tx_info *info,
 175                                  struct iwlagn_tx_resp *tx_resp,
 176                                  int txq_id, bool is_agg)
 177 {
 178         u16  status = le16_to_cpu(tx_resp->status.status);
 179
 180         info->status.rates[0].count = tx_resp->failure_frame + 1;
 181         if (is_agg)
 182                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
 183         info->flags |= iwl_tx_status_to_mac80211(status);
 184         iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
 185                                     info);
 186         if (!iwl_is_tx_success(status))
 187                 iwlagn_count_tx_err_status(priv, status);
 188
 189         IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
 190                            "0x%x retries %d\n",
 191                            txq_id,
 192                            iwl_get_tx_fail_reason(status), status,
 193                            le32_to_cpu(tx_resp->rate_n_flags),
 194                            tx_resp->failure_frame);
 195 }
 196
 197 #ifdef CONFIG_IWLWIFI_DEBUG
 198 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
 199
 200 const char *iwl_get_agg_tx_fail_reason(u16 status)
 201 {
 202         status &= AGG_TX_STATUS_MSK;
 203         switch (status) {
 204         case AGG_TX_STATE_TRANSMITTED:
 205                 return "SUCCESS";
 206                 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
 207                 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
 208                 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
 209                 AGG_TX_STATE_FAIL(ABORT_MSK);
 210                 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
 211                 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
 212                 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
 213                 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
 214                 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
 215                 AGG_TX_STATE_FAIL(RESPONSE_MSK);
 216                 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
 217                 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
 218         }
 219
 220         return "UNKNOWN";
 221 }
 222 #endif /* CONFIG_IWLWIFI_DEBUG */
 223
 224 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
 225                                       struct iwl_ht_agg *agg,
 226                                       struct iwlagn_tx_resp *tx_resp,
 227                                       int txq_id, u16 start_idx)
 228 {
 229         u16 status;
 230         struct agg_tx_status *frame_status = &tx_resp->status;
 231         struct ieee80211_hdr *hdr = NULL;
 232         int i, sh, idx;
 233         u16 seq;
 234
 235         if (agg->wait_for_ba)
 236                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
 237
 238         agg->frame_count = tx_resp->frame_count;
 239         agg->start_idx = start_idx;
 240         agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
 241         agg->bitmap = 0;
 242
 243         /* # frames attempted by Tx command */
 244         if (agg->frame_count == 1) {
 245                 /* Only one frame was attempted; no block-ack will arrive */
 246                 idx = start_idx;
 247
 248                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
 249                                    agg->frame_count, agg->start_idx, idx);
 250                 iwlagn_set_tx_status(priv,
 251                                      IEEE80211_SKB_CB(
 252                                         priv->txq[txq_id].txb[idx].skb),
 253                                      tx_resp, txq_id, true);
 254                 agg->wait_for_ba = 0;
 255         } else {
 256                 /* Two or more frames were attempted; expect block-ack */
 257                 u64 bitmap = 0;
 258
 259                 /*
 260                  * Start is the lowest frame sent. It may not be the first
 261                  * frame in the batch; we figure this out dynamically during
 262                  * the following loop.
 263                  */
 264                 int start = agg->start_idx;
 265
 266                 /* Construct bit-map of pending frames within Tx window */
 267                 for (i = 0; i < agg->frame_count; i++) {
 268                         u16 sc;
 269                         status = le16_to_cpu(frame_status[i].status);
 270                         seq  = le16_to_cpu(frame_status[i].sequence);
 271                         idx = SEQ_TO_INDEX(seq);
 272                         txq_id = SEQ_TO_QUEUE(seq);
 273
 274                         if (status & AGG_TX_STATUS_MSK)
 275                                 iwlagn_count_agg_tx_err_status(priv, status);
 276
 277                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
 278                                       AGG_TX_STATE_ABORT_MSK))
 279                                 continue;
 280
 281                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
 282                                            agg->frame_count, txq_id, idx);
 283                         IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
 284                                            "try-count (0x%08x)\n",
 285                                            iwl_get_agg_tx_fail_reason(status),
 286                                            status & AGG_TX_STATUS_MSK,
 287                                            status & AGG_TX_TRY_MSK);
 288
 289                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
 290                         if (!hdr) {
 291                                 IWL_ERR(priv,
 292                                         "BUG_ON idx doesn't point to valid skb"
 293                                         " idx=%d, txq_id=%d\n", idx, txq_id);
 294                                 return -1;
 295                         }
 296
 297                         sc = le16_to_cpu(hdr->seq_ctrl);
 298                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
 299                                 IWL_ERR(priv,
 300                                         "BUG_ON idx doesn't match seq control"
 301                                         " idx=%d, seq_idx=%d, seq=%d\n",
 302                                           idx, SEQ_TO_SN(sc),
 303                                           hdr->seq_ctrl);
 304                                 return -1;
 305                         }
 306
 307                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
 308                                            i, idx, SEQ_TO_SN(sc));
 309
 310                         /*
 311                          * sh -> how many frames ahead of the starting frame is
 312                          * the current one?
 313                          *
 314                          * Note that all frames sent in the batch must be in a
 315                          * 64-frame window, so this number should be in [0,63].
 316                          * If outside of this window, then we've found a new
 317                          * "first" frame in the batch and need to change start.
 318                          */
 319                         sh = idx - start;
 320
 321                         /*
 322                          * If >= 64, out of window. start must be at the front
 323                          * of the circular buffer, idx must be near the end of
 324                          * the buffer, and idx is the new "first" frame. Shift
 325                          * the indices around.
 326                          */
 327                         if (sh >= 64) {
 328                                 /* Shift bitmap by start - idx, wrapped */
 329                                 sh = 0x100 - idx + start;
 330                                 bitmap = bitmap << sh;
 331                                 /* Now idx is the new start so sh = 0 */
 332                                 sh = 0;
 333                                 start = idx;
 334                         /*
 335                          * If <= -64 then wraps the 256-pkt circular buffer
 336                          * (e.g., start = 255 and idx = 0, sh should be 1)
 337                          */
 338                         } else if (sh <= -64) {
 339                                 sh  = 0x100 - start + idx;
 340                         /*
 341                          * If < 0 but > -64, out of window. idx is before start
 342                          * but not wrapped. Shift the indices around.
 343                          */
 344                         } else if (sh < 0) {
 345                                 /* Shift by how far start is ahead of idx */
 346                                 sh = start - idx;
 347                                 bitmap = bitmap << sh;
 348                                 /* Now idx is the new start so sh = 0 */
 349                                 start = idx;
 350                                 sh = 0;
 351                         }
 352                         /* Sequence number start + sh was sent in this batch */
 353                         bitmap |= 1ULL << sh;
 354                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
 355                                            start, (unsigned long long)bitmap);
 356                 }
 357
 358                 /*
 359                  * Store the bitmap and possibly the new start, if we wrapped
 360                  * the buffer above
 361                  */
 362                 agg->bitmap = bitmap;
 363                 agg->start_idx = start;
 364                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
 365                                    agg->frame_count, agg->start_idx,
 366                                    (unsigned long long)agg->bitmap);
 367
 368                 if (bitmap)
 369                         agg->wait_for_ba = 1;
 370         }
 371         return 0;
 372 }
 373
 374 void iwl_check_abort_status(struct iwl_priv *priv,
 375                             u8 frame_count, u32 status)
 376 {
 377         if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
 378                 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
 379                 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 380                         queue_work(priv->workqueue, &priv->tx_flush);
 381         }
 382 }
 383
 384 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
 385                                 struct iwl_rx_mem_buffer *rxb)
 386 {
 387         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 388         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 389         int txq_id = SEQ_TO_QUEUE(sequence);
 390         int index = SEQ_TO_INDEX(sequence);
 391         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 392         struct ieee80211_tx_info *info;
 393         struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 394         u32  status = le16_to_cpu(tx_resp->status.status);
 395         int tid;
 396         int sta_id;
 397         int freed;
 398         unsigned long flags;
 399
 400         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 401                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 402                           "is out of range [0-%d] %d %d\n", txq_id,
 403                           index, txq->q.n_bd, txq->q.write_ptr,
 404                           txq->q.read_ptr);
 405                 return;
 406         }
 407
 408         txq->time_stamp = jiffies;
 409         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
 410         memset(&info->status, 0, sizeof(info->status));
 411
 412         tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
 413                 IWLAGN_TX_RES_TID_POS;
 414         sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
 415                 IWLAGN_TX_RES_RA_POS;
 416
 417         spin_lock_irqsave(&priv->sta_lock, flags);
 418         if (txq->sched_retry) {
 419                 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
 420                 struct iwl_ht_agg *agg;
 421
 422                 agg = &priv->stations[sta_id].tid[tid].agg;
 423                 /*
 424                  * If the BT kill count is non-zero, we'll get this
 425                  * notification again.
 426                  */
 427                 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
 428                     priv->cfg->bt_params &&
 429                     priv->cfg->bt_params->advanced_bt_coexist) {
 430                         IWL_WARN(priv, "receive reply tx with bt_kill\n");
 431                 }
 432                 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
 433
 434                 /* check if BAR is needed */
 435                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
 436                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
 437
 438                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
 439                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
 440                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
 441                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
 442                                         scd_ssn , index, txq_id, txq->swq_id);
 443
 444                         freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
 445                         iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 446
 447                         if (priv->mac80211_registered &&
 448                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
 449                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
 450                                 iwl_wake_queue(priv, txq);
 451                 }
 452         } else {
 453                 iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
 454                 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
 455                 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 456
 457                 if (priv->mac80211_registered &&
 458                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
 459                         iwl_wake_queue(priv, txq);
 460         }
 461
 462         iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
 463
 464         iwl_check_abort_status(priv, tx_resp->frame_count, status);
 465         spin_unlock_irqrestore(&priv->sta_lock, flags);
 466 }
 467
 468 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
 469 {
 470         /* init calibration handlers */
 471         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
 472                                         iwlagn_rx_calib_result;
 473         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
 474                                         iwlagn_rx_calib_complete;
 475         priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
 476
 477         /* set up notification wait support */
 478         spin_lock_init(&priv->_agn.notif_wait_lock);
 479         INIT_LIST_HEAD(&priv->_agn.notif_waits);
 480         init_waitqueue_head(&priv->_agn.notif_waitq);
 481 }
 482
 483 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
 484 {
 485         /* in agn, the tx power calibration is done in uCode */
 486         priv->disable_tx_power_cal = 1;
 487 }
 488
 489 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
 490 {
 491         return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
 492                 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
 493 }
 494
 495 int iwlagn_send_tx_power(struct iwl_priv *priv)
 496 {
 497         struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
 498         u8 tx_ant_cfg_cmd;
 499
 500         if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
 501                       "TX Power requested while scanning!\n"))
 502                 return -EAGAIN;
 503
 504         /* half dBm need to multiply */
 505         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
 506
 507         if (priv->tx_power_lmt_in_half_dbm &&
 508             priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
 509                 /*
 510                  * For the newer devices which using enhanced/extend tx power
 511                  * table in EEPROM, the format is in half dBm. driver need to
 512                  * convert to dBm format before report to mac80211.
 513                  * By doing so, there is a possibility of 1/2 dBm resolution
 514                  * lost. driver will perform "round-up" operation before
 515                  * reporting, but it will cause 1/2 dBm tx power over the
 516                  * regulatory limit. Perform the checking here, if the
 517                  * "tx_power_user_lmt" is higher than EEPROM value (in
 518                  * half-dBm format), lower the tx power based on EEPROM
 519                  */
 520                 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
 521         }
 522         tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
 523         tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
 524
 525         if (IWL_UCODE_API(priv->ucode_ver) == 1)
 526                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
 527         else
 528                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
 529
 530         return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
 531                                 &tx_power_cmd);
 532 }
 533
 534 void iwlagn_temperature(struct iwl_priv *priv)
 535 {
 536         /* store temperature from correct statistics (in Celsius) */
 537         priv->temperature = le32_to_cpu((iwl_bt_statistics(priv)) ?
 538                 priv->_agn.statistics_bt.general.common.temperature :
 539                 priv->_agn.statistics.general.common.temperature);
 540         iwl_tt_handler(priv);
 541 }
 542
 543 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
 544 {
 545         struct iwl_eeprom_calib_hdr {
 546                 u8 version;
 547                 u8 pa_type;
 548                 u16 voltage;
 549         } *hdr;
 550
 551         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 552                                                         EEPROM_CALIB_ALL);
 553         return hdr->version;
 554
 555 }
 556
 557 /*
 558  * EEPROM
 559  */
 560 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 561 {
 562         u16 offset = 0;
 563
 564         if ((address & INDIRECT_ADDRESS) == 0)
 565                 return address;
 566
 567         switch (address & INDIRECT_TYPE_MSK) {
 568         case INDIRECT_HOST:
 569                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
 570                 break;
 571         case INDIRECT_GENERAL:
 572                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
 573                 break;
 574         case INDIRECT_REGULATORY:
 575                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
 576                 break;
 577         case INDIRECT_TXP_LIMIT:
 578                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
 579                 break;
 580         case INDIRECT_TXP_LIMIT_SIZE:
 581                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
 582                 break;
 583         case INDIRECT_CALIBRATION:
 584                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
 585                 break;
 586         case INDIRECT_PROCESS_ADJST:
 587                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
 588                 break;
 589         case INDIRECT_OTHERS:
 590                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
 591                 break;
 592         default:
 593                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 594                 address & INDIRECT_TYPE_MSK);
 595                 break;
 596         }
 597
 598         /* translate the offset from words to byte */
 599         return (address & ADDRESS_MSK) + (offset << 1);
 600 }
 601
 602 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
 603                                            size_t offset)
 604 {
 605         u32 address = eeprom_indirect_address(priv, offset);
 606         BUG_ON(address >= priv->cfg->base_params->eeprom_size);
 607         return &priv->eeprom[address];
 608 }
 609
 610 struct iwl_mod_params iwlagn_mod_params = {
 611         .amsdu_size_8K = 1,
 612         .restart_fw = 1,
 613         .plcp_check = true,
 614         /* the rest are 0 by default */
 615 };
 616
 617 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 618 {
 619         unsigned long flags;
 620         int i;
 621         spin_lock_irqsave(&rxq->lock, flags);
 622         INIT_LIST_HEAD(&rxq->rx_free);
 623         INIT_LIST_HEAD(&rxq->rx_used);
 624         /* Fill the rx_used queue with _all_ of the Rx buffers */
 625         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 626                 /* In the reset function, these buffers may have been allocated
 627                  * to an SKB, so we need to unmap and free potential storage */
 628                 if (rxq->pool[i].page != NULL) {
 629                         pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
 630                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 631                                 PCI_DMA_FROMDEVICE);
 632                         __iwl_free_pages(priv, rxq->pool[i].page);
 633                         rxq->pool[i].page = NULL;
 634                 }
 635                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 636         }
 637
 638         for (i = 0; i < RX_QUEUE_SIZE; i++)
 639                 rxq->queue[i] = NULL;
 640
 641         /* Set us so that we have processed and used all buffers, but have
 642          * not restocked the Rx queue with fresh buffers */
 643         rxq->read = rxq->write = 0;
 644         rxq->write_actual = 0;
 645         rxq->free_count = 0;
 646         spin_unlock_irqrestore(&rxq->lock, flags);
 647 }
 648
 649 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 650 {
 651         u32 rb_size;
 652         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 653         u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
 654
 655         rb_timeout = RX_RB_TIMEOUT;
 656
 657         if (priv->cfg->mod_params->amsdu_size_8K)
 658                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 659         else
 660                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 661
 662         /* Stop Rx DMA */
 663         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 664
 665         /* Reset driver's Rx queue write index */
 666         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 667
 668         /* Tell device where to find RBD circular buffer in DRAM */
 669         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 670                            (u32)(rxq->bd_dma >> 8));
 671
 672         /* Tell device where in DRAM to update its Rx status */
 673         iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 674                            rxq->rb_stts_dma >> 4);
 675
 676         /* Enable Rx DMA
 677          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 678          *      the credit mechanism in 5000 HW RX FIFO
 679          * Direct rx interrupts to hosts
 680          * Rx buffer size 4 or 8k
 681          * RB timeout 0x10
 682          * 256 RBDs
 683          */
 684         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 685                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 686                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 687                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 688                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 689                            rb_size|
 690                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 691                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 692
 693         /* Set interrupt coalescing timer to default (2048 usecs) */
 694         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 695
 696         return 0;
 697 }
 698
 699 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
 700 {
 701 /*
 702  * (for documentation purposes)
 703  * to set power to V_AUX, do:
 704
 705                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 706                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 707                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 708                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 709  */
 710
 711         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 712                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 713                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 714 }
 715
 716 int iwlagn_hw_nic_init(struct iwl_priv *priv)
 717 {
 718         unsigned long flags;
 719         struct iwl_rx_queue *rxq = &priv->rxq;
 720         int ret;
 721
 722         /* nic_init */
 723         spin_lock_irqsave(&priv->lock, flags);
 724         priv->cfg->ops->lib->apm_ops.init(priv);
 725
 726         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 727         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 728
 729         spin_unlock_irqrestore(&priv->lock, flags);
 730
 731         iwlagn_set_pwr_vmain(priv);
 732
 733         priv->cfg->ops->lib->apm_ops.config(priv);
 734
 735         /* Allocate the RX queue, or reset if it is already allocated */
 736         if (!rxq->bd) {
 737                 ret = iwl_rx_queue_alloc(priv);
 738                 if (ret) {
 739                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
 740                         return -ENOMEM;
 741                 }
 742         } else
 743                 iwlagn_rx_queue_reset(priv, rxq);
 744
 745         iwlagn_rx_replenish(priv);
 746
 747         iwlagn_rx_init(priv, rxq);
 748
 749         spin_lock_irqsave(&priv->lock, flags);
 750
 751         rxq->need_update = 1;
 752         iwl_rx_queue_update_write_ptr(priv, rxq);
 753
 754         spin_unlock_irqrestore(&priv->lock, flags);
 755
 756         /* Allocate or reset and init all Tx and Command queues */
 757         if (!priv->txq) {
 758                 ret = iwlagn_txq_ctx_alloc(priv);
 759                 if (ret)
 760                         return ret;
 761         } else
 762                 iwlagn_txq_ctx_reset(priv);
 763
 764         if (priv->cfg->base_params->shadow_reg_enable) {
 765                 /* enable shadow regs in HW */
 766                 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
 767                         0x800FFFFF);
 768         }
 769
 770         set_bit(STATUS_INIT, &priv->status);
 771
 772         return 0;
 773 }
 774
 775 /**
 776  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 777  */
 778 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
 779                                           dma_addr_t dma_addr)
 780 {
 781         return cpu_to_le32((u32)(dma_addr >> 8));
 782 }
 783
 784 /**
 785  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 786  *
 787  * If there are slots in the RX queue that need to be restocked,
 788  * and we have free pre-allocated buffers, fill the ranks as much
 789  * as we can, pulling from rx_free.
 790  *
 791  * This moves the 'write' index forward to catch up with 'processed', and
 792  * also updates the memory address in the firmware to reference the new
 793  * target buffer.
 794  */
 795 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
 796 {
 797         struct iwl_rx_queue *rxq = &priv->rxq;
 798         struct list_head *element;
 799         struct iwl_rx_mem_buffer *rxb;
 800         unsigned long flags;
 801
 802         spin_lock_irqsave(&rxq->lock, flags);
 803         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 804                 /* The overwritten rxb must be a used one */
 805                 rxb = rxq->queue[rxq->write];
 806                 BUG_ON(rxb && rxb->page);
 807
 808                 /* Get next free Rx buffer, remove from free list */
 809                 element = rxq->rx_free.next;
 810                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 811                 list_del(element);
 812
 813                 /* Point to Rx buffer via next RBD in circular buffer */
 814                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
 815                                                               rxb->page_dma);
 816                 rxq->queue[rxq->write] = rxb;
 817                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 818                 rxq->free_count--;
 819         }
 820         spin_unlock_irqrestore(&rxq->lock, flags);
 821         /* If the pre-allocated buffer pool is dropping low, schedule to
 822          * refill it */
 823         if (rxq->free_count <= RX_LOW_WATERMARK)
 824                 queue_work(priv->workqueue, &priv->rx_replenish);
 825
 826
 827         /* If we've added more space for the firmware to place data, tell it.
 828          * Increment device's write pointer in multiples of 8. */
 829         if (rxq->write_actual != (rxq->write & ~0x7)) {
 830                 spin_lock_irqsave(&rxq->lock, flags);
 831                 rxq->need_update = 1;
 832                 spin_unlock_irqrestore(&rxq->lock, flags);
 833                 iwl_rx_queue_update_write_ptr(priv, rxq);
 834         }
 835 }
 836
 837 /**
 838  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 839  *
 840  * When moving to rx_free an SKB is allocated for the slot.
 841  *
 842  * Also restock the Rx queue via iwl_rx_queue_restock.
 843  * This is called as a scheduled work item (except for during initialization)
 844  */
 845 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
 846 {
 847         struct iwl_rx_queue *rxq = &priv->rxq;
 848         struct list_head *element;
 849         struct iwl_rx_mem_buffer *rxb;
 850         struct page *page;
 851         unsigned long flags;
 852         gfp_t gfp_mask = priority;
 853
 854         while (1) {
 855                 spin_lock_irqsave(&rxq->lock, flags);
 856                 if (list_empty(&rxq->rx_used)) {
 857                         spin_unlock_irqrestore(&rxq->lock, flags);
 858                         return;
 859                 }
 860                 spin_unlock_irqrestore(&rxq->lock, flags);
 861
 862                 if (rxq->free_count > RX_LOW_WATERMARK)
 863                         gfp_mask |= __GFP_NOWARN;
 864
 865                 if (priv->hw_params.rx_page_order > 0)
 866                         gfp_mask |= __GFP_COMP;
 867
 868                 /* Alloc a new receive buffer */
 869                 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
 870                 if (!page) {
 871                         if (net_ratelimit())
 872                                 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
 873                                                "order: %d\n",
 874                                                priv->hw_params.rx_page_order);
 875
 876                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 877                             net_ratelimit())
 878                                 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
 879                                          priority == GFP_ATOMIC ?  "GFP_ATOMIC" : "GFP_KERNEL",
 880                                          rxq->free_count);
 881                         /* We don't reschedule replenish work here -- we will
 882                          * call the restock method and if it still needs
 883                          * more buffers it will schedule replenish */
 884                         return;
 885                 }
 886
 887                 spin_lock_irqsave(&rxq->lock, flags);
 888
 889                 if (list_empty(&rxq->rx_used)) {
 890                         spin_unlock_irqrestore(&rxq->lock, flags);
 891                         __free_pages(page, priv->hw_params.rx_page_order);
 892                         return;
 893                 }
 894                 element = rxq->rx_used.next;
 895                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 896                 list_del(element);
 897
 898                 spin_unlock_irqrestore(&rxq->lock, flags);
 899
 900                 BUG_ON(rxb->page);
 901                 rxb->page = page;
 902                 /* Get physical address of the RB */
 903                 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
 904                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 905                                 PCI_DMA_FROMDEVICE);
 906                 /* dma address must be no more than 36 bits */
 907                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 908                 /* and also 256 byte aligned! */
 909                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 910
 911                 spin_lock_irqsave(&rxq->lock, flags);
 912
 913                 list_add_tail(&rxb->list, &rxq->rx_free);
 914                 rxq->free_count++;
 915                 priv->alloc_rxb_page++;
 916
 917                 spin_unlock_irqrestore(&rxq->lock, flags);
 918         }
 919 }
 920
 921 void iwlagn_rx_replenish(struct iwl_priv *priv)
 922 {
 923         unsigned long flags;
 924
 925         iwlagn_rx_allocate(priv, GFP_KERNEL);
 926
 927         spin_lock_irqsave(&priv->lock, flags);
 928         iwlagn_rx_queue_restock(priv);
 929         spin_unlock_irqrestore(&priv->lock, flags);
 930 }
 931
 932 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
 933 {
 934         iwlagn_rx_allocate(priv, GFP_ATOMIC);
 935
 936         iwlagn_rx_queue_restock(priv);
 937 }
 938
 939 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
 940  * If an SKB has been detached, the POOL needs to have its SKB set to NULL
 941  * This free routine walks the list of POOL entries and if SKB is set to
 942  * non NULL it is unmapped and freed
 943  */
 944 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 945 {
 946         int i;
 947         for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
 948                 if (rxq->pool[i].page != NULL) {
 949                         pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
 950                                 PAGE_SIZE << priv->hw_params.rx_page_order,
 951                                 PCI_DMA_FROMDEVICE);
 952                         __iwl_free_pages(priv, rxq->pool[i].page);
 953                         rxq->pool[i].page = NULL;
 954                 }
 955         }
 956
 957         dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
 958                           rxq->bd_dma);
 959         dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
 960                           rxq->rb_stts, rxq->rb_stts_dma);
 961         rxq->bd = NULL;
 962         rxq->rb_stts  = NULL;
 963 }
 964
 965 int iwlagn_rxq_stop(struct iwl_priv *priv)
 966 {
 967
 968         /* stop Rx DMA */
 969         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 970         iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
 971                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 972
 973         return 0;
 974 }
 975
 976 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
 977 {
 978         int idx = 0;
 979         int band_offset = 0;
 980
 981         /* HT rate format: mac80211 wants an MCS number, which is just LSB */
 982         if (rate_n_flags & RATE_MCS_HT_MSK) {
 983                 idx = (rate_n_flags & 0xff);
 984                 return idx;
 985         /* Legacy rate format, search for match in table */
 986         } else {
 987                 if (band == IEEE80211_BAND_5GHZ)
 988                         band_offset = IWL_FIRST_OFDM_RATE;
 989                 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
 990                         if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
 991                                 return idx - band_offset;
 992         }
 993
 994         return -1;
 995 }
 996
 997 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
 998                                            struct ieee80211_vif *vif,
 999                                            enum ieee80211_band band,
1000                                            struct iwl_scan_channel *scan_ch)
1001 {
1002         const struct ieee80211_supported_band *sband;
1003         u16 passive_dwell = 0;
1004         u16 active_dwell = 0;
1005         int added = 0;
1006         u16 channel = 0;
1007
1008         sband = iwl_get_hw_mode(priv, band);
1009         if (!sband) {
1010                 IWL_ERR(priv, "invalid band\n");
1011                 return added;
1012         }
1013
1014         active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1015         passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1016
1017         if (passive_dwell <= active_dwell)
1018                 passive_dwell = active_dwell + 1;
1019
1020         channel = iwl_get_single_channel_number(priv, band);
1021         if (channel) {
1022                 scan_ch->channel = cpu_to_le16(channel);
1023                 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1024                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1025                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1026                 /* Set txpower levels to defaults */
1027                 scan_ch->dsp_atten = 110;
1028                 if (band == IEEE80211_BAND_5GHZ)
1029                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1030                 else
1031                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1032                 added++;
1033         } else
1034                 IWL_ERR(priv, "no valid channel found\n");
1035         return added;
1036 }
1037
1038 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1039                                      struct ieee80211_vif *vif,
1040                                      enum ieee80211_band band,
1041                                      u8 is_active, u8 n_probes,
1042                                      struct iwl_scan_channel *scan_ch)
1043 {
1044         struct ieee80211_channel *chan;
1045         const struct ieee80211_supported_band *sband;
1046         const struct iwl_channel_info *ch_info;
1047         u16 passive_dwell = 0;
1048         u16 active_dwell = 0;
1049         int added, i;
1050         u16 channel;
1051
1052         sband = iwl_get_hw_mode(priv, band);
1053         if (!sband)
1054                 return 0;
1055
1056         active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1057         passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1058
1059         if (passive_dwell <= active_dwell)
1060                 passive_dwell = active_dwell + 1;
1061
1062         for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1063                 chan = priv->scan_request->channels[i];
1064
1065                 if (chan->band != band)
1066                         continue;
1067
1068                 channel = chan->hw_value;
1069                 scan_ch->channel = cpu_to_le16(channel);
1070
1071                 ch_info = iwl_get_channel_info(priv, band, channel);
1072                 if (!is_channel_valid(ch_info)) {
1073                         IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1074                                         channel);
1075                         continue;
1076                 }
1077
1078                 if (!is_active || is_channel_passive(ch_info) ||
1079                     (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1080                         scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1081                 else
1082                         scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1083
1084                 if (n_probes)
1085                         scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1086
1087                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1088                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1089
1090                 /* Set txpower levels to defaults */
1091                 scan_ch->dsp_atten = 110;
1092
1093                 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1094                  * power level:
1095                  * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1096                  */
1097                 if (band == IEEE80211_BAND_5GHZ)
1098                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1099                 else
1100                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1101
1102                 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1103                                channel, le32_to_cpu(scan_ch->type),
1104                                (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1105                                 "ACTIVE" : "PASSIVE",
1106                                (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1107                                active_dwell : passive_dwell);
1108
1109                 scan_ch++;
1110                 added++;
1111         }
1112
1113         IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1114         return added;
1115 }
1116
1117 static int iwl_fill_offch_tx(struct iwl_priv *priv, void *data, size_t maxlen)
1118 {
1119         struct sk_buff *skb = priv->_agn.offchan_tx_skb;
1120
1121         if (skb->len < maxlen)
1122                 maxlen = skb->len;
1123
1124         memcpy(data, skb->data, maxlen);
1125
1126         return maxlen;
1127 }
1128
1129 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1130 {
1131         struct iwl_host_cmd cmd = {
1132                 .id = REPLY_SCAN_CMD,
1133                 .len = sizeof(struct iwl_scan_cmd),
1134                 .flags = CMD_SIZE_HUGE,
1135         };
1136         struct iwl_scan_cmd *scan;
1137         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1138         u32 rate_flags = 0;
1139         u16 cmd_len;
1140         u16 rx_chain = 0;
1141         enum ieee80211_band band;
1142         u8 n_probes = 0;
1143         u8 rx_ant = priv->hw_params.valid_rx_ant;
1144         u8 rate;
1145         bool is_active = false;
1146         int  chan_mod;
1147         u8 active_chains;
1148         u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1149         int ret;
1150
1151         lockdep_assert_held(&priv->mutex);
1152
1153         if (vif)
1154                 ctx = iwl_rxon_ctx_from_vif(vif);
1155
1156         if (!priv->scan_cmd) {
1157                 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1158                                          IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1159                 if (!priv->scan_cmd) {
1160                         IWL_DEBUG_SCAN(priv,
1161                                        "fail to allocate memory for scan\n");
1162                         return -ENOMEM;
1163                 }
1164         }
1165         scan = priv->scan_cmd;
1166         memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1167
1168         scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1169         scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1170
1171         if (priv->scan_type != IWL_SCAN_OFFCH_TX &&
1172             iwl_is_any_associated(priv)) {
1173                 u16 interval = 0;
1174                 u32 extra;
1175                 u32 suspend_time = 100;
1176                 u32 scan_suspend_time = 100;
1177
1178                 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1179                 switch (priv->scan_type) {
1180                 case IWL_SCAN_OFFCH_TX:
1181                         WARN_ON(1);
1182                         break;
1183                 case IWL_SCAN_RADIO_RESET:
1184                         interval = 0;
1185                         break;
1186                 case IWL_SCAN_NORMAL:
1187                         interval = vif->bss_conf.beacon_int;
1188                         break;
1189                 }
1190
1191                 scan->suspend_time = 0;
1192                 scan->max_out_time = cpu_to_le32(200 * 1024);
1193                 if (!interval)
1194                         interval = suspend_time;
1195
1196                 extra = (suspend_time / interval) << 22;
1197                 scan_suspend_time = (extra |
1198                     ((suspend_time % interval) * 1024));
1199                 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1200                 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1201                                scan_suspend_time, interval);
1202         } else if (priv->scan_type == IWL_SCAN_OFFCH_TX) {
1203                 scan->suspend_time = 0;
1204                 scan->max_out_time =
1205                         cpu_to_le32(1024 * priv->_agn.offchan_tx_timeout);
1206         }
1207
1208         switch (priv->scan_type) {
1209         case IWL_SCAN_RADIO_RESET:
1210                 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1211                 break;
1212         case IWL_SCAN_NORMAL:
1213                 if (priv->scan_request->n_ssids) {
1214                         int i, p = 0;
1215                         IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1216                         for (i = 0; i < priv->scan_request->n_ssids; i++) {
1217                                 /* always does wildcard anyway */
1218                                 if (!priv->scan_request->ssids[i].ssid_len)
1219                                         continue;
1220                                 scan->direct_scan[p].id = WLAN_EID_SSID;
1221                                 scan->direct_scan[p].len =
1222                                         priv->scan_request->ssids[i].ssid_len;
1223                                 memcpy(scan->direct_scan[p].ssid,
1224                                        priv->scan_request->ssids[i].ssid,
1225                                        priv->scan_request->ssids[i].ssid_len);
1226                                 n_probes++;
1227                                 p++;
1228                         }
1229                         is_active = true;
1230                 } else
1231                         IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1232                 break;
1233         case IWL_SCAN_OFFCH_TX:
1234                 IWL_DEBUG_SCAN(priv, "Start offchannel TX scan.\n");
1235                 break;
1236         }
1237
1238         scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1239         scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1240         scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1241
1242         switch (priv->scan_band) {
1243         case IEEE80211_BAND_2GHZ:
1244                 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1245                 chan_mod = le32_to_cpu(
1246                         priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1247                                                 RXON_FLG_CHANNEL_MODE_MSK)
1248                                        >> RXON_FLG_CHANNEL_MODE_POS;
1249                 if (chan_mod == CHANNEL_MODE_PURE_40) {
1250                         rate = IWL_RATE_6M_PLCP;
1251                 } else {
1252                         rate = IWL_RATE_1M_PLCP;
1253                         rate_flags = RATE_MCS_CCK_MSK;
1254                 }
1255                 /*
1256                  * Internal scans are passive, so we can indiscriminately set
1257                  * the BT ignore flag on 2.4 GHz since it applies to TX only.
1258                  */
1259                 if (priv->cfg->bt_params &&
1260                     priv->cfg->bt_params->advanced_bt_coexist)
1261                         scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1262                 break;
1263         case IEEE80211_BAND_5GHZ:
1264                 rate = IWL_RATE_6M_PLCP;
1265                 break;
1266         default:
1267                 IWL_WARN(priv, "Invalid scan band\n");
1268                 return -EIO;
1269         }
1270
1271         /*
1272          * If active scanning is requested but a certain channel is
1273          * marked passive, we can do active scanning if we detect
1274          * transmissions.
1275          *
1276          * There is an issue with some firmware versions that triggers
1277          * a sysassert on a "good CRC threshold" of zero (== disabled),
1278          * on a radar channel even though this means that we should NOT
1279          * send probes.
1280          *
1281          * The "good CRC threshold" is the number of frames that we
1282          * need to receive during our dwell time on a channel before
1283          * sending out probes -- setting this to a huge value will
1284          * mean we never reach it, but at the same time work around
1285          * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1286          * here instead of IWL_GOOD_CRC_TH_DISABLED.
1287          */
1288         scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1289                                         IWL_GOOD_CRC_TH_NEVER;
1290
1291         band = priv->scan_band;
1292
1293         if (priv->cfg->scan_rx_antennas[band])
1294                 rx_ant = priv->cfg->scan_rx_antennas[band];
1295
1296         if (band == IEEE80211_BAND_2GHZ &&
1297             priv->cfg->bt_params &&
1298             priv->cfg->bt_params->advanced_bt_coexist) {
1299                 /* transmit 2.4 GHz probes only on first antenna */
1300                 scan_tx_antennas = first_antenna(scan_tx_antennas);
1301         }
1302
1303         priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1304                                                     scan_tx_antennas);
1305         rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1306         scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1307
1308         /* In power save mode use one chain, otherwise use all chains */
1309         if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1310                 /* rx_ant has been set to all valid chains previously */
1311                 active_chains = rx_ant &
1312                                 ((u8)(priv->chain_noise_data.active_chains));
1313                 if (!active_chains)
1314                         active_chains = rx_ant;
1315
1316                 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1317                                 priv->chain_noise_data.active_chains);
1318
1319                 rx_ant = first_antenna(active_chains);
1320         }
1321         if (priv->cfg->bt_params &&
1322             priv->cfg->bt_params->advanced_bt_coexist &&
1323             priv->bt_full_concurrent) {
1324                 /* operated as 1x1 in full concurrency mode */
1325                 rx_ant = first_antenna(rx_ant);
1326         }
1327
1328         /* MIMO is not used here, but value is required */
1329         rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1330         rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1331         rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1332         rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1333         scan->rx_chain = cpu_to_le16(rx_chain);
1334         switch (priv->scan_type) {
1335         case IWL_SCAN_NORMAL:
1336                 cmd_len = iwl_fill_probe_req(priv,
1337                                         (struct ieee80211_mgmt *)scan->data,
1338                                         vif->addr,
1339                                         priv->scan_request->ie,
1340                                         priv->scan_request->ie_len,
1341                                         IWL_MAX_SCAN_SIZE - sizeof(*scan));
1342                 break;
1343         case IWL_SCAN_RADIO_RESET:
1344                 /* use bcast addr, will not be transmitted but must be valid */
1345                 cmd_len = iwl_fill_probe_req(priv,
1346                                         (struct ieee80211_mgmt *)scan->data,
1347                                         iwl_bcast_addr, NULL, 0,
1348                                         IWL_MAX_SCAN_SIZE - sizeof(*scan));
1349                 break;
1350         case IWL_SCAN_OFFCH_TX:
1351                 cmd_len = iwl_fill_offch_tx(priv, scan->data,
1352                                             IWL_MAX_SCAN_SIZE
1353                                              - sizeof(*scan)
1354                                              - sizeof(struct iwl_scan_channel));
1355                 scan->scan_flags |= IWL_SCAN_FLAGS_ACTION_FRAME_TX;
1356                 break;
1357         default:
1358                 BUG();
1359         }
1360         scan->tx_cmd.len = cpu_to_le16(cmd_len);
1361
1362         scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1363                                RXON_FILTER_BCON_AWARE_MSK);
1364
1365         switch (priv->scan_type) {
1366         case IWL_SCAN_RADIO_RESET:
1367                 scan->channel_count =
1368                         iwl_get_single_channel_for_scan(priv, vif, band,
1369                                 (void *)&scan->data[cmd_len]);
1370                 break;
1371         case IWL_SCAN_NORMAL:
1372                 scan->channel_count =
1373                         iwl_get_channels_for_scan(priv, vif, band,
1374                                 is_active, n_probes,
1375                                 (void *)&scan->data[cmd_len]);
1376                 break;
1377         case IWL_SCAN_OFFCH_TX: {
1378                 struct iwl_scan_channel *scan_ch;
1379
1380                 scan->channel_count = 1;
1381
1382                 scan_ch = (void *)&scan->data[cmd_len];
1383                 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1384                 scan_ch->channel =
1385                         cpu_to_le16(priv->_agn.offchan_tx_chan->hw_value);
1386                 scan_ch->active_dwell =
1387                         cpu_to_le16(priv->_agn.offchan_tx_timeout);
1388                 scan_ch->passive_dwell = 0;
1389
1390                 /* Set txpower levels to defaults */
1391                 scan_ch->dsp_atten = 110;
1392
1393                 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1394                  * power level:
1395                  * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1396                  */
1397                 if (priv->_agn.offchan_tx_chan->band == IEEE80211_BAND_5GHZ)
1398                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1399                 else
1400                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1401                 }
1402                 break;
1403         }
1404
1405         if (scan->channel_count == 0) {
1406                 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1407                 return -EIO;
1408         }
1409
1410         cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1411             scan->channel_count * sizeof(struct iwl_scan_channel);
1412         cmd.data = scan;
1413         scan->len = cpu_to_le16(cmd.len);
1414
1415         /* set scan bit here for PAN params */
1416         set_bit(STATUS_SCAN_HW, &priv->status);
1417
1418         if (priv->cfg->ops->hcmd->set_pan_params) {
1419                 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1420                 if (ret)
1421                         return ret;
1422         }
1423
1424         ret = iwl_send_cmd_sync(priv, &cmd);
1425         if (ret) {
1426                 clear_bit(STATUS_SCAN_HW, &priv->status);
1427                 if (priv->cfg->ops->hcmd->set_pan_params)
1428                         priv->cfg->ops->hcmd->set_pan_params(priv);
1429         }
1430
1431         return ret;
1432 }
1433
1434 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1435                                struct ieee80211_vif *vif, bool add)
1436 {
1437         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1438
1439         if (add)
1440                 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1441                                                 vif->bss_conf.bssid,
1442                                                 &vif_priv->ibss_bssid_sta_id);
1443         return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1444                                   vif->bss_conf.bssid);
1445 }
1446
1447 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1448                             int sta_id, int tid, int freed)
1449 {
1450         lockdep_assert_held(&priv->sta_lock);
1451
1452         if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1453                 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1454         else {
1455                 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1456                         priv->stations[sta_id].tid[tid].tfds_in_queue,
1457                         freed);
1458                 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1459         }
1460 }
1461
1462 #define IWL_FLUSH_WAIT_MS       2000
1463
1464 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1465 {
1466         struct iwl_tx_queue *txq;
1467         struct iwl_queue *q;
1468         int cnt;
1469         unsigned long now = jiffies;
1470         int ret = 0;
1471
1472         /* waiting for all the tx frames complete might take a while */
1473         for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1474                 if (cnt == priv->cmd_queue)
1475                         continue;
1476                 txq = &priv->txq[cnt];
1477                 q = &txq->q;
1478                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1479                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1480                                 msleep(1);
1481
1482                 if (q->read_ptr != q->write_ptr) {
1483                         IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1484                         ret = -ETIMEDOUT;
1485                         break;
1486                 }
1487         }
1488         return ret;
1489 }
1490
1491 #define IWL_TX_QUEUE_MSK        0xfffff
1492
1493 /**
1494  * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1495  *
1496  * pre-requirements:
1497  *  1. acquire mutex before calling
1498  *  2. make sure rf is on and not in exit state
1499  */
1500 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1501 {
1502         struct iwl_txfifo_flush_cmd flush_cmd;
1503         struct iwl_host_cmd cmd = {
1504                 .id = REPLY_TXFIFO_FLUSH,
1505                 .len = sizeof(struct iwl_txfifo_flush_cmd),
1506                 .flags = CMD_SYNC,
1507                 .data = &flush_cmd,
1508         };
1509
1510         might_sleep();
1511
1512         memset(&flush_cmd, 0, sizeof(flush_cmd));
1513         flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1514                                  IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1515         if (priv->cfg->sku & IWL_SKU_N)
1516                 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1517
1518         IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1519                        flush_cmd.fifo_control);
1520         flush_cmd.flush_control = cpu_to_le16(flush_control);
1521
1522         return iwl_send_cmd(priv, &cmd);
1523 }
1524
1525 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1526 {
1527         mutex_lock(&priv->mutex);
1528         ieee80211_stop_queues(priv->hw);
1529         if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1530                 IWL_ERR(priv, "flush request fail\n");
1531                 goto done;
1532         }
1533         IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1534         iwlagn_wait_tx_queue_empty(priv);
1535 done:
1536         ieee80211_wake_queues(priv->hw);
1537         mutex_unlock(&priv->mutex);
1538 }
1539
1540 /*
1541  * BT coex
1542  */
1543 /*
1544  * Macros to access the lookup table.
1545  *
1546  * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1547 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1548  *
1549  * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1550  *
1551  * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1552  * one after another in 32-bit registers, and "registers" 0 through 7 contain
1553  * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1554  *
1555  * These macros encode that format.
1556  */
1557 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1558                   wifi_txrx, wifi_sh_ant_req) \
1559         (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1560         (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1561
1562 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1563         lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1564 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1565                                  wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1566         (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1567                                    bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1568                                    wifi_sh_ant_req))))
1569 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1570                                 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1571         LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1572                                bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1573                                wifi_sh_ant_req))
1574 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1575                                   wifi_req, wifi_prio, wifi_txrx, \
1576                                   wifi_sh_ant_req) \
1577         LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1578                                bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1579                                wifi_sh_ant_req))
1580
1581 #define LUT_WLAN_KILL_OP(lut, op, val) \
1582         lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1583 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1584                            wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1585         (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1586                              wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1587 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1588                           wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1589         LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1590                          wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1591 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1592                             wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1593         LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1594                          wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1595
1596 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1597         lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1598 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1599                             wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1600         (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1601                               wifi_req, wifi_prio, wifi_txrx, \
1602                               wifi_sh_ant_req))))
1603 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1604                            wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1605         LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1606                           wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1607 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1608                              wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1609         LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1610                           wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1611
1612 static const __le32 iwlagn_def_3w_lookup[12] = {
1613         cpu_to_le32(0xaaaaaaaa),
1614         cpu_to_le32(0xaaaaaaaa),
1615         cpu_to_le32(0xaeaaaaaa),
1616         cpu_to_le32(0xaaaaaaaa),
1617         cpu_to_le32(0xcc00ff28),
1618         cpu_to_le32(0x0000aaaa),
1619         cpu_to_le32(0xcc00aaaa),
1620         cpu_to_le32(0x0000aaaa),
1621         cpu_to_le32(0xc0004000),
1622         cpu_to_le32(0x00004000),
1623         cpu_to_le32(0xf0005000),
1624         cpu_to_le32(0xf0005000),
1625 };
1626
1627 static const __le32 iwlagn_concurrent_lookup[12] = {
1628         cpu_to_le32(0xaaaaaaaa),
1629         cpu_to_le32(0xaaaaaaaa),
1630         cpu_to_le32(0xaaaaaaaa),
1631         cpu_to_le32(0xaaaaaaaa),
1632         cpu_to_le32(0xaaaaaaaa),
1633         cpu_to_le32(0xaaaaaaaa),
1634         cpu_to_le32(0xaaaaaaaa),
1635         cpu_to_le32(0xaaaaaaaa),
1636         cpu_to_le32(0x00000000),
1637         cpu_to_le32(0x00000000),
1638         cpu_to_le32(0x00000000),
1639         cpu_to_le32(0x00000000),
1640 };
1641
1642 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1643 {
1644         struct iwl_basic_bt_cmd basic = {
1645                 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1646                 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1647                 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1648                 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1649         };
1650         struct iwl6000_bt_cmd bt_cmd_6000;
1651         struct iwl2000_bt_cmd bt_cmd_2000;
1652         int ret;
1653
1654         BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1655                         sizeof(basic.bt3_lookup_table));
1656
1657         if (priv->cfg->bt_params) {
1658                 if (priv->cfg->bt_params->bt_session_2) {
1659                         bt_cmd_2000.prio_boost = cpu_to_le32(
1660                                 priv->cfg->bt_params->bt_prio_boost);
1661                         bt_cmd_2000.tx_prio_boost = 0;
1662                         bt_cmd_2000.rx_prio_boost = 0;
1663                 } else {
1664                         bt_cmd_6000.prio_boost =
1665                                 priv->cfg->bt_params->bt_prio_boost;
1666                         bt_cmd_6000.tx_prio_boost = 0;
1667                         bt_cmd_6000.rx_prio_boost = 0;
1668                 }
1669         } else {
1670                 IWL_ERR(priv, "failed to construct BT Coex Config\n");
1671                 return;
1672         }
1673
1674         basic.kill_ack_mask = priv->kill_ack_mask;
1675         basic.kill_cts_mask = priv->kill_cts_mask;
1676         basic.valid = priv->bt_valid;
1677
1678         /*
1679          * Configure BT coex mode to "no coexistence" when the
1680          * user disabled BT coexistence, we have no interface
1681          * (might be in monitor mode), or the interface is in
1682          * IBSS mode (no proper uCode support for coex then).
1683          */
1684         if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1685                 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_DISABLED;
1686         } else {
1687                 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1688                                         IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1689                 if (priv->cfg->bt_params &&
1690                     priv->cfg->bt_params->bt_sco_disable)
1691                         basic.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1692
1693                 if (priv->bt_ch_announce)
1694                         basic.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1695                 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", basic.flags);
1696         }
1697         priv->bt_enable_flag = basic.flags;
1698         if (priv->bt_full_concurrent)
1699                 memcpy(basic.bt3_lookup_table, iwlagn_concurrent_lookup,
1700                         sizeof(iwlagn_concurrent_lookup));
1701         else
1702                 memcpy(basic.bt3_lookup_table, iwlagn_def_3w_lookup,
1703                         sizeof(iwlagn_def_3w_lookup));
1704
1705         IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1706                        basic.flags ? "active" : "disabled",
1707                        priv->bt_full_concurrent ?
1708                        "full concurrency" : "3-wire");
1709
1710         if (priv->cfg->bt_params->bt_session_2) {
1711                 memcpy(&bt_cmd_2000.basic, &basic,
1712                         sizeof(basic));
1713                 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1714                         sizeof(bt_cmd_2000), &bt_cmd_2000);
1715         } else {
1716                 memcpy(&bt_cmd_6000.basic, &basic,
1717                         sizeof(basic));
1718                 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1719                         sizeof(bt_cmd_6000), &bt_cmd_6000);
1720         }
1721         if (ret)
1722                 IWL_ERR(priv, "failed to send BT Coex Config\n");
1723
1724 }
1725
1726 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1727 {
1728         struct iwl_priv *priv =
1729                 container_of(work, struct iwl_priv, bt_traffic_change_work);
1730         struct iwl_rxon_context *ctx;
1731         int smps_request = -1;
1732
1733         if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1734                 /* bt coex disabled */
1735                 return;
1736         }
1737
1738         /*
1739          * Note: bt_traffic_load can be overridden by scan complete and
1740          * coex profile notifications. Ignore that since only bad consequence
1741          * can be not matching debug print with actual state.
1742          */
1743         IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1744                        priv->bt_traffic_load);
1745
1746         switch (priv->bt_traffic_load) {
1747         case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1748                 if (priv->bt_status)
1749                         smps_request = IEEE80211_SMPS_DYNAMIC;
1750                 else
1751                         smps_request = IEEE80211_SMPS_AUTOMATIC;
1752                 break;
1753         case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1754                 smps_request = IEEE80211_SMPS_DYNAMIC;
1755                 break;
1756         case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1757         case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1758                 smps_request = IEEE80211_SMPS_STATIC;
1759                 break;
1760         default:
1761                 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1762                         priv->bt_traffic_load);
1763                 break;
1764         }
1765
1766         mutex_lock(&priv->mutex);
1767
1768         /*
1769          * We can not send command to firmware while scanning. When the scan
1770          * complete we will schedule this work again. We do check with mutex
1771          * locked to prevent new scan request to arrive. We do not check
1772          * STATUS_SCANNING to avoid race when queue_work two times from
1773          * different notifications, but quit and not perform any work at all.
1774          */
1775         if (test_bit(STATUS_SCAN_HW, &priv->status))
1776                 goto out;
1777
1778         if (priv->cfg->ops->lib->update_chain_flags)
1779                 priv->cfg->ops->lib->update_chain_flags(priv);
1780
1781         if (smps_request != -1) {
1782                 for_each_context(priv, ctx) {
1783                         if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1784                                 ieee80211_request_smps(ctx->vif, smps_request);
1785                 }
1786         }
1787 out:
1788         mutex_unlock(&priv->mutex);
1789 }
1790
1791 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1792                                 struct iwl_bt_uart_msg *uart_msg)
1793 {
1794         IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1795                         "Update Req = 0x%X",
1796                 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1797                         BT_UART_MSG_FRAME1MSGTYPE_POS,
1798                 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1799                         BT_UART_MSG_FRAME1SSN_POS,
1800                 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1801                         BT_UART_MSG_FRAME1UPDATEREQ_POS);
1802
1803         IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1804                         "Chl_SeqN = 0x%X, In band = 0x%X",
1805                 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1806                         BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1807                 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1808                         BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1809                 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1810                         BT_UART_MSG_FRAME2CHLSEQN_POS,
1811                 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1812                         BT_UART_MSG_FRAME2INBAND_POS);
1813
1814         IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1815                         "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1816                 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1817                         BT_UART_MSG_FRAME3SCOESCO_POS,
1818                 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1819                         BT_UART_MSG_FRAME3SNIFF_POS,
1820                 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1821                         BT_UART_MSG_FRAME3A2DP_POS,
1822                 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1823                         BT_UART_MSG_FRAME3ACL_POS,
1824                 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1825                         BT_UART_MSG_FRAME3MASTER_POS,
1826                 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1827                         BT_UART_MSG_FRAME3OBEX_POS);
1828
1829         IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1830                 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1831                         BT_UART_MSG_FRAME4IDLEDURATION_POS);
1832
1833         IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1834                         "eSCO Retransmissions = 0x%X",
1835                 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1836                         BT_UART_MSG_FRAME5TXACTIVITY_POS,
1837                 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1838                         BT_UART_MSG_FRAME5RXACTIVITY_POS,
1839                 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1840                         BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1841
1842         IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1843                 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1844                         BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1845                 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1846                         BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1847
1848         IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Page = "
1849                         "0x%X, Inquiry = 0x%X, Connectable = 0x%X",
1850                 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1851                         BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1852                 (BT_UART_MSG_FRAME7PAGE_MSK & uart_msg->frame7) >>
1853                         BT_UART_MSG_FRAME7PAGE_POS,
1854                 (BT_UART_MSG_FRAME7INQUIRY_MSK & uart_msg->frame7) >>
1855                         BT_UART_MSG_FRAME7INQUIRY_POS,
1856                 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1857                         BT_UART_MSG_FRAME7CONNECTABLE_POS);
1858 }
1859
1860 static void iwlagn_set_kill_msk(struct iwl_priv *priv,
1861                                 struct iwl_bt_uart_msg *uart_msg)
1862 {
1863         u8 kill_msk;
1864         static const __le32 bt_kill_ack_msg[2] = {
1865                 IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
1866                 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1867         static const __le32 bt_kill_cts_msg[2] = {
1868                 IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
1869                 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1870
1871         kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
1872                 ? 1 : 0;
1873         if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
1874             priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
1875                 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
1876                 priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
1877                 priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
1878                 priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
1879
1880                 /* schedule to send runtime bt_config */
1881                 queue_work(priv->workqueue, &priv->bt_runtime_config);
1882         }
1883 }
1884
1885 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1886                                              struct iwl_rx_mem_buffer *rxb)
1887 {
1888         unsigned long flags;
1889         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1890         struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
1891         struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
1892
1893         if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1894                 /* bt coex disabled */
1895                 return;
1896         }
1897
1898         IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
1899         IWL_DEBUG_NOTIF(priv, "    status: %d\n", coex->bt_status);
1900         IWL_DEBUG_NOTIF(priv, "    traffic load: %d\n", coex->bt_traffic_load);
1901         IWL_DEBUG_NOTIF(priv, "    CI compliance: %d\n",
1902                         coex->bt_ci_compliance);
1903         iwlagn_print_uartmsg(priv, uart_msg);
1904
1905         priv->last_bt_traffic_load = priv->bt_traffic_load;
1906         if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
1907                 if (priv->bt_status != coex->bt_status ||
1908                     priv->last_bt_traffic_load != coex->bt_traffic_load) {
1909                         if (coex->bt_status) {
1910                                 /* BT on */
1911                                 if (!priv->bt_ch_announce)
1912                                         priv->bt_traffic_load =
1913                                                 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
1914                                 else
1915                                         priv->bt_traffic_load =
1916                                                 coex->bt_traffic_load;
1917                         } else {
1918                                 /* BT off */
1919                                 priv->bt_traffic_load =
1920                                         IWL_BT_COEX_TRAFFIC_LOAD_NONE;
1921                         }
1922                         priv->bt_status = coex->bt_status;
1923                         queue_work(priv->workqueue,
1924                                    &priv->bt_traffic_change_work);
1925                 }
1926         }
1927
1928         iwlagn_set_kill_msk(priv, uart_msg);
1929
1930         /* FIXME: based on notification, adjust the prio_boost */
1931
1932         spin_lock_irqsave(&priv->lock, flags);
1933         priv->bt_ci_compliance = coex->bt_ci_compliance;
1934         spin_unlock_irqrestore(&priv->lock, flags);
1935 }
1936
1937 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
1938 {
1939         iwlagn_rx_handler_setup(priv);
1940         priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
1941                 iwlagn_bt_coex_profile_notif;
1942 }
1943
1944 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
1945 {
1946         iwlagn_setup_deferred_work(priv);
1947
1948         INIT_WORK(&priv->bt_traffic_change_work,
1949                   iwlagn_bt_traffic_change_work);
1950 }
1951
1952 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
1953 {
1954         cancel_work_sync(&priv->bt_traffic_change_work);
1955 }
1956
1957 static bool is_single_rx_stream(struct iwl_priv *priv)
1958 {
1959         return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1960                priv->current_ht_config.single_chain_sufficient;
1961 }
1962
1963 #define IWL_NUM_RX_CHAINS_MULTIPLE      3
1964 #define IWL_NUM_RX_CHAINS_SINGLE        2
1965 #define IWL_NUM_IDLE_CHAINS_DUAL        2
1966 #define IWL_NUM_IDLE_CHAINS_SINGLE      1
1967
1968 /*
1969  * Determine how many receiver/antenna chains to use.
1970  *
1971  * More provides better reception via diversity.  Fewer saves power
1972  * at the expense of throughput, but only when not in powersave to
1973  * start with.
1974  *
1975  * MIMO (dual stream) requires at least 2, but works better with 3.
1976  * This does not determine *which* chains to use, just how many.
1977  */
1978 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
1979 {
1980         if (priv->cfg->bt_params &&
1981             priv->cfg->bt_params->advanced_bt_coexist &&
1982             (priv->bt_full_concurrent ||
1983              priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
1984                 /*
1985                  * only use chain 'A' in bt high traffic load or
1986                  * full concurrency mode
1987                  */
1988                 return IWL_NUM_RX_CHAINS_SINGLE;
1989         }
1990         /* # of Rx chains to use when expecting MIMO. */
1991         if (is_single_rx_stream(priv))
1992                 return IWL_NUM_RX_CHAINS_SINGLE;
1993         else
1994                 return IWL_NUM_RX_CHAINS_MULTIPLE;
1995 }
1996
1997 /*
1998  * When we are in power saving mode, unless device support spatial
1999  * multiplexing power save, use the active count for rx chain count.
2000  */
2001 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
2002 {
2003         /* # Rx chains when idling, depending on SMPS mode */
2004         switch (priv->current_ht_config.smps) {
2005         case IEEE80211_SMPS_STATIC:
2006         case IEEE80211_SMPS_DYNAMIC:
2007                 return IWL_NUM_IDLE_CHAINS_SINGLE;
2008         case IEEE80211_SMPS_OFF:
2009                 return active_cnt;
2010         default:
2011                 WARN(1, "invalid SMPS mode %d",
2012                      priv->current_ht_config.smps);
2013                 return active_cnt;
2014         }
2015 }
2016
2017 /* up to 4 chains */
2018 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
2019 {
2020         u8 res;
2021         res = (chain_bitmap & BIT(0)) >> 0;
2022         res += (chain_bitmap & BIT(1)) >> 1;
2023         res += (chain_bitmap & BIT(2)) >> 2;
2024         res += (chain_bitmap & BIT(3)) >> 3;
2025         return res;
2026 }
2027
2028 /**
2029  * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2030  *
2031  * Selects how many and which Rx receivers/antennas/chains to use.
2032  * This should not be used for scan command ... it puts data in wrong place.
2033  */
2034 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2035 {
2036         bool is_single = is_single_rx_stream(priv);
2037         bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
2038         u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
2039         u32 active_chains;
2040         u16 rx_chain;
2041
2042         /* Tell uCode which antennas are actually connected.
2043          * Before first association, we assume all antennas are connected.
2044          * Just after first association, iwl_chain_noise_calibration()
2045          *    checks which antennas actually *are* connected. */
2046         if (priv->chain_noise_data.active_chains)
2047                 active_chains = priv->chain_noise_data.active_chains;
2048         else
2049                 active_chains = priv->hw_params.valid_rx_ant;
2050
2051         if (priv->cfg->bt_params &&
2052             priv->cfg->bt_params->advanced_bt_coexist &&
2053             (priv->bt_full_concurrent ||
2054              priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2055                 /*
2056                  * only use chain 'A' in bt high traffic load or
2057                  * full concurrency mode
2058                  */
2059                 active_chains = first_antenna(active_chains);
2060         }
2061
2062         rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2063
2064         /* How many receivers should we use? */
2065         active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2066         idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2067
2068
2069         /* correct rx chain count according hw settings
2070          * and chain noise calibration
2071          */
2072         valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2073         if (valid_rx_cnt < active_rx_cnt)
2074                 active_rx_cnt = valid_rx_cnt;
2075
2076         if (valid_rx_cnt < idle_rx_cnt)
2077                 idle_rx_cnt = valid_rx_cnt;
2078
2079         rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2080         rx_chain |= idle_rx_cnt  << RXON_RX_CHAIN_CNT_POS;
2081
2082         ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2083
2084         if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2085                 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2086         else
2087                 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2088
2089         IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2090                         ctx->staging.rx_chain,
2091                         active_rx_cnt, idle_rx_cnt);
2092
2093         WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2094                 active_rx_cnt < idle_rx_cnt);
2095 }
2096
2097 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2098 {
2099         int i;
2100         u8 ind = ant;
2101
2102         if (priv->band == IEEE80211_BAND_2GHZ &&
2103             priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2104                 return 0;
2105
2106         for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2107                 ind = (ind + 1) < RATE_ANT_NUM ?  ind + 1 : 0;
2108                 if (valid & BIT(ind))
2109                         return ind;
2110         }
2111         return ant;
2112 }
2113
2114 static const char *get_csr_string(int cmd)
2115 {
2116         switch (cmd) {
2117         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2118         IWL_CMD(CSR_INT_COALESCING);
2119         IWL_CMD(CSR_INT);
2120         IWL_CMD(CSR_INT_MASK);
2121         IWL_CMD(CSR_FH_INT_STATUS);
2122         IWL_CMD(CSR_GPIO_IN);
2123         IWL_CMD(CSR_RESET);
2124         IWL_CMD(CSR_GP_CNTRL);
2125         IWL_CMD(CSR_HW_REV);
2126         IWL_CMD(CSR_EEPROM_REG);
2127         IWL_CMD(CSR_EEPROM_GP);
2128         IWL_CMD(CSR_OTP_GP_REG);
2129         IWL_CMD(CSR_GIO_REG);
2130         IWL_CMD(CSR_GP_UCODE_REG);
2131         IWL_CMD(CSR_GP_DRIVER_REG);
2132         IWL_CMD(CSR_UCODE_DRV_GP1);
2133         IWL_CMD(CSR_UCODE_DRV_GP2);
2134         IWL_CMD(CSR_LED_REG);
2135         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2136         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2137         IWL_CMD(CSR_ANA_PLL_CFG);
2138         IWL_CMD(CSR_HW_REV_WA_REG);
2139         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2140         default:
2141                 return "UNKNOWN";
2142         }
2143 }
2144
2145 void iwl_dump_csr(struct iwl_priv *priv)
2146 {
2147         int i;
2148         static const u32 csr_tbl[] = {
2149                 CSR_HW_IF_CONFIG_REG,
2150                 CSR_INT_COALESCING,
2151                 CSR_INT,
2152                 CSR_INT_MASK,
2153                 CSR_FH_INT_STATUS,
2154                 CSR_GPIO_IN,
2155                 CSR_RESET,
2156                 CSR_GP_CNTRL,
2157                 CSR_HW_REV,
2158                 CSR_EEPROM_REG,
2159                 CSR_EEPROM_GP,
2160                 CSR_OTP_GP_REG,
2161                 CSR_GIO_REG,
2162                 CSR_GP_UCODE_REG,
2163                 CSR_GP_DRIVER_REG,
2164                 CSR_UCODE_DRV_GP1,
2165                 CSR_UCODE_DRV_GP2,
2166                 CSR_LED_REG,
2167                 CSR_DRAM_INT_TBL_REG,
2168                 CSR_GIO_CHICKEN_BITS,
2169                 CSR_ANA_PLL_CFG,
2170                 CSR_HW_REV_WA_REG,
2171                 CSR_DBG_HPET_MEM_REG
2172         };
2173         IWL_ERR(priv, "CSR values:\n");
2174         IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2175                 "CSR_INT_PERIODIC_REG)\n");
2176         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2177                 IWL_ERR(priv, "  %25s: 0X%08x\n",
2178                         get_csr_string(csr_tbl[i]),
2179                         iwl_read32(priv, csr_tbl[i]));
2180         }
2181 }
2182
2183 static const char *get_fh_string(int cmd)
2184 {
2185         switch (cmd) {
2186         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2187         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2188         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2189         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2190         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2191         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2192         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2193         IWL_CMD(FH_TSSR_TX_STATUS_REG);
2194         IWL_CMD(FH_TSSR_TX_ERROR_REG);
2195         default:
2196                 return "UNKNOWN";
2197         }
2198 }
2199
2200 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2201 {
2202         int i;
2203 #ifdef CONFIG_IWLWIFI_DEBUG
2204         int pos = 0;
2205         size_t bufsz = 0;
2206 #endif
2207         static const u32 fh_tbl[] = {
2208                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2209                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2210                 FH_RSCSR_CHNL0_WPTR,
2211                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2212                 FH_MEM_RSSR_SHARED_CTRL_REG,
2213                 FH_MEM_RSSR_RX_STATUS_REG,
2214                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2215                 FH_TSSR_TX_STATUS_REG,
2216                 FH_TSSR_TX_ERROR_REG
2217         };
2218 #ifdef CONFIG_IWLWIFI_DEBUG
2219         if (display) {
2220                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2221                 *buf = kmalloc(bufsz, GFP_KERNEL);
2222                 if (!*buf)
2223                         return -ENOMEM;
2224                 pos += scnprintf(*buf + pos, bufsz - pos,
2225                                 "FH register values:\n");
2226                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2227                         pos += scnprintf(*buf + pos, bufsz - pos,
2228                                 "  %34s: 0X%08x\n",
2229                                 get_fh_string(fh_tbl[i]),
2230                                 iwl_read_direct32(priv, fh_tbl[i]));
2231                 }
2232                 return pos;
2233         }
2234 #endif
2235         IWL_ERR(priv, "FH register values:\n");
2236         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
2237                 IWL_ERR(priv, "  %34s: 0X%08x\n",
2238                         get_fh_string(fh_tbl[i]),
2239                         iwl_read_direct32(priv, fh_tbl[i]));
2240         }
2241         return 0;
2242 }
2243
2244 /* notification wait support */
2245 void iwlagn_init_notification_wait(struct iwl_priv *priv,
2246                                    struct iwl_notification_wait *wait_entry,
2247                                    void (*fn)(struct iwl_priv *priv,
2248                                               struct iwl_rx_packet *pkt),
2249                                    u8 cmd)
2250 {
2251         wait_entry->fn = fn;
2252         wait_entry->cmd = cmd;
2253         wait_entry->triggered = false;
2254
2255         spin_lock_bh(&priv->_agn.notif_wait_lock);
2256         list_add(&wait_entry->list, &priv->_agn.notif_waits);
2257         spin_unlock_bh(&priv->_agn.notif_wait_lock);
2258 }
2259
2260 signed long iwlagn_wait_notification(struct iwl_priv *priv,
2261                                      struct iwl_notification_wait *wait_entry,
2262                                      unsigned long timeout)
2263 {
2264         int ret;
2265
2266         ret = wait_event_timeout(priv->_agn.notif_waitq,
2267                                  wait_entry->triggered,
2268                                  timeout);
2269
2270         spin_lock_bh(&priv->_agn.notif_wait_lock);
2271         list_del(&wait_entry->list);
2272         spin_unlock_bh(&priv->_agn.notif_wait_lock);
2273
2274         return ret;
2275 }
2276
2277 void iwlagn_remove_notification(struct iwl_priv *priv,
2278                                 struct iwl_notification_wait *wait_entry)
2279 {
2280         spin_lock_bh(&priv->_agn.notif_wait_lock);
2281         list_del(&wait_entry->list);
2282         spin_unlock_bh(&priv->_agn.notif_wait_lock);
2283 }