drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <linux/firmware.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39 #include <net/mac80211.h>
  40
  41 #include "iwl-fh.h"
  42 #include "iwl-3945-fh.h"
  43 #include "iwl-commands.h"
  44 #include "iwl-sta.h"
  45 #include "iwl-3945.h"
  46 #include "iwl-eeprom.h"
  47 #include "iwl-helpers.h"
  48 #include "iwl-core.h"
  49 #include "iwl-agn-rs.h"
  50
  51 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  52         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  53                                     IWL_RATE_##r##M_IEEE,   \
  54                                     IWL_RATE_##ip##M_INDEX, \
  55                                     IWL_RATE_##in##M_INDEX, \
  56                                     IWL_RATE_##rp##M_INDEX, \
  57                                     IWL_RATE_##rn##M_INDEX, \
  58                                     IWL_RATE_##pp##M_INDEX, \
  59                                     IWL_RATE_##np##M_INDEX, \
  60                                     IWL_RATE_##r##M_INDEX_TABLE, \
  61                                     IWL_RATE_##ip##M_INDEX_TABLE }
  62
  63 /*
  64  * Parameter order:
  65  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  66  *
  67  * If there isn't a valid next or previous rate then INV is used which
  68  * maps to IWL_RATE_INVALID
  69  *
  70  */
  71 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  72         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  73         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  74         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  75         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  76         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  77         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  78         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  79         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  80         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  81         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  82         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  83         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  84 };
  85
  86 /* 1 = enable the iwl3945_disable_events() function */
  87 #define IWL_EVT_DISABLE (0)
  88 #define IWL_EVT_DISABLE_SIZE (1532/32)
  89
  90 /**
  91  * iwl3945_disable_events - Disable selected events in uCode event log
  92  *
  93  * Disable an event by writing "1"s into "disable"
  94  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  95  *   Default values of 0 enable uCode events to be logged.
  96  * Use for only special debugging.  This function is just a placeholder as-is,
  97  *   you'll need to provide the special bits! ...
  98  *   ... and set IWL_EVT_DISABLE to 1. */
  99 void iwl3945_disable_events(struct iwl_priv *priv)
 100 {
 101         int ret;
 102         int i;
 103         u32 base;               /* SRAM address of event log header */
 104         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 105         u32 array_size;         /* # of u32 entries in array */
 106         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 107                 0x00000000,     /*   31 -    0  Event id numbers */
 108                 0x00000000,     /*   63 -   32 */
 109                 0x00000000,     /*   95 -   64 */
 110                 0x00000000,     /*  127 -   96 */
 111                 0x00000000,     /*  159 -  128 */
 112                 0x00000000,     /*  191 -  160 */
 113                 0x00000000,     /*  223 -  192 */
 114                 0x00000000,     /*  255 -  224 */
 115                 0x00000000,     /*  287 -  256 */
 116                 0x00000000,     /*  319 -  288 */
 117                 0x00000000,     /*  351 -  320 */
 118                 0x00000000,     /*  383 -  352 */
 119                 0x00000000,     /*  415 -  384 */
 120                 0x00000000,     /*  447 -  416 */
 121                 0x00000000,     /*  479 -  448 */
 122                 0x00000000,     /*  511 -  480 */
 123                 0x00000000,     /*  543 -  512 */
 124                 0x00000000,     /*  575 -  544 */
 125                 0x00000000,     /*  607 -  576 */
 126                 0x00000000,     /*  639 -  608 */
 127                 0x00000000,     /*  671 -  640 */
 128                 0x00000000,     /*  703 -  672 */
 129                 0x00000000,     /*  735 -  704 */
 130                 0x00000000,     /*  767 -  736 */
 131                 0x00000000,     /*  799 -  768 */
 132                 0x00000000,     /*  831 -  800 */
 133                 0x00000000,     /*  863 -  832 */
 134                 0x00000000,     /*  895 -  864 */
 135                 0x00000000,     /*  927 -  896 */
 136                 0x00000000,     /*  959 -  928 */
 137                 0x00000000,     /*  991 -  960 */
 138                 0x00000000,     /* 1023 -  992 */
 139                 0x00000000,     /* 1055 - 1024 */
 140                 0x00000000,     /* 1087 - 1056 */
 141                 0x00000000,     /* 1119 - 1088 */
 142                 0x00000000,     /* 1151 - 1120 */
 143                 0x00000000,     /* 1183 - 1152 */
 144                 0x00000000,     /* 1215 - 1184 */
 145                 0x00000000,     /* 1247 - 1216 */
 146                 0x00000000,     /* 1279 - 1248 */
 147                 0x00000000,     /* 1311 - 1280 */
 148                 0x00000000,     /* 1343 - 1312 */
 149                 0x00000000,     /* 1375 - 1344 */
 150                 0x00000000,     /* 1407 - 1376 */
 151                 0x00000000,     /* 1439 - 1408 */
 152                 0x00000000,     /* 1471 - 1440 */
 153                 0x00000000,     /* 1503 - 1472 */
 154         };
 155
 156         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 157         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 158                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 159                 return;
 160         }
 161
 162         ret = iwl_grab_nic_access(priv);
 163         if (ret) {
 164                 IWL_WARN(priv, "Can not read from adapter at this time.\n");
 165                 return;
 166         }
 167
 168         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 169         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 170         iwl_release_nic_access(priv);
 171
 172         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 173                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
 174                                disable_ptr);
 175                 ret = iwl_grab_nic_access(priv);
 176                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 177                         iwl_write_targ_mem(priv,
 178                                            disable_ptr + (i * sizeof(u32)),
 179                                            evt_disable[i]);
 180
 181                 iwl_release_nic_access(priv);
 182         } else {
 183                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
 184                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
 185                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
 186                                disable_ptr, array_size);
 187         }
 188
 189 }
 190
 191 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 192 {
 193         int idx;
 194
 195         for (idx = 0; idx < IWL_RATE_COUNT; idx++)
 196                 if (iwl3945_rates[idx].plcp == plcp)
 197                         return idx;
 198         return -1;
 199 }
 200
 201 #ifdef CONFIG_IWLWIFI_DEBUG
 202 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
 203
 204 static const char *iwl3945_get_tx_fail_reason(u32 status)
 205 {
 206         switch (status & TX_STATUS_MSK) {
 207         case TX_STATUS_SUCCESS:
 208                 return "SUCCESS";
 209                 TX_STATUS_ENTRY(SHORT_LIMIT);
 210                 TX_STATUS_ENTRY(LONG_LIMIT);
 211                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 212                 TX_STATUS_ENTRY(MGMNT_ABORT);
 213                 TX_STATUS_ENTRY(NEXT_FRAG);
 214                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 215                 TX_STATUS_ENTRY(DEST_PS);
 216                 TX_STATUS_ENTRY(ABORTED);
 217                 TX_STATUS_ENTRY(BT_RETRY);
 218                 TX_STATUS_ENTRY(STA_INVALID);
 219                 TX_STATUS_ENTRY(FRAG_DROPPED);
 220                 TX_STATUS_ENTRY(TID_DISABLE);
 221                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 222                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 223                 TX_STATUS_ENTRY(TX_LOCKED);
 224                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 225         }
 226
 227         return "UNKNOWN";
 228 }
 229 #else
 230 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 231 {
 232         return "";
 233 }
 234 #endif
 235
 236 /*
 237  * get ieee prev rate from rate scale table.
 238  * for A and B mode we need to overright prev
 239  * value
 240  */
 241 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 242 {
 243         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 244
 245         switch (priv->band) {
 246         case IEEE80211_BAND_5GHZ:
 247                 if (rate == IWL_RATE_12M_INDEX)
 248                         next_rate = IWL_RATE_9M_INDEX;
 249                 else if (rate == IWL_RATE_6M_INDEX)
 250                         next_rate = IWL_RATE_6M_INDEX;
 251                 break;
 252         case IEEE80211_BAND_2GHZ:
 253                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 254                     iwl_is_associated(priv)) {
 255                         if (rate == IWL_RATE_11M_INDEX)
 256                                 next_rate = IWL_RATE_5M_INDEX;
 257                 }
 258                 break;
 259
 260         default:
 261                 break;
 262         }
 263
 264         return next_rate;
 265 }
 266
 267
 268 /**
 269  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 270  *
 271  * When FW advances 'R' index, all entries between old and new 'R' index
 272  * need to be reclaimed. As result, some free space forms. If there is
 273  * enough free space (> low mark), wake the stack that feeds us.
 274  */
 275 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 276                                      int txq_id, int index)
 277 {
 278         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 279         struct iwl_queue *q = &txq->q;
 280         struct iwl_tx_info *tx_info;
 281
 282         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 283
 284         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 285                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 286
 287                 tx_info = &txq->txb[txq->q.read_ptr];
 288                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
 289                 tx_info->skb[0] = NULL;
 290                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 291         }
 292
 293         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 294                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 295                         priv->mac80211_registered)
 296                 iwl_wake_queue(priv, txq_id);
 297 }
 298
 299 /**
 300  * iwl3945_rx_reply_tx - Handle Tx response
 301  */
 302 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 303                             struct iwl_rx_mem_buffer *rxb)
 304 {
 305         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 306         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 307         int txq_id = SEQ_TO_QUEUE(sequence);
 308         int index = SEQ_TO_INDEX(sequence);
 309         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 310         struct ieee80211_tx_info *info;
 311         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 312         u32  status = le32_to_cpu(tx_resp->status);
 313         int rate_idx;
 314         int fail;
 315
 316         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 317                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 318                           "is out of range [0-%d] %d %d\n", txq_id,
 319                           index, txq->q.n_bd, txq->q.write_ptr,
 320                           txq->q.read_ptr);
 321                 return;
 322         }
 323
 324         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
 325         ieee80211_tx_info_clear_status(info);
 326
 327         /* Fill the MRR chain with some info about on-chip retransmissions */
 328         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 329         if (info->band == IEEE80211_BAND_5GHZ)
 330                 rate_idx -= IWL_FIRST_OFDM_RATE;
 331
 332         fail = tx_resp->failure_frame;
 333
 334         info->status.rates[0].idx = rate_idx;
 335         info->status.rates[0].count = fail + 1; /* add final attempt */
 336
 337         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 338         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 339                                 IEEE80211_TX_STAT_ACK : 0;
 340
 341         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 342                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 343                         tx_resp->rate, tx_resp->failure_frame);
 344
 345         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
 346         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 347
 348         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 349                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 350 }
 351
 352
 353
 354 /*****************************************************************************
 355  *
 356  * Intel PRO/Wireless 3945ABG/BG Network Connection
 357  *
 358  *  RX handler implementations
 359  *
 360  *****************************************************************************/
 361
 362 void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
 363 {
 364         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 365         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
 366                      (int)sizeof(struct iwl3945_notif_statistics),
 367                      le32_to_cpu(pkt->len));
 368
 369         memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
 370
 371         iwl3945_led_background(priv);
 372
 373         priv->last_statistics_time = jiffies;
 374 }
 375
 376 /******************************************************************************
 377  *
 378  * Misc. internal state and helper functions
 379  *
 380  ******************************************************************************/
 381 #ifdef CONFIG_IWLWIFI_DEBUG
 382
 383 /**
 384  * iwl3945_report_frame - dump frame to syslog during debug sessions
 385  *
 386  * You may hack this function to show different aspects of received frames,
 387  * including selective frame dumps.
 388  * group100 parameter selects whether to show 1 out of 100 good frames.
 389  */
 390 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
 391                       struct iwl_rx_packet *pkt,
 392                       struct ieee80211_hdr *header, int group100)
 393 {
 394         u32 to_us;
 395         u32 print_summary = 0;
 396         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
 397         u32 hundred = 0;
 398         u32 dataframe = 0;
 399         __le16 fc;
 400         u16 seq_ctl;
 401         u16 channel;
 402         u16 phy_flags;
 403         u16 length;
 404         u16 status;
 405         u16 bcn_tmr;
 406         u32 tsf_low;
 407         u64 tsf;
 408         u8 rssi;
 409         u8 agc;
 410         u16 sig_avg;
 411         u16 noise_diff;
 412         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 413         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 414         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 415         u8 *data = IWL_RX_DATA(pkt);
 416
 417         /* MAC header */
 418         fc = header->frame_control;
 419         seq_ctl = le16_to_cpu(header->seq_ctrl);
 420
 421         /* metadata */
 422         channel = le16_to_cpu(rx_hdr->channel);
 423         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
 424         length = le16_to_cpu(rx_hdr->len);
 425
 426         /* end-of-frame status and timestamp */
 427         status = le32_to_cpu(rx_end->status);
 428         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
 429         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
 430         tsf = le64_to_cpu(rx_end->timestamp);
 431
 432         /* signal statistics */
 433         rssi = rx_stats->rssi;
 434         agc = rx_stats->agc;
 435         sig_avg = le16_to_cpu(rx_stats->sig_avg);
 436         noise_diff = le16_to_cpu(rx_stats->noise_diff);
 437
 438         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
 439
 440         /* if data frame is to us and all is good,
 441          *   (optionally) print summary for only 1 out of every 100 */
 442         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
 443             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
 444                 dataframe = 1;
 445                 if (!group100)
 446                         print_summary = 1;      /* print each frame */
 447                 else if (priv->framecnt_to_us < 100) {
 448                         priv->framecnt_to_us++;
 449                         print_summary = 0;
 450                 } else {
 451                         priv->framecnt_to_us = 0;
 452                         print_summary = 1;
 453                         hundred = 1;
 454                 }
 455         } else {
 456                 /* print summary for all other frames */
 457                 print_summary = 1;
 458         }
 459
 460         if (print_summary) {
 461                 char *title;
 462                 int rate;
 463
 464                 if (hundred)
 465                         title = "100Frames";
 466                 else if (ieee80211_has_retry(fc))
 467                         title = "Retry";
 468                 else if (ieee80211_is_assoc_resp(fc))
 469                         title = "AscRsp";
 470                 else if (ieee80211_is_reassoc_resp(fc))
 471                         title = "RasRsp";
 472                 else if (ieee80211_is_probe_resp(fc)) {
 473                         title = "PrbRsp";
 474                         print_dump = 1; /* dump frame contents */
 475                 } else if (ieee80211_is_beacon(fc)) {
 476                         title = "Beacon";
 477                         print_dump = 1; /* dump frame contents */
 478                 } else if (ieee80211_is_atim(fc))
 479                         title = "ATIM";
 480                 else if (ieee80211_is_auth(fc))
 481                         title = "Auth";
 482                 else if (ieee80211_is_deauth(fc))
 483                         title = "DeAuth";
 484                 else if (ieee80211_is_disassoc(fc))
 485                         title = "DisAssoc";
 486                 else
 487                         title = "Frame";
 488
 489                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 490                 if (rate == -1)
 491                         rate = 0;
 492                 else
 493                         rate = iwl3945_rates[rate].ieee / 2;
 494
 495                 /* print frame summary.
 496                  * MAC addresses show just the last byte (for brevity),
 497                  *    but you can hack it to show more, if you'd like to. */
 498                 if (dataframe)
 499                         IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
 500                                      "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
 501                                      title, le16_to_cpu(fc), header->addr1[5],
 502                                      length, rssi, channel, rate);
 503                 else {
 504                         /* src/dst addresses assume managed mode */
 505                         IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
 506                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
 507                                      "phy=0x%02x, chnl=%d\n",
 508                                      title, le16_to_cpu(fc), header->addr1[5],
 509                                      header->addr3[5], rssi,
 510                                      tsf_low - priv->scan_start_tsf,
 511                                      phy_flags, channel);
 512                 }
 513         }
 514         if (print_dump)
 515                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
 516 }
 517
 518 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 519                       struct iwl_rx_packet *pkt,
 520                       struct ieee80211_hdr *header, int group100)
 521 {
 522         if (priv->debug_level & IWL_DL_RX)
 523                 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
 524 }
 525
 526 #else
 527 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 528                       struct iwl_rx_packet *pkt,
 529                       struct ieee80211_hdr *header, int group100)
 530 {
 531 }
 532 #endif
 533
 534 /* This is necessary only for a number of statistics, see the caller. */
 535 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 536                 struct ieee80211_hdr *header)
 537 {
 538         /* Filter incoming packets to determine if they are targeted toward
 539          * this network, discarding packets coming from ourselves */
 540         switch (priv->iw_mode) {
 541         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 542                 /* packets to our IBSS update information */
 543                 return !compare_ether_addr(header->addr3, priv->bssid);
 544         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 545                 /* packets to our IBSS update information */
 546                 return !compare_ether_addr(header->addr2, priv->bssid);
 547         default:
 548                 return 1;
 549         }
 550 }
 551
 552 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 553                                    struct iwl_rx_mem_buffer *rxb,
 554                                    struct ieee80211_rx_status *stats)
 555 {
 556         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
 557 #ifdef CONFIG_IWLWIFI_LEDS
 558         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 559 #endif
 560         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 561         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 562         short len = le16_to_cpu(rx_hdr->len);
 563
 564         /* We received data from the HW, so stop the watchdog */
 565         if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
 566                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
 567                 return;
 568         }
 569
 570         /* We only process data packets if the interface is open */
 571         if (unlikely(!priv->is_open)) {
 572                 IWL_DEBUG_DROP_LIMIT(priv,
 573                         "Dropping packet while interface is not open.\n");
 574                 return;
 575         }
 576
 577         skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
 578         /* Set the size of the skb to the size of the frame */
 579         skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
 580
 581         if (!iwl3945_mod_params.sw_crypto)
 582                 iwl_set_decrypted_flag(priv,
 583                                        (struct ieee80211_hdr *)rxb->skb->data,
 584                                        le32_to_cpu(rx_end->status), stats);
 585
 586 #ifdef CONFIG_IWLWIFI_LEDS
 587         if (ieee80211_is_data(hdr->frame_control))
 588                 priv->rxtxpackets += len;
 589 #endif
 590         ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
 591         rxb->skb = NULL;
 592 }
 593
 594 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 595
 596 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 597                                 struct iwl_rx_mem_buffer *rxb)
 598 {
 599         struct ieee80211_hdr *header;
 600         struct ieee80211_rx_status rx_status;
 601         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 602         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 603         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 604         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 605         int snr;
 606         u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
 607         u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
 608         u8 network_packet;
 609
 610         rx_status.flag = 0;
 611         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 612         rx_status.freq =
 613                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 614         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 615                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 616
 617         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 618         if (rx_status.band == IEEE80211_BAND_5GHZ)
 619                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 620
 621         rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
 622                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 623
 624         /* set the preamble flag if appropriate */
 625         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 626                 rx_status.flag |= RX_FLAG_SHORTPRE;
 627
 628         if ((unlikely(rx_stats->phy_count > 20))) {
 629                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
 630                                 rx_stats->phy_count);
 631                 return;
 632         }
 633
 634         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 635             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 636                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 637                 return;
 638         }
 639
 640
 641
 642         /* Convert 3945's rssi indicator to dBm */
 643         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 644
 645         /* Set default noise value to -127 */
 646         if (priv->last_rx_noise == 0)
 647                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
 648
 649         /* 3945 provides noise info for OFDM frames only.
 650          * sig_avg and noise_diff are measured by the 3945's digital signal
 651          *   processor (DSP), and indicate linear levels of signal level and
 652          *   distortion/noise within the packet preamble after
 653          *   automatic gain control (AGC).  sig_avg should stay fairly
 654          *   constant if the radio's AGC is working well.
 655          * Since these values are linear (not dB or dBm), linear
 656          *   signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
 657          * Convert linear SNR to dB SNR, then subtract that from rssi dBm
 658          *   to obtain noise level in dBm.
 659          * Calculate rx_status.signal (quality indicator in %) based on SNR. */
 660         if (rx_stats_noise_diff) {
 661                 snr = rx_stats_sig_avg / rx_stats_noise_diff;
 662                 rx_status.noise = rx_status.signal -
 663                                         iwl3945_calc_db_from_ratio(snr);
 664                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
 665                                                          rx_status.noise);
 666
 667         /* If noise info not available, calculate signal quality indicator (%)
 668          *   using just the dBm signal level. */
 669         } else {
 670                 rx_status.noise = priv->last_rx_noise;
 671                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
 672         }
 673
 674
 675         IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
 676                         rx_status.signal, rx_status.noise, rx_status.qual,
 677                         rx_stats_sig_avg, rx_stats_noise_diff);
 678
 679         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 680
 681         network_packet = iwl3945_is_network_packet(priv, header);
 682
 683         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
 684                               network_packet ? '*' : ' ',
 685                               le16_to_cpu(rx_hdr->channel),
 686                               rx_status.signal, rx_status.signal,
 687                               rx_status.noise, rx_status.rate_idx);
 688
 689         /* Set "1" to report good data frames in groups of 100 */
 690         iwl3945_dbg_report_frame(priv, pkt, header, 1);
 691
 692         if (network_packet) {
 693                 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
 694                 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
 695                 priv->last_rx_rssi = rx_status.signal;
 696                 priv->last_rx_noise = rx_status.noise;
 697         }
 698
 699         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 700 }
 701
 702 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 703                                      struct iwl_tx_queue *txq,
 704                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 705 {
 706         int count;
 707         struct iwl_queue *q;
 708         struct iwl3945_tfd *tfd, *tfd_tmp;
 709
 710         q = &txq->q;
 711         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 712         tfd = &tfd_tmp[q->write_ptr];
 713
 714         if (reset)
 715                 memset(tfd, 0, sizeof(*tfd));
 716
 717         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 718
 719         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 720                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 721                           NUM_TFD_CHUNKS);
 722                 return -EINVAL;
 723         }
 724
 725         tfd->tbs[count].addr = cpu_to_le32(addr);
 726         tfd->tbs[count].len = cpu_to_le32(len);
 727
 728         count++;
 729
 730         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 731                                          TFD_CTL_PAD_SET(pad));
 732
 733         return 0;
 734 }
 735
 736 /**
 737  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 738  *
 739  * Does NOT advance any indexes
 740  */
 741 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 742 {
 743         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 744         int index = txq->q.read_ptr;
 745         struct iwl3945_tfd *tfd = &tfd_tmp[index];
 746         struct pci_dev *dev = priv->pci_dev;
 747         int i;
 748         int counter;
 749
 750         /* sanity check */
 751         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 752         if (counter > NUM_TFD_CHUNKS) {
 753                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 754                 /* @todo issue fatal error, it is quite serious situation */
 755                 return;
 756         }
 757
 758         /* Unmap tx_cmd */
 759         if (counter)
 760                 pci_unmap_single(dev,
 761                                 pci_unmap_addr(&txq->cmd[index]->meta, mapping),
 762                                 pci_unmap_len(&txq->cmd[index]->meta, len),
 763                                 PCI_DMA_TODEVICE);
 764
 765         /* unmap chunks if any */
 766
 767         for (i = 1; i < counter; i++) {
 768                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 769                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 770                 if (txq->txb[txq->q.read_ptr].skb[0]) {
 771                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
 772                         if (txq->txb[txq->q.read_ptr].skb[0]) {
 773                                 /* Can be called from interrupt context */
 774                                 dev_kfree_skb_any(skb);
 775                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
 776                         }
 777                 }
 778         }
 779         return ;
 780 }
 781
 782 u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
 783 {
 784         int i, start = IWL_AP_ID;
 785         int ret = IWL_INVALID_STATION;
 786         unsigned long flags;
 787
 788         if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
 789             (priv->iw_mode == NL80211_IFTYPE_AP))
 790                 start = IWL_STA_ID;
 791
 792         if (is_broadcast_ether_addr(addr))
 793                 return priv->hw_params.bcast_sta_id;
 794
 795         spin_lock_irqsave(&priv->sta_lock, flags);
 796         for (i = start; i < priv->hw_params.max_stations; i++)
 797                 if ((priv->stations_39[i].used) &&
 798                     (!compare_ether_addr
 799                      (priv->stations_39[i].sta.sta.addr, addr))) {
 800                         ret = i;
 801                         goto out;
 802                 }
 803
 804         IWL_DEBUG_INFO(priv, "can not find STA %pM (total %d)\n",
 805                        addr, priv->num_stations);
 806  out:
 807         spin_unlock_irqrestore(&priv->sta_lock, flags);
 808         return ret;
 809 }
 810
 811 /**
 812  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 813  *
 814 */
 815 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
 816                               struct ieee80211_tx_info *info,
 817                               struct ieee80211_hdr *hdr, int sta_id, int tx_id)
 818 {
 819         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 820         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
 821         u16 rate_mask;
 822         int rate;
 823         u8 rts_retry_limit;
 824         u8 data_retry_limit;
 825         __le32 tx_flags;
 826         __le16 fc = hdr->frame_control;
 827         struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 828
 829         rate = iwl3945_rates[rate_index].plcp;
 830         tx_flags = tx->tx_flags;
 831
 832         /* We need to figure out how to get the sta->supp_rates while
 833          * in this running context */
 834         rate_mask = IWL_RATES_MASK;
 835
 836         if (tx_id >= IWL_CMD_QUEUE_NUM)
 837                 rts_retry_limit = 3;
 838         else
 839                 rts_retry_limit = 7;
 840
 841         if (ieee80211_is_probe_resp(fc)) {
 842                 data_retry_limit = 3;
 843                 if (data_retry_limit < rts_retry_limit)
 844                         rts_retry_limit = data_retry_limit;
 845         } else
 846                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 847
 848         if (priv->data_retry_limit != -1)
 849                 data_retry_limit = priv->data_retry_limit;
 850
 851         if (ieee80211_is_mgmt(fc)) {
 852                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 853                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 854                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 855                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 856                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 857                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 858                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 859                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 860                         }
 861                         break;
 862                 default:
 863                         break;
 864                 }
 865         }
 866
 867         tx->rts_retry_limit = rts_retry_limit;
 868         tx->data_retry_limit = data_retry_limit;
 869         tx->rate = rate;
 870         tx->tx_flags = tx_flags;
 871
 872         /* OFDM */
 873         tx->supp_rates[0] =
 874            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 875
 876         /* CCK */
 877         tx->supp_rates[1] = (rate_mask & 0xF);
 878
 879         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 880                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 881                        tx->rate, le32_to_cpu(tx->tx_flags),
 882                        tx->supp_rates[1], tx->supp_rates[0]);
 883 }
 884
 885 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
 886 {
 887         unsigned long flags_spin;
 888         struct iwl3945_station_entry *station;
 889
 890         if (sta_id == IWL_INVALID_STATION)
 891                 return IWL_INVALID_STATION;
 892
 893         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 894         station = &priv->stations_39[sta_id];
 895
 896         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 897         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 898         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 899
 900         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 901
 902         iwl_send_add_sta(priv,
 903                          (struct iwl_addsta_cmd *)&station->sta, flags);
 904         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
 905                         sta_id, tx_rate);
 906         return sta_id;
 907 }
 908
 909 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 910 {
 911         int ret;
 912         unsigned long flags;
 913
 914         spin_lock_irqsave(&priv->lock, flags);
 915         ret = iwl_grab_nic_access(priv);
 916         if (ret) {
 917                 spin_unlock_irqrestore(&priv->lock, flags);
 918                 return ret;
 919         }
 920
 921         if (src == IWL_PWR_SRC_VAUX) {
 922                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
 923                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 924                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 925                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 926                         iwl_release_nic_access(priv);
 927
 928                         iwl_poll_bit(priv, CSR_GPIO_IN,
 929                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 930                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 931                 } else {
 932                         iwl_release_nic_access(priv);
 933                 }
 934         } else {
 935                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 936                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 937                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 938
 939                 iwl_release_nic_access(priv);
 940                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 941                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 942         }
 943         spin_unlock_irqrestore(&priv->lock, flags);
 944
 945         return ret;
 946 }
 947
 948 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 949 {
 950         int rc;
 951         unsigned long flags;
 952
 953         spin_lock_irqsave(&priv->lock, flags);
 954         rc = iwl_grab_nic_access(priv);
 955         if (rc) {
 956                 spin_unlock_irqrestore(&priv->lock, flags);
 957                 return rc;
 958         }
 959
 960         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
 961         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 962         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 963         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 964                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 965                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 966                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 967                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 968                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 969                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 970                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 971                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 972
 973         /* fake read to flush all prev I/O */
 974         iwl_read_direct32(priv, FH39_RSSR_CTRL);
 975
 976         iwl_release_nic_access(priv);
 977         spin_unlock_irqrestore(&priv->lock, flags);
 978
 979         return 0;
 980 }
 981
 982 static int iwl3945_tx_reset(struct iwl_priv *priv)
 983 {
 984         int rc;
 985         unsigned long flags;
 986
 987         spin_lock_irqsave(&priv->lock, flags);
 988         rc = iwl_grab_nic_access(priv);
 989         if (rc) {
 990                 spin_unlock_irqrestore(&priv->lock, flags);
 991                 return rc;
 992         }
 993
 994         /* bypass mode */
 995         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
 996
 997         /* RA 0 is active */
 998         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
 999
1000         /* all 6 fifo are active */
1001         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
1002
1003         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1004         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1005         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1006         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
1007
1008         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
1009                              priv->shared_phys);
1010
1011         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
1012                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1013                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1014                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1015                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1016                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1017                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1018                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1019
1020         iwl_release_nic_access(priv);
1021         spin_unlock_irqrestore(&priv->lock, flags);
1022
1023         return 0;
1024 }
1025
1026 /**
1027  * iwl3945_txq_ctx_reset - Reset TX queue context
1028  *
1029  * Destroys all DMA structures and initialize them again
1030  */
1031 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
1032 {
1033         int rc;
1034         int txq_id, slots_num;
1035
1036         iwl3945_hw_txq_ctx_free(priv);
1037
1038         /* Tx CMD queue */
1039         rc = iwl3945_tx_reset(priv);
1040         if (rc)
1041                 goto error;
1042
1043         /* Tx queue(s) */
1044         for (txq_id = 0; txq_id <= priv->hw_params.max_txq_num; txq_id++) {
1045                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1046                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1047                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1048                                        txq_id);
1049                 if (rc) {
1050                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1051                         goto error;
1052                 }
1053         }
1054
1055         return rc;
1056
1057  error:
1058         iwl3945_hw_txq_ctx_free(priv);
1059         return rc;
1060 }
1061
1062 static int iwl3945_apm_init(struct iwl_priv *priv)
1063 {
1064         int ret = 0;
1065
1066         iwl_power_initialize(priv);
1067
1068         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1069                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1070
1071         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1072         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1073                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1074
1075         /* set "initialization complete" bit to move adapter
1076         * D0U* --> D0A* state */
1077         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1078
1079         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1080                             CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1081         if (ret < 0) {
1082                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1083                 goto out;
1084         }
1085
1086         ret = iwl_grab_nic_access(priv);
1087         if (ret)
1088                 goto out;
1089
1090         /* enable DMA */
1091         iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1092                                                 APMG_CLK_VAL_BSM_CLK_RQT);
1093
1094         udelay(20);
1095
1096         /* disable L1-Active */
1097         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1098                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1099
1100         iwl_release_nic_access(priv);
1101 out:
1102         return ret;
1103 }
1104
1105 static void iwl3945_nic_config(struct iwl_priv *priv)
1106 {
1107         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1108         unsigned long flags;
1109         u8 rev_id = 0;
1110
1111         spin_lock_irqsave(&priv->lock, flags);
1112
1113         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1114                 IWL_DEBUG_INFO(priv, "RTP type \n");
1115         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1116                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1117                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1118                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1119         } else {
1120                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1121                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1122                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1123         }
1124
1125         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1126                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1127                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1128                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1129         } else
1130                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1131
1132         if ((eeprom->board_revision & 0xF0) == 0xD0) {
1133                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1134                                eeprom->board_revision);
1135                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1136                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1137         } else {
1138                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1139                                eeprom->board_revision);
1140                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1141                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1142         }
1143
1144         if (eeprom->almgor_m_version <= 1) {
1145                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1146                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1147                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1148                                eeprom->almgor_m_version);
1149         } else {
1150                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1151                                eeprom->almgor_m_version);
1152                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1153                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1154         }
1155         spin_unlock_irqrestore(&priv->lock, flags);
1156
1157         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1158                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1159
1160         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1161                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1162 }
1163
1164 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1165 {
1166         u8 rev_id;
1167         int rc;
1168         unsigned long flags;
1169         struct iwl_rx_queue *rxq = &priv->rxq;
1170
1171         spin_lock_irqsave(&priv->lock, flags);
1172         priv->cfg->ops->lib->apm_ops.init(priv);
1173         spin_unlock_irqrestore(&priv->lock, flags);
1174
1175         /* Determine HW type */
1176         rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1177         if (rc)
1178                 return rc;
1179         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1180
1181         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1182         if (rc)
1183                 return rc;
1184
1185         priv->cfg->ops->lib->apm_ops.config(priv);
1186
1187         /* Allocate the RX queue, or reset if it is already allocated */
1188         if (!rxq->bd) {
1189                 rc = iwl_rx_queue_alloc(priv);
1190                 if (rc) {
1191                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1192                         return -ENOMEM;
1193                 }
1194         } else
1195                 iwl3945_rx_queue_reset(priv, rxq);
1196
1197         iwl3945_rx_replenish(priv);
1198
1199         iwl3945_rx_init(priv, rxq);
1200
1201         spin_lock_irqsave(&priv->lock, flags);
1202
1203         /* Look at using this instead:
1204         rxq->need_update = 1;
1205         iwl_rx_queue_update_write_ptr(priv, rxq);
1206         */
1207
1208         rc = iwl_grab_nic_access(priv);
1209         if (rc) {
1210                 spin_unlock_irqrestore(&priv->lock, flags);
1211                 return rc;
1212         }
1213         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1214         iwl_release_nic_access(priv);
1215
1216         spin_unlock_irqrestore(&priv->lock, flags);
1217
1218         rc = iwl3945_txq_ctx_reset(priv);
1219         if (rc)
1220                 return rc;
1221
1222         set_bit(STATUS_INIT, &priv->status);
1223
1224         return 0;
1225 }
1226
1227 /**
1228  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1229  *
1230  * Destroy all TX DMA queues and structures
1231  */
1232 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1233 {
1234         int txq_id;
1235
1236         /* Tx queues */
1237         for (txq_id = 0; txq_id <= priv->hw_params.max_txq_num; txq_id++)
1238                 if (txq_id == IWL_CMD_QUEUE_NUM)
1239                         iwl_cmd_queue_free(priv);
1240                 else
1241                         iwl_tx_queue_free(priv, txq_id);
1242
1243 }
1244
1245 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1246 {
1247         int txq_id;
1248         unsigned long flags;
1249
1250         spin_lock_irqsave(&priv->lock, flags);
1251         if (iwl_grab_nic_access(priv)) {
1252                 spin_unlock_irqrestore(&priv->lock, flags);
1253                 iwl3945_hw_txq_ctx_free(priv);
1254                 return;
1255         }
1256
1257         /* stop SCD */
1258         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1259
1260         /* reset TFD queues */
1261         for (txq_id = 0; txq_id <= priv->hw_params.max_txq_num; txq_id++) {
1262                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1263                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1264                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1265                                 1000);
1266         }
1267
1268         iwl_release_nic_access(priv);
1269         spin_unlock_irqrestore(&priv->lock, flags);
1270
1271         iwl3945_hw_txq_ctx_free(priv);
1272 }
1273
1274 static int iwl3945_apm_stop_master(struct iwl_priv *priv)
1275 {
1276         int ret = 0;
1277         unsigned long flags;
1278
1279         spin_lock_irqsave(&priv->lock, flags);
1280
1281         /* set stop master bit */
1282         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1283
1284         iwl_poll_direct_bit(priv, CSR_RESET,
1285                             CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1286
1287         if (ret < 0)
1288                 goto out;
1289
1290 out:
1291         spin_unlock_irqrestore(&priv->lock, flags);
1292         IWL_DEBUG_INFO(priv, "stop master\n");
1293
1294         return ret;
1295 }
1296
1297 static void iwl3945_apm_stop(struct iwl_priv *priv)
1298 {
1299         unsigned long flags;
1300
1301         iwl3945_apm_stop_master(priv);
1302
1303         spin_lock_irqsave(&priv->lock, flags);
1304
1305         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1306
1307         udelay(10);
1308         /* clear "init complete"  move adapter D0A* --> D0U state */
1309         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1310         spin_unlock_irqrestore(&priv->lock, flags);
1311 }
1312
1313 static int iwl3945_apm_reset(struct iwl_priv *priv)
1314 {
1315         int rc;
1316         unsigned long flags;
1317
1318         iwl3945_apm_stop_master(priv);
1319
1320         spin_lock_irqsave(&priv->lock, flags);
1321
1322         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1323         udelay(10);
1324
1325         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1326
1327         iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1328                          CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1329
1330         rc = iwl_grab_nic_access(priv);
1331         if (!rc) {
1332                 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1333                                          APMG_CLK_VAL_BSM_CLK_RQT);
1334
1335                 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1336                 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1337                                         0xFFFFFFFF);
1338
1339                 /* enable DMA */
1340                 iwl_write_prph(priv, APMG_CLK_EN_REG,
1341                                          APMG_CLK_VAL_DMA_CLK_RQT |
1342                                          APMG_CLK_VAL_BSM_CLK_RQT);
1343                 udelay(10);
1344
1345                 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1346                                 APMG_PS_CTRL_VAL_RESET_REQ);
1347                 udelay(5);
1348                 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1349                                 APMG_PS_CTRL_VAL_RESET_REQ);
1350                 iwl_release_nic_access(priv);
1351         }
1352
1353         /* Clear the 'host command active' bit... */
1354         clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1355
1356         wake_up_interruptible(&priv->wait_command_queue);
1357         spin_unlock_irqrestore(&priv->lock, flags);
1358
1359         return rc;
1360 }
1361
1362 /**
1363  * iwl3945_hw_reg_adjust_power_by_temp
1364  * return index delta into power gain settings table
1365 */
1366 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1367 {
1368         return (new_reading - old_reading) * (-11) / 100;
1369 }
1370
1371 /**
1372  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1373  */
1374 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1375 {
1376         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1377 }
1378
1379 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1380 {
1381         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1382 }
1383
1384 /**
1385  * iwl3945_hw_reg_txpower_get_temperature
1386  * get the current temperature by reading from NIC
1387 */
1388 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1389 {
1390         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1391         int temperature;
1392
1393         temperature = iwl3945_hw_get_temperature(priv);
1394
1395         /* driver's okay range is -260 to +25.
1396          *   human readable okay range is 0 to +285 */
1397         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1398
1399         /* handle insane temp reading */
1400         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1401                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1402
1403                 /* if really really hot(?),
1404                  *   substitute the 3rd band/group's temp measured at factory */
1405                 if (priv->last_temperature > 100)
1406                         temperature = eeprom->groups[2].temperature;
1407                 else /* else use most recent "sane" value from driver */
1408                         temperature = priv->last_temperature;
1409         }
1410
1411         return temperature;     /* raw, not "human readable" */
1412 }
1413
1414 /* Adjust Txpower only if temperature variance is greater than threshold.
1415  *
1416  * Both are lower than older versions' 9 degrees */
1417 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1418
1419 /**
1420  * is_temp_calib_needed - determines if new calibration is needed
1421  *
1422  * records new temperature in tx_mgr->temperature.
1423  * replaces tx_mgr->last_temperature *only* if calib needed
1424  *    (assumes caller will actually do the calibration!). */
1425 static int is_temp_calib_needed(struct iwl_priv *priv)
1426 {
1427         int temp_diff;
1428
1429         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1430         temp_diff = priv->temperature - priv->last_temperature;
1431
1432         /* get absolute value */
1433         if (temp_diff < 0) {
1434                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1435                 temp_diff = -temp_diff;
1436         } else if (temp_diff == 0)
1437                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1438         else
1439                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1440
1441         /* if we don't need calibration, *don't* update last_temperature */
1442         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1443                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1444                 return 0;
1445         }
1446
1447         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1448
1449         /* assume that caller will actually do calib ...
1450          *   update the "last temperature" value */
1451         priv->last_temperature = priv->temperature;
1452         return 1;
1453 }
1454
1455 #define IWL_MAX_GAIN_ENTRIES 78
1456 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1457 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1458
1459 /* radio and DSP power table, each step is 1/2 dB.
1460  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1461 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1462         {
1463          {251, 127},            /* 2.4 GHz, highest power */
1464          {251, 127},
1465          {251, 127},
1466          {251, 127},
1467          {251, 125},
1468          {251, 110},
1469          {251, 105},
1470          {251, 98},
1471          {187, 125},
1472          {187, 115},
1473          {187, 108},
1474          {187, 99},
1475          {243, 119},
1476          {243, 111},
1477          {243, 105},
1478          {243, 97},
1479          {243, 92},
1480          {211, 106},
1481          {211, 100},
1482          {179, 120},
1483          {179, 113},
1484          {179, 107},
1485          {147, 125},
1486          {147, 119},
1487          {147, 112},
1488          {147, 106},
1489          {147, 101},
1490          {147, 97},
1491          {147, 91},
1492          {115, 107},
1493          {235, 121},
1494          {235, 115},
1495          {235, 109},
1496          {203, 127},
1497          {203, 121},
1498          {203, 115},
1499          {203, 108},
1500          {203, 102},
1501          {203, 96},
1502          {203, 92},
1503          {171, 110},
1504          {171, 104},
1505          {171, 98},
1506          {139, 116},
1507          {227, 125},
1508          {227, 119},
1509          {227, 113},
1510          {227, 107},
1511          {227, 101},
1512          {227, 96},
1513          {195, 113},
1514          {195, 106},
1515          {195, 102},
1516          {195, 95},
1517          {163, 113},
1518          {163, 106},
1519          {163, 102},
1520          {163, 95},
1521          {131, 113},
1522          {131, 106},
1523          {131, 102},
1524          {131, 95},
1525          {99, 113},
1526          {99, 106},
1527          {99, 102},
1528          {99, 95},
1529          {67, 113},
1530          {67, 106},
1531          {67, 102},
1532          {67, 95},
1533          {35, 113},
1534          {35, 106},
1535          {35, 102},
1536          {35, 95},
1537          {3, 113},
1538          {3, 106},
1539          {3, 102},
1540          {3, 95} },             /* 2.4 GHz, lowest power */
1541         {
1542          {251, 127},            /* 5.x GHz, highest power */
1543          {251, 120},
1544          {251, 114},
1545          {219, 119},
1546          {219, 101},
1547          {187, 113},
1548          {187, 102},
1549          {155, 114},
1550          {155, 103},
1551          {123, 117},
1552          {123, 107},
1553          {123, 99},
1554          {123, 92},
1555          {91, 108},
1556          {59, 125},
1557          {59, 118},
1558          {59, 109},
1559          {59, 102},
1560          {59, 96},
1561          {59, 90},
1562          {27, 104},
1563          {27, 98},
1564          {27, 92},
1565          {115, 118},
1566          {115, 111},
1567          {115, 104},
1568          {83, 126},
1569          {83, 121},
1570          {83, 113},
1571          {83, 105},
1572          {83, 99},
1573          {51, 118},
1574          {51, 111},
1575          {51, 104},
1576          {51, 98},
1577          {19, 116},
1578          {19, 109},
1579          {19, 102},
1580          {19, 98},
1581          {19, 93},
1582          {171, 113},
1583          {171, 107},
1584          {171, 99},
1585          {139, 120},
1586          {139, 113},
1587          {139, 107},
1588          {139, 99},
1589          {107, 120},
1590          {107, 113},
1591          {107, 107},
1592          {107, 99},
1593          {75, 120},
1594          {75, 113},
1595          {75, 107},
1596          {75, 99},
1597          {43, 120},
1598          {43, 113},
1599          {43, 107},
1600          {43, 99},
1601          {11, 120},
1602          {11, 113},
1603          {11, 107},
1604          {11, 99},
1605          {131, 107},
1606          {131, 99},
1607          {99, 120},
1608          {99, 113},
1609          {99, 107},
1610          {99, 99},
1611          {67, 120},
1612          {67, 113},
1613          {67, 107},
1614          {67, 99},
1615          {35, 120},
1616          {35, 113},
1617          {35, 107},
1618          {35, 99},
1619          {3, 120} }             /* 5.x GHz, lowest power */
1620 };
1621
1622 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1623 {
1624         if (index < 0)
1625                 return 0;
1626         if (index >= IWL_MAX_GAIN_ENTRIES)
1627                 return IWL_MAX_GAIN_ENTRIES - 1;
1628         return (u8) index;
1629 }
1630
1631 /* Kick off thermal recalibration check every 60 seconds */
1632 #define REG_RECALIB_PERIOD (60)
1633
1634 /**
1635  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1636  *
1637  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1638  * or 6 Mbit (OFDM) rates.
1639  */
1640 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1641                                s32 rate_index, const s8 *clip_pwrs,
1642                                struct iwl_channel_info *ch_info,
1643                                int band_index)
1644 {
1645         struct iwl3945_scan_power_info *scan_power_info;
1646         s8 power;
1647         u8 power_index;
1648
1649         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1650
1651         /* use this channel group's 6Mbit clipping/saturation pwr,
1652          *   but cap at regulatory scan power restriction (set during init
1653          *   based on eeprom channel data) for this channel.  */
1654         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1655
1656         /* further limit to user's max power preference.
1657          * FIXME:  Other spectrum management power limitations do not
1658          *   seem to apply?? */
1659         power = min(power, priv->tx_power_user_lmt);
1660         scan_power_info->requested_power = power;
1661
1662         /* find difference between new scan *power* and current "normal"
1663          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1664          *   current "normal" temperature-compensated Tx power *index* for
1665          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1666          *   *index*. */
1667         power_index = ch_info->power_info[rate_index].power_table_index
1668             - (power - ch_info->power_info
1669                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1670
1671         /* store reference index that we use when adjusting *all* scan
1672          *   powers.  So we can accommodate user (all channel) or spectrum
1673          *   management (single channel) power changes "between" temperature
1674          *   feedback compensation procedures.
1675          * don't force fit this reference index into gain table; it may be a
1676          *   negative number.  This will help avoid errors when we're at
1677          *   the lower bounds (highest gains, for warmest temperatures)
1678          *   of the table. */
1679
1680         /* don't exceed table bounds for "real" setting */
1681         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1682
1683         scan_power_info->power_table_index = power_index;
1684         scan_power_info->tpc.tx_gain =
1685             power_gain_table[band_index][power_index].tx_gain;
1686         scan_power_info->tpc.dsp_atten =
1687             power_gain_table[band_index][power_index].dsp_atten;
1688 }
1689
1690 /**
1691  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1692  *
1693  * Configures power settings for all rates for the current channel,
1694  * using values from channel info struct, and send to NIC
1695  */
1696 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1697 {
1698         int rate_idx, i;
1699         const struct iwl_channel_info *ch_info = NULL;
1700         struct iwl3945_txpowertable_cmd txpower = {
1701                 .channel = priv->active_rxon.channel,
1702         };
1703
1704         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1705         ch_info = iwl_get_channel_info(priv,
1706                                        priv->band,
1707                                        le16_to_cpu(priv->active_rxon.channel));
1708         if (!ch_info) {
1709                 IWL_ERR(priv,
1710                         "Failed to get channel info for channel %d [%d]\n",
1711                         le16_to_cpu(priv->active_rxon.channel), priv->band);
1712                 return -EINVAL;
1713         }
1714
1715         if (!is_channel_valid(ch_info)) {
1716                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1717                                 "non-Tx channel.\n");
1718                 return 0;
1719         }
1720
1721         /* fill cmd with power settings for all rates for current channel */
1722         /* Fill OFDM rate */
1723         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1724              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1725
1726                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1727                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1728
1729                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1730                                 le16_to_cpu(txpower.channel),
1731                                 txpower.band,
1732                                 txpower.power[i].tpc.tx_gain,
1733                                 txpower.power[i].tpc.dsp_atten,
1734                                 txpower.power[i].rate);
1735         }
1736         /* Fill CCK rates */
1737         for (rate_idx = IWL_FIRST_CCK_RATE;
1738              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1739                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1740                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1741
1742                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1743                                 le16_to_cpu(txpower.channel),
1744                                 txpower.band,
1745                                 txpower.power[i].tpc.tx_gain,
1746                                 txpower.power[i].tpc.dsp_atten,
1747                                 txpower.power[i].rate);
1748         }
1749
1750         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1751                                 sizeof(struct iwl3945_txpowertable_cmd),
1752                                 &txpower);
1753
1754 }
1755
1756 /**
1757  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1758  * @ch_info: Channel to update.  Uses power_info.requested_power.
1759  *
1760  * Replace requested_power and base_power_index ch_info fields for
1761  * one channel.
1762  *
1763  * Called if user or spectrum management changes power preferences.
1764  * Takes into account h/w and modulation limitations (clip power).
1765  *
1766  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1767  *
1768  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1769  *       properly fill out the scan powers, and actual h/w gain settings,
1770  *       and send changes to NIC
1771  */
1772 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1773                              struct iwl_channel_info *ch_info)
1774 {
1775         struct iwl3945_channel_power_info *power_info;
1776         int power_changed = 0;
1777         int i;
1778         const s8 *clip_pwrs;
1779         int power;
1780
1781         /* Get this chnlgrp's rate-to-max/clip-powers table */
1782         clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1783
1784         /* Get this channel's rate-to-current-power settings table */
1785         power_info = ch_info->power_info;
1786
1787         /* update OFDM Txpower settings */
1788         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1789              i++, ++power_info) {
1790                 int delta_idx;
1791
1792                 /* limit new power to be no more than h/w capability */
1793                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1794                 if (power == power_info->requested_power)
1795                         continue;
1796
1797                 /* find difference between old and new requested powers,
1798                  *    update base (non-temp-compensated) power index */
1799                 delta_idx = (power - power_info->requested_power) * 2;
1800                 power_info->base_power_index -= delta_idx;
1801
1802                 /* save new requested power value */
1803                 power_info->requested_power = power;
1804
1805                 power_changed = 1;
1806         }
1807
1808         /* update CCK Txpower settings, based on OFDM 12M setting ...
1809          *    ... all CCK power settings for a given channel are the *same*. */
1810         if (power_changed) {
1811                 power =
1812                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1813                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1814
1815                 /* do all CCK rates' iwl3945_channel_power_info structures */
1816                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1817                         power_info->requested_power = power;
1818                         power_info->base_power_index =
1819                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1820                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1821                         ++power_info;
1822                 }
1823         }
1824
1825         return 0;
1826 }
1827
1828 /**
1829  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1830  *
1831  * NOTE: Returned power limit may be less (but not more) than requested,
1832  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1833  *       (no consideration for h/w clipping limitations).
1834  */
1835 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1836 {
1837         s8 max_power;
1838
1839 #if 0
1840         /* if we're using TGd limits, use lower of TGd or EEPROM */
1841         if (ch_info->tgd_data.max_power != 0)
1842                 max_power = min(ch_info->tgd_data.max_power,
1843                                 ch_info->eeprom.max_power_avg);
1844
1845         /* else just use EEPROM limits */
1846         else
1847 #endif
1848                 max_power = ch_info->eeprom.max_power_avg;
1849
1850         return min(max_power, ch_info->max_power_avg);
1851 }
1852
1853 /**
1854  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1855  *
1856  * Compensate txpower settings of *all* channels for temperature.
1857  * This only accounts for the difference between current temperature
1858  *   and the factory calibration temperatures, and bases the new settings
1859  *   on the channel's base_power_index.
1860  *
1861  * If RxOn is "associated", this sends the new Txpower to NIC!
1862  */
1863 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1864 {
1865         struct iwl_channel_info *ch_info = NULL;
1866         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1867         int delta_index;
1868         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1869         u8 a_band;
1870         u8 rate_index;
1871         u8 scan_tbl_index;
1872         u8 i;
1873         int ref_temp;
1874         int temperature = priv->temperature;
1875
1876         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1877         for (i = 0; i < priv->channel_count; i++) {
1878                 ch_info = &priv->channel_info[i];
1879                 a_band = is_channel_a_band(ch_info);
1880
1881                 /* Get this chnlgrp's factory calibration temperature */
1882                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1883                     temperature;
1884
1885                 /* get power index adjustment based on current and factory
1886                  * temps */
1887                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1888                                                               ref_temp);
1889
1890                 /* set tx power value for all rates, OFDM and CCK */
1891                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1892                      rate_index++) {
1893                         int power_idx =
1894                             ch_info->power_info[rate_index].base_power_index;
1895
1896                         /* temperature compensate */
1897                         power_idx += delta_index;
1898
1899                         /* stay within table range */
1900                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1901                         ch_info->power_info[rate_index].
1902                             power_table_index = (u8) power_idx;
1903                         ch_info->power_info[rate_index].tpc =
1904                             power_gain_table[a_band][power_idx];
1905                 }
1906
1907                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1908                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1909
1910                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1911                 for (scan_tbl_index = 0;
1912                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1913                         s32 actual_index = (scan_tbl_index == 0) ?
1914                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1915                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1916                                            actual_index, clip_pwrs,
1917                                            ch_info, a_band);
1918                 }
1919         }
1920
1921         /* send Txpower command for current channel to ucode */
1922         return priv->cfg->ops->lib->send_tx_power(priv);
1923 }
1924
1925 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1926 {
1927         struct iwl_channel_info *ch_info;
1928         s8 max_power;
1929         u8 a_band;
1930         u8 i;
1931
1932         if (priv->tx_power_user_lmt == power) {
1933                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1934                                 "limit: %ddBm.\n", power);
1935                 return 0;
1936         }
1937
1938         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1939         priv->tx_power_user_lmt = power;
1940
1941         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1942
1943         for (i = 0; i < priv->channel_count; i++) {
1944                 ch_info = &priv->channel_info[i];
1945                 a_band = is_channel_a_band(ch_info);
1946
1947                 /* find minimum power of all user and regulatory constraints
1948                  *    (does not consider h/w clipping limitations) */
1949                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1950                 max_power = min(power, max_power);
1951                 if (max_power != ch_info->curr_txpow) {
1952                         ch_info->curr_txpow = max_power;
1953
1954                         /* this considers the h/w clipping limitations */
1955                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1956                 }
1957         }
1958
1959         /* update txpower settings for all channels,
1960          *   send to NIC if associated. */
1961         is_temp_calib_needed(priv);
1962         iwl3945_hw_reg_comp_txpower_temp(priv);
1963
1964         return 0;
1965 }
1966
1967 /* will add 3945 channel switch cmd handling later */
1968 int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1969 {
1970         return 0;
1971 }
1972
1973 /**
1974  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1975  *
1976  * -- reset periodic timer
1977  * -- see if temp has changed enough to warrant re-calibration ... if so:
1978  *     -- correct coeffs for temp (can reset temp timer)
1979  *     -- save this temp as "last",
1980  *     -- send new set of gain settings to NIC
1981  * NOTE:  This should continue working, even when we're not associated,
1982  *   so we can keep our internal table of scan powers current. */
1983 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1984 {
1985         /* This will kick in the "brute force"
1986          * iwl3945_hw_reg_comp_txpower_temp() below */
1987         if (!is_temp_calib_needed(priv))
1988                 goto reschedule;
1989
1990         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1991          * This is based *only* on current temperature,
1992          * ignoring any previous power measurements */
1993         iwl3945_hw_reg_comp_txpower_temp(priv);
1994
1995  reschedule:
1996         queue_delayed_work(priv->workqueue,
1997                            &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1998 }
1999
2000 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2001 {
2002         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2003                                              thermal_periodic.work);
2004
2005         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2006                 return;
2007
2008         mutex_lock(&priv->mutex);
2009         iwl3945_reg_txpower_periodic(priv);
2010         mutex_unlock(&priv->mutex);
2011 }
2012
2013 /**
2014  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2015  *                                 for the channel.
2016  *
2017  * This function is used when initializing channel-info structs.
2018  *
2019  * NOTE: These channel groups do *NOT* match the bands above!
2020  *       These channel groups are based on factory-tested channels;
2021  *       on A-band, EEPROM's "group frequency" entries represent the top
2022  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
2023  */
2024 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2025                                        const struct iwl_channel_info *ch_info)
2026 {
2027         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2028         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2029         u8 group;
2030         u16 group_index = 0;    /* based on factory calib frequencies */
2031         u8 grp_channel;
2032
2033         /* Find the group index for the channel ... don't use index 1(?) */
2034         if (is_channel_a_band(ch_info)) {
2035                 for (group = 1; group < 5; group++) {
2036                         grp_channel = ch_grp[group].group_channel;
2037                         if (ch_info->channel <= grp_channel) {
2038                                 group_index = group;
2039                                 break;
2040                         }
2041                 }
2042                 /* group 4 has a few channels *above* its factory cal freq */
2043                 if (group == 5)
2044                         group_index = 4;
2045         } else
2046                 group_index = 0;        /* 2.4 GHz, group 0 */
2047
2048         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2049                         group_index);
2050         return group_index;
2051 }
2052
2053 /**
2054  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2055  *
2056  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2057  *   into radio/DSP gain settings table for requested power.
2058  */
2059 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2060                                        s8 requested_power,
2061                                        s32 setting_index, s32 *new_index)
2062 {
2063         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2064         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2065         s32 index0, index1;
2066         s32 power = 2 * requested_power;
2067         s32 i;
2068         const struct iwl3945_eeprom_txpower_sample *samples;
2069         s32 gains0, gains1;
2070         s32 res;
2071         s32 denominator;
2072
2073         chnl_grp = &eeprom->groups[setting_index];
2074         samples = chnl_grp->samples;
2075         for (i = 0; i < 5; i++) {
2076                 if (power == samples[i].power) {
2077                         *new_index = samples[i].gain_index;
2078                         return 0;
2079                 }
2080         }
2081
2082         if (power > samples[1].power) {
2083                 index0 = 0;
2084                 index1 = 1;
2085         } else if (power > samples[2].power) {
2086                 index0 = 1;
2087                 index1 = 2;
2088         } else if (power > samples[3].power) {
2089                 index0 = 2;
2090                 index1 = 3;
2091         } else {
2092                 index0 = 3;
2093                 index1 = 4;
2094         }
2095
2096         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2097         if (denominator == 0)
2098                 return -EINVAL;
2099         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2100         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2101         res = gains0 + (gains1 - gains0) *
2102             ((s32) power - (s32) samples[index0].power) / denominator +
2103             (1 << 18);
2104         *new_index = res >> 19;
2105         return 0;
2106 }
2107
2108 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2109 {
2110         u32 i;
2111         s32 rate_index;
2112         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2113         const struct iwl3945_eeprom_txpower_group *group;
2114
2115         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2116
2117         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2118                 s8 *clip_pwrs;  /* table of power levels for each rate */
2119                 s8 satur_pwr;   /* saturation power for each chnl group */
2120                 group = &eeprom->groups[i];
2121
2122                 /* sanity check on factory saturation power value */
2123                 if (group->saturation_power < 40) {
2124                         IWL_WARN(priv, "Error: saturation power is %d, "
2125                                     "less than minimum expected 40\n",
2126                                     group->saturation_power);
2127                         return;
2128                 }
2129
2130                 /*
2131                  * Derive requested power levels for each rate, based on
2132                  *   hardware capabilities (saturation power for band).
2133                  * Basic value is 3dB down from saturation, with further
2134                  *   power reductions for highest 3 data rates.  These
2135                  *   backoffs provide headroom for high rate modulation
2136                  *   power peaks, without too much distortion (clipping).
2137                  */
2138                 /* we'll fill in this array with h/w max power levels */
2139                 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2140
2141                 /* divide factory saturation power by 2 to find -3dB level */
2142                 satur_pwr = (s8) (group->saturation_power >> 1);
2143
2144                 /* fill in channel group's nominal powers for each rate */
2145                 for (rate_index = 0;
2146                      rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2147                         switch (rate_index) {
2148                         case IWL_RATE_36M_INDEX_TABLE:
2149                                 if (i == 0)     /* B/G */
2150                                         *clip_pwrs = satur_pwr;
2151                                 else    /* A */
2152                                         *clip_pwrs = satur_pwr - 5;
2153                                 break;
2154                         case IWL_RATE_48M_INDEX_TABLE:
2155                                 if (i == 0)
2156                                         *clip_pwrs = satur_pwr - 7;
2157                                 else
2158                                         *clip_pwrs = satur_pwr - 10;
2159                                 break;
2160                         case IWL_RATE_54M_INDEX_TABLE:
2161                                 if (i == 0)
2162                                         *clip_pwrs = satur_pwr - 9;
2163                                 else
2164                                         *clip_pwrs = satur_pwr - 12;
2165                                 break;
2166                         default:
2167                                 *clip_pwrs = satur_pwr;
2168                                 break;
2169                         }
2170                 }
2171         }
2172 }
2173
2174 /**
2175  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2176  *
2177  * Second pass (during init) to set up priv->channel_info
2178  *
2179  * Set up Tx-power settings in our channel info database for each VALID
2180  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2181  * and current temperature.
2182  *
2183  * Since this is based on current temperature (at init time), these values may
2184  * not be valid for very long, but it gives us a starting/default point,
2185  * and allows us to active (i.e. using Tx) scan.
2186  *
2187  * This does *not* write values to NIC, just sets up our internal table.
2188  */
2189 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2190 {
2191         struct iwl_channel_info *ch_info = NULL;
2192         struct iwl3945_channel_power_info *pwr_info;
2193         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2194         int delta_index;
2195         u8 rate_index;
2196         u8 scan_tbl_index;
2197         const s8 *clip_pwrs;    /* array of power levels for each rate */
2198         u8 gain, dsp_atten;
2199         s8 power;
2200         u8 pwr_index, base_pwr_index, a_band;
2201         u8 i;
2202         int temperature;
2203
2204         /* save temperature reference,
2205          *   so we can determine next time to calibrate */
2206         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2207         priv->last_temperature = temperature;
2208
2209         iwl3945_hw_reg_init_channel_groups(priv);
2210
2211         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2212         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2213              i++, ch_info++) {
2214                 a_band = is_channel_a_band(ch_info);
2215                 if (!is_channel_valid(ch_info))
2216                         continue;
2217
2218                 /* find this channel's channel group (*not* "band") index */
2219                 ch_info->group_index =
2220                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2221
2222                 /* Get this chnlgrp's rate->max/clip-powers table */
2223                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2224
2225                 /* calculate power index *adjustment* value according to
2226                  *  diff between current temperature and factory temperature */
2227                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2228                                 eeprom->groups[ch_info->group_index].
2229                                 temperature);
2230
2231                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2232                                 ch_info->channel, delta_index, temperature +
2233                                 IWL_TEMP_CONVERT);
2234
2235                 /* set tx power value for all OFDM rates */
2236                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2237                      rate_index++) {
2238                         s32 uninitialized_var(power_idx);
2239                         int rc;
2240
2241                         /* use channel group's clip-power table,
2242                          *   but don't exceed channel's max power */
2243                         s8 pwr = min(ch_info->max_power_avg,
2244                                      clip_pwrs[rate_index]);
2245
2246                         pwr_info = &ch_info->power_info[rate_index];
2247
2248                         /* get base (i.e. at factory-measured temperature)
2249                          *    power table index for this rate's power */
2250                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2251                                                          ch_info->group_index,
2252                                                          &power_idx);
2253                         if (rc) {
2254                                 IWL_ERR(priv, "Invalid power index\n");
2255                                 return rc;
2256                         }
2257                         pwr_info->base_power_index = (u8) power_idx;
2258
2259                         /* temperature compensate */
2260                         power_idx += delta_index;
2261
2262                         /* stay within range of gain table */
2263                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2264
2265                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2266                         pwr_info->requested_power = pwr;
2267                         pwr_info->power_table_index = (u8) power_idx;
2268                         pwr_info->tpc.tx_gain =
2269                             power_gain_table[a_band][power_idx].tx_gain;
2270                         pwr_info->tpc.dsp_atten =
2271                             power_gain_table[a_band][power_idx].dsp_atten;
2272                 }
2273
2274                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2275                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2276                 power = pwr_info->requested_power +
2277                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2278                 pwr_index = pwr_info->power_table_index +
2279                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2280                 base_pwr_index = pwr_info->base_power_index +
2281                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2282
2283                 /* stay within table range */
2284                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2285                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2286                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2287
2288                 /* fill each CCK rate's iwl3945_channel_power_info structure
2289                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2290                  * NOTE:  CCK rates start at end of OFDM rates! */
2291                 for (rate_index = 0;
2292                      rate_index < IWL_CCK_RATES; rate_index++) {
2293                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2294                         pwr_info->requested_power = power;
2295                         pwr_info->power_table_index = pwr_index;
2296                         pwr_info->base_power_index = base_pwr_index;
2297                         pwr_info->tpc.tx_gain = gain;
2298                         pwr_info->tpc.dsp_atten = dsp_atten;
2299                 }
2300
2301                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2302                 for (scan_tbl_index = 0;
2303                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2304                         s32 actual_index = (scan_tbl_index == 0) ?
2305                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2306                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2307                                 actual_index, clip_pwrs, ch_info, a_band);
2308                 }
2309         }
2310
2311         return 0;
2312 }
2313
2314 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2315 {
2316         int rc;
2317         unsigned long flags;
2318
2319         spin_lock_irqsave(&priv->lock, flags);
2320         rc = iwl_grab_nic_access(priv);
2321         if (rc) {
2322                 spin_unlock_irqrestore(&priv->lock, flags);
2323                 return rc;
2324         }
2325
2326         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2327         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2328                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2329         if (rc < 0)
2330                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2331
2332         iwl_release_nic_access(priv);
2333         spin_unlock_irqrestore(&priv->lock, flags);
2334
2335         return 0;
2336 }
2337
2338 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2339 {
2340         int rc;
2341         unsigned long flags;
2342         int txq_id = txq->q.id;
2343
2344         struct iwl3945_shared *shared_data = priv->shared_virt;
2345
2346         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2347
2348         spin_lock_irqsave(&priv->lock, flags);
2349         rc = iwl_grab_nic_access(priv);
2350         if (rc) {
2351                 spin_unlock_irqrestore(&priv->lock, flags);
2352                 return rc;
2353         }
2354         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2355         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2356
2357         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2358                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2359                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2360                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2361                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2362                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2363         iwl_release_nic_access(priv);
2364
2365         /* fake read to flush all prev. writes */
2366         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2367         spin_unlock_irqrestore(&priv->lock, flags);
2368
2369         return 0;
2370 }
2371
2372 /*
2373  * HCMD utils
2374  */
2375 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2376 {
2377         switch (cmd_id) {
2378         case REPLY_RXON:
2379                 return sizeof(struct iwl3945_rxon_cmd);
2380         case POWER_TABLE_CMD:
2381                 return sizeof(struct iwl3945_powertable_cmd);
2382         default:
2383                 return len;
2384         }
2385 }
2386
2387 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2388 {
2389         u16 size = (u16)sizeof(struct iwl3945_addsta_cmd);
2390         memcpy(data, cmd, size);
2391         return size;
2392 }
2393
2394 /**
2395  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2396  */
2397 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2398 {
2399         int rc, i, index, prev_index;
2400         struct iwl3945_rate_scaling_cmd rate_cmd = {
2401                 .reserved = {0, 0, 0},
2402         };
2403         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2404
2405         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2406                 index = iwl3945_rates[i].table_rs_index;
2407
2408                 table[index].rate_n_flags =
2409                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2410                 table[index].try_cnt = priv->retry_rate;
2411                 prev_index = iwl3945_get_prev_ieee_rate(i);
2412                 table[index].next_rate_index =
2413                                 iwl3945_rates[prev_index].table_rs_index;
2414         }
2415
2416         switch (priv->band) {
2417         case IEEE80211_BAND_5GHZ:
2418                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2419                 /* If one of the following CCK rates is used,
2420                  * have it fall back to the 6M OFDM rate */
2421                 for (i = IWL_RATE_1M_INDEX_TABLE;
2422                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2423                         table[i].next_rate_index =
2424                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2425
2426                 /* Don't fall back to CCK rates */
2427                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2428                                                 IWL_RATE_9M_INDEX_TABLE;
2429
2430                 /* Don't drop out of OFDM rates */
2431                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2432                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2433                 break;
2434
2435         case IEEE80211_BAND_2GHZ:
2436                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2437                 /* If an OFDM rate is used, have it fall back to the
2438                  * 1M CCK rates */
2439
2440                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2441                     iwl_is_associated(priv)) {
2442
2443                         index = IWL_FIRST_CCK_RATE;
2444                         for (i = IWL_RATE_6M_INDEX_TABLE;
2445                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2446                                 table[i].next_rate_index =
2447                                         iwl3945_rates[index].table_rs_index;
2448
2449                         index = IWL_RATE_11M_INDEX_TABLE;
2450                         /* CCK shouldn't fall back to OFDM... */
2451                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2452                 }
2453                 break;
2454
2455         default:
2456                 WARN_ON(1);
2457                 break;
2458         }
2459
2460         /* Update the rate scaling for control frame Tx */
2461         rate_cmd.table_id = 0;
2462         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2463                               &rate_cmd);
2464         if (rc)
2465                 return rc;
2466
2467         /* Update the rate scaling for data frame Tx */
2468         rate_cmd.table_id = 1;
2469         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2470                                 &rate_cmd);
2471 }
2472
2473 /* Called when initializing driver */
2474 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2475 {
2476         memset((void *)&priv->hw_params, 0,
2477                sizeof(struct iwl_hw_params));
2478
2479         priv->shared_virt =
2480             pci_alloc_consistent(priv->pci_dev,
2481                                  sizeof(struct iwl3945_shared),
2482                                  &priv->shared_phys);
2483
2484         if (!priv->shared_virt) {
2485                 IWL_ERR(priv, "failed to allocate pci memory\n");
2486                 mutex_unlock(&priv->mutex);
2487                 return -ENOMEM;
2488         }
2489
2490         /* Assign number of Usable TX queues */
2491         priv->hw_params.max_txq_num = TFD_QUEUE_MAX;
2492
2493         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2494         priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
2495         priv->hw_params.max_pkt_size = 2342;
2496         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2497         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2498         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2499         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2500
2501         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2502
2503         return 0;
2504 }
2505
2506 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2507                           struct iwl3945_frame *frame, u8 rate)
2508 {
2509         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2510         unsigned int frame_size;
2511
2512         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2513         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2514
2515         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2516         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2517
2518         frame_size = iwl3945_fill_beacon_frame(priv,
2519                                 tx_beacon_cmd->frame,
2520                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2521
2522         BUG_ON(frame_size > MAX_MPDU_SIZE);
2523         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2524
2525         tx_beacon_cmd->tx.rate = rate;
2526         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2527                                       TX_CMD_FLG_TSF_MSK);
2528
2529         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2530         tx_beacon_cmd->tx.supp_rates[0] =
2531                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2532
2533         tx_beacon_cmd->tx.supp_rates[1] =
2534                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2535
2536         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2537 }
2538
2539 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2540 {
2541         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2542         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2543 }
2544
2545 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2546 {
2547         INIT_DELAYED_WORK(&priv->thermal_periodic,
2548                           iwl3945_bg_reg_txpower_periodic);
2549 }
2550
2551 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2552 {
2553         cancel_delayed_work(&priv->thermal_periodic);
2554 }
2555
2556 /* check contents of special bootstrap uCode SRAM */
2557 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2558  {
2559         __le32 *image = priv->ucode_boot.v_addr;
2560         u32 len = priv->ucode_boot.len;
2561         u32 reg;
2562         u32 val;
2563
2564         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2565
2566         /* verify BSM SRAM contents */
2567         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2568         for (reg = BSM_SRAM_LOWER_BOUND;
2569              reg < BSM_SRAM_LOWER_BOUND + len;
2570              reg += sizeof(u32), image++) {
2571                 val = iwl_read_prph(priv, reg);
2572                 if (val != le32_to_cpu(*image)) {
2573                         IWL_ERR(priv, "BSM uCode verification failed at "
2574                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2575                                   BSM_SRAM_LOWER_BOUND,
2576                                   reg - BSM_SRAM_LOWER_BOUND, len,
2577                                   val, le32_to_cpu(*image));
2578                         return -EIO;
2579                 }
2580         }
2581
2582         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2583
2584         return 0;
2585 }
2586
2587
2588 /******************************************************************************
2589  *
2590  * EEPROM related functions
2591  *
2592  ******************************************************************************/
2593
2594 /*
2595  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2596  * embedded controller) as EEPROM reader; each read is a series of pulses
2597  * to/from the EEPROM chip, not a single event, so even reads could conflict
2598  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2599  * simply claims ownership, which should be safe when this function is called
2600  * (i.e. before loading uCode!).
2601  */
2602 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2603 {
2604         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2605         return 0;
2606 }
2607
2608
2609 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2610 {
2611         return;
2612 }
2613
2614  /**
2615   * iwl3945_load_bsm - Load bootstrap instructions
2616   *
2617   * BSM operation:
2618   *
2619   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2620   * in special SRAM that does not power down during RFKILL.  When powering back
2621   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2622   * the bootstrap program into the on-board processor, and starts it.
2623   *
2624   * The bootstrap program loads (via DMA) instructions and data for a new
2625   * program from host DRAM locations indicated by the host driver in the
2626   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2627   * automatically.
2628   *
2629   * When initializing the NIC, the host driver points the BSM to the
2630   * "initialize" uCode image.  This uCode sets up some internal data, then
2631   * notifies host via "initialize alive" that it is complete.
2632   *
2633   * The host then replaces the BSM_DRAM_* pointer values to point to the
2634   * normal runtime uCode instructions and a backup uCode data cache buffer
2635   * (filled initially with starting data values for the on-board processor),
2636   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2637   * which begins normal operation.
2638   *
2639   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2640   * the backup data cache in DRAM before SRAM is powered down.
2641   *
2642   * When powering back up, the BSM loads the bootstrap program.  This reloads
2643   * the runtime uCode instructions and the backup data cache into SRAM,
2644   * and re-launches the runtime uCode from where it left off.
2645   */
2646 static int iwl3945_load_bsm(struct iwl_priv *priv)
2647 {
2648         __le32 *image = priv->ucode_boot.v_addr;
2649         u32 len = priv->ucode_boot.len;
2650         dma_addr_t pinst;
2651         dma_addr_t pdata;
2652         u32 inst_len;
2653         u32 data_len;
2654         int rc;
2655         int i;
2656         u32 done;
2657         u32 reg_offset;
2658
2659         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2660
2661         /* make sure bootstrap program is no larger than BSM's SRAM size */
2662         if (len > IWL39_MAX_BSM_SIZE)
2663                 return -EINVAL;
2664
2665         /* Tell bootstrap uCode where to find the "Initialize" uCode
2666         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2667         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2668         *        after the "initialize" uCode has run, to point to
2669         *        runtime/protocol instructions and backup data cache. */
2670         pinst = priv->ucode_init.p_addr;
2671         pdata = priv->ucode_init_data.p_addr;
2672         inst_len = priv->ucode_init.len;
2673         data_len = priv->ucode_init_data.len;
2674
2675         rc = iwl_grab_nic_access(priv);
2676         if (rc)
2677                 return rc;
2678
2679         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2680         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2681         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2682         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2683
2684         /* Fill BSM memory with bootstrap instructions */
2685         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2686              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2687              reg_offset += sizeof(u32), image++)
2688                 _iwl_write_prph(priv, reg_offset,
2689                                           le32_to_cpu(*image));
2690
2691         rc = iwl3945_verify_bsm(priv);
2692         if (rc) {
2693                 iwl_release_nic_access(priv);
2694                 return rc;
2695         }
2696
2697         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2698         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2699         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2700                                  IWL39_RTC_INST_LOWER_BOUND);
2701         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2702
2703         /* Load bootstrap code into instruction SRAM now,
2704          *   to prepare to load "initialize" uCode */
2705         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2706                 BSM_WR_CTRL_REG_BIT_START);
2707
2708         /* Wait for load of bootstrap uCode to finish */
2709         for (i = 0; i < 100; i++) {
2710                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2711                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2712                         break;
2713                 udelay(10);
2714         }
2715         if (i < 100)
2716                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2717         else {
2718                 IWL_ERR(priv, "BSM write did not complete!\n");
2719                 return -EIO;
2720         }
2721
2722         /* Enable future boot loads whenever power management unit triggers it
2723          *   (e.g. when powering back up after power-save shutdown) */
2724         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2725                 BSM_WR_CTRL_REG_BIT_START_EN);
2726
2727         iwl_release_nic_access(priv);
2728
2729         return 0;
2730 }
2731
2732 static struct iwl_lib_ops iwl3945_lib = {
2733         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2734         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2735         .txq_init = iwl3945_hw_tx_queue_init,
2736         .load_ucode = iwl3945_load_bsm,
2737         .apm_ops = {
2738                 .init = iwl3945_apm_init,
2739                 .reset = iwl3945_apm_reset,
2740                 .stop = iwl3945_apm_stop,
2741                 .config = iwl3945_nic_config,
2742                 .set_pwr_src = iwl3945_set_pwr_src,
2743         },
2744         .eeprom_ops = {
2745                 .regulatory_bands = {
2746                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2747                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2748                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2749                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2750                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2751                         EEPROM_REGULATORY_BAND_NO_FAT,
2752                         EEPROM_REGULATORY_BAND_NO_FAT,
2753                 },
2754                 .verify_signature  = iwlcore_eeprom_verify_signature,
2755                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2756                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2757                 .query_addr = iwlcore_eeprom_query_addr,
2758         },
2759         .send_tx_power  = iwl3945_send_tx_power,
2760         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2761 };
2762
2763 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2764         .get_hcmd_size = iwl3945_get_hcmd_size,
2765         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2766 };
2767
2768 static struct iwl_ops iwl3945_ops = {
2769         .lib = &iwl3945_lib,
2770         .utils = &iwl3945_hcmd_utils,
2771 };
2772
2773 static struct iwl_cfg iwl3945_bg_cfg = {
2774         .name = "3945BG",
2775         .fw_name_pre = IWL3945_FW_PRE,
2776         .ucode_api_max = IWL3945_UCODE_API_MAX,
2777         .ucode_api_min = IWL3945_UCODE_API_MIN,
2778         .sku = IWL_SKU_G,
2779         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2780         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2781         .ops = &iwl3945_ops,
2782         .mod_params = &iwl3945_mod_params
2783 };
2784
2785 static struct iwl_cfg iwl3945_abg_cfg = {
2786         .name = "3945ABG",
2787         .fw_name_pre = IWL3945_FW_PRE,
2788         .ucode_api_max = IWL3945_UCODE_API_MAX,
2789         .ucode_api_min = IWL3945_UCODE_API_MIN,
2790         .sku = IWL_SKU_A|IWL_SKU_G,
2791         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2792         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2793         .ops = &iwl3945_ops,
2794         .mod_params = &iwl3945_mod_params
2795 };
2796
2797 struct pci_device_id iwl3945_hw_card_ids[] = {
2798         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2799         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2800         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2801         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2802         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2803         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2804         {0}
2805 };
2806
2807 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);