drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/slab.h>
  31 #include <linux/pci.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/delay.h>
  34 #include <linux/sched.h>
  35 #include <linux/skbuff.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/wireless.h>
  38 #include <linux/firmware.h>
  39 #include <linux/etherdevice.h>
  40 #include <asm/unaligned.h>
  41 #include <net/mac80211.h>
  42
  43 #include "iwl-fh.h"
  44 #include "iwl-3945-fh.h"
  45 #include "iwl-commands.h"
  46 #include "iwl-sta.h"
  47 #include "iwl-3945.h"
  48 #include "iwl-eeprom.h"
  49 #include "iwl-core.h"
  50 #include "iwl-helpers.h"
  51 #include "iwl-led.h"
  52 #include "iwl-3945-led.h"
  53 #include "iwl-3945-debugfs.h"
  54
  55 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  56         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  57                                     IWL_RATE_##r##M_IEEE,   \
  58                                     IWL_RATE_##ip##M_INDEX, \
  59                                     IWL_RATE_##in##M_INDEX, \
  60                                     IWL_RATE_##rp##M_INDEX, \
  61                                     IWL_RATE_##rn##M_INDEX, \
  62                                     IWL_RATE_##pp##M_INDEX, \
  63                                     IWL_RATE_##np##M_INDEX, \
  64                                     IWL_RATE_##r##M_INDEX_TABLE, \
  65                                     IWL_RATE_##ip##M_INDEX_TABLE }
  66
  67 /*
  68  * Parameter order:
  69  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  70  *
  71  * If there isn't a valid next or previous rate then INV is used which
  72  * maps to IWL_RATE_INVALID
  73  *
  74  */
  75 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  76         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  77         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  78         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  79         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  80         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  81         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  82         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  83         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  84         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  85         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  86         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  87         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  88 };
  89
  90 /* 1 = enable the iwl3945_disable_events() function */
  91 #define IWL_EVT_DISABLE (0)
  92 #define IWL_EVT_DISABLE_SIZE (1532/32)
  93
  94 /**
  95  * iwl3945_disable_events - Disable selected events in uCode event log
  96  *
  97  * Disable an event by writing "1"s into "disable"
  98  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  99  *   Default values of 0 enable uCode events to be logged.
 100  * Use for only special debugging.  This function is just a placeholder as-is,
 101  *   you'll need to provide the special bits! ...
 102  *   ... and set IWL_EVT_DISABLE to 1. */
 103 void iwl3945_disable_events(struct iwl_priv *priv)
 104 {
 105         int i;
 106         u32 base;               /* SRAM address of event log header */
 107         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 108         u32 array_size;         /* # of u32 entries in array */
 109         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 110                 0x00000000,     /*   31 -    0  Event id numbers */
 111                 0x00000000,     /*   63 -   32 */
 112                 0x00000000,     /*   95 -   64 */
 113                 0x00000000,     /*  127 -   96 */
 114                 0x00000000,     /*  159 -  128 */
 115                 0x00000000,     /*  191 -  160 */
 116                 0x00000000,     /*  223 -  192 */
 117                 0x00000000,     /*  255 -  224 */
 118                 0x00000000,     /*  287 -  256 */
 119                 0x00000000,     /*  319 -  288 */
 120                 0x00000000,     /*  351 -  320 */
 121                 0x00000000,     /*  383 -  352 */
 122                 0x00000000,     /*  415 -  384 */
 123                 0x00000000,     /*  447 -  416 */
 124                 0x00000000,     /*  479 -  448 */
 125                 0x00000000,     /*  511 -  480 */
 126                 0x00000000,     /*  543 -  512 */
 127                 0x00000000,     /*  575 -  544 */
 128                 0x00000000,     /*  607 -  576 */
 129                 0x00000000,     /*  639 -  608 */
 130                 0x00000000,     /*  671 -  640 */
 131                 0x00000000,     /*  703 -  672 */
 132                 0x00000000,     /*  735 -  704 */
 133                 0x00000000,     /*  767 -  736 */
 134                 0x00000000,     /*  799 -  768 */
 135                 0x00000000,     /*  831 -  800 */
 136                 0x00000000,     /*  863 -  832 */
 137                 0x00000000,     /*  895 -  864 */
 138                 0x00000000,     /*  927 -  896 */
 139                 0x00000000,     /*  959 -  928 */
 140                 0x00000000,     /*  991 -  960 */
 141                 0x00000000,     /* 1023 -  992 */
 142                 0x00000000,     /* 1055 - 1024 */
 143                 0x00000000,     /* 1087 - 1056 */
 144                 0x00000000,     /* 1119 - 1088 */
 145                 0x00000000,     /* 1151 - 1120 */
 146                 0x00000000,     /* 1183 - 1152 */
 147                 0x00000000,     /* 1215 - 1184 */
 148                 0x00000000,     /* 1247 - 1216 */
 149                 0x00000000,     /* 1279 - 1248 */
 150                 0x00000000,     /* 1311 - 1280 */
 151                 0x00000000,     /* 1343 - 1312 */
 152                 0x00000000,     /* 1375 - 1344 */
 153                 0x00000000,     /* 1407 - 1376 */
 154                 0x00000000,     /* 1439 - 1408 */
 155                 0x00000000,     /* 1471 - 1440 */
 156                 0x00000000,     /* 1503 - 1472 */
 157         };
 158
 159         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 160         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 161                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 162                 return;
 163         }
 164
 165         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 166         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 167
 168         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 169                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
 170                                disable_ptr);
 171                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 172                         iwl_write_targ_mem(priv,
 173                                            disable_ptr + (i * sizeof(u32)),
 174                                            evt_disable[i]);
 175
 176         } else {
 177                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
 178                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
 179                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
 180                                disable_ptr, array_size);
 181         }
 182
 183 }
 184
 185 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 186 {
 187         int idx;
 188
 189         for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
 190                 if (iwl3945_rates[idx].plcp == plcp)
 191                         return idx;
 192         return -1;
 193 }
 194
 195 #ifdef CONFIG_IWLWIFI_DEBUG
 196 #define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
 197
 198 static const char *iwl3945_get_tx_fail_reason(u32 status)
 199 {
 200         switch (status & TX_STATUS_MSK) {
 201         case TX_3945_STATUS_SUCCESS:
 202                 return "SUCCESS";
 203                 TX_STATUS_ENTRY(SHORT_LIMIT);
 204                 TX_STATUS_ENTRY(LONG_LIMIT);
 205                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 206                 TX_STATUS_ENTRY(MGMNT_ABORT);
 207                 TX_STATUS_ENTRY(NEXT_FRAG);
 208                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 209                 TX_STATUS_ENTRY(DEST_PS);
 210                 TX_STATUS_ENTRY(ABORTED);
 211                 TX_STATUS_ENTRY(BT_RETRY);
 212                 TX_STATUS_ENTRY(STA_INVALID);
 213                 TX_STATUS_ENTRY(FRAG_DROPPED);
 214                 TX_STATUS_ENTRY(TID_DISABLE);
 215                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 216                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 217                 TX_STATUS_ENTRY(TX_LOCKED);
 218                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 219         }
 220
 221         return "UNKNOWN";
 222 }
 223 #else
 224 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 225 {
 226         return "";
 227 }
 228 #endif
 229
 230 /*
 231  * get ieee prev rate from rate scale table.
 232  * for A and B mode we need to overright prev
 233  * value
 234  */
 235 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 236 {
 237         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 238
 239         switch (priv->band) {
 240         case IEEE80211_BAND_5GHZ:
 241                 if (rate == IWL_RATE_12M_INDEX)
 242                         next_rate = IWL_RATE_9M_INDEX;
 243                 else if (rate == IWL_RATE_6M_INDEX)
 244                         next_rate = IWL_RATE_6M_INDEX;
 245                 break;
 246         case IEEE80211_BAND_2GHZ:
 247                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 248                     iwl_is_associated(priv)) {
 249                         if (rate == IWL_RATE_11M_INDEX)
 250                                 next_rate = IWL_RATE_5M_INDEX;
 251                 }
 252                 break;
 253
 254         default:
 255                 break;
 256         }
 257
 258         return next_rate;
 259 }
 260
 261
 262 /**
 263  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 264  *
 265  * When FW advances 'R' index, all entries between old and new 'R' index
 266  * need to be reclaimed. As result, some free space forms. If there is
 267  * enough free space (> low mark), wake the stack that feeds us.
 268  */
 269 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 270                                      int txq_id, int index)
 271 {
 272         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 273         struct iwl_queue *q = &txq->q;
 274         struct iwl_tx_info *tx_info;
 275
 276         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 277
 278         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 279                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 280
 281                 tx_info = &txq->txb[txq->q.read_ptr];
 282                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
 283                 tx_info->skb[0] = NULL;
 284                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 285         }
 286
 287         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 288                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 289                         priv->mac80211_registered)
 290                 iwl_wake_queue(priv, txq_id);
 291 }
 292
 293 /**
 294  * iwl3945_rx_reply_tx - Handle Tx response
 295  */
 296 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 297                                 struct iwl_rx_mem_buffer *rxb)
 298 {
 299         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 300         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 301         int txq_id = SEQ_TO_QUEUE(sequence);
 302         int index = SEQ_TO_INDEX(sequence);
 303         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 304         struct ieee80211_tx_info *info;
 305         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 306         u32  status = le32_to_cpu(tx_resp->status);
 307         int rate_idx;
 308         int fail;
 309
 310         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 311                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 312                           "is out of range [0-%d] %d %d\n", txq_id,
 313                           index, txq->q.n_bd, txq->q.write_ptr,
 314                           txq->q.read_ptr);
 315                 return;
 316         }
 317
 318         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
 319         ieee80211_tx_info_clear_status(info);
 320
 321         /* Fill the MRR chain with some info about on-chip retransmissions */
 322         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 323         if (info->band == IEEE80211_BAND_5GHZ)
 324                 rate_idx -= IWL_FIRST_OFDM_RATE;
 325
 326         fail = tx_resp->failure_frame;
 327
 328         info->status.rates[0].idx = rate_idx;
 329         info->status.rates[0].count = fail + 1; /* add final attempt */
 330
 331         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 332         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 333                                 IEEE80211_TX_STAT_ACK : 0;
 334
 335         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 336                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 337                         tx_resp->rate, tx_resp->failure_frame);
 338
 339         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
 340         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 341
 342         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 343                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 344 }
 345
 346
 347
 348 /*****************************************************************************
 349  *
 350  * Intel PRO/Wireless 3945ABG/BG Network Connection
 351  *
 352  *  RX handler implementations
 353  *
 354  *****************************************************************************/
 355 #ifdef CONFIG_IWLWIFI_DEBUG
 356 /*
 357  *  based on the assumption of all statistics counter are in DWORD
 358  *  FIXME: This function is for debugging, do not deal with
 359  *  the case of counters roll-over.
 360  */
 361 static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
 362                                             __le32 *stats)
 363 {
 364         int i;
 365         __le32 *prev_stats;
 366         u32 *accum_stats;
 367         u32 *delta, *max_delta;
 368
 369         prev_stats = (__le32 *)&priv->_3945.statistics;
 370         accum_stats = (u32 *)&priv->_3945.accum_statistics;
 371         delta = (u32 *)&priv->_3945.delta_statistics;
 372         max_delta = (u32 *)&priv->_3945.max_delta;
 373
 374         for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
 375              i += sizeof(__le32), stats++, prev_stats++, delta++,
 376              max_delta++, accum_stats++) {
 377                 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
 378                         *delta = (le32_to_cpu(*stats) -
 379                                 le32_to_cpu(*prev_stats));
 380                         *accum_stats += *delta;
 381                         if (*delta > *max_delta)
 382                                 *max_delta = *delta;
 383                 }
 384         }
 385
 386         /* reset accumulative statistics for "no-counter" type statistics */
 387         priv->_3945.accum_statistics.general.temperature =
 388                 priv->_3945.statistics.general.temperature;
 389         priv->_3945.accum_statistics.general.ttl_timestamp =
 390                 priv->_3945.statistics.general.ttl_timestamp;
 391 }
 392 #endif
 393
 394 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
 395                 struct iwl_rx_mem_buffer *rxb)
 396 {
 397         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 398
 399         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
 400                      (int)sizeof(struct iwl3945_notif_statistics),
 401                      le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
 402 #ifdef CONFIG_IWLWIFI_DEBUG
 403         iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
 404 #endif
 405
 406         memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
 407 }
 408
 409 void iwl3945_reply_statistics(struct iwl_priv *priv,
 410                               struct iwl_rx_mem_buffer *rxb)
 411 {
 412         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 413         __le32 *flag = (__le32 *)&pkt->u.raw;
 414
 415         if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
 416 #ifdef CONFIG_IWLWIFI_DEBUG
 417                 memset(&priv->_3945.accum_statistics, 0,
 418                         sizeof(struct iwl3945_notif_statistics));
 419                 memset(&priv->_3945.delta_statistics, 0,
 420                         sizeof(struct iwl3945_notif_statistics));
 421                 memset(&priv->_3945.max_delta, 0,
 422                         sizeof(struct iwl3945_notif_statistics));
 423 #endif
 424                 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
 425         }
 426         iwl3945_hw_rx_statistics(priv, rxb);
 427 }
 428
 429
 430 /******************************************************************************
 431  *
 432  * Misc. internal state and helper functions
 433  *
 434  ******************************************************************************/
 435 #ifdef CONFIG_IWLWIFI_DEBUG
 436
 437 /**
 438  * iwl3945_report_frame - dump frame to syslog during debug sessions
 439  *
 440  * You may hack this function to show different aspects of received frames,
 441  * including selective frame dumps.
 442  * group100 parameter selects whether to show 1 out of 100 good frames.
 443  */
 444 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
 445                       struct iwl_rx_packet *pkt,
 446                       struct ieee80211_hdr *header, int group100)
 447 {
 448         u32 to_us;
 449         u32 print_summary = 0;
 450         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
 451         u32 hundred = 0;
 452         u32 dataframe = 0;
 453         __le16 fc;
 454         u16 seq_ctl;
 455         u16 channel;
 456         u16 phy_flags;
 457         u16 length;
 458         u16 status;
 459         u16 bcn_tmr;
 460         u32 tsf_low;
 461         u64 tsf;
 462         u8 rssi;
 463         u8 agc;
 464         u16 sig_avg;
 465         u16 noise_diff;
 466         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 467         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 468         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 469         u8 *data = IWL_RX_DATA(pkt);
 470
 471         /* MAC header */
 472         fc = header->frame_control;
 473         seq_ctl = le16_to_cpu(header->seq_ctrl);
 474
 475         /* metadata */
 476         channel = le16_to_cpu(rx_hdr->channel);
 477         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
 478         length = le16_to_cpu(rx_hdr->len);
 479
 480         /* end-of-frame status and timestamp */
 481         status = le32_to_cpu(rx_end->status);
 482         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
 483         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
 484         tsf = le64_to_cpu(rx_end->timestamp);
 485
 486         /* signal statistics */
 487         rssi = rx_stats->rssi;
 488         agc = rx_stats->agc;
 489         sig_avg = le16_to_cpu(rx_stats->sig_avg);
 490         noise_diff = le16_to_cpu(rx_stats->noise_diff);
 491
 492         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
 493
 494         /* if data frame is to us and all is good,
 495          *   (optionally) print summary for only 1 out of every 100 */
 496         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
 497             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
 498                 dataframe = 1;
 499                 if (!group100)
 500                         print_summary = 1;      /* print each frame */
 501                 else if (priv->framecnt_to_us < 100) {
 502                         priv->framecnt_to_us++;
 503                         print_summary = 0;
 504                 } else {
 505                         priv->framecnt_to_us = 0;
 506                         print_summary = 1;
 507                         hundred = 1;
 508                 }
 509         } else {
 510                 /* print summary for all other frames */
 511                 print_summary = 1;
 512         }
 513
 514         if (print_summary) {
 515                 char *title;
 516                 int rate;
 517
 518                 if (hundred)
 519                         title = "100Frames";
 520                 else if (ieee80211_has_retry(fc))
 521                         title = "Retry";
 522                 else if (ieee80211_is_assoc_resp(fc))
 523                         title = "AscRsp";
 524                 else if (ieee80211_is_reassoc_resp(fc))
 525                         title = "RasRsp";
 526                 else if (ieee80211_is_probe_resp(fc)) {
 527                         title = "PrbRsp";
 528                         print_dump = 1; /* dump frame contents */
 529                 } else if (ieee80211_is_beacon(fc)) {
 530                         title = "Beacon";
 531                         print_dump = 1; /* dump frame contents */
 532                 } else if (ieee80211_is_atim(fc))
 533                         title = "ATIM";
 534                 else if (ieee80211_is_auth(fc))
 535                         title = "Auth";
 536                 else if (ieee80211_is_deauth(fc))
 537                         title = "DeAuth";
 538                 else if (ieee80211_is_disassoc(fc))
 539                         title = "DisAssoc";
 540                 else
 541                         title = "Frame";
 542
 543                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 544                 if (rate == -1)
 545                         rate = 0;
 546                 else
 547                         rate = iwl3945_rates[rate].ieee / 2;
 548
 549                 /* print frame summary.
 550                  * MAC addresses show just the last byte (for brevity),
 551                  *    but you can hack it to show more, if you'd like to. */
 552                 if (dataframe)
 553                         IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
 554                                      "len=%u, rssi=%d, chnl=%d, rate=%d,\n",
 555                                      title, le16_to_cpu(fc), header->addr1[5],
 556                                      length, rssi, channel, rate);
 557                 else {
 558                         /* src/dst addresses assume managed mode */
 559                         IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
 560                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
 561                                      "phy=0x%02x, chnl=%d\n",
 562                                      title, le16_to_cpu(fc), header->addr1[5],
 563                                      header->addr3[5], rssi,
 564                                      tsf_low - priv->scan_start_tsf,
 565                                      phy_flags, channel);
 566                 }
 567         }
 568         if (print_dump)
 569                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
 570 }
 571
 572 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 573                       struct iwl_rx_packet *pkt,
 574                       struct ieee80211_hdr *header, int group100)
 575 {
 576         if (iwl_get_debug_level(priv) & IWL_DL_RX)
 577                 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
 578 }
 579
 580 #else
 581 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 582                       struct iwl_rx_packet *pkt,
 583                       struct ieee80211_hdr *header, int group100)
 584 {
 585 }
 586 #endif
 587
 588 /* This is necessary only for a number of statistics, see the caller. */
 589 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 590                 struct ieee80211_hdr *header)
 591 {
 592         /* Filter incoming packets to determine if they are targeted toward
 593          * this network, discarding packets coming from ourselves */
 594         switch (priv->iw_mode) {
 595         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 596                 /* packets to our IBSS update information */
 597                 return !compare_ether_addr(header->addr3, priv->bssid);
 598         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 599                 /* packets to our IBSS update information */
 600                 return !compare_ether_addr(header->addr2, priv->bssid);
 601         default:
 602                 return 1;
 603         }
 604 }
 605
 606 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 607                                    struct iwl_rx_mem_buffer *rxb,
 608                                    struct ieee80211_rx_status *stats)
 609 {
 610         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 611         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 612         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 613         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 614         u16 len = le16_to_cpu(rx_hdr->len);
 615         struct sk_buff *skb;
 616         __le16 fc = hdr->frame_control;
 617
 618         /* We received data from the HW, so stop the watchdog */
 619         if (unlikely(len + IWL39_RX_FRAME_SIZE >
 620                      PAGE_SIZE << priv->hw_params.rx_page_order)) {
 621                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
 622                 return;
 623         }
 624
 625         /* We only process data packets if the interface is open */
 626         if (unlikely(!priv->is_open)) {
 627                 IWL_DEBUG_DROP_LIMIT(priv,
 628                         "Dropping packet while interface is not open.\n");
 629                 return;
 630         }
 631
 632         skb = dev_alloc_skb(128);
 633         if (!skb) {
 634                 IWL_ERR(priv, "dev_alloc_skb failed\n");
 635                 return;
 636         }
 637
 638         if (!iwl3945_mod_params.sw_crypto)
 639                 iwl_set_decrypted_flag(priv,
 640                                        (struct ieee80211_hdr *)rxb_addr(rxb),
 641                                        le32_to_cpu(rx_end->status), stats);
 642
 643         skb_add_rx_frag(skb, 0, rxb->page,
 644                         (void *)rx_hdr->payload - (void *)pkt, len);
 645
 646         iwl_update_stats(priv, false, fc, len);
 647         memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
 648
 649         ieee80211_rx(priv->hw, skb);
 650         priv->alloc_rxb_page--;
 651         rxb->page = NULL;
 652 }
 653
 654 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 655
 656 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 657                                 struct iwl_rx_mem_buffer *rxb)
 658 {
 659         struct ieee80211_hdr *header;
 660         struct ieee80211_rx_status rx_status;
 661         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 662         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 663         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 664         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 665         u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
 666         u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
 667         u8 network_packet;
 668
 669         rx_status.flag = 0;
 670         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 671         rx_status.freq =
 672                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 673         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 674                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 675
 676         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 677         if (rx_status.band == IEEE80211_BAND_5GHZ)
 678                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 679
 680         rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
 681                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 682
 683         /* set the preamble flag if appropriate */
 684         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 685                 rx_status.flag |= RX_FLAG_SHORTPRE;
 686
 687         if ((unlikely(rx_stats->phy_count > 20))) {
 688                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
 689                                 rx_stats->phy_count);
 690                 return;
 691         }
 692
 693         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 694             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 695                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 696                 return;
 697         }
 698
 699
 700
 701         /* Convert 3945's rssi indicator to dBm */
 702         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 703
 704         IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
 705                         rx_status.signal, rx_stats_sig_avg,
 706                         rx_stats_noise_diff);
 707
 708         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 709
 710         network_packet = iwl3945_is_network_packet(priv, header);
 711
 712         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
 713                               network_packet ? '*' : ' ',
 714                               le16_to_cpu(rx_hdr->channel),
 715                               rx_status.signal, rx_status.signal,
 716                               rx_status.rate_idx);
 717
 718         /* Set "1" to report good data frames in groups of 100 */
 719         iwl3945_dbg_report_frame(priv, pkt, header, 1);
 720         iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
 721
 722         if (network_packet) {
 723                 priv->_3945.last_beacon_time =
 724                         le32_to_cpu(rx_end->beacon_timestamp);
 725                 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
 726                 priv->_3945.last_rx_rssi = rx_status.signal;
 727         }
 728
 729         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 730 }
 731
 732 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 733                                      struct iwl_tx_queue *txq,
 734                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 735 {
 736         int count;
 737         struct iwl_queue *q;
 738         struct iwl3945_tfd *tfd, *tfd_tmp;
 739
 740         q = &txq->q;
 741         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 742         tfd = &tfd_tmp[q->write_ptr];
 743
 744         if (reset)
 745                 memset(tfd, 0, sizeof(*tfd));
 746
 747         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 748
 749         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 750                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 751                           NUM_TFD_CHUNKS);
 752                 return -EINVAL;
 753         }
 754
 755         tfd->tbs[count].addr = cpu_to_le32(addr);
 756         tfd->tbs[count].len = cpu_to_le32(len);
 757
 758         count++;
 759
 760         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 761                                          TFD_CTL_PAD_SET(pad));
 762
 763         return 0;
 764 }
 765
 766 /**
 767  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 768  *
 769  * Does NOT advance any indexes
 770  */
 771 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 772 {
 773         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 774         int index = txq->q.read_ptr;
 775         struct iwl3945_tfd *tfd = &tfd_tmp[index];
 776         struct pci_dev *dev = priv->pci_dev;
 777         int i;
 778         int counter;
 779
 780         /* sanity check */
 781         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 782         if (counter > NUM_TFD_CHUNKS) {
 783                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 784                 /* @todo issue fatal error, it is quite serious situation */
 785                 return;
 786         }
 787
 788         /* Unmap tx_cmd */
 789         if (counter)
 790                 pci_unmap_single(dev,
 791                                 pci_unmap_addr(&txq->meta[index], mapping),
 792                                 pci_unmap_len(&txq->meta[index], len),
 793                                 PCI_DMA_TODEVICE);
 794
 795         /* unmap chunks if any */
 796
 797         for (i = 1; i < counter; i++) {
 798                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 799                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 800                 if (txq->txb[txq->q.read_ptr].skb[0]) {
 801                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
 802                         if (txq->txb[txq->q.read_ptr].skb[0]) {
 803                                 /* Can be called from interrupt context */
 804                                 dev_kfree_skb_any(skb);
 805                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
 806                         }
 807                 }
 808         }
 809         return ;
 810 }
 811
 812 /**
 813  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 814  *
 815 */
 816 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
 817                                   struct iwl_device_cmd *cmd,
 818                                   struct ieee80211_tx_info *info,
 819                                   struct ieee80211_hdr *hdr,
 820                                   int sta_id, int tx_id)
 821 {
 822         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 823         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
 824         u16 rate_mask;
 825         int rate;
 826         u8 rts_retry_limit;
 827         u8 data_retry_limit;
 828         __le32 tx_flags;
 829         __le16 fc = hdr->frame_control;
 830         struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 831
 832         rate = iwl3945_rates[rate_index].plcp;
 833         tx_flags = tx_cmd->tx_flags;
 834
 835         /* We need to figure out how to get the sta->supp_rates while
 836          * in this running context */
 837         rate_mask = IWL_RATES_MASK;
 838
 839
 840         /* Set retry limit on DATA packets and Probe Responses*/
 841         if (ieee80211_is_probe_resp(fc))
 842                 data_retry_limit = 3;
 843         else
 844                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 845         tx_cmd->data_retry_limit = data_retry_limit;
 846
 847         if (tx_id >= IWL_CMD_QUEUE_NUM)
 848                 rts_retry_limit = 3;
 849         else
 850                 rts_retry_limit = 7;
 851
 852         if (data_retry_limit < rts_retry_limit)
 853                 rts_retry_limit = data_retry_limit;
 854         tx_cmd->rts_retry_limit = rts_retry_limit;
 855
 856         if (ieee80211_is_mgmt(fc)) {
 857                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 858                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 859                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 860                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 861                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 862                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 863                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 864                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 865                         }
 866                         break;
 867                 default:
 868                         break;
 869                 }
 870         }
 871
 872         tx_cmd->rate = rate;
 873         tx_cmd->tx_flags = tx_flags;
 874
 875         /* OFDM */
 876         tx_cmd->supp_rates[0] =
 877            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 878
 879         /* CCK */
 880         tx_cmd->supp_rates[1] = (rate_mask & 0xF);
 881
 882         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 883                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 884                        tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
 885                        tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
 886 }
 887
 888 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
 889 {
 890         unsigned long flags_spin;
 891         struct iwl_station_entry *station;
 892
 893         if (sta_id == IWL_INVALID_STATION)
 894                 return IWL_INVALID_STATION;
 895
 896         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 897         station = &priv->stations[sta_id];
 898
 899         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 900         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 901         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 902
 903         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 904
 905         iwl_send_add_sta(priv, &station->sta, flags);
 906         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
 907                         sta_id, tx_rate);
 908         return sta_id;
 909 }
 910
 911 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 912 {
 913         if (src == IWL_PWR_SRC_VAUX) {
 914                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
 915                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 916                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 917                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 918
 919                         iwl_poll_bit(priv, CSR_GPIO_IN,
 920                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 921                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 922                 }
 923         } else {
 924                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 925                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 926                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 927
 928                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 929                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 930         }
 931
 932         return 0;
 933 }
 934
 935 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 936 {
 937         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
 938         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 939         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 940         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 941                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 942                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 943                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 944                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 945                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 946                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 947                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 948                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 949
 950         /* fake read to flush all prev I/O */
 951         iwl_read_direct32(priv, FH39_RSSR_CTRL);
 952
 953         return 0;
 954 }
 955
 956 static int iwl3945_tx_reset(struct iwl_priv *priv)
 957 {
 958
 959         /* bypass mode */
 960         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
 961
 962         /* RA 0 is active */
 963         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
 964
 965         /* all 6 fifo are active */
 966         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
 967
 968         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
 969         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
 970         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
 971         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
 972
 973         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
 974                              priv->_3945.shared_phys);
 975
 976         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
 977                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
 978                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
 979                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
 980                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
 981                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
 982                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
 983                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
 984
 985
 986         return 0;
 987 }
 988
 989 /**
 990  * iwl3945_txq_ctx_reset - Reset TX queue context
 991  *
 992  * Destroys all DMA structures and initialize them again
 993  */
 994 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
 995 {
 996         int rc;
 997         int txq_id, slots_num;
 998
 999         iwl3945_hw_txq_ctx_free(priv);
1000
1001         /* allocate tx queue structure */
1002         rc = iwl_alloc_txq_mem(priv);
1003         if (rc)
1004                 return rc;
1005
1006         /* Tx CMD queue */
1007         rc = iwl3945_tx_reset(priv);
1008         if (rc)
1009                 goto error;
1010
1011         /* Tx queue(s) */
1012         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1013                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1014                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1015                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1016                                        txq_id);
1017                 if (rc) {
1018                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1019                         goto error;
1020                 }
1021         }
1022
1023         return rc;
1024
1025  error:
1026         iwl3945_hw_txq_ctx_free(priv);
1027         return rc;
1028 }
1029
1030
1031 /*
1032  * Start up 3945's basic functionality after it has been reset
1033  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
1034  * NOTE:  This does not load uCode nor start the embedded processor
1035  */
1036 static int iwl3945_apm_init(struct iwl_priv *priv)
1037 {
1038         int ret = iwl_apm_init(priv);
1039
1040         /* Clear APMG (NIC's internal power management) interrupts */
1041         iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1042         iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1043
1044         /* Reset radio chip */
1045         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1046         udelay(5);
1047         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1048
1049         return ret;
1050 }
1051
1052 static void iwl3945_nic_config(struct iwl_priv *priv)
1053 {
1054         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1055         unsigned long flags;
1056         u8 rev_id = 0;
1057
1058         spin_lock_irqsave(&priv->lock, flags);
1059
1060         /* Determine HW type */
1061         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1062
1063         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1064
1065         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1066                 IWL_DEBUG_INFO(priv, "RTP type\n");
1067         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1068                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1069                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1070                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1071         } else {
1072                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1073                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1074                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1075         }
1076
1077         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1078                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1079                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1080                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1081         } else
1082                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1083
1084         if ((eeprom->board_revision & 0xF0) == 0xD0) {
1085                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1086                                eeprom->board_revision);
1087                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1088                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1089         } else {
1090                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1091                                eeprom->board_revision);
1092                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1093                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1094         }
1095
1096         if (eeprom->almgor_m_version <= 1) {
1097                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1098                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1099                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1100                                eeprom->almgor_m_version);
1101         } else {
1102                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1103                                eeprom->almgor_m_version);
1104                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1105                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1106         }
1107         spin_unlock_irqrestore(&priv->lock, flags);
1108
1109         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1110                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1111
1112         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1113                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1114 }
1115
1116 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1117 {
1118         int rc;
1119         unsigned long flags;
1120         struct iwl_rx_queue *rxq = &priv->rxq;
1121
1122         spin_lock_irqsave(&priv->lock, flags);
1123         priv->cfg->ops->lib->apm_ops.init(priv);
1124         spin_unlock_irqrestore(&priv->lock, flags);
1125
1126         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1127         if (rc)
1128                 return rc;
1129
1130         priv->cfg->ops->lib->apm_ops.config(priv);
1131
1132         /* Allocate the RX queue, or reset if it is already allocated */
1133         if (!rxq->bd) {
1134                 rc = iwl_rx_queue_alloc(priv);
1135                 if (rc) {
1136                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1137                         return -ENOMEM;
1138                 }
1139         } else
1140                 iwl3945_rx_queue_reset(priv, rxq);
1141
1142         iwl3945_rx_replenish(priv);
1143
1144         iwl3945_rx_init(priv, rxq);
1145
1146
1147         /* Look at using this instead:
1148         rxq->need_update = 1;
1149         iwl_rx_queue_update_write_ptr(priv, rxq);
1150         */
1151
1152         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1153
1154         rc = iwl3945_txq_ctx_reset(priv);
1155         if (rc)
1156                 return rc;
1157
1158         set_bit(STATUS_INIT, &priv->status);
1159
1160         return 0;
1161 }
1162
1163 /**
1164  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1165  *
1166  * Destroy all TX DMA queues and structures
1167  */
1168 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1169 {
1170         int txq_id;
1171
1172         /* Tx queues */
1173         if (priv->txq)
1174                 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1175                      txq_id++)
1176                         if (txq_id == IWL_CMD_QUEUE_NUM)
1177                                 iwl_cmd_queue_free(priv);
1178                         else
1179                                 iwl_tx_queue_free(priv, txq_id);
1180
1181         /* free tx queue structure */
1182         iwl_free_txq_mem(priv);
1183 }
1184
1185 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1186 {
1187         int txq_id;
1188
1189         /* stop SCD */
1190         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1191         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1192
1193         /* reset TFD queues */
1194         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1195                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1196                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1197                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1198                                 1000);
1199         }
1200
1201         iwl3945_hw_txq_ctx_free(priv);
1202 }
1203
1204 /**
1205  * iwl3945_hw_reg_adjust_power_by_temp
1206  * return index delta into power gain settings table
1207 */
1208 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1209 {
1210         return (new_reading - old_reading) * (-11) / 100;
1211 }
1212
1213 /**
1214  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1215  */
1216 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1217 {
1218         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1219 }
1220
1221 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1222 {
1223         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1224 }
1225
1226 /**
1227  * iwl3945_hw_reg_txpower_get_temperature
1228  * get the current temperature by reading from NIC
1229 */
1230 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1231 {
1232         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1233         int temperature;
1234
1235         temperature = iwl3945_hw_get_temperature(priv);
1236
1237         /* driver's okay range is -260 to +25.
1238          *   human readable okay range is 0 to +285 */
1239         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1240
1241         /* handle insane temp reading */
1242         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1243                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1244
1245                 /* if really really hot(?),
1246                  *   substitute the 3rd band/group's temp measured at factory */
1247                 if (priv->last_temperature > 100)
1248                         temperature = eeprom->groups[2].temperature;
1249                 else /* else use most recent "sane" value from driver */
1250                         temperature = priv->last_temperature;
1251         }
1252
1253         return temperature;     /* raw, not "human readable" */
1254 }
1255
1256 /* Adjust Txpower only if temperature variance is greater than threshold.
1257  *
1258  * Both are lower than older versions' 9 degrees */
1259 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1260
1261 /**
1262  * is_temp_calib_needed - determines if new calibration is needed
1263  *
1264  * records new temperature in tx_mgr->temperature.
1265  * replaces tx_mgr->last_temperature *only* if calib needed
1266  *    (assumes caller will actually do the calibration!). */
1267 static int is_temp_calib_needed(struct iwl_priv *priv)
1268 {
1269         int temp_diff;
1270
1271         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1272         temp_diff = priv->temperature - priv->last_temperature;
1273
1274         /* get absolute value */
1275         if (temp_diff < 0) {
1276                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1277                 temp_diff = -temp_diff;
1278         } else if (temp_diff == 0)
1279                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1280         else
1281                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1282
1283         /* if we don't need calibration, *don't* update last_temperature */
1284         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1285                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1286                 return 0;
1287         }
1288
1289         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1290
1291         /* assume that caller will actually do calib ...
1292          *   update the "last temperature" value */
1293         priv->last_temperature = priv->temperature;
1294         return 1;
1295 }
1296
1297 #define IWL_MAX_GAIN_ENTRIES 78
1298 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1299 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1300
1301 /* radio and DSP power table, each step is 1/2 dB.
1302  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1303 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1304         {
1305          {251, 127},            /* 2.4 GHz, highest power */
1306          {251, 127},
1307          {251, 127},
1308          {251, 127},
1309          {251, 125},
1310          {251, 110},
1311          {251, 105},
1312          {251, 98},
1313          {187, 125},
1314          {187, 115},
1315          {187, 108},
1316          {187, 99},
1317          {243, 119},
1318          {243, 111},
1319          {243, 105},
1320          {243, 97},
1321          {243, 92},
1322          {211, 106},
1323          {211, 100},
1324          {179, 120},
1325          {179, 113},
1326          {179, 107},
1327          {147, 125},
1328          {147, 119},
1329          {147, 112},
1330          {147, 106},
1331          {147, 101},
1332          {147, 97},
1333          {147, 91},
1334          {115, 107},
1335          {235, 121},
1336          {235, 115},
1337          {235, 109},
1338          {203, 127},
1339          {203, 121},
1340          {203, 115},
1341          {203, 108},
1342          {203, 102},
1343          {203, 96},
1344          {203, 92},
1345          {171, 110},
1346          {171, 104},
1347          {171, 98},
1348          {139, 116},
1349          {227, 125},
1350          {227, 119},
1351          {227, 113},
1352          {227, 107},
1353          {227, 101},
1354          {227, 96},
1355          {195, 113},
1356          {195, 106},
1357          {195, 102},
1358          {195, 95},
1359          {163, 113},
1360          {163, 106},
1361          {163, 102},
1362          {163, 95},
1363          {131, 113},
1364          {131, 106},
1365          {131, 102},
1366          {131, 95},
1367          {99, 113},
1368          {99, 106},
1369          {99, 102},
1370          {99, 95},
1371          {67, 113},
1372          {67, 106},
1373          {67, 102},
1374          {67, 95},
1375          {35, 113},
1376          {35, 106},
1377          {35, 102},
1378          {35, 95},
1379          {3, 113},
1380          {3, 106},
1381          {3, 102},
1382          {3, 95} },             /* 2.4 GHz, lowest power */
1383         {
1384          {251, 127},            /* 5.x GHz, highest power */
1385          {251, 120},
1386          {251, 114},
1387          {219, 119},
1388          {219, 101},
1389          {187, 113},
1390          {187, 102},
1391          {155, 114},
1392          {155, 103},
1393          {123, 117},
1394          {123, 107},
1395          {123, 99},
1396          {123, 92},
1397          {91, 108},
1398          {59, 125},
1399          {59, 118},
1400          {59, 109},
1401          {59, 102},
1402          {59, 96},
1403          {59, 90},
1404          {27, 104},
1405          {27, 98},
1406          {27, 92},
1407          {115, 118},
1408          {115, 111},
1409          {115, 104},
1410          {83, 126},
1411          {83, 121},
1412          {83, 113},
1413          {83, 105},
1414          {83, 99},
1415          {51, 118},
1416          {51, 111},
1417          {51, 104},
1418          {51, 98},
1419          {19, 116},
1420          {19, 109},
1421          {19, 102},
1422          {19, 98},
1423          {19, 93},
1424          {171, 113},
1425          {171, 107},
1426          {171, 99},
1427          {139, 120},
1428          {139, 113},
1429          {139, 107},
1430          {139, 99},
1431          {107, 120},
1432          {107, 113},
1433          {107, 107},
1434          {107, 99},
1435          {75, 120},
1436          {75, 113},
1437          {75, 107},
1438          {75, 99},
1439          {43, 120},
1440          {43, 113},
1441          {43, 107},
1442          {43, 99},
1443          {11, 120},
1444          {11, 113},
1445          {11, 107},
1446          {11, 99},
1447          {131, 107},
1448          {131, 99},
1449          {99, 120},
1450          {99, 113},
1451          {99, 107},
1452          {99, 99},
1453          {67, 120},
1454          {67, 113},
1455          {67, 107},
1456          {67, 99},
1457          {35, 120},
1458          {35, 113},
1459          {35, 107},
1460          {35, 99},
1461          {3, 120} }             /* 5.x GHz, lowest power */
1462 };
1463
1464 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1465 {
1466         if (index < 0)
1467                 return 0;
1468         if (index >= IWL_MAX_GAIN_ENTRIES)
1469                 return IWL_MAX_GAIN_ENTRIES - 1;
1470         return (u8) index;
1471 }
1472
1473 /* Kick off thermal recalibration check every 60 seconds */
1474 #define REG_RECALIB_PERIOD (60)
1475
1476 /**
1477  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1478  *
1479  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1480  * or 6 Mbit (OFDM) rates.
1481  */
1482 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1483                                s32 rate_index, const s8 *clip_pwrs,
1484                                struct iwl_channel_info *ch_info,
1485                                int band_index)
1486 {
1487         struct iwl3945_scan_power_info *scan_power_info;
1488         s8 power;
1489         u8 power_index;
1490
1491         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1492
1493         /* use this channel group's 6Mbit clipping/saturation pwr,
1494          *   but cap at regulatory scan power restriction (set during init
1495          *   based on eeprom channel data) for this channel.  */
1496         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1497
1498         /* further limit to user's max power preference.
1499          * FIXME:  Other spectrum management power limitations do not
1500          *   seem to apply?? */
1501         power = min(power, priv->tx_power_user_lmt);
1502         scan_power_info->requested_power = power;
1503
1504         /* find difference between new scan *power* and current "normal"
1505          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1506          *   current "normal" temperature-compensated Tx power *index* for
1507          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1508          *   *index*. */
1509         power_index = ch_info->power_info[rate_index].power_table_index
1510             - (power - ch_info->power_info
1511                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1512
1513         /* store reference index that we use when adjusting *all* scan
1514          *   powers.  So we can accommodate user (all channel) or spectrum
1515          *   management (single channel) power changes "between" temperature
1516          *   feedback compensation procedures.
1517          * don't force fit this reference index into gain table; it may be a
1518          *   negative number.  This will help avoid errors when we're at
1519          *   the lower bounds (highest gains, for warmest temperatures)
1520          *   of the table. */
1521
1522         /* don't exceed table bounds for "real" setting */
1523         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1524
1525         scan_power_info->power_table_index = power_index;
1526         scan_power_info->tpc.tx_gain =
1527             power_gain_table[band_index][power_index].tx_gain;
1528         scan_power_info->tpc.dsp_atten =
1529             power_gain_table[band_index][power_index].dsp_atten;
1530 }
1531
1532 /**
1533  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1534  *
1535  * Configures power settings for all rates for the current channel,
1536  * using values from channel info struct, and send to NIC
1537  */
1538 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1539 {
1540         int rate_idx, i;
1541         const struct iwl_channel_info *ch_info = NULL;
1542         struct iwl3945_txpowertable_cmd txpower = {
1543                 .channel = priv->active_rxon.channel,
1544         };
1545
1546         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1547         ch_info = iwl_get_channel_info(priv,
1548                                        priv->band,
1549                                        le16_to_cpu(priv->active_rxon.channel));
1550         if (!ch_info) {
1551                 IWL_ERR(priv,
1552                         "Failed to get channel info for channel %d [%d]\n",
1553                         le16_to_cpu(priv->active_rxon.channel), priv->band);
1554                 return -EINVAL;
1555         }
1556
1557         if (!is_channel_valid(ch_info)) {
1558                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1559                                 "non-Tx channel.\n");
1560                 return 0;
1561         }
1562
1563         /* fill cmd with power settings for all rates for current channel */
1564         /* Fill OFDM rate */
1565         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1566              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1567
1568                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1569                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1570
1571                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1572                                 le16_to_cpu(txpower.channel),
1573                                 txpower.band,
1574                                 txpower.power[i].tpc.tx_gain,
1575                                 txpower.power[i].tpc.dsp_atten,
1576                                 txpower.power[i].rate);
1577         }
1578         /* Fill CCK rates */
1579         for (rate_idx = IWL_FIRST_CCK_RATE;
1580              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1581                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1582                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1583
1584                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1585                                 le16_to_cpu(txpower.channel),
1586                                 txpower.band,
1587                                 txpower.power[i].tpc.tx_gain,
1588                                 txpower.power[i].tpc.dsp_atten,
1589                                 txpower.power[i].rate);
1590         }
1591
1592         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1593                                 sizeof(struct iwl3945_txpowertable_cmd),
1594                                 &txpower);
1595
1596 }
1597
1598 /**
1599  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1600  * @ch_info: Channel to update.  Uses power_info.requested_power.
1601  *
1602  * Replace requested_power and base_power_index ch_info fields for
1603  * one channel.
1604  *
1605  * Called if user or spectrum management changes power preferences.
1606  * Takes into account h/w and modulation limitations (clip power).
1607  *
1608  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1609  *
1610  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1611  *       properly fill out the scan powers, and actual h/w gain settings,
1612  *       and send changes to NIC
1613  */
1614 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1615                              struct iwl_channel_info *ch_info)
1616 {
1617         struct iwl3945_channel_power_info *power_info;
1618         int power_changed = 0;
1619         int i;
1620         const s8 *clip_pwrs;
1621         int power;
1622
1623         /* Get this chnlgrp's rate-to-max/clip-powers table */
1624         clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1625
1626         /* Get this channel's rate-to-current-power settings table */
1627         power_info = ch_info->power_info;
1628
1629         /* update OFDM Txpower settings */
1630         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1631              i++, ++power_info) {
1632                 int delta_idx;
1633
1634                 /* limit new power to be no more than h/w capability */
1635                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1636                 if (power == power_info->requested_power)
1637                         continue;
1638
1639                 /* find difference between old and new requested powers,
1640                  *    update base (non-temp-compensated) power index */
1641                 delta_idx = (power - power_info->requested_power) * 2;
1642                 power_info->base_power_index -= delta_idx;
1643
1644                 /* save new requested power value */
1645                 power_info->requested_power = power;
1646
1647                 power_changed = 1;
1648         }
1649
1650         /* update CCK Txpower settings, based on OFDM 12M setting ...
1651          *    ... all CCK power settings for a given channel are the *same*. */
1652         if (power_changed) {
1653                 power =
1654                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1655                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1656
1657                 /* do all CCK rates' iwl3945_channel_power_info structures */
1658                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1659                         power_info->requested_power = power;
1660                         power_info->base_power_index =
1661                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1662                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1663                         ++power_info;
1664                 }
1665         }
1666
1667         return 0;
1668 }
1669
1670 /**
1671  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1672  *
1673  * NOTE: Returned power limit may be less (but not more) than requested,
1674  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1675  *       (no consideration for h/w clipping limitations).
1676  */
1677 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1678 {
1679         s8 max_power;
1680
1681 #if 0
1682         /* if we're using TGd limits, use lower of TGd or EEPROM */
1683         if (ch_info->tgd_data.max_power != 0)
1684                 max_power = min(ch_info->tgd_data.max_power,
1685                                 ch_info->eeprom.max_power_avg);
1686
1687         /* else just use EEPROM limits */
1688         else
1689 #endif
1690                 max_power = ch_info->eeprom.max_power_avg;
1691
1692         return min(max_power, ch_info->max_power_avg);
1693 }
1694
1695 /**
1696  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1697  *
1698  * Compensate txpower settings of *all* channels for temperature.
1699  * This only accounts for the difference between current temperature
1700  *   and the factory calibration temperatures, and bases the new settings
1701  *   on the channel's base_power_index.
1702  *
1703  * If RxOn is "associated", this sends the new Txpower to NIC!
1704  */
1705 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1706 {
1707         struct iwl_channel_info *ch_info = NULL;
1708         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1709         int delta_index;
1710         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1711         u8 a_band;
1712         u8 rate_index;
1713         u8 scan_tbl_index;
1714         u8 i;
1715         int ref_temp;
1716         int temperature = priv->temperature;
1717
1718         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1719         for (i = 0; i < priv->channel_count; i++) {
1720                 ch_info = &priv->channel_info[i];
1721                 a_band = is_channel_a_band(ch_info);
1722
1723                 /* Get this chnlgrp's factory calibration temperature */
1724                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1725                     temperature;
1726
1727                 /* get power index adjustment based on current and factory
1728                  * temps */
1729                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1730                                                               ref_temp);
1731
1732                 /* set tx power value for all rates, OFDM and CCK */
1733                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1734                      rate_index++) {
1735                         int power_idx =
1736                             ch_info->power_info[rate_index].base_power_index;
1737
1738                         /* temperature compensate */
1739                         power_idx += delta_index;
1740
1741                         /* stay within table range */
1742                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1743                         ch_info->power_info[rate_index].
1744                             power_table_index = (u8) power_idx;
1745                         ch_info->power_info[rate_index].tpc =
1746                             power_gain_table[a_band][power_idx];
1747                 }
1748
1749                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1750                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1751
1752                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1753                 for (scan_tbl_index = 0;
1754                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1755                         s32 actual_index = (scan_tbl_index == 0) ?
1756                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1757                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1758                                            actual_index, clip_pwrs,
1759                                            ch_info, a_band);
1760                 }
1761         }
1762
1763         /* send Txpower command for current channel to ucode */
1764         return priv->cfg->ops->lib->send_tx_power(priv);
1765 }
1766
1767 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1768 {
1769         struct iwl_channel_info *ch_info;
1770         s8 max_power;
1771         u8 a_band;
1772         u8 i;
1773
1774         if (priv->tx_power_user_lmt == power) {
1775                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1776                                 "limit: %ddBm.\n", power);
1777                 return 0;
1778         }
1779
1780         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1781         priv->tx_power_user_lmt = power;
1782
1783         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1784
1785         for (i = 0; i < priv->channel_count; i++) {
1786                 ch_info = &priv->channel_info[i];
1787                 a_band = is_channel_a_band(ch_info);
1788
1789                 /* find minimum power of all user and regulatory constraints
1790                  *    (does not consider h/w clipping limitations) */
1791                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1792                 max_power = min(power, max_power);
1793                 if (max_power != ch_info->curr_txpow) {
1794                         ch_info->curr_txpow = max_power;
1795
1796                         /* this considers the h/w clipping limitations */
1797                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1798                 }
1799         }
1800
1801         /* update txpower settings for all channels,
1802          *   send to NIC if associated. */
1803         is_temp_calib_needed(priv);
1804         iwl3945_hw_reg_comp_txpower_temp(priv);
1805
1806         return 0;
1807 }
1808
1809 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1810 {
1811         int rc = 0;
1812         struct iwl_rx_packet *pkt;
1813         struct iwl3945_rxon_assoc_cmd rxon_assoc;
1814         struct iwl_host_cmd cmd = {
1815                 .id = REPLY_RXON_ASSOC,
1816                 .len = sizeof(rxon_assoc),
1817                 .flags = CMD_WANT_SKB,
1818                 .data = &rxon_assoc,
1819         };
1820         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1821         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1822
1823         if ((rxon1->flags == rxon2->flags) &&
1824             (rxon1->filter_flags == rxon2->filter_flags) &&
1825             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1826             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1827                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1828                 return 0;
1829         }
1830
1831         rxon_assoc.flags = priv->staging_rxon.flags;
1832         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1833         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1834         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1835         rxon_assoc.reserved = 0;
1836
1837         rc = iwl_send_cmd_sync(priv, &cmd);
1838         if (rc)
1839                 return rc;
1840
1841         pkt = (struct iwl_rx_packet *)cmd.reply_page;
1842         if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1843                 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1844                 rc = -EIO;
1845         }
1846
1847         iwl_free_pages(priv, cmd.reply_page);
1848
1849         return rc;
1850 }
1851
1852 /**
1853  * iwl3945_commit_rxon - commit staging_rxon to hardware
1854  *
1855  * The RXON command in staging_rxon is committed to the hardware and
1856  * the active_rxon structure is updated with the new data.  This
1857  * function correctly transitions out of the RXON_ASSOC_MSK state if
1858  * a HW tune is required based on the RXON structure changes.
1859  */
1860 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1861 {
1862         /* cast away the const for active_rxon in this function */
1863         struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1864         struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1865         int rc = 0;
1866         bool new_assoc =
1867                 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1868
1869         if (!iwl_is_alive(priv))
1870                 return -1;
1871
1872         /* always get timestamp with Rx frame */
1873         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1874
1875         /* select antenna */
1876         staging_rxon->flags &=
1877             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1878         staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1879
1880         rc = iwl_check_rxon_cmd(priv);
1881         if (rc) {
1882                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
1883                 return -EINVAL;
1884         }
1885
1886         /* If we don't need to send a full RXON, we can use
1887          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1888          * and other flags for the current radio configuration. */
1889         if (!iwl_full_rxon_required(priv)) {
1890                 rc = iwl_send_rxon_assoc(priv);
1891                 if (rc) {
1892                         IWL_ERR(priv, "Error setting RXON_ASSOC "
1893                                   "configuration (%d).\n", rc);
1894                         return rc;
1895                 }
1896
1897                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1898
1899                 return 0;
1900         }
1901
1902         /* If we are currently associated and the new config requires
1903          * an RXON_ASSOC and the new config wants the associated mask enabled,
1904          * we must clear the associated from the active configuration
1905          * before we apply the new config */
1906         if (iwl_is_associated(priv) && new_assoc) {
1907                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1908                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1909
1910                 /*
1911                  * reserved4 and 5 could have been filled by the iwlcore code.
1912                  * Let's clear them before pushing to the 3945.
1913                  */
1914                 active_rxon->reserved4 = 0;
1915                 active_rxon->reserved5 = 0;
1916                 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1917                                       sizeof(struct iwl3945_rxon_cmd),
1918                                       &priv->active_rxon);
1919
1920                 /* If the mask clearing failed then we set
1921                  * active_rxon back to what it was previously */
1922                 if (rc) {
1923                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1924                         IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1925                                   "configuration (%d).\n", rc);
1926                         return rc;
1927                 }
1928                 iwl_clear_ucode_stations(priv, false);
1929                 iwl_restore_stations(priv);
1930         }
1931
1932         IWL_DEBUG_INFO(priv, "Sending RXON\n"
1933                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1934                        "* channel = %d\n"
1935                        "* bssid = %pM\n",
1936                        (new_assoc ? "" : "out"),
1937                        le16_to_cpu(staging_rxon->channel),
1938                        staging_rxon->bssid_addr);
1939
1940         /*
1941          * reserved4 and 5 could have been filled by the iwlcore code.
1942          * Let's clear them before pushing to the 3945.
1943          */
1944         staging_rxon->reserved4 = 0;
1945         staging_rxon->reserved5 = 0;
1946
1947         iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1948
1949         /* Apply the new configuration */
1950         rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1951                               sizeof(struct iwl3945_rxon_cmd),
1952                               staging_rxon);
1953         if (rc) {
1954                 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1955                 return rc;
1956         }
1957
1958         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1959
1960         if (!new_assoc) {
1961                 iwl_clear_ucode_stations(priv, false);
1962                 iwl_restore_stations(priv);
1963         }
1964
1965         /* If we issue a new RXON command which required a tune then we must
1966          * send a new TXPOWER command or we won't be able to Tx any frames */
1967         rc = priv->cfg->ops->lib->send_tx_power(priv);
1968         if (rc) {
1969                 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1970                 return rc;
1971         }
1972
1973         /* Init the hardware's rate fallback order based on the band */
1974         rc = iwl3945_init_hw_rate_table(priv);
1975         if (rc) {
1976                 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1977                 return -EIO;
1978         }
1979
1980         return 0;
1981 }
1982
1983 /**
1984  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1985  *
1986  * -- reset periodic timer
1987  * -- see if temp has changed enough to warrant re-calibration ... if so:
1988  *     -- correct coeffs for temp (can reset temp timer)
1989  *     -- save this temp as "last",
1990  *     -- send new set of gain settings to NIC
1991  * NOTE:  This should continue working, even when we're not associated,
1992  *   so we can keep our internal table of scan powers current. */
1993 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1994 {
1995         /* This will kick in the "brute force"
1996          * iwl3945_hw_reg_comp_txpower_temp() below */
1997         if (!is_temp_calib_needed(priv))
1998                 goto reschedule;
1999
2000         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2001          * This is based *only* on current temperature,
2002          * ignoring any previous power measurements */
2003         iwl3945_hw_reg_comp_txpower_temp(priv);
2004
2005  reschedule:
2006         queue_delayed_work(priv->workqueue,
2007                            &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
2008 }
2009
2010 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2011 {
2012         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2013                                              _3945.thermal_periodic.work);
2014
2015         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2016                 return;
2017
2018         mutex_lock(&priv->mutex);
2019         iwl3945_reg_txpower_periodic(priv);
2020         mutex_unlock(&priv->mutex);
2021 }
2022
2023 /**
2024  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2025  *                                 for the channel.
2026  *
2027  * This function is used when initializing channel-info structs.
2028  *
2029  * NOTE: These channel groups do *NOT* match the bands above!
2030  *       These channel groups are based on factory-tested channels;
2031  *       on A-band, EEPROM's "group frequency" entries represent the top
2032  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
2033  */
2034 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2035                                        const struct iwl_channel_info *ch_info)
2036 {
2037         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2038         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2039         u8 group;
2040         u16 group_index = 0;    /* based on factory calib frequencies */
2041         u8 grp_channel;
2042
2043         /* Find the group index for the channel ... don't use index 1(?) */
2044         if (is_channel_a_band(ch_info)) {
2045                 for (group = 1; group < 5; group++) {
2046                         grp_channel = ch_grp[group].group_channel;
2047                         if (ch_info->channel <= grp_channel) {
2048                                 group_index = group;
2049                                 break;
2050                         }
2051                 }
2052                 /* group 4 has a few channels *above* its factory cal freq */
2053                 if (group == 5)
2054                         group_index = 4;
2055         } else
2056                 group_index = 0;        /* 2.4 GHz, group 0 */
2057
2058         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2059                         group_index);
2060         return group_index;
2061 }
2062
2063 /**
2064  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2065  *
2066  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2067  *   into radio/DSP gain settings table for requested power.
2068  */
2069 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2070                                        s8 requested_power,
2071                                        s32 setting_index, s32 *new_index)
2072 {
2073         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2074         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2075         s32 index0, index1;
2076         s32 power = 2 * requested_power;
2077         s32 i;
2078         const struct iwl3945_eeprom_txpower_sample *samples;
2079         s32 gains0, gains1;
2080         s32 res;
2081         s32 denominator;
2082
2083         chnl_grp = &eeprom->groups[setting_index];
2084         samples = chnl_grp->samples;
2085         for (i = 0; i < 5; i++) {
2086                 if (power == samples[i].power) {
2087                         *new_index = samples[i].gain_index;
2088                         return 0;
2089                 }
2090         }
2091
2092         if (power > samples[1].power) {
2093                 index0 = 0;
2094                 index1 = 1;
2095         } else if (power > samples[2].power) {
2096                 index0 = 1;
2097                 index1 = 2;
2098         } else if (power > samples[3].power) {
2099                 index0 = 2;
2100                 index1 = 3;
2101         } else {
2102                 index0 = 3;
2103                 index1 = 4;
2104         }
2105
2106         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2107         if (denominator == 0)
2108                 return -EINVAL;
2109         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2110         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2111         res = gains0 + (gains1 - gains0) *
2112             ((s32) power - (s32) samples[index0].power) / denominator +
2113             (1 << 18);
2114         *new_index = res >> 19;
2115         return 0;
2116 }
2117
2118 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2119 {
2120         u32 i;
2121         s32 rate_index;
2122         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2123         const struct iwl3945_eeprom_txpower_group *group;
2124
2125         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2126
2127         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2128                 s8 *clip_pwrs;  /* table of power levels for each rate */
2129                 s8 satur_pwr;   /* saturation power for each chnl group */
2130                 group = &eeprom->groups[i];
2131
2132                 /* sanity check on factory saturation power value */
2133                 if (group->saturation_power < 40) {
2134                         IWL_WARN(priv, "Error: saturation power is %d, "
2135                                     "less than minimum expected 40\n",
2136                                     group->saturation_power);
2137                         return;
2138                 }
2139
2140                 /*
2141                  * Derive requested power levels for each rate, based on
2142                  *   hardware capabilities (saturation power for band).
2143                  * Basic value is 3dB down from saturation, with further
2144                  *   power reductions for highest 3 data rates.  These
2145                  *   backoffs provide headroom for high rate modulation
2146                  *   power peaks, without too much distortion (clipping).
2147                  */
2148                 /* we'll fill in this array with h/w max power levels */
2149                 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
2150
2151                 /* divide factory saturation power by 2 to find -3dB level */
2152                 satur_pwr = (s8) (group->saturation_power >> 1);
2153
2154                 /* fill in channel group's nominal powers for each rate */
2155                 for (rate_index = 0;
2156                      rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
2157                         switch (rate_index) {
2158                         case IWL_RATE_36M_INDEX_TABLE:
2159                                 if (i == 0)     /* B/G */
2160                                         *clip_pwrs = satur_pwr;
2161                                 else    /* A */
2162                                         *clip_pwrs = satur_pwr - 5;
2163                                 break;
2164                         case IWL_RATE_48M_INDEX_TABLE:
2165                                 if (i == 0)
2166                                         *clip_pwrs = satur_pwr - 7;
2167                                 else
2168                                         *clip_pwrs = satur_pwr - 10;
2169                                 break;
2170                         case IWL_RATE_54M_INDEX_TABLE:
2171                                 if (i == 0)
2172                                         *clip_pwrs = satur_pwr - 9;
2173                                 else
2174                                         *clip_pwrs = satur_pwr - 12;
2175                                 break;
2176                         default:
2177                                 *clip_pwrs = satur_pwr;
2178                                 break;
2179                         }
2180                 }
2181         }
2182 }
2183
2184 /**
2185  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2186  *
2187  * Second pass (during init) to set up priv->channel_info
2188  *
2189  * Set up Tx-power settings in our channel info database for each VALID
2190  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2191  * and current temperature.
2192  *
2193  * Since this is based on current temperature (at init time), these values may
2194  * not be valid for very long, but it gives us a starting/default point,
2195  * and allows us to active (i.e. using Tx) scan.
2196  *
2197  * This does *not* write values to NIC, just sets up our internal table.
2198  */
2199 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2200 {
2201         struct iwl_channel_info *ch_info = NULL;
2202         struct iwl3945_channel_power_info *pwr_info;
2203         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2204         int delta_index;
2205         u8 rate_index;
2206         u8 scan_tbl_index;
2207         const s8 *clip_pwrs;    /* array of power levels for each rate */
2208         u8 gain, dsp_atten;
2209         s8 power;
2210         u8 pwr_index, base_pwr_index, a_band;
2211         u8 i;
2212         int temperature;
2213
2214         /* save temperature reference,
2215          *   so we can determine next time to calibrate */
2216         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2217         priv->last_temperature = temperature;
2218
2219         iwl3945_hw_reg_init_channel_groups(priv);
2220
2221         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2222         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2223              i++, ch_info++) {
2224                 a_band = is_channel_a_band(ch_info);
2225                 if (!is_channel_valid(ch_info))
2226                         continue;
2227
2228                 /* find this channel's channel group (*not* "band") index */
2229                 ch_info->group_index =
2230                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2231
2232                 /* Get this chnlgrp's rate->max/clip-powers table */
2233                 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
2234
2235                 /* calculate power index *adjustment* value according to
2236                  *  diff between current temperature and factory temperature */
2237                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2238                                 eeprom->groups[ch_info->group_index].
2239                                 temperature);
2240
2241                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2242                                 ch_info->channel, delta_index, temperature +
2243                                 IWL_TEMP_CONVERT);
2244
2245                 /* set tx power value for all OFDM rates */
2246                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2247                      rate_index++) {
2248                         s32 uninitialized_var(power_idx);
2249                         int rc;
2250
2251                         /* use channel group's clip-power table,
2252                          *   but don't exceed channel's max power */
2253                         s8 pwr = min(ch_info->max_power_avg,
2254                                      clip_pwrs[rate_index]);
2255
2256                         pwr_info = &ch_info->power_info[rate_index];
2257
2258                         /* get base (i.e. at factory-measured temperature)
2259                          *    power table index for this rate's power */
2260                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2261                                                          ch_info->group_index,
2262                                                          &power_idx);
2263                         if (rc) {
2264                                 IWL_ERR(priv, "Invalid power index\n");
2265                                 return rc;
2266                         }
2267                         pwr_info->base_power_index = (u8) power_idx;
2268
2269                         /* temperature compensate */
2270                         power_idx += delta_index;
2271
2272                         /* stay within range of gain table */
2273                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2274
2275                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2276                         pwr_info->requested_power = pwr;
2277                         pwr_info->power_table_index = (u8) power_idx;
2278                         pwr_info->tpc.tx_gain =
2279                             power_gain_table[a_band][power_idx].tx_gain;
2280                         pwr_info->tpc.dsp_atten =
2281                             power_gain_table[a_band][power_idx].dsp_atten;
2282                 }
2283
2284                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2285                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2286                 power = pwr_info->requested_power +
2287                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2288                 pwr_index = pwr_info->power_table_index +
2289                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2290                 base_pwr_index = pwr_info->base_power_index +
2291                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2292
2293                 /* stay within table range */
2294                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2295                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2296                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2297
2298                 /* fill each CCK rate's iwl3945_channel_power_info structure
2299                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2300                  * NOTE:  CCK rates start at end of OFDM rates! */
2301                 for (rate_index = 0;
2302                      rate_index < IWL_CCK_RATES; rate_index++) {
2303                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2304                         pwr_info->requested_power = power;
2305                         pwr_info->power_table_index = pwr_index;
2306                         pwr_info->base_power_index = base_pwr_index;
2307                         pwr_info->tpc.tx_gain = gain;
2308                         pwr_info->tpc.dsp_atten = dsp_atten;
2309                 }
2310
2311                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2312                 for (scan_tbl_index = 0;
2313                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2314                         s32 actual_index = (scan_tbl_index == 0) ?
2315                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2316                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2317                                 actual_index, clip_pwrs, ch_info, a_band);
2318                 }
2319         }
2320
2321         return 0;
2322 }
2323
2324 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2325 {
2326         int rc;
2327
2328         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2329         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2330                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2331         if (rc < 0)
2332                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2333
2334         return 0;
2335 }
2336
2337 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2338 {
2339         int txq_id = txq->q.id;
2340
2341         struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
2342
2343         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2344
2345         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2346         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2347
2348         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2349                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2350                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2351                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2352                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2353                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2354
2355         /* fake read to flush all prev. writes */
2356         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2357
2358         return 0;
2359 }
2360
2361 /*
2362  * HCMD utils
2363  */
2364 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2365 {
2366         switch (cmd_id) {
2367         case REPLY_RXON:
2368                 return sizeof(struct iwl3945_rxon_cmd);
2369         case POWER_TABLE_CMD:
2370                 return sizeof(struct iwl3945_powertable_cmd);
2371         default:
2372                 return len;
2373         }
2374 }
2375
2376
2377 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2378 {
2379         struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2380         addsta->mode = cmd->mode;
2381         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2382         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2383         addsta->station_flags = cmd->station_flags;
2384         addsta->station_flags_msk = cmd->station_flags_msk;
2385         addsta->tid_disable_tx = cpu_to_le16(0);
2386         addsta->rate_n_flags = cmd->rate_n_flags;
2387         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2388         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2389         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2390
2391         return (u16)sizeof(struct iwl3945_addsta_cmd);
2392 }
2393
2394
2395 /**
2396  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2397  */
2398 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2399 {
2400         int rc, i, index, prev_index;
2401         struct iwl3945_rate_scaling_cmd rate_cmd = {
2402                 .reserved = {0, 0, 0},
2403         };
2404         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2405
2406         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2407                 index = iwl3945_rates[i].table_rs_index;
2408
2409                 table[index].rate_n_flags =
2410                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2411                 table[index].try_cnt = priv->retry_rate;
2412                 prev_index = iwl3945_get_prev_ieee_rate(i);
2413                 table[index].next_rate_index =
2414                                 iwl3945_rates[prev_index].table_rs_index;
2415         }
2416
2417         switch (priv->band) {
2418         case IEEE80211_BAND_5GHZ:
2419                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2420                 /* If one of the following CCK rates is used,
2421                  * have it fall back to the 6M OFDM rate */
2422                 for (i = IWL_RATE_1M_INDEX_TABLE;
2423                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2424                         table[i].next_rate_index =
2425                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2426
2427                 /* Don't fall back to CCK rates */
2428                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2429                                                 IWL_RATE_9M_INDEX_TABLE;
2430
2431                 /* Don't drop out of OFDM rates */
2432                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2433                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2434                 break;
2435
2436         case IEEE80211_BAND_2GHZ:
2437                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2438                 /* If an OFDM rate is used, have it fall back to the
2439                  * 1M CCK rates */
2440
2441                 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2442                     iwl_is_associated(priv)) {
2443
2444                         index = IWL_FIRST_CCK_RATE;
2445                         for (i = IWL_RATE_6M_INDEX_TABLE;
2446                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2447                                 table[i].next_rate_index =
2448                                         iwl3945_rates[index].table_rs_index;
2449
2450                         index = IWL_RATE_11M_INDEX_TABLE;
2451                         /* CCK shouldn't fall back to OFDM... */
2452                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2453                 }
2454                 break;
2455
2456         default:
2457                 WARN_ON(1);
2458                 break;
2459         }
2460
2461         /* Update the rate scaling for control frame Tx */
2462         rate_cmd.table_id = 0;
2463         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2464                               &rate_cmd);
2465         if (rc)
2466                 return rc;
2467
2468         /* Update the rate scaling for data frame Tx */
2469         rate_cmd.table_id = 1;
2470         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2471                                 &rate_cmd);
2472 }
2473
2474 /* Called when initializing driver */
2475 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2476 {
2477         memset((void *)&priv->hw_params, 0,
2478                sizeof(struct iwl_hw_params));
2479
2480         priv->_3945.shared_virt =
2481                 dma_alloc_coherent(&priv->pci_dev->dev,
2482                                    sizeof(struct iwl3945_shared),
2483                                    &priv->_3945.shared_phys, GFP_KERNEL);
2484         if (!priv->_3945.shared_virt) {
2485                 IWL_ERR(priv, "failed to allocate pci memory\n");
2486                 return -ENOMEM;
2487         }
2488
2489         /* Assign number of Usable TX queues */
2490         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
2491
2492         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2493         priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2494         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2495         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2496         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2497         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2498
2499         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2500         priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2501
2502         return 0;
2503 }
2504
2505 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2506                           struct iwl3945_frame *frame, u8 rate)
2507 {
2508         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2509         unsigned int frame_size;
2510
2511         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2512         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2513
2514         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2515         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2516
2517         frame_size = iwl3945_fill_beacon_frame(priv,
2518                                 tx_beacon_cmd->frame,
2519                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2520
2521         BUG_ON(frame_size > MAX_MPDU_SIZE);
2522         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2523
2524         tx_beacon_cmd->tx.rate = rate;
2525         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2526                                       TX_CMD_FLG_TSF_MSK);
2527
2528         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2529         tx_beacon_cmd->tx.supp_rates[0] =
2530                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2531
2532         tx_beacon_cmd->tx.supp_rates[1] =
2533                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2534
2535         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2536 }
2537
2538 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2539 {
2540         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2541         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2542 }
2543
2544 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2545 {
2546         INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
2547                           iwl3945_bg_reg_txpower_periodic);
2548 }
2549
2550 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2551 {
2552         cancel_delayed_work(&priv->_3945.thermal_periodic);
2553 }
2554
2555 /* check contents of special bootstrap uCode SRAM */
2556 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2557  {
2558         __le32 *image = priv->ucode_boot.v_addr;
2559         u32 len = priv->ucode_boot.len;
2560         u32 reg;
2561         u32 val;
2562
2563         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2564
2565         /* verify BSM SRAM contents */
2566         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2567         for (reg = BSM_SRAM_LOWER_BOUND;
2568              reg < BSM_SRAM_LOWER_BOUND + len;
2569              reg += sizeof(u32), image++) {
2570                 val = iwl_read_prph(priv, reg);
2571                 if (val != le32_to_cpu(*image)) {
2572                         IWL_ERR(priv, "BSM uCode verification failed at "
2573                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2574                                   BSM_SRAM_LOWER_BOUND,
2575                                   reg - BSM_SRAM_LOWER_BOUND, len,
2576                                   val, le32_to_cpu(*image));
2577                         return -EIO;
2578                 }
2579         }
2580
2581         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2582
2583         return 0;
2584 }
2585
2586
2587 /******************************************************************************
2588  *
2589  * EEPROM related functions
2590  *
2591  ******************************************************************************/
2592
2593 /*
2594  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2595  * embedded controller) as EEPROM reader; each read is a series of pulses
2596  * to/from the EEPROM chip, not a single event, so even reads could conflict
2597  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2598  * simply claims ownership, which should be safe when this function is called
2599  * (i.e. before loading uCode!).
2600  */
2601 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2602 {
2603         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2604         return 0;
2605 }
2606
2607
2608 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2609 {
2610         return;
2611 }
2612
2613  /**
2614   * iwl3945_load_bsm - Load bootstrap instructions
2615   *
2616   * BSM operation:
2617   *
2618   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2619   * in special SRAM that does not power down during RFKILL.  When powering back
2620   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2621   * the bootstrap program into the on-board processor, and starts it.
2622   *
2623   * The bootstrap program loads (via DMA) instructions and data for a new
2624   * program from host DRAM locations indicated by the host driver in the
2625   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2626   * automatically.
2627   *
2628   * When initializing the NIC, the host driver points the BSM to the
2629   * "initialize" uCode image.  This uCode sets up some internal data, then
2630   * notifies host via "initialize alive" that it is complete.
2631   *
2632   * The host then replaces the BSM_DRAM_* pointer values to point to the
2633   * normal runtime uCode instructions and a backup uCode data cache buffer
2634   * (filled initially with starting data values for the on-board processor),
2635   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2636   * which begins normal operation.
2637   *
2638   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2639   * the backup data cache in DRAM before SRAM is powered down.
2640   *
2641   * When powering back up, the BSM loads the bootstrap program.  This reloads
2642   * the runtime uCode instructions and the backup data cache into SRAM,
2643   * and re-launches the runtime uCode from where it left off.
2644   */
2645 static int iwl3945_load_bsm(struct iwl_priv *priv)
2646 {
2647         __le32 *image = priv->ucode_boot.v_addr;
2648         u32 len = priv->ucode_boot.len;
2649         dma_addr_t pinst;
2650         dma_addr_t pdata;
2651         u32 inst_len;
2652         u32 data_len;
2653         int rc;
2654         int i;
2655         u32 done;
2656         u32 reg_offset;
2657
2658         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2659
2660         /* make sure bootstrap program is no larger than BSM's SRAM size */
2661         if (len > IWL39_MAX_BSM_SIZE)
2662                 return -EINVAL;
2663
2664         /* Tell bootstrap uCode where to find the "Initialize" uCode
2665         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2666         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2667         *        after the "initialize" uCode has run, to point to
2668         *        runtime/protocol instructions and backup data cache. */
2669         pinst = priv->ucode_init.p_addr;
2670         pdata = priv->ucode_init_data.p_addr;
2671         inst_len = priv->ucode_init.len;
2672         data_len = priv->ucode_init_data.len;
2673
2674         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2675         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2676         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2677         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2678
2679         /* Fill BSM memory with bootstrap instructions */
2680         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2681              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2682              reg_offset += sizeof(u32), image++)
2683                 _iwl_write_prph(priv, reg_offset,
2684                                           le32_to_cpu(*image));
2685
2686         rc = iwl3945_verify_bsm(priv);
2687         if (rc)
2688                 return rc;
2689
2690         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2691         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2692         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2693                                  IWL39_RTC_INST_LOWER_BOUND);
2694         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2695
2696         /* Load bootstrap code into instruction SRAM now,
2697          *   to prepare to load "initialize" uCode */
2698         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2699                 BSM_WR_CTRL_REG_BIT_START);
2700
2701         /* Wait for load of bootstrap uCode to finish */
2702         for (i = 0; i < 100; i++) {
2703                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2704                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2705                         break;
2706                 udelay(10);
2707         }
2708         if (i < 100)
2709                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2710         else {
2711                 IWL_ERR(priv, "BSM write did not complete!\n");
2712                 return -EIO;
2713         }
2714
2715         /* Enable future boot loads whenever power management unit triggers it
2716          *   (e.g. when powering back up after power-save shutdown) */
2717         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2718                 BSM_WR_CTRL_REG_BIT_START_EN);
2719
2720         return 0;
2721 }
2722
2723 #define IWL3945_UCODE_GET(item)                                         \
2724 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2725                                     u32 api_ver)                        \
2726 {                                                                       \
2727         return le32_to_cpu(ucode->u.v1.item);                           \
2728 }
2729
2730 static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2731 {
2732         return UCODE_HEADER_SIZE(1);
2733 }
2734 static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2735                                    u32 api_ver)
2736 {
2737         return 0;
2738 }
2739 static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2740                                   u32 api_ver)
2741 {
2742         return (u8 *) ucode->u.v1.data;
2743 }
2744
2745 IWL3945_UCODE_GET(inst_size);
2746 IWL3945_UCODE_GET(data_size);
2747 IWL3945_UCODE_GET(init_size);
2748 IWL3945_UCODE_GET(init_data_size);
2749 IWL3945_UCODE_GET(boot_size);
2750
2751 static struct iwl_hcmd_ops iwl3945_hcmd = {
2752         .rxon_assoc = iwl3945_send_rxon_assoc,
2753         .commit_rxon = iwl3945_commit_rxon,
2754         .send_bt_config = iwl_send_bt_config,
2755 };
2756
2757 static struct iwl_ucode_ops iwl3945_ucode = {
2758         .get_header_size = iwl3945_ucode_get_header_size,
2759         .get_build = iwl3945_ucode_get_build,
2760         .get_inst_size = iwl3945_ucode_get_inst_size,
2761         .get_data_size = iwl3945_ucode_get_data_size,
2762         .get_init_size = iwl3945_ucode_get_init_size,
2763         .get_init_data_size = iwl3945_ucode_get_init_data_size,
2764         .get_boot_size = iwl3945_ucode_get_boot_size,
2765         .get_data = iwl3945_ucode_get_data,
2766 };
2767
2768 static struct iwl_lib_ops iwl3945_lib = {
2769         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2770         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2771         .txq_init = iwl3945_hw_tx_queue_init,
2772         .load_ucode = iwl3945_load_bsm,
2773         .dump_nic_event_log = iwl3945_dump_nic_event_log,
2774         .dump_nic_error_log = iwl3945_dump_nic_error_log,
2775         .apm_ops = {
2776                 .init = iwl3945_apm_init,
2777                 .stop = iwl_apm_stop,
2778                 .config = iwl3945_nic_config,
2779                 .set_pwr_src = iwl3945_set_pwr_src,
2780         },
2781         .eeprom_ops = {
2782                 .regulatory_bands = {
2783                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2784                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2785                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2786                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2787                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2788                         EEPROM_REGULATORY_BAND_NO_HT40,
2789                         EEPROM_REGULATORY_BAND_NO_HT40,
2790                 },
2791                 .verify_signature  = iwlcore_eeprom_verify_signature,
2792                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2793                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2794                 .query_addr = iwlcore_eeprom_query_addr,
2795         },
2796         .send_tx_power  = iwl3945_send_tx_power,
2797         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2798         .post_associate = iwl3945_post_associate,
2799         .isr = iwl_isr_legacy,
2800         .config_ap = iwl3945_config_ap,
2801         .add_bcast_station = iwl3945_add_bcast_station,
2802
2803         .debugfs_ops = {
2804                 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2805                 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2806                 .general_stats_read = iwl3945_ucode_general_stats_read,
2807         },
2808 };
2809
2810 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2811         .get_hcmd_size = iwl3945_get_hcmd_size,
2812         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2813         .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
2814         .request_scan = iwl3945_request_scan,
2815 };
2816
2817 static const struct iwl_ops iwl3945_ops = {
2818         .ucode = &iwl3945_ucode,
2819         .lib = &iwl3945_lib,
2820         .hcmd = &iwl3945_hcmd,
2821         .utils = &iwl3945_hcmd_utils,
2822         .led = &iwl3945_led_ops,
2823 };
2824
2825 static struct iwl_cfg iwl3945_bg_cfg = {
2826         .name = "3945BG",
2827         .fw_name_pre = IWL3945_FW_PRE,
2828         .ucode_api_max = IWL3945_UCODE_API_MAX,
2829         .ucode_api_min = IWL3945_UCODE_API_MIN,
2830         .sku = IWL_SKU_G,
2831         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2832         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2833         .ops = &iwl3945_ops,
2834         .num_of_queues = IWL39_NUM_QUEUES,
2835         .mod_params = &iwl3945_mod_params,
2836         .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2837         .set_l0s = false,
2838         .use_bsm = true,
2839         .use_isr_legacy = true,
2840         .ht_greenfield_support = false,
2841         .led_compensation = 64,
2842         .broken_powersave = true,
2843         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2844         .monitor_recover_period = IWL_MONITORING_PERIOD,
2845         .max_event_log_size = 512,
2846 };
2847
2848 static struct iwl_cfg iwl3945_abg_cfg = {
2849         .name = "3945ABG",
2850         .fw_name_pre = IWL3945_FW_PRE,
2851         .ucode_api_max = IWL3945_UCODE_API_MAX,
2852         .ucode_api_min = IWL3945_UCODE_API_MIN,
2853         .sku = IWL_SKU_A|IWL_SKU_G,
2854         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2855         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2856         .ops = &iwl3945_ops,
2857         .num_of_queues = IWL39_NUM_QUEUES,
2858         .mod_params = &iwl3945_mod_params,
2859         .use_isr_legacy = true,
2860         .ht_greenfield_support = false,
2861         .led_compensation = 64,
2862         .broken_powersave = true,
2863         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2864         .monitor_recover_period = IWL_MONITORING_PERIOD,
2865         .max_event_log_size = 512,
2866 };
2867
2868 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
2869         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2870         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2871         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2872         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2873         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2874         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2875         {0}
2876 };
2877
2878 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);