drivers/net/wireless/b43legacy/main.c

   1 /*
   2  *
   3  *  Broadcom B43legacy wireless driver
   4  *
   5  *  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6  *  Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
   7  *  Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
   8  *  Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9  *  Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10  *  Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
  11  *
  12  *  Some parts of the code in this file are derived from the ipw2200
  13  *  driver  Copyright(c) 2003 - 2004 Intel Corporation.
  14
  15  *  This program is free software; you can redistribute it and/or modify
  16  *  it under the terms of the GNU General Public License as published by
  17  *  the Free Software Foundation; either version 2 of the License, or
  18  *  (at your option) any later version.
  19  *
  20  *  This program is distributed in the hope that it will be useful,
  21  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  *  GNU General Public License for more details.
  24  *
  25  *  You should have received a copy of the GNU General Public License
  26  *  along with this program; see the file COPYING.  If not, write to
  27  *  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  28  *  Boston, MA 02110-1301, USA.
  29  *
  30  */
  31
  32 #include <linux/delay.h>
  33 #include <linux/init.h>
  34 #include <linux/module.h>
  35 #include <linux/if_arp.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/firmware.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/sched.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/slab.h>
  43 #include <net/dst.h>
  44 #include <asm/unaligned.h>
  45
  46 #include "b43legacy.h"
  47 #include "main.h"
  48 #include "debugfs.h"
  49 #include "phy.h"
  50 #include "dma.h"
  51 #include "pio.h"
  52 #include "sysfs.h"
  53 #include "xmit.h"
  54 #include "radio.h"
  55
  56
  57 MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
  58 MODULE_AUTHOR("Martin Langer");
  59 MODULE_AUTHOR("Stefano Brivio");
  60 MODULE_AUTHOR("Michael Buesch");
  61 MODULE_LICENSE("GPL");
  62
  63 MODULE_FIRMWARE("b43legacy/ucode2.fw");
  64 MODULE_FIRMWARE("b43legacy/ucode4.fw");
  65
  66 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
  67 static int modparam_pio;
  68 module_param_named(pio, modparam_pio, int, 0444);
  69 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  70 #elif defined(CONFIG_B43LEGACY_DMA)
  71 # define modparam_pio   0
  72 #elif defined(CONFIG_B43LEGACY_PIO)
  73 # define modparam_pio   1
  74 #endif
  75
  76 static int modparam_bad_frames_preempt;
  77 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  78 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
  79                  " Preemption");
  80
  81 static char modparam_fwpostfix[16];
  82 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  83 MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
  84
  85 /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
  86 static const struct ssb_device_id b43legacy_ssb_tbl[] = {
  87         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
  88         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
  89         SSB_DEVTABLE_END
  90 };
  91 MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
  92
  93
  94 /* Channel and ratetables are shared for all devices.
  95  * They can't be const, because ieee80211 puts some precalculated
  96  * data in there. This data is the same for all devices, so we don't
  97  * get concurrency issues */
  98 #define RATETAB_ENT(_rateid, _flags) \
  99         {                                                               \
 100                 .bitrate        = B43legacy_RATE_TO_100KBPS(_rateid),   \
 101                 .hw_value       = (_rateid),                            \
 102                 .flags          = (_flags),                             \
 103         }
 104 /*
 105  * NOTE: When changing this, sync with xmit.c's
 106  *       b43legacy_plcp_get_bitrate_idx_* functions!
 107  */
 108 static struct ieee80211_rate __b43legacy_ratetable[] = {
 109         RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
 110         RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
 111         RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
 112         RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
 113         RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
 114         RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
 115         RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
 116         RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
 117         RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
 118         RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
 119         RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
 120         RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
 121 };
 122 #define b43legacy_b_ratetable           (__b43legacy_ratetable + 0)
 123 #define b43legacy_b_ratetable_size      4
 124 #define b43legacy_g_ratetable           (__b43legacy_ratetable + 0)
 125 #define b43legacy_g_ratetable_size      12
 126
 127 #define CHANTAB_ENT(_chanid, _freq) \
 128         {                                                       \
 129                 .center_freq    = (_freq),                      \
 130                 .hw_value       = (_chanid),                    \
 131         }
 132 static struct ieee80211_channel b43legacy_bg_chantable[] = {
 133         CHANTAB_ENT(1, 2412),
 134         CHANTAB_ENT(2, 2417),
 135         CHANTAB_ENT(3, 2422),
 136         CHANTAB_ENT(4, 2427),
 137         CHANTAB_ENT(5, 2432),
 138         CHANTAB_ENT(6, 2437),
 139         CHANTAB_ENT(7, 2442),
 140         CHANTAB_ENT(8, 2447),
 141         CHANTAB_ENT(9, 2452),
 142         CHANTAB_ENT(10, 2457),
 143         CHANTAB_ENT(11, 2462),
 144         CHANTAB_ENT(12, 2467),
 145         CHANTAB_ENT(13, 2472),
 146         CHANTAB_ENT(14, 2484),
 147 };
 148
 149 static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
 150         .channels = b43legacy_bg_chantable,
 151         .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
 152         .bitrates = b43legacy_b_ratetable,
 153         .n_bitrates = b43legacy_b_ratetable_size,
 154 };
 155
 156 static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
 157         .channels = b43legacy_bg_chantable,
 158         .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
 159         .bitrates = b43legacy_g_ratetable,
 160         .n_bitrates = b43legacy_g_ratetable_size,
 161 };
 162
 163 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
 164 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
 165 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
 166 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
 167
 168
 169 static int b43legacy_ratelimit(struct b43legacy_wl *wl)
 170 {
 171         if (!wl || !wl->current_dev)
 172                 return 1;
 173         if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
 174                 return 1;
 175         /* We are up and running.
 176          * Ratelimit the messages to avoid DoS over the net. */
 177         return net_ratelimit();
 178 }
 179
 180 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
 181 {
 182         struct va_format vaf;
 183         va_list args;
 184
 185         if (!b43legacy_ratelimit(wl))
 186                 return;
 187
 188         va_start(args, fmt);
 189
 190         vaf.fmt = fmt;
 191         vaf.va = &args;
 192
 193         printk(KERN_INFO "b43legacy-%s: %pV",
 194                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 195
 196         va_end(args);
 197 }
 198
 199 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
 200 {
 201         struct va_format vaf;
 202         va_list args;
 203
 204         if (!b43legacy_ratelimit(wl))
 205                 return;
 206
 207         va_start(args, fmt);
 208
 209         vaf.fmt = fmt;
 210         vaf.va = &args;
 211
 212         printk(KERN_ERR "b43legacy-%s ERROR: %pV",
 213                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 214
 215         va_end(args);
 216 }
 217
 218 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
 219 {
 220         struct va_format vaf;
 221         va_list args;
 222
 223         if (!b43legacy_ratelimit(wl))
 224                 return;
 225
 226         va_start(args, fmt);
 227
 228         vaf.fmt = fmt;
 229         vaf.va = &args;
 230
 231         printk(KERN_WARNING "b43legacy-%s warning: %pV",
 232                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 233
 234         va_end(args);
 235 }
 236
 237 #if B43legacy_DEBUG
 238 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
 239 {
 240         struct va_format vaf;
 241         va_list args;
 242
 243         va_start(args, fmt);
 244
 245         vaf.fmt = fmt;
 246         vaf.va = &args;
 247
 248         printk(KERN_DEBUG "b43legacy-%s debug: %pV",
 249                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 250
 251         va_end(args);
 252 }
 253 #endif /* DEBUG */
 254
 255 static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
 256                                 u32 val)
 257 {
 258         u32 status;
 259
 260         B43legacy_WARN_ON(offset % 4 != 0);
 261
 262         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 263         if (status & B43legacy_MACCTL_BE)
 264                 val = swab32(val);
 265
 266         b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
 267         mmiowb();
 268         b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
 269 }
 270
 271 static inline
 272 void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
 273                                 u16 routing, u16 offset)
 274 {
 275         u32 control;
 276
 277         /* "offset" is the WORD offset. */
 278
 279         control = routing;
 280         control <<= 16;
 281         control |= offset;
 282         b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
 283 }
 284
 285 u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
 286                        u16 routing, u16 offset)
 287 {
 288         u32 ret;
 289
 290         if (routing == B43legacy_SHM_SHARED) {
 291                 B43legacy_WARN_ON((offset & 0x0001) != 0);
 292                 if (offset & 0x0003) {
 293                         /* Unaligned access */
 294                         b43legacy_shm_control_word(dev, routing, offset >> 2);
 295                         ret = b43legacy_read16(dev,
 296                                 B43legacy_MMIO_SHM_DATA_UNALIGNED);
 297                         ret <<= 16;
 298                         b43legacy_shm_control_word(dev, routing,
 299                                                      (offset >> 2) + 1);
 300                         ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
 301
 302                         return ret;
 303                 }
 304                 offset >>= 2;
 305         }
 306         b43legacy_shm_control_word(dev, routing, offset);
 307         ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
 308
 309         return ret;
 310 }
 311
 312 u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
 313                            u16 routing, u16 offset)
 314 {
 315         u16 ret;
 316
 317         if (routing == B43legacy_SHM_SHARED) {
 318                 B43legacy_WARN_ON((offset & 0x0001) != 0);
 319                 if (offset & 0x0003) {
 320                         /* Unaligned access */
 321                         b43legacy_shm_control_word(dev, routing, offset >> 2);
 322                         ret = b43legacy_read16(dev,
 323                                              B43legacy_MMIO_SHM_DATA_UNALIGNED);
 324
 325                         return ret;
 326                 }
 327                 offset >>= 2;
 328         }
 329         b43legacy_shm_control_word(dev, routing, offset);
 330         ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
 331
 332         return ret;
 333 }
 334
 335 void b43legacy_shm_write32(struct b43legacy_wldev *dev,
 336                            u16 routing, u16 offset,
 337                            u32 value)
 338 {
 339         if (routing == B43legacy_SHM_SHARED) {
 340                 B43legacy_WARN_ON((offset & 0x0001) != 0);
 341                 if (offset & 0x0003) {
 342                         /* Unaligned access */
 343                         b43legacy_shm_control_word(dev, routing, offset >> 2);
 344                         mmiowb();
 345                         b43legacy_write16(dev,
 346                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
 347                                           (value >> 16) & 0xffff);
 348                         mmiowb();
 349                         b43legacy_shm_control_word(dev, routing,
 350                                                    (offset >> 2) + 1);
 351                         mmiowb();
 352                         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
 353                                           value & 0xffff);
 354                         return;
 355                 }
 356                 offset >>= 2;
 357         }
 358         b43legacy_shm_control_word(dev, routing, offset);
 359         mmiowb();
 360         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
 361 }
 362
 363 void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
 364                            u16 value)
 365 {
 366         if (routing == B43legacy_SHM_SHARED) {
 367                 B43legacy_WARN_ON((offset & 0x0001) != 0);
 368                 if (offset & 0x0003) {
 369                         /* Unaligned access */
 370                         b43legacy_shm_control_word(dev, routing, offset >> 2);
 371                         mmiowb();
 372                         b43legacy_write16(dev,
 373                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
 374                                           value);
 375                         return;
 376                 }
 377                 offset >>= 2;
 378         }
 379         b43legacy_shm_control_word(dev, routing, offset);
 380         mmiowb();
 381         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
 382 }
 383
 384 /* Read HostFlags */
 385 u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
 386 {
 387         u32 ret;
 388
 389         ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
 390                                    B43legacy_SHM_SH_HOSTFHI);
 391         ret <<= 16;
 392         ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
 393                                     B43legacy_SHM_SH_HOSTFLO);
 394
 395         return ret;
 396 }
 397
 398 /* Write HostFlags */
 399 void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
 400 {
 401         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
 402                               B43legacy_SHM_SH_HOSTFLO,
 403                               (value & 0x0000FFFF));
 404         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
 405                               B43legacy_SHM_SH_HOSTFHI,
 406                               ((value & 0xFFFF0000) >> 16));
 407 }
 408
 409 void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
 410 {
 411         /* We need to be careful. As we read the TSF from multiple
 412          * registers, we should take care of register overflows.
 413          * In theory, the whole tsf read process should be atomic.
 414          * We try to be atomic here, by restaring the read process,
 415          * if any of the high registers changed (overflew).
 416          */
 417         if (dev->dev->id.revision >= 3) {
 418                 u32 low;
 419                 u32 high;
 420                 u32 high2;
 421
 422                 do {
 423                         high = b43legacy_read32(dev,
 424                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
 425                         low = b43legacy_read32(dev,
 426                                         B43legacy_MMIO_REV3PLUS_TSF_LOW);
 427                         high2 = b43legacy_read32(dev,
 428                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
 429                 } while (unlikely(high != high2));
 430
 431                 *tsf = high;
 432                 *tsf <<= 32;
 433                 *tsf |= low;
 434         } else {
 435                 u64 tmp;
 436                 u16 v0;
 437                 u16 v1;
 438                 u16 v2;
 439                 u16 v3;
 440                 u16 test1;
 441                 u16 test2;
 442                 u16 test3;
 443
 444                 do {
 445                         v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
 446                         v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
 447                         v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
 448                         v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
 449
 450                         test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
 451                         test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
 452                         test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
 453                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 454
 455                 *tsf = v3;
 456                 *tsf <<= 48;
 457                 tmp = v2;
 458                 tmp <<= 32;
 459                 *tsf |= tmp;
 460                 tmp = v1;
 461                 tmp <<= 16;
 462                 *tsf |= tmp;
 463                 *tsf |= v0;
 464         }
 465 }
 466
 467 static void b43legacy_time_lock(struct b43legacy_wldev *dev)
 468 {
 469         u32 status;
 470
 471         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 472         status |= B43legacy_MACCTL_TBTTHOLD;
 473         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
 474         mmiowb();
 475 }
 476
 477 static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
 478 {
 479         u32 status;
 480
 481         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 482         status &= ~B43legacy_MACCTL_TBTTHOLD;
 483         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
 484 }
 485
 486 static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
 487 {
 488         /* Be careful with the in-progress timer.
 489          * First zero out the low register, so we have a full
 490          * register-overflow duration to complete the operation.
 491          */
 492         if (dev->dev->id.revision >= 3) {
 493                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 494                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 495
 496                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
 497                 mmiowb();
 498                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
 499                                     hi);
 500                 mmiowb();
 501                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
 502                                     lo);
 503         } else {
 504                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 505                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 506                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 507                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 508
 509                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
 510                 mmiowb();
 511                 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
 512                 mmiowb();
 513                 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
 514                 mmiowb();
 515                 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
 516                 mmiowb();
 517                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
 518         }
 519 }
 520
 521 void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
 522 {
 523         b43legacy_time_lock(dev);
 524         b43legacy_tsf_write_locked(dev, tsf);
 525         b43legacy_time_unlock(dev);
 526 }
 527
 528 static
 529 void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
 530                              u16 offset, const u8 *mac)
 531 {
 532         static const u8 zero_addr[ETH_ALEN] = { 0 };
 533         u16 data;
 534
 535         if (!mac)
 536                 mac = zero_addr;
 537
 538         offset |= 0x0020;
 539         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
 540
 541         data = mac[0];
 542         data |= mac[1] << 8;
 543         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
 544         data = mac[2];
 545         data |= mac[3] << 8;
 546         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
 547         data = mac[4];
 548         data |= mac[5] << 8;
 549         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
 550 }
 551
 552 static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
 553 {
 554         static const u8 zero_addr[ETH_ALEN] = { 0 };
 555         const u8 *mac = dev->wl->mac_addr;
 556         const u8 *bssid = dev->wl->bssid;
 557         u8 mac_bssid[ETH_ALEN * 2];
 558         int i;
 559         u32 tmp;
 560
 561         if (!bssid)
 562                 bssid = zero_addr;
 563         if (!mac)
 564                 mac = zero_addr;
 565
 566         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
 567
 568         memcpy(mac_bssid, mac, ETH_ALEN);
 569         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 570
 571         /* Write our MAC address and BSSID to template ram */
 572         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 573                 tmp =  (u32)(mac_bssid[i + 0]);
 574                 tmp |= (u32)(mac_bssid[i + 1]) << 8;
 575                 tmp |= (u32)(mac_bssid[i + 2]) << 16;
 576                 tmp |= (u32)(mac_bssid[i + 3]) << 24;
 577                 b43legacy_ram_write(dev, 0x20 + i, tmp);
 578                 b43legacy_ram_write(dev, 0x78 + i, tmp);
 579                 b43legacy_ram_write(dev, 0x478 + i, tmp);
 580         }
 581 }
 582
 583 static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
 584 {
 585         b43legacy_write_mac_bssid_templates(dev);
 586         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
 587                                 dev->wl->mac_addr);
 588 }
 589
 590 static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
 591                                     u16 slot_time)
 592 {
 593         /* slot_time is in usec. */
 594         if (dev->phy.type != B43legacy_PHYTYPE_G)
 595                 return;
 596         b43legacy_write16(dev, 0x684, 510 + slot_time);
 597         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
 598                               slot_time);
 599 }
 600
 601 static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
 602 {
 603         b43legacy_set_slot_time(dev, 9);
 604 }
 605
 606 static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
 607 {
 608         b43legacy_set_slot_time(dev, 20);
 609 }
 610
 611 /* Synchronize IRQ top- and bottom-half.
 612  * IRQs must be masked before calling this.
 613  * This must not be called with the irq_lock held.
 614  */
 615 static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
 616 {
 617         synchronize_irq(dev->dev->irq);
 618         tasklet_kill(&dev->isr_tasklet);
 619 }
 620
 621 /* DummyTransmission function, as documented on
 622  * http://bcm-specs.sipsolutions.net/DummyTransmission
 623  */
 624 void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
 625 {
 626         struct b43legacy_phy *phy = &dev->phy;
 627         unsigned int i;
 628         unsigned int max_loop;
 629         u16 value;
 630         u32 buffer[5] = {
 631                 0x00000000,
 632                 0x00D40000,
 633                 0x00000000,
 634                 0x01000000,
 635                 0x00000000,
 636         };
 637
 638         switch (phy->type) {
 639         case B43legacy_PHYTYPE_B:
 640         case B43legacy_PHYTYPE_G:
 641                 max_loop = 0xFA;
 642                 buffer[0] = 0x000B846E;
 643                 break;
 644         default:
 645                 B43legacy_BUG_ON(1);
 646                 return;
 647         }
 648
 649         for (i = 0; i < 5; i++)
 650                 b43legacy_ram_write(dev, i * 4, buffer[i]);
 651
 652         /* dummy read follows */
 653         b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 654
 655         b43legacy_write16(dev, 0x0568, 0x0000);
 656         b43legacy_write16(dev, 0x07C0, 0x0000);
 657         b43legacy_write16(dev, 0x050C, 0x0000);
 658         b43legacy_write16(dev, 0x0508, 0x0000);
 659         b43legacy_write16(dev, 0x050A, 0x0000);
 660         b43legacy_write16(dev, 0x054C, 0x0000);
 661         b43legacy_write16(dev, 0x056A, 0x0014);
 662         b43legacy_write16(dev, 0x0568, 0x0826);
 663         b43legacy_write16(dev, 0x0500, 0x0000);
 664         b43legacy_write16(dev, 0x0502, 0x0030);
 665
 666         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 667                 b43legacy_radio_write16(dev, 0x0051, 0x0017);
 668         for (i = 0x00; i < max_loop; i++) {
 669                 value = b43legacy_read16(dev, 0x050E);
 670                 if (value & 0x0080)
 671                         break;
 672                 udelay(10);
 673         }
 674         for (i = 0x00; i < 0x0A; i++) {
 675                 value = b43legacy_read16(dev, 0x050E);
 676                 if (value & 0x0400)
 677                         break;
 678                 udelay(10);
 679         }
 680         for (i = 0x00; i < 0x0A; i++) {
 681                 value = b43legacy_read16(dev, 0x0690);
 682                 if (!(value & 0x0100))
 683                         break;
 684                 udelay(10);
 685         }
 686         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 687                 b43legacy_radio_write16(dev, 0x0051, 0x0037);
 688 }
 689
 690 /* Turn the Analog ON/OFF */
 691 static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
 692 {
 693         b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
 694 }
 695
 696 void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
 697 {
 698         u32 tmslow;
 699         u32 macctl;
 700
 701         flags |= B43legacy_TMSLOW_PHYCLKEN;
 702         flags |= B43legacy_TMSLOW_PHYRESET;
 703         ssb_device_enable(dev->dev, flags);
 704         msleep(2); /* Wait for the PLL to turn on. */
 705
 706         /* Now take the PHY out of Reset again */
 707         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 708         tmslow |= SSB_TMSLOW_FGC;
 709         tmslow &= ~B43legacy_TMSLOW_PHYRESET;
 710         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 711         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
 712         msleep(1);
 713         tmslow &= ~SSB_TMSLOW_FGC;
 714         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 715         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
 716         msleep(1);
 717
 718         /* Turn Analog ON */
 719         b43legacy_switch_analog(dev, 1);
 720
 721         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 722         macctl &= ~B43legacy_MACCTL_GMODE;
 723         if (flags & B43legacy_TMSLOW_GMODE) {
 724                 macctl |= B43legacy_MACCTL_GMODE;
 725                 dev->phy.gmode = 1;
 726         } else
 727                 dev->phy.gmode = 0;
 728         macctl |= B43legacy_MACCTL_IHR_ENABLED;
 729         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
 730 }
 731
 732 static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
 733 {
 734         u32 v0;
 735         u32 v1;
 736         u16 tmp;
 737         struct b43legacy_txstatus stat;
 738
 739         while (1) {
 740                 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
 741                 if (!(v0 & 0x00000001))
 742                         break;
 743                 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
 744
 745                 stat.cookie = (v0 >> 16);
 746                 stat.seq = (v1 & 0x0000FFFF);
 747                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
 748                 tmp = (v0 & 0x0000FFFF);
 749                 stat.frame_count = ((tmp & 0xF000) >> 12);
 750                 stat.rts_count = ((tmp & 0x0F00) >> 8);
 751                 stat.supp_reason = ((tmp & 0x001C) >> 2);
 752                 stat.pm_indicated = !!(tmp & 0x0080);
 753                 stat.intermediate = !!(tmp & 0x0040);
 754                 stat.for_ampdu = !!(tmp & 0x0020);
 755                 stat.acked = !!(tmp & 0x0002);
 756
 757                 b43legacy_handle_txstatus(dev, &stat);
 758         }
 759 }
 760
 761 static void drain_txstatus_queue(struct b43legacy_wldev *dev)
 762 {
 763         u32 dummy;
 764
 765         if (dev->dev->id.revision < 5)
 766                 return;
 767         /* Read all entries from the microcode TXstatus FIFO
 768          * and throw them away.
 769          */
 770         while (1) {
 771                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
 772                 if (!(dummy & 0x00000001))
 773                         break;
 774                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
 775         }
 776 }
 777
 778 static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
 779 {
 780         u32 val = 0;
 781
 782         val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
 783         val <<= 16;
 784         val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
 785
 786         return val;
 787 }
 788
 789 static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
 790 {
 791         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
 792                               (jssi & 0x0000FFFF));
 793         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
 794                               (jssi & 0xFFFF0000) >> 16);
 795 }
 796
 797 static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
 798 {
 799         b43legacy_jssi_write(dev, 0x7F7F7F7F);
 800         b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
 801                           b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
 802                           | B43legacy_MACCMD_BGNOISE);
 803         B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
 804                             dev->phy.channel);
 805 }
 806
 807 static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
 808 {
 809         /* Top half of Link Quality calculation. */
 810
 811         if (dev->noisecalc.calculation_running)
 812                 return;
 813         dev->noisecalc.channel_at_start = dev->phy.channel;
 814         dev->noisecalc.calculation_running = 1;
 815         dev->noisecalc.nr_samples = 0;
 816
 817         b43legacy_generate_noise_sample(dev);
 818 }
 819
 820 static void handle_irq_noise(struct b43legacy_wldev *dev)
 821 {
 822         struct b43legacy_phy *phy = &dev->phy;
 823         u16 tmp;
 824         u8 noise[4];
 825         u8 i;
 826         u8 j;
 827         s32 average;
 828
 829         /* Bottom half of Link Quality calculation. */
 830
 831         B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
 832         if (dev->noisecalc.channel_at_start != phy->channel)
 833                 goto drop_calculation;
 834         *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
 835         if (noise[0] == 0x7F || noise[1] == 0x7F ||
 836             noise[2] == 0x7F || noise[3] == 0x7F)
 837                 goto generate_new;
 838
 839         /* Get the noise samples. */
 840         B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
 841         i = dev->noisecalc.nr_samples;
 842         noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
 843         noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
 844         noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
 845         noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
 846         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
 847         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
 848         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
 849         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
 850         dev->noisecalc.nr_samples++;
 851         if (dev->noisecalc.nr_samples == 8) {
 852                 /* Calculate the Link Quality by the noise samples. */
 853                 average = 0;
 854                 for (i = 0; i < 8; i++) {
 855                         for (j = 0; j < 4; j++)
 856                                 average += dev->noisecalc.samples[i][j];
 857                 }
 858                 average /= (8 * 4);
 859                 average *= 125;
 860                 average += 64;
 861                 average /= 128;
 862                 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
 863                                              0x40C);
 864                 tmp = (tmp / 128) & 0x1F;
 865                 if (tmp >= 8)
 866                         average += 2;
 867                 else
 868                         average -= 25;
 869                 if (tmp == 8)
 870                         average -= 72;
 871                 else
 872                         average -= 48;
 873
 874                 dev->stats.link_noise = average;
 875 drop_calculation:
 876                 dev->noisecalc.calculation_running = 0;
 877                 return;
 878         }
 879 generate_new:
 880         b43legacy_generate_noise_sample(dev);
 881 }
 882
 883 static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
 884 {
 885         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
 886                 /* TODO: PS TBTT */
 887         } else {
 888                 if (1/*FIXME: the last PSpoll frame was sent successfully */)
 889                         b43legacy_power_saving_ctl_bits(dev, -1, -1);
 890         }
 891         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
 892                 dev->dfq_valid = 1;
 893 }
 894
 895 static void handle_irq_atim_end(struct b43legacy_wldev *dev)
 896 {
 897         if (dev->dfq_valid) {
 898                 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
 899                                   b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
 900                                   | B43legacy_MACCMD_DFQ_VALID);
 901                 dev->dfq_valid = 0;
 902         }
 903 }
 904
 905 static void handle_irq_pmq(struct b43legacy_wldev *dev)
 906 {
 907         u32 tmp;
 908
 909         /* TODO: AP mode. */
 910
 911         while (1) {
 912                 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
 913                 if (!(tmp & 0x00000008))
 914                         break;
 915         }
 916         /* 16bit write is odd, but correct. */
 917         b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
 918 }
 919
 920 static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
 921                                             const u8 *data, u16 size,
 922                                             u16 ram_offset,
 923                                             u16 shm_size_offset, u8 rate)
 924 {
 925         u32 i;
 926         u32 tmp;
 927         struct b43legacy_plcp_hdr4 plcp;
 928
 929         plcp.data = 0;
 930         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
 931         b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
 932         ram_offset += sizeof(u32);
 933         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
 934          * So leave the first two bytes of the next write blank.
 935          */
 936         tmp = (u32)(data[0]) << 16;
 937         tmp |= (u32)(data[1]) << 24;
 938         b43legacy_ram_write(dev, ram_offset, tmp);
 939         ram_offset += sizeof(u32);
 940         for (i = 2; i < size; i += sizeof(u32)) {
 941                 tmp = (u32)(data[i + 0]);
 942                 if (i + 1 < size)
 943                         tmp |= (u32)(data[i + 1]) << 8;
 944                 if (i + 2 < size)
 945                         tmp |= (u32)(data[i + 2]) << 16;
 946                 if (i + 3 < size)
 947                         tmp |= (u32)(data[i + 3]) << 24;
 948                 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
 949         }
 950         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
 951                               size + sizeof(struct b43legacy_plcp_hdr6));
 952 }
 953
 954 /* Convert a b43legacy antenna number value to the PHY TX control value. */
 955 static u16 b43legacy_antenna_to_phyctl(int antenna)
 956 {
 957         switch (antenna) {
 958         case B43legacy_ANTENNA0:
 959                 return B43legacy_TX4_PHY_ANT0;
 960         case B43legacy_ANTENNA1:
 961                 return B43legacy_TX4_PHY_ANT1;
 962         }
 963         return B43legacy_TX4_PHY_ANTLAST;
 964 }
 965
 966 static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
 967                                             u16 ram_offset,
 968                                             u16 shm_size_offset)
 969 {
 970
 971         unsigned int i, len, variable_len;
 972         const struct ieee80211_mgmt *bcn;
 973         const u8 *ie;
 974         bool tim_found = 0;
 975         unsigned int rate;
 976         u16 ctl;
 977         int antenna;
 978         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
 979
 980         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
 981         len = min((size_t)dev->wl->current_beacon->len,
 982                   0x200 - sizeof(struct b43legacy_plcp_hdr6));
 983         rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
 984
 985         b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
 986                                         shm_size_offset, rate);
 987
 988         /* Write the PHY TX control parameters. */
 989         antenna = B43legacy_ANTENNA_DEFAULT;
 990         antenna = b43legacy_antenna_to_phyctl(antenna);
 991         ctl = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
 992                                    B43legacy_SHM_SH_BEACPHYCTL);
 993         /* We can't send beacons with short preamble. Would get PHY errors. */
 994         ctl &= ~B43legacy_TX4_PHY_SHORTPRMBL;
 995         ctl &= ~B43legacy_TX4_PHY_ANT;
 996         ctl &= ~B43legacy_TX4_PHY_ENC;
 997         ctl |= antenna;
 998         ctl |= B43legacy_TX4_PHY_ENC_CCK;
 999         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1000                               B43legacy_SHM_SH_BEACPHYCTL, ctl);
1001
1002         /* Find the position of the TIM and the DTIM_period value
1003          * and write them to SHM. */
1004         ie = bcn->u.beacon.variable;
1005         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1006         for (i = 0; i < variable_len - 2; ) {
1007                 uint8_t ie_id, ie_len;
1008
1009                 ie_id = ie[i];
1010                 ie_len = ie[i + 1];
1011                 if (ie_id == 5) {
1012                         u16 tim_position;
1013                         u16 dtim_period;
1014                         /* This is the TIM Information Element */
1015
1016                         /* Check whether the ie_len is in the beacon data range. */
1017                         if (variable_len < ie_len + 2 + i)
1018                                 break;
1019                         /* A valid TIM is at least 4 bytes long. */
1020                         if (ie_len < 4)
1021                                 break;
1022                         tim_found = 1;
1023
1024                         tim_position = sizeof(struct b43legacy_plcp_hdr6);
1025                         tim_position += offsetof(struct ieee80211_mgmt,
1026                                                  u.beacon.variable);
1027                         tim_position += i;
1028
1029                         dtim_period = ie[i + 3];
1030
1031                         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1032                                         B43legacy_SHM_SH_TIMPOS, tim_position);
1033                         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1034                                         B43legacy_SHM_SH_DTIMP, dtim_period);
1035                         break;
1036                 }
1037                 i += ie_len + 2;
1038         }
1039         if (!tim_found) {
1040                 b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
1041                               "beacon template packet. AP or IBSS operation "
1042                               "may be broken.\n");
1043         } else
1044                 b43legacydbg(dev->wl, "Updated beacon template\n");
1045 }
1046
1047 static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
1048                                             u16 shm_offset, u16 size,
1049                                             struct ieee80211_rate *rate)
1050 {
1051         struct b43legacy_plcp_hdr4 plcp;
1052         u32 tmp;
1053         __le16 dur;
1054
1055         plcp.data = 0;
1056         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1057         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1058                                                dev->wl->vif,
1059                                                size,
1060                                                rate);
1061         /* Write PLCP in two parts and timing for packet transfer */
1062         tmp = le32_to_cpu(plcp.data);
1063         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
1064                               tmp & 0xFFFF);
1065         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
1066                               tmp >> 16);
1067         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
1068                               le16_to_cpu(dur));
1069 }
1070
1071 /* Instead of using custom probe response template, this function
1072  * just patches custom beacon template by:
1073  * 1) Changing packet type
1074  * 2) Patching duration field
1075  * 3) Stripping TIM
1076  */
1077 static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
1078                                                u16 *dest_size,
1079                                                struct ieee80211_rate *rate)
1080 {
1081         const u8 *src_data;
1082         u8 *dest_data;
1083         u16 src_size, elem_size, src_pos, dest_pos;
1084         __le16 dur;
1085         struct ieee80211_hdr *hdr;
1086         size_t ie_start;
1087
1088         src_size = dev->wl->current_beacon->len;
1089         src_data = (const u8 *)dev->wl->current_beacon->data;
1090
1091         /* Get the start offset of the variable IEs in the packet. */
1092         ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1093         B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
1094                                                u.beacon.variable));
1095
1096         if (B43legacy_WARN_ON(src_size < ie_start))
1097                 return NULL;
1098
1099         dest_data = kmalloc(src_size, GFP_ATOMIC);
1100         if (unlikely(!dest_data))
1101                 return NULL;
1102
1103         /* Copy the static data and all Information Elements, except the TIM. */
1104         memcpy(dest_data, src_data, ie_start);
1105         src_pos = ie_start;
1106         dest_pos = ie_start;
1107         for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1108                 elem_size = src_data[src_pos + 1] + 2;
1109                 if (src_data[src_pos] == 5) {
1110                         /* This is the TIM. */
1111                         continue;
1112                 }
1113                 memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
1114                 dest_pos += elem_size;
1115         }
1116         *dest_size = dest_pos;
1117         hdr = (struct ieee80211_hdr *)dest_data;
1118
1119         /* Set the frame control. */
1120         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1121                                          IEEE80211_STYPE_PROBE_RESP);
1122         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1123                                                dev->wl->vif,
1124                                                *dest_size,
1125                                                rate);
1126         hdr->duration_id = dur;
1127
1128         return dest_data;
1129 }
1130
1131 static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1132                                                 u16 ram_offset,
1133                                                 u16 shm_size_offset,
1134                                                 struct ieee80211_rate *rate)
1135 {
1136         const u8 *probe_resp_data;
1137         u16 size;
1138
1139         size = dev->wl->current_beacon->len;
1140         probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1141         if (unlikely(!probe_resp_data))
1142                 return;
1143
1144         /* Looks like PLCP headers plus packet timings are stored for
1145          * all possible basic rates
1146          */
1147         b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
1148                                         &b43legacy_b_ratetable[0]);
1149         b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
1150                                         &b43legacy_b_ratetable[1]);
1151         b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
1152                                         &b43legacy_b_ratetable[2]);
1153         b43legacy_write_probe_resp_plcp(dev, 0x350, size,
1154                                         &b43legacy_b_ratetable[3]);
1155
1156         size = min((size_t)size,
1157                    0x200 - sizeof(struct b43legacy_plcp_hdr6));
1158         b43legacy_write_template_common(dev, probe_resp_data,
1159                                         size, ram_offset,
1160                                         shm_size_offset, rate->hw_value);
1161         kfree(probe_resp_data);
1162 }
1163
1164 static void b43legacy_upload_beacon0(struct b43legacy_wldev *dev)
1165 {
1166         struct b43legacy_wl *wl = dev->wl;
1167
1168         if (wl->beacon0_uploaded)
1169                 return;
1170         b43legacy_write_beacon_template(dev, 0x68, 0x18);
1171         /* FIXME: Probe resp upload doesn't really belong here,
1172          *        but we don't use that feature anyway. */
1173         b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
1174                                       &__b43legacy_ratetable[3]);
1175         wl->beacon0_uploaded = 1;
1176 }
1177
1178 static void b43legacy_upload_beacon1(struct b43legacy_wldev *dev)
1179 {
1180         struct b43legacy_wl *wl = dev->wl;
1181
1182         if (wl->beacon1_uploaded)
1183                 return;
1184         b43legacy_write_beacon_template(dev, 0x468, 0x1A);
1185         wl->beacon1_uploaded = 1;
1186 }
1187
1188 static void handle_irq_beacon(struct b43legacy_wldev *dev)
1189 {
1190         struct b43legacy_wl *wl = dev->wl;
1191         u32 cmd, beacon0_valid, beacon1_valid;
1192
1193         if (!b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1194                 return;
1195
1196         /* This is the bottom half of the asynchronous beacon update. */
1197
1198         /* Ignore interrupt in the future. */
1199         dev->irq_mask &= ~B43legacy_IRQ_BEACON;
1200
1201         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1202         beacon0_valid = (cmd & B43legacy_MACCMD_BEACON0_VALID);
1203         beacon1_valid = (cmd & B43legacy_MACCMD_BEACON1_VALID);
1204
1205         /* Schedule interrupt manually, if busy. */
1206         if (beacon0_valid && beacon1_valid) {
1207                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, B43legacy_IRQ_BEACON);
1208                 dev->irq_mask |= B43legacy_IRQ_BEACON;
1209                 return;
1210         }
1211
1212         if (unlikely(wl->beacon_templates_virgin)) {
1213                 /* We never uploaded a beacon before.
1214                  * Upload both templates now, but only mark one valid. */
1215                 wl->beacon_templates_virgin = 0;
1216                 b43legacy_upload_beacon0(dev);
1217                 b43legacy_upload_beacon1(dev);
1218                 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1219                 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1220                 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1221         } else {
1222                 if (!beacon0_valid) {
1223                         b43legacy_upload_beacon0(dev);
1224                         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1225                         cmd |= B43legacy_MACCMD_BEACON0_VALID;
1226                         b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1227                 } else if (!beacon1_valid) {
1228                         b43legacy_upload_beacon1(dev);
1229                         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1230                         cmd |= B43legacy_MACCMD_BEACON1_VALID;
1231                         b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1232                 }
1233         }
1234 }
1235
1236 static void b43legacy_beacon_update_trigger_work(struct work_struct *work)
1237 {
1238         struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
1239                                          beacon_update_trigger);
1240         struct b43legacy_wldev *dev;
1241
1242         mutex_lock(&wl->mutex);
1243         dev = wl->current_dev;
1244         if (likely(dev && (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED))) {
1245                 spin_lock_irq(&wl->irq_lock);
1246                 /* Update beacon right away or defer to IRQ. */
1247                 handle_irq_beacon(dev);
1248                 /* The handler might have updated the IRQ mask. */
1249                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1250                                   dev->irq_mask);
1251                 mmiowb();
1252                 spin_unlock_irq(&wl->irq_lock);
1253         }
1254         mutex_unlock(&wl->mutex);
1255 }
1256
1257 /* Asynchronously update the packet templates in template RAM.
1258  * Locking: Requires wl->irq_lock to be locked. */
1259 static void b43legacy_update_templates(struct b43legacy_wl *wl)
1260 {
1261         struct sk_buff *beacon;
1262         /* This is the top half of the ansynchronous beacon update. The bottom
1263          * half is the beacon IRQ. Beacon update must be asynchronous to avoid
1264          * sending an invalid beacon. This can happen for example, if the
1265          * firmware transmits a beacon while we are updating it. */
1266
1267         /* We could modify the existing beacon and set the aid bit in the TIM
1268          * field, but that would probably require resizing and moving of data
1269          * within the beacon template. Simply request a new beacon and let
1270          * mac80211 do the hard work. */
1271         beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1272         if (unlikely(!beacon))
1273                 return;
1274
1275         if (wl->current_beacon)
1276                 dev_kfree_skb_any(wl->current_beacon);
1277         wl->current_beacon = beacon;
1278         wl->beacon0_uploaded = 0;
1279         wl->beacon1_uploaded = 0;
1280         ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1281 }
1282
1283 static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1284                                      u16 beacon_int)
1285 {
1286         b43legacy_time_lock(dev);
1287         if (dev->dev->id.revision >= 3) {
1288                 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_REP,
1289                                  (beacon_int << 16));
1290                 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_START,
1291                                  (beacon_int << 10));
1292         } else {
1293                 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1294                 b43legacy_write16(dev, 0x610, beacon_int);
1295         }
1296         b43legacy_time_unlock(dev);
1297         b43legacydbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1298 }
1299
1300 static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1301 {
1302 }
1303
1304 /* Interrupt handler bottom-half */
1305 static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1306 {
1307         u32 reason;
1308         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1309         u32 merged_dma_reason = 0;
1310         int i;
1311         unsigned long flags;
1312
1313         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1314
1315         B43legacy_WARN_ON(b43legacy_status(dev) <
1316                           B43legacy_STAT_INITIALIZED);
1317
1318         reason = dev->irq_reason;
1319         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1320                 dma_reason[i] = dev->dma_reason[i];
1321                 merged_dma_reason |= dma_reason[i];
1322         }
1323
1324         if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1325                 b43legacyerr(dev->wl, "MAC transmission error\n");
1326
1327         if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
1328                 b43legacyerr(dev->wl, "PHY transmission error\n");
1329                 rmb();
1330                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1331                         b43legacyerr(dev->wl, "Too many PHY TX errors, "
1332                                               "restarting the controller\n");
1333                         b43legacy_controller_restart(dev, "PHY TX errors");
1334                 }
1335         }
1336
1337         if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1338                                           B43legacy_DMAIRQ_NONFATALMASK))) {
1339                 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1340                         b43legacyerr(dev->wl, "Fatal DMA error: "
1341                                "0x%08X, 0x%08X, 0x%08X, "
1342                                "0x%08X, 0x%08X, 0x%08X\n",
1343                                dma_reason[0], dma_reason[1],
1344                                dma_reason[2], dma_reason[3],
1345                                dma_reason[4], dma_reason[5]);
1346                         b43legacy_controller_restart(dev, "DMA error");
1347                         mmiowb();
1348                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1349                         return;
1350                 }
1351                 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1352                         b43legacyerr(dev->wl, "DMA error: "
1353                                "0x%08X, 0x%08X, 0x%08X, "
1354                                "0x%08X, 0x%08X, 0x%08X\n",
1355                                dma_reason[0], dma_reason[1],
1356                                dma_reason[2], dma_reason[3],
1357                                dma_reason[4], dma_reason[5]);
1358         }
1359
1360         if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1361                 handle_irq_ucode_debug(dev);
1362         if (reason & B43legacy_IRQ_TBTT_INDI)
1363                 handle_irq_tbtt_indication(dev);
1364         if (reason & B43legacy_IRQ_ATIM_END)
1365                 handle_irq_atim_end(dev);
1366         if (reason & B43legacy_IRQ_BEACON)
1367                 handle_irq_beacon(dev);
1368         if (reason & B43legacy_IRQ_PMQ)
1369                 handle_irq_pmq(dev);
1370         if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1371                 ;/*TODO*/
1372         if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1373                 handle_irq_noise(dev);
1374
1375         /* Check the DMA reason registers for received data. */
1376         if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1377                 if (b43legacy_using_pio(dev))
1378                         b43legacy_pio_rx(dev->pio.queue0);
1379                 else
1380                         b43legacy_dma_rx(dev->dma.rx_ring0);
1381         }
1382         B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1383         B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1384         if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1385                 if (b43legacy_using_pio(dev))
1386                         b43legacy_pio_rx(dev->pio.queue3);
1387                 else
1388                         b43legacy_dma_rx(dev->dma.rx_ring3);
1389         }
1390         B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1391         B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1392
1393         if (reason & B43legacy_IRQ_TX_OK)
1394                 handle_irq_transmit_status(dev);
1395
1396         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1397         mmiowb();
1398         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1399 }
1400
1401 static void pio_irq_workaround(struct b43legacy_wldev *dev,
1402                                u16 base, int queueidx)
1403 {
1404         u16 rxctl;
1405
1406         rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1407         if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1408                 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1409         else
1410                 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1411 }
1412
1413 static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1414 {
1415         if (b43legacy_using_pio(dev) &&
1416             (dev->dev->id.revision < 3) &&
1417             (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1418                 /* Apply a PIO specific workaround to the dma_reasons */
1419                 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1420                 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1421                 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1422                 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1423         }
1424
1425         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1426
1427         b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1428                           dev->dma_reason[0]);
1429         b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1430                           dev->dma_reason[1]);
1431         b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1432                           dev->dma_reason[2]);
1433         b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1434                           dev->dma_reason[3]);
1435         b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1436                           dev->dma_reason[4]);
1437         b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1438                           dev->dma_reason[5]);
1439 }
1440
1441 /* Interrupt handler top-half */
1442 static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1443 {
1444         irqreturn_t ret = IRQ_NONE;
1445         struct b43legacy_wldev *dev = dev_id;
1446         u32 reason;
1447
1448         B43legacy_WARN_ON(!dev);
1449
1450         spin_lock(&dev->wl->irq_lock);
1451
1452         if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
1453                 /* This can only happen on shared IRQ lines. */
1454                 goto out;
1455         reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1456         if (reason == 0xffffffff) /* shared IRQ */
1457                 goto out;
1458         ret = IRQ_HANDLED;
1459         reason &= dev->irq_mask;
1460         if (!reason)
1461                 goto out;
1462
1463         dev->dma_reason[0] = b43legacy_read32(dev,
1464                                               B43legacy_MMIO_DMA0_REASON)
1465                                               & 0x0001DC00;
1466         dev->dma_reason[1] = b43legacy_read32(dev,
1467                                               B43legacy_MMIO_DMA1_REASON)
1468                                               & 0x0000DC00;
1469         dev->dma_reason[2] = b43legacy_read32(dev,
1470                                               B43legacy_MMIO_DMA2_REASON)
1471                                               & 0x0000DC00;
1472         dev->dma_reason[3] = b43legacy_read32(dev,
1473                                               B43legacy_MMIO_DMA3_REASON)
1474                                               & 0x0001DC00;
1475         dev->dma_reason[4] = b43legacy_read32(dev,
1476                                               B43legacy_MMIO_DMA4_REASON)
1477                                               & 0x0000DC00;
1478         dev->dma_reason[5] = b43legacy_read32(dev,
1479                                               B43legacy_MMIO_DMA5_REASON)
1480                                               & 0x0000DC00;
1481
1482         b43legacy_interrupt_ack(dev, reason);
1483         /* Disable all IRQs. They are enabled again in the bottom half. */
1484         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1485         /* Save the reason code and call our bottom half. */
1486         dev->irq_reason = reason;
1487         tasklet_schedule(&dev->isr_tasklet);
1488 out:
1489         mmiowb();
1490         spin_unlock(&dev->wl->irq_lock);
1491
1492         return ret;
1493 }
1494
1495 static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1496 {
1497         release_firmware(dev->fw.ucode);
1498         dev->fw.ucode = NULL;
1499         release_firmware(dev->fw.pcm);
1500         dev->fw.pcm = NULL;
1501         release_firmware(dev->fw.initvals);
1502         dev->fw.initvals = NULL;
1503         release_firmware(dev->fw.initvals_band);
1504         dev->fw.initvals_band = NULL;
1505 }
1506
1507 static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1508 {
1509         b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
1510                      "Drivers/b43#devicefirmware "
1511                      "and download the correct firmware (version 3).\n");
1512 }
1513
1514 static int do_request_fw(struct b43legacy_wldev *dev,
1515                          const char *name,
1516                          const struct firmware **fw)
1517 {
1518         char path[sizeof(modparam_fwpostfix) + 32];
1519         struct b43legacy_fw_header *hdr;
1520         u32 size;
1521         int err;
1522
1523         if (!name)
1524                 return 0;
1525
1526         snprintf(path, ARRAY_SIZE(path),
1527                  "b43legacy%s/%s.fw",
1528                  modparam_fwpostfix, name);
1529         err = request_firmware(fw, path, dev->dev->dev);
1530         if (err) {
1531                 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1532                        "or load failed.\n", path);
1533                 return err;
1534         }
1535         if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1536                 goto err_format;
1537         hdr = (struct b43legacy_fw_header *)((*fw)->data);
1538         switch (hdr->type) {
1539         case B43legacy_FW_TYPE_UCODE:
1540         case B43legacy_FW_TYPE_PCM:
1541                 size = be32_to_cpu(hdr->size);
1542                 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1543                         goto err_format;
1544                 /* fallthrough */
1545         case B43legacy_FW_TYPE_IV:
1546                 if (hdr->ver != 1)
1547                         goto err_format;
1548                 break;
1549         default:
1550                 goto err_format;
1551         }
1552
1553         return err;
1554
1555 err_format:
1556         b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1557         return -EPROTO;
1558 }
1559
1560 static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1561 {
1562         struct b43legacy_firmware *fw = &dev->fw;
1563         const u8 rev = dev->dev->id.revision;
1564         const char *filename;
1565         int err;
1566
1567         if (!fw->ucode) {
1568                 if (rev == 2)
1569                         filename = "ucode2";
1570                 else if (rev == 4)
1571                         filename = "ucode4";
1572                 else
1573                         filename = "ucode5";
1574                 err = do_request_fw(dev, filename, &fw->ucode);
1575                 if (err)
1576                         goto err_load;
1577         }
1578         if (!fw->pcm) {
1579                 if (rev < 5)
1580                         filename = "pcm4";
1581                 else
1582                         filename = "pcm5";
1583                 err = do_request_fw(dev, filename, &fw->pcm);
1584                 if (err)
1585                         goto err_load;
1586         }
1587         if (!fw->initvals) {
1588                 switch (dev->phy.type) {
1589                 case B43legacy_PHYTYPE_B:
1590                 case B43legacy_PHYTYPE_G:
1591                         if ((rev >= 5) && (rev <= 10))
1592                                 filename = "b0g0initvals5";
1593                         else if (rev == 2 || rev == 4)
1594                                 filename = "b0g0initvals2";
1595                         else
1596                                 goto err_no_initvals;
1597                         break;
1598                 default:
1599                         goto err_no_initvals;
1600                 }
1601                 err = do_request_fw(dev, filename, &fw->initvals);
1602                 if (err)
1603                         goto err_load;
1604         }
1605         if (!fw->initvals_band) {
1606                 switch (dev->phy.type) {
1607                 case B43legacy_PHYTYPE_B:
1608                 case B43legacy_PHYTYPE_G:
1609                         if ((rev >= 5) && (rev <= 10))
1610                                 filename = "b0g0bsinitvals5";
1611                         else if (rev >= 11)
1612                                 filename = NULL;
1613                         else if (rev == 2 || rev == 4)
1614                                 filename = NULL;
1615                         else
1616                                 goto err_no_initvals;
1617                         break;
1618                 default:
1619                         goto err_no_initvals;
1620                 }
1621                 err = do_request_fw(dev, filename, &fw->initvals_band);
1622                 if (err)
1623                         goto err_load;
1624         }
1625
1626         return 0;
1627
1628 err_load:
1629         b43legacy_print_fw_helptext(dev->wl);
1630         goto error;
1631
1632 err_no_initvals:
1633         err = -ENODEV;
1634         b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1635                "core rev %u\n", dev->phy.type, rev);
1636         goto error;
1637
1638 error:
1639         b43legacy_release_firmware(dev);
1640         return err;
1641 }
1642
1643 static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1644 {
1645         struct wiphy *wiphy = dev->wl->hw->wiphy;
1646         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1647         const __be32 *data;
1648         unsigned int i;
1649         unsigned int len;
1650         u16 fwrev;
1651         u16 fwpatch;
1652         u16 fwdate;
1653         u16 fwtime;
1654         u32 tmp, macctl;
1655         int err = 0;
1656
1657         /* Jump the microcode PSM to offset 0 */
1658         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1659         B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1660         macctl |= B43legacy_MACCTL_PSM_JMP0;
1661         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1662         /* Zero out all microcode PSM registers and shared memory. */
1663         for (i = 0; i < 64; i++)
1664                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1665         for (i = 0; i < 4096; i += 2)
1666                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1667
1668         /* Upload Microcode. */
1669         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1670         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1671         b43legacy_shm_control_word(dev,
1672                                    B43legacy_SHM_UCODE |
1673                                    B43legacy_SHM_AUTOINC_W,
1674                                    0x0000);
1675         for (i = 0; i < len; i++) {
1676                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1677                                     be32_to_cpu(data[i]));
1678                 udelay(10);
1679         }
1680
1681         if (dev->fw.pcm) {
1682                 /* Upload PCM data. */
1683                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1684                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1685                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1686                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1687                 /* No need for autoinc bit in SHM_HW */
1688                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1689                 for (i = 0; i < len; i++) {
1690                         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1691                                           be32_to_cpu(data[i]));
1692                         udelay(10);
1693                 }
1694         }
1695
1696         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1697                           B43legacy_IRQ_ALL);
1698
1699         /* Start the microcode PSM */
1700         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1701         macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1702         macctl |= B43legacy_MACCTL_PSM_RUN;
1703         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1704
1705         /* Wait for the microcode to load and respond */
1706         i = 0;
1707         while (1) {
1708                 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1709                 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1710                         break;
1711                 i++;
1712                 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1713                         b43legacyerr(dev->wl, "Microcode not responding\n");
1714                         b43legacy_print_fw_helptext(dev->wl);
1715                         err = -ENODEV;
1716                         goto error;
1717                 }
1718                 msleep_interruptible(50);
1719                 if (signal_pending(current)) {
1720                         err = -EINTR;
1721                         goto error;
1722                 }
1723         }
1724         /* dummy read follows */
1725         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1726
1727         /* Get and check the revisions. */
1728         fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1729                                      B43legacy_SHM_SH_UCODEREV);
1730         fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1731                                        B43legacy_SHM_SH_UCODEPATCH);
1732         fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1733                                       B43legacy_SHM_SH_UCODEDATE);
1734         fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1735                                       B43legacy_SHM_SH_UCODETIME);
1736
1737         if (fwrev > 0x128) {
1738                 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1739                              " Only firmware from binary drivers version 3.x"
1740                              " is supported. You must change your firmware"
1741                              " files.\n");
1742                 b43legacy_print_fw_helptext(dev->wl);
1743                 err = -EOPNOTSUPP;
1744                 goto error;
1745         }
1746         b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1747                       "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1748                       (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1749                       (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1750                       fwtime & 0x1F);
1751
1752         dev->fw.rev = fwrev;
1753         dev->fw.patch = fwpatch;
1754
1755         snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
1756                         dev->fw.rev, dev->fw.patch);
1757         wiphy->hw_version = dev->dev->id.coreid;
1758
1759         return 0;
1760
1761 error:
1762         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1763         macctl &= ~B43legacy_MACCTL_PSM_RUN;
1764         macctl |= B43legacy_MACCTL_PSM_JMP0;
1765         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1766
1767         return err;
1768 }
1769
1770 static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1771                                     const struct b43legacy_iv *ivals,
1772                                     size_t count,
1773                                     size_t array_size)
1774 {
1775         const struct b43legacy_iv *iv;
1776         u16 offset;
1777         size_t i;
1778         bool bit32;
1779
1780         BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1781         iv = ivals;
1782         for (i = 0; i < count; i++) {
1783                 if (array_size < sizeof(iv->offset_size))
1784                         goto err_format;
1785                 array_size -= sizeof(iv->offset_size);
1786                 offset = be16_to_cpu(iv->offset_size);
1787                 bit32 = !!(offset & B43legacy_IV_32BIT);
1788                 offset &= B43legacy_IV_OFFSET_MASK;
1789                 if (offset >= 0x1000)
1790                         goto err_format;
1791                 if (bit32) {
1792                         u32 value;
1793
1794                         if (array_size < sizeof(iv->data.d32))
1795                                 goto err_format;
1796                         array_size -= sizeof(iv->data.d32);
1797
1798                         value = get_unaligned_be32(&iv->data.d32);
1799                         b43legacy_write32(dev, offset, value);
1800
1801                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1802                                                         sizeof(__be16) +
1803                                                         sizeof(__be32));
1804                 } else {
1805                         u16 value;
1806
1807                         if (array_size < sizeof(iv->data.d16))
1808                                 goto err_format;
1809                         array_size -= sizeof(iv->data.d16);
1810
1811                         value = be16_to_cpu(iv->data.d16);
1812                         b43legacy_write16(dev, offset, value);
1813
1814                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1815                                                         sizeof(__be16) +
1816                                                         sizeof(__be16));
1817                 }
1818         }
1819         if (array_size)
1820                 goto err_format;
1821
1822         return 0;
1823
1824 err_format:
1825         b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1826         b43legacy_print_fw_helptext(dev->wl);
1827
1828         return -EPROTO;
1829 }
1830
1831 static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1832 {
1833         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1834         const struct b43legacy_fw_header *hdr;
1835         struct b43legacy_firmware *fw = &dev->fw;
1836         const struct b43legacy_iv *ivals;
1837         size_t count;
1838         int err;
1839
1840         hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1841         ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1842         count = be32_to_cpu(hdr->size);
1843         err = b43legacy_write_initvals(dev, ivals, count,
1844                                  fw->initvals->size - hdr_len);
1845         if (err)
1846                 goto out;
1847         if (fw->initvals_band) {
1848                 hdr = (const struct b43legacy_fw_header *)
1849                       (fw->initvals_band->data);
1850                 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1851                         + hdr_len);
1852                 count = be32_to_cpu(hdr->size);
1853                 err = b43legacy_write_initvals(dev, ivals, count,
1854                                          fw->initvals_band->size - hdr_len);
1855                 if (err)
1856                         goto out;
1857         }
1858 out:
1859
1860         return err;
1861 }
1862
1863 /* Initialize the GPIOs
1864  * http://bcm-specs.sipsolutions.net/GPIO
1865  */
1866 static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1867 {
1868         struct ssb_bus *bus = dev->dev->bus;
1869         struct ssb_device *gpiodev, *pcidev = NULL;
1870         u32 mask;
1871         u32 set;
1872
1873         b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1874                           b43legacy_read32(dev,
1875                           B43legacy_MMIO_MACCTL)
1876                           & 0xFFFF3FFF);
1877
1878         b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1879                           b43legacy_read16(dev,
1880                           B43legacy_MMIO_GPIO_MASK)
1881                           | 0x000F);
1882
1883         mask = 0x0000001F;
1884         set = 0x0000000F;
1885         if (dev->dev->bus->chip_id == 0x4301) {
1886                 mask |= 0x0060;
1887                 set |= 0x0060;
1888         }
1889         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
1890                 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1891                                   b43legacy_read16(dev,
1892                                   B43legacy_MMIO_GPIO_MASK)
1893                                   | 0x0200);
1894                 mask |= 0x0200;
1895                 set |= 0x0200;
1896         }
1897         if (dev->dev->id.revision >= 2)
1898                 mask  |= 0x0010; /* FIXME: This is redundant. */
1899
1900 #ifdef CONFIG_SSB_DRIVER_PCICORE
1901         pcidev = bus->pcicore.dev;
1902 #endif
1903         gpiodev = bus->chipco.dev ? : pcidev;
1904         if (!gpiodev)
1905                 return 0;
1906         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1907                     (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1908                      & mask) | set);
1909
1910         return 0;
1911 }
1912
1913 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1914 static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1915 {
1916         struct ssb_bus *bus = dev->dev->bus;
1917         struct ssb_device *gpiodev, *pcidev = NULL;
1918
1919 #ifdef CONFIG_SSB_DRIVER_PCICORE
1920         pcidev = bus->pcicore.dev;
1921 #endif
1922         gpiodev = bus->chipco.dev ? : pcidev;
1923         if (!gpiodev)
1924                 return;
1925         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1926 }
1927
1928 /* http://bcm-specs.sipsolutions.net/EnableMac */
1929 void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1930 {
1931         dev->mac_suspended--;
1932         B43legacy_WARN_ON(dev->mac_suspended < 0);
1933         B43legacy_WARN_ON(irqs_disabled());
1934         if (dev->mac_suspended == 0) {
1935                 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1936                                   b43legacy_read32(dev,
1937                                   B43legacy_MMIO_MACCTL)
1938                                   | B43legacy_MACCTL_ENABLED);
1939                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1940                                   B43legacy_IRQ_MAC_SUSPENDED);
1941                 /* the next two are dummy reads */
1942                 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1943                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1944                 b43legacy_power_saving_ctl_bits(dev, -1, -1);
1945
1946                 /* Re-enable IRQs. */
1947                 spin_lock_irq(&dev->wl->irq_lock);
1948                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1949                                   dev->irq_mask);
1950                 spin_unlock_irq(&dev->wl->irq_lock);
1951         }
1952 }
1953
1954 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1955 void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1956 {
1957         int i;
1958         u32 tmp;
1959
1960         might_sleep();
1961         B43legacy_WARN_ON(irqs_disabled());
1962         B43legacy_WARN_ON(dev->mac_suspended < 0);
1963
1964         if (dev->mac_suspended == 0) {
1965                 /* Mask IRQs before suspending MAC. Otherwise
1966                  * the MAC stays busy and won't suspend. */
1967                 spin_lock_irq(&dev->wl->irq_lock);
1968                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1969                 spin_unlock_irq(&dev->wl->irq_lock);
1970                 b43legacy_synchronize_irq(dev);
1971
1972                 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1973                 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1974                                   b43legacy_read32(dev,
1975                                   B43legacy_MMIO_MACCTL)
1976                                   & ~B43legacy_MACCTL_ENABLED);
1977                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1978                 for (i = 40; i; i--) {
1979                         tmp = b43legacy_read32(dev,
1980                                                B43legacy_MMIO_GEN_IRQ_REASON);
1981                         if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1982                                 goto out;
1983                         msleep(1);
1984                 }
1985                 b43legacyerr(dev->wl, "MAC suspend failed\n");
1986         }
1987 out:
1988         dev->mac_suspended++;
1989 }
1990
1991 static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
1992 {
1993         struct b43legacy_wl *wl = dev->wl;
1994         u32 ctl;
1995         u16 cfp_pretbtt;
1996
1997         ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1998         /* Reset status to STA infrastructure mode. */
1999         ctl &= ~B43legacy_MACCTL_AP;
2000         ctl &= ~B43legacy_MACCTL_KEEP_CTL;
2001         ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
2002         ctl &= ~B43legacy_MACCTL_KEEP_BAD;
2003         ctl &= ~B43legacy_MACCTL_PROMISC;
2004         ctl &= ~B43legacy_MACCTL_BEACPROMISC;
2005         ctl |= B43legacy_MACCTL_INFRA;
2006
2007         if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
2008                 ctl |= B43legacy_MACCTL_AP;
2009         else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))
2010                 ctl &= ~B43legacy_MACCTL_INFRA;
2011
2012         if (wl->filter_flags & FIF_CONTROL)
2013                 ctl |= B43legacy_MACCTL_KEEP_CTL;
2014         if (wl->filter_flags & FIF_FCSFAIL)
2015                 ctl |= B43legacy_MACCTL_KEEP_BAD;
2016         if (wl->filter_flags & FIF_PLCPFAIL)
2017                 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
2018         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2019                 ctl |= B43legacy_MACCTL_PROMISC;
2020         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2021                 ctl |= B43legacy_MACCTL_BEACPROMISC;
2022
2023         /* Workaround: On old hardware the HW-MAC-address-filter
2024          * doesn't work properly, so always run promisc in filter
2025          * it in software. */
2026         if (dev->dev->id.revision <= 4)
2027                 ctl |= B43legacy_MACCTL_PROMISC;
2028
2029         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
2030
2031         cfp_pretbtt = 2;
2032         if ((ctl & B43legacy_MACCTL_INFRA) &&
2033             !(ctl & B43legacy_MACCTL_AP)) {
2034                 if (dev->dev->bus->chip_id == 0x4306 &&
2035                     dev->dev->bus->chip_rev == 3)
2036                         cfp_pretbtt = 100;
2037                 else
2038                         cfp_pretbtt = 50;
2039         }
2040         b43legacy_write16(dev, 0x612, cfp_pretbtt);
2041 }
2042
2043 static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
2044                                         u16 rate,
2045                                         int is_ofdm)
2046 {
2047         u16 offset;
2048
2049         if (is_ofdm) {
2050                 offset = 0x480;
2051                 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2052         } else {
2053                 offset = 0x4C0;
2054                 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2055         }
2056         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
2057                               b43legacy_shm_read16(dev,
2058                               B43legacy_SHM_SHARED, offset));
2059 }
2060
2061 static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
2062 {
2063         switch (dev->phy.type) {
2064         case B43legacy_PHYTYPE_G:
2065                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
2066                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
2067                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
2068                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
2069                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
2070                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
2071                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
2072                 /* fallthrough */
2073         case B43legacy_PHYTYPE_B:
2074                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
2075                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
2076                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
2077                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
2078                 break;
2079         default:
2080                 B43legacy_BUG_ON(1);
2081         }
2082 }
2083
2084 /* Set the TX-Antenna for management frames sent by firmware. */
2085 static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
2086                                           int antenna)
2087 {
2088         u16 ant = 0;
2089         u16 tmp;
2090
2091         switch (antenna) {
2092         case B43legacy_ANTENNA0:
2093                 ant |= B43legacy_TX4_PHY_ANT0;
2094                 break;
2095         case B43legacy_ANTENNA1:
2096                 ant |= B43legacy_TX4_PHY_ANT1;
2097                 break;
2098         case B43legacy_ANTENNA_AUTO:
2099                 ant |= B43legacy_TX4_PHY_ANTLAST;
2100                 break;
2101         default:
2102                 B43legacy_BUG_ON(1);
2103         }
2104
2105         /* FIXME We also need to set the other flags of the PHY control
2106          * field somewhere. */
2107
2108         /* For Beacons */
2109         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2110                                    B43legacy_SHM_SH_BEACPHYCTL);
2111         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2112         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2113                               B43legacy_SHM_SH_BEACPHYCTL, tmp);
2114         /* For ACK/CTS */
2115         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2116                                    B43legacy_SHM_SH_ACKCTSPHYCTL);
2117         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2118         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2119                               B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2120         /* For Probe Resposes */
2121         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2122                                    B43legacy_SHM_SH_PRPHYCTL);
2123         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2124         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2125                               B43legacy_SHM_SH_PRPHYCTL, tmp);
2126 }
2127
2128 /* This is the opposite of b43legacy_chip_init() */
2129 static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2130 {
2131         b43legacy_radio_turn_off(dev, 1);
2132         b43legacy_gpio_cleanup(dev);
2133         /* firmware is released later */
2134 }
2135
2136 /* Initialize the chip
2137  * http://bcm-specs.sipsolutions.net/ChipInit
2138  */
2139 static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2140 {
2141         struct b43legacy_phy *phy = &dev->phy;
2142         int err;
2143         int tmp;
2144         u32 value32, macctl;
2145         u16 value16;
2146
2147         /* Initialize the MAC control */
2148         macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2149         if (dev->phy.gmode)
2150                 macctl |= B43legacy_MACCTL_GMODE;
2151         macctl |= B43legacy_MACCTL_INFRA;
2152         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
2153
2154         err = b43legacy_request_firmware(dev);
2155         if (err)
2156                 goto out;
2157         err = b43legacy_upload_microcode(dev);
2158         if (err)
2159                 goto out; /* firmware is released later */
2160
2161         err = b43legacy_gpio_init(dev);
2162         if (err)
2163                 goto out; /* firmware is released later */
2164
2165         err = b43legacy_upload_initvals(dev);
2166         if (err)
2167                 goto err_gpio_clean;
2168         b43legacy_radio_turn_on(dev);
2169
2170         b43legacy_write16(dev, 0x03E6, 0x0000);
2171         err = b43legacy_phy_init(dev);
2172         if (err)
2173                 goto err_radio_off;
2174
2175         /* Select initial Interference Mitigation. */
2176         tmp = phy->interfmode;
2177         phy->interfmode = B43legacy_INTERFMODE_NONE;
2178         b43legacy_radio_set_interference_mitigation(dev, tmp);
2179
2180         b43legacy_phy_set_antenna_diversity(dev);
2181         b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2182
2183         if (phy->type == B43legacy_PHYTYPE_B) {
2184                 value16 = b43legacy_read16(dev, 0x005E);
2185                 value16 |= 0x0004;
2186                 b43legacy_write16(dev, 0x005E, value16);
2187         }
2188         b43legacy_write32(dev, 0x0100, 0x01000000);
2189         if (dev->dev->id.revision < 5)
2190                 b43legacy_write32(dev, 0x010C, 0x01000000);
2191
2192         value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2193         value32 &= ~B43legacy_MACCTL_INFRA;
2194         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2195         value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2196         value32 |= B43legacy_MACCTL_INFRA;
2197         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2198
2199         if (b43legacy_using_pio(dev)) {
2200                 b43legacy_write32(dev, 0x0210, 0x00000100);
2201                 b43legacy_write32(dev, 0x0230, 0x00000100);
2202                 b43legacy_write32(dev, 0x0250, 0x00000100);
2203                 b43legacy_write32(dev, 0x0270, 0x00000100);
2204                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2205                                       0x0000);
2206         }
2207
2208         /* Probe Response Timeout value */
2209         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2210         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2211
2212         /* Initially set the wireless operation mode. */
2213         b43legacy_adjust_opmode(dev);
2214
2215         if (dev->dev->id.revision < 3) {
2216                 b43legacy_write16(dev, 0x060E, 0x0000);
2217                 b43legacy_write16(dev, 0x0610, 0x8000);
2218                 b43legacy_write16(dev, 0x0604, 0x0000);
2219                 b43legacy_write16(dev, 0x0606, 0x0200);
2220         } else {
2221                 b43legacy_write32(dev, 0x0188, 0x80000000);
2222                 b43legacy_write32(dev, 0x018C, 0x02000000);
2223         }
2224         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2225         b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2226         b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2227         b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2228         b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2229         b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2230         b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2231
2232         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2233         value32 |= B43legacy_TMSLOW_MACPHYCLKEN;
2234         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2235
2236         b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2237                           dev->dev->bus->chipco.fast_pwrup_delay);
2238
2239         /* PHY TX errors counter. */
2240         atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2241
2242         B43legacy_WARN_ON(err != 0);
2243         b43legacydbg(dev->wl, "Chip initialized\n");
2244 out:
2245         return err;
2246
2247 err_radio_off:
2248         b43legacy_radio_turn_off(dev, 1);
2249 err_gpio_clean:
2250         b43legacy_gpio_cleanup(dev);
2251         goto out;
2252 }
2253
2254 static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2255 {
2256         struct b43legacy_phy *phy = &dev->phy;
2257
2258         if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2259                 return;
2260
2261         b43legacy_mac_suspend(dev);
2262         b43legacy_phy_lo_g_measure(dev);
2263         b43legacy_mac_enable(dev);
2264 }
2265
2266 static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2267 {
2268         b43legacy_phy_lo_mark_all_unused(dev);
2269         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
2270                 b43legacy_mac_suspend(dev);
2271                 b43legacy_calc_nrssi_slope(dev);
2272                 b43legacy_mac_enable(dev);
2273         }
2274 }
2275
2276 static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2277 {
2278         /* Update device statistics. */
2279         b43legacy_calculate_link_quality(dev);
2280 }
2281
2282 static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2283 {
2284         b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
2285
2286         atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2287         wmb();
2288 }
2289
2290 static void do_periodic_work(struct b43legacy_wldev *dev)
2291 {
2292         unsigned int state;
2293
2294         state = dev->periodic_state;
2295         if (state % 8 == 0)
2296                 b43legacy_periodic_every120sec(dev);
2297         if (state % 4 == 0)
2298                 b43legacy_periodic_every60sec(dev);
2299         if (state % 2 == 0)
2300                 b43legacy_periodic_every30sec(dev);
2301         b43legacy_periodic_every15sec(dev);
2302 }
2303
2304 /* Periodic work locking policy:
2305  *      The whole periodic work handler is protected by
2306  *      wl->mutex. If another lock is needed somewhere in the
2307  *      pwork callchain, it's acquired in-place, where it's needed.
2308  */
2309 static void b43legacy_periodic_work_handler(struct work_struct *work)
2310 {
2311         struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2312                                              periodic_work.work);
2313         struct b43legacy_wl *wl = dev->wl;
2314         unsigned long delay;
2315
2316         mutex_lock(&wl->mutex);
2317
2318         if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2319                 goto out;
2320         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2321                 goto out_requeue;
2322
2323         do_periodic_work(dev);
2324
2325         dev->periodic_state++;
2326 out_requeue:
2327         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2328                 delay = msecs_to_jiffies(50);
2329         else
2330                 delay = round_jiffies_relative(HZ * 15);
2331         ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2332 out:
2333         mutex_unlock(&wl->mutex);
2334 }
2335
2336 static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2337 {
2338         struct delayed_work *work = &dev->periodic_work;
2339
2340         dev->periodic_state = 0;
2341         INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
2342         ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
2343 }
2344
2345 /* Validate access to the chip (SHM) */
2346 static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2347 {
2348         u32 value;
2349         u32 shm_backup;
2350
2351         shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2352         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2353         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2354                                  0xAA5555AA)
2355                 goto error;
2356         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2357         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2358                                  0x55AAAA55)
2359                 goto error;
2360         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2361
2362         value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2363         if ((value | B43legacy_MACCTL_GMODE) !=
2364             (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2365                 goto error;
2366
2367         value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2368         if (value)
2369                 goto error;
2370
2371         return 0;
2372 error:
2373         b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2374         return -ENODEV;
2375 }
2376
2377 static void b43legacy_security_init(struct b43legacy_wldev *dev)
2378 {
2379         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2380         B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2381         dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2382                                         0x0056);
2383         /* KTP is a word address, but we address SHM bytewise.
2384          * So multiply by two.
2385          */
2386         dev->ktp *= 2;
2387         if (dev->dev->id.revision >= 5)
2388                 /* Number of RCMTA address slots */
2389                 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2390                                   dev->max_nr_keys - 8);
2391 }
2392
2393 #ifdef CONFIG_B43LEGACY_HWRNG
2394 static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2395 {
2396         struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2397         unsigned long flags;
2398
2399         /* Don't take wl->mutex here, as it could deadlock with
2400          * hwrng internal locking. It's not needed to take
2401          * wl->mutex here, anyway. */
2402
2403         spin_lock_irqsave(&wl->irq_lock, flags);
2404         *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2405         spin_unlock_irqrestore(&wl->irq_lock, flags);
2406
2407         return (sizeof(u16));
2408 }
2409 #endif
2410
2411 static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2412 {
2413 #ifdef CONFIG_B43LEGACY_HWRNG
2414         if (wl->rng_initialized)
2415                 hwrng_unregister(&wl->rng);
2416 #endif
2417 }
2418
2419 static int b43legacy_rng_init(struct b43legacy_wl *wl)
2420 {
2421         int err = 0;
2422
2423 #ifdef CONFIG_B43LEGACY_HWRNG
2424         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2425                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2426         wl->rng.name = wl->rng_name;
2427         wl->rng.data_read = b43legacy_rng_read;
2428         wl->rng.priv = (unsigned long)wl;
2429         wl->rng_initialized = 1;
2430         err = hwrng_register(&wl->rng);
2431         if (err) {
2432                 wl->rng_initialized = 0;
2433                 b43legacyerr(wl, "Failed to register the random "
2434                        "number generator (%d)\n", err);
2435         }
2436
2437 #endif
2438         return err;
2439 }
2440
2441 static void b43legacy_op_tx(struct ieee80211_hw *hw,
2442                             struct sk_buff *skb)
2443 {
2444         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2445         struct b43legacy_wldev *dev = wl->current_dev;
2446         int err = -ENODEV;
2447         unsigned long flags;
2448
2449         if (unlikely(!dev))
2450                 goto out;
2451         if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
2452                 goto out;
2453         /* DMA-TX is done without a global lock. */
2454         if (b43legacy_using_pio(dev)) {
2455                 spin_lock_irqsave(&wl->irq_lock, flags);
2456                 err = b43legacy_pio_tx(dev, skb);
2457                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2458         } else
2459                 err = b43legacy_dma_tx(dev, skb);
2460 out:
2461         if (unlikely(err)) {
2462                 /* Drop the packet. */
2463                 dev_kfree_skb_any(skb);
2464         }
2465 }
2466
2467 static int b43legacy_op_conf_tx(struct ieee80211_hw *hw,
2468                                 struct ieee80211_vif *vif, u16 queue,
2469                                 const struct ieee80211_tx_queue_params *params)
2470 {
2471         return 0;
2472 }
2473
2474 static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2475                                   struct ieee80211_low_level_stats *stats)
2476 {
2477         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2478         unsigned long flags;
2479
2480         spin_lock_irqsave(&wl->irq_lock, flags);
2481         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2482         spin_unlock_irqrestore(&wl->irq_lock, flags);
2483
2484         return 0;
2485 }
2486
2487 static const char *phymode_to_string(unsigned int phymode)
2488 {
2489         switch (phymode) {
2490         case B43legacy_PHYMODE_B:
2491                 return "B";
2492         case B43legacy_PHYMODE_G:
2493                 return "G";
2494         default:
2495                 B43legacy_BUG_ON(1);
2496         }
2497         return "";
2498 }
2499
2500 static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2501                                   unsigned int phymode,
2502                                   struct b43legacy_wldev **dev,
2503                                   bool *gmode)
2504 {
2505         struct b43legacy_wldev *d;
2506
2507         list_for_each_entry(d, &wl->devlist, list) {
2508                 if (d->phy.possible_phymodes & phymode) {
2509                         /* Ok, this device supports the PHY-mode.
2510                          * Set the gmode bit. */
2511                         *gmode = 1;
2512                         *dev = d;
2513
2514                         return 0;
2515                 }
2516         }
2517
2518         return -ESRCH;
2519 }
2520
2521 static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2522 {
2523         struct ssb_device *sdev = dev->dev;
2524         u32 tmslow;
2525
2526         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2527         tmslow &= ~B43legacy_TMSLOW_GMODE;
2528         tmslow |= B43legacy_TMSLOW_PHYRESET;
2529         tmslow |= SSB_TMSLOW_FGC;
2530         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2531         msleep(1);
2532
2533         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2534         tmslow &= ~SSB_TMSLOW_FGC;
2535         tmslow |= B43legacy_TMSLOW_PHYRESET;
2536         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2537         msleep(1);
2538 }
2539
2540 /* Expects wl->mutex locked */
2541 static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2542                                       unsigned int new_mode)
2543 {
2544         struct b43legacy_wldev *uninitialized_var(up_dev);
2545         struct b43legacy_wldev *down_dev;
2546         int err;
2547         bool gmode = 0;
2548         int prev_status;
2549
2550         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2551         if (err) {
2552                 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2553                        phymode_to_string(new_mode));
2554                 return err;
2555         }
2556         if ((up_dev == wl->current_dev) &&
2557             (!!wl->current_dev->phy.gmode == !!gmode))
2558                 /* This device is already running. */
2559                 return 0;
2560         b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2561                phymode_to_string(new_mode));
2562         down_dev = wl->current_dev;
2563
2564         prev_status = b43legacy_status(down_dev);
2565         /* Shutdown the currently running core. */
2566         if (prev_status >= B43legacy_STAT_STARTED)
2567                 b43legacy_wireless_core_stop(down_dev);
2568         if (prev_status >= B43legacy_STAT_INITIALIZED)
2569                 b43legacy_wireless_core_exit(down_dev);
2570
2571         if (down_dev != up_dev)
2572                 /* We switch to a different core, so we put PHY into
2573                  * RESET on the old core. */
2574                 b43legacy_put_phy_into_reset(down_dev);
2575
2576         /* Now start the new core. */
2577         up_dev->phy.gmode = gmode;
2578         if (prev_status >= B43legacy_STAT_INITIALIZED) {
2579                 err = b43legacy_wireless_core_init(up_dev);
2580                 if (err) {
2581                         b43legacyerr(wl, "Fatal: Could not initialize device"
2582                                      " for newly selected %s-PHY mode\n",
2583                                      phymode_to_string(new_mode));
2584                         goto init_failure;
2585                 }
2586         }
2587         if (prev_status >= B43legacy_STAT_STARTED) {
2588                 err = b43legacy_wireless_core_start(up_dev);
2589                 if (err) {
2590                         b43legacyerr(wl, "Fatal: Coult not start device for "
2591                                "newly selected %s-PHY mode\n",
2592                                phymode_to_string(new_mode));
2593                         b43legacy_wireless_core_exit(up_dev);
2594                         goto init_failure;
2595                 }
2596         }
2597         B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2598
2599         b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2600
2601         wl->current_dev = up_dev;
2602
2603         return 0;
2604 init_failure:
2605         /* Whoops, failed to init the new core. No core is operating now. */
2606         wl->current_dev = NULL;
2607         return err;
2608 }
2609
2610 /* Write the short and long frame retry limit values. */
2611 static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2612                                        unsigned int short_retry,
2613                                        unsigned int long_retry)
2614 {
2615         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2616          * the chip-internal counter. */
2617         short_retry = min(short_retry, (unsigned int)0xF);
2618         long_retry = min(long_retry, (unsigned int)0xF);
2619
2620         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2621         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2622 }
2623
2624 static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2625                                    u32 changed)
2626 {
2627         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2628         struct b43legacy_wldev *dev;
2629         struct b43legacy_phy *phy;
2630         struct ieee80211_conf *conf = &hw->conf;
2631         unsigned long flags;
2632         unsigned int new_phymode = 0xFFFF;
2633         int antenna_tx;
2634         int err = 0;
2635
2636         antenna_tx = B43legacy_ANTENNA_DEFAULT;
2637
2638         mutex_lock(&wl->mutex);
2639         dev = wl->current_dev;
2640         phy = &dev->phy;
2641
2642         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2643                 b43legacy_set_retry_limits(dev,
2644                                            conf->short_frame_max_tx_count,
2645                                            conf->long_frame_max_tx_count);
2646         changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
2647         if (!changed)
2648                 goto out_unlock_mutex;
2649
2650         /* Switch the PHY mode (if necessary). */
2651         switch (conf->channel->band) {
2652         case IEEE80211_BAND_2GHZ:
2653                 if (phy->type == B43legacy_PHYTYPE_B)
2654                         new_phymode = B43legacy_PHYMODE_B;
2655                 else
2656                         new_phymode = B43legacy_PHYMODE_G;
2657                 break;
2658         default:
2659                 B43legacy_WARN_ON(1);
2660         }
2661         err = b43legacy_switch_phymode(wl, new_phymode);
2662         if (err)
2663                 goto out_unlock_mutex;
2664
2665         /* Disable IRQs while reconfiguring the device.
2666          * This makes it possible to drop the spinlock throughout
2667          * the reconfiguration process. */
2668         spin_lock_irqsave(&wl->irq_lock, flags);
2669         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2670                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2671                 goto out_unlock_mutex;
2672         }
2673         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2674         spin_unlock_irqrestore(&wl->irq_lock, flags);
2675         b43legacy_synchronize_irq(dev);
2676
2677         /* Switch to the requested channel.
2678          * The firmware takes care of races with the TX handler. */
2679         if (conf->channel->hw_value != phy->channel)
2680                 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
2681
2682         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
2683
2684         /* Adjust the desired TX power level. */
2685         if (conf->power_level != 0) {
2686                 if (conf->power_level != phy->power_level) {
2687                         phy->power_level = conf->power_level;
2688                         b43legacy_phy_xmitpower(dev);
2689                 }
2690         }
2691
2692         /* Antennas for RX and management frame TX. */
2693         b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2694
2695         if (wl->radio_enabled != phy->radio_on) {
2696                 if (wl->radio_enabled) {
2697                         b43legacy_radio_turn_on(dev);
2698                         b43legacyinfo(dev->wl, "Radio turned on by software\n");
2699                         if (!dev->radio_hw_enable)
2700                                 b43legacyinfo(dev->wl, "The hardware RF-kill"
2701                                               " button still turns the radio"
2702                                               " physically off. Press the"
2703                                               " button to turn it on.\n");
2704                 } else {
2705                         b43legacy_radio_turn_off(dev, 0);
2706                         b43legacyinfo(dev->wl, "Radio turned off by"
2707                                       " software\n");
2708                 }
2709         }
2710
2711         spin_lock_irqsave(&wl->irq_lock, flags);
2712         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2713         mmiowb();
2714         spin_unlock_irqrestore(&wl->irq_lock, flags);
2715 out_unlock_mutex:
2716         mutex_unlock(&wl->mutex);
2717
2718         return err;
2719 }
2720
2721 static void b43legacy_update_basic_rates(struct b43legacy_wldev *dev, u32 brates)
2722 {
2723         struct ieee80211_supported_band *sband =
2724                 dev->wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2725         struct ieee80211_rate *rate;
2726         int i;
2727         u16 basic, direct, offset, basic_offset, rateptr;
2728
2729         for (i = 0; i < sband->n_bitrates; i++) {
2730                 rate = &sband->bitrates[i];
2731
2732                 if (b43legacy_is_cck_rate(rate->hw_value)) {
2733                         direct = B43legacy_SHM_SH_CCKDIRECT;
2734                         basic = B43legacy_SHM_SH_CCKBASIC;
2735                         offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2736                         offset &= 0xF;
2737                 } else {
2738                         direct = B43legacy_SHM_SH_OFDMDIRECT;
2739                         basic = B43legacy_SHM_SH_OFDMBASIC;
2740                         offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2741                         offset &= 0xF;
2742                 }
2743
2744                 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
2745
2746                 if (b43legacy_is_cck_rate(rate->hw_value)) {
2747                         basic_offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2748                         basic_offset &= 0xF;
2749                 } else {
2750                         basic_offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2751                         basic_offset &= 0xF;
2752                 }
2753
2754                 /*
2755                  * Get the pointer that we need to point to
2756                  * from the direct map
2757                  */
2758                 rateptr = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2759                                                direct + 2 * basic_offset);
2760                 /* and write it to the basic map */
2761                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2762                                       basic + 2 * offset, rateptr);
2763         }
2764 }
2765
2766 static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw,
2767                                     struct ieee80211_vif *vif,
2768                                     struct ieee80211_bss_conf *conf,
2769                                     u32 changed)
2770 {
2771         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2772         struct b43legacy_wldev *dev;
2773         unsigned long flags;
2774
2775         mutex_lock(&wl->mutex);
2776         B43legacy_WARN_ON(wl->vif != vif);
2777
2778         dev = wl->current_dev;
2779
2780         /* Disable IRQs while reconfiguring the device.
2781          * This makes it possible to drop the spinlock throughout
2782          * the reconfiguration process. */
2783         spin_lock_irqsave(&wl->irq_lock, flags);
2784         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2785                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2786                 goto out_unlock_mutex;
2787         }
2788         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2789
2790         if (changed & BSS_CHANGED_BSSID) {
2791                 b43legacy_synchronize_irq(dev);
2792
2793                 if (conf->bssid)
2794                         memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2795                 else
2796                         memset(wl->bssid, 0, ETH_ALEN);
2797         }
2798
2799         if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2800                 if (changed & BSS_CHANGED_BEACON &&
2801                     (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2802                      b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2803                         b43legacy_update_templates(wl);
2804
2805                 if (changed & BSS_CHANGED_BSSID)
2806                         b43legacy_write_mac_bssid_templates(dev);
2807         }
2808         spin_unlock_irqrestore(&wl->irq_lock, flags);
2809
2810         b43legacy_mac_suspend(dev);
2811
2812         if (changed & BSS_CHANGED_BEACON_INT &&
2813             (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2814              b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2815                 b43legacy_set_beacon_int(dev, conf->beacon_int);
2816
2817         if (changed & BSS_CHANGED_BASIC_RATES)
2818                 b43legacy_update_basic_rates(dev, conf->basic_rates);
2819
2820         if (changed & BSS_CHANGED_ERP_SLOT) {
2821                 if (conf->use_short_slot)
2822                         b43legacy_short_slot_timing_enable(dev);
2823                 else
2824                         b43legacy_short_slot_timing_disable(dev);
2825         }
2826
2827         b43legacy_mac_enable(dev);
2828
2829         spin_lock_irqsave(&wl->irq_lock, flags);
2830         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2831         /* XXX: why? */
2832         mmiowb();
2833         spin_unlock_irqrestore(&wl->irq_lock, flags);
2834  out_unlock_mutex:
2835         mutex_unlock(&wl->mutex);
2836 }
2837
2838 static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2839                                           unsigned int changed,
2840                                           unsigned int *fflags,u64 multicast)
2841 {
2842         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2843         struct b43legacy_wldev *dev = wl->current_dev;
2844         unsigned long flags;
2845
2846         if (!dev) {
2847                 *fflags = 0;
2848                 return;
2849         }
2850
2851         spin_lock_irqsave(&wl->irq_lock, flags);
2852         *fflags &= FIF_PROMISC_IN_BSS |
2853                   FIF_ALLMULTI |
2854                   FIF_FCSFAIL |
2855                   FIF_PLCPFAIL |
2856                   FIF_CONTROL |
2857                   FIF_OTHER_BSS |
2858                   FIF_BCN_PRBRESP_PROMISC;
2859
2860         changed &= FIF_PROMISC_IN_BSS |
2861                    FIF_ALLMULTI |
2862                    FIF_FCSFAIL |
2863                    FIF_PLCPFAIL |
2864                    FIF_CONTROL |
2865                    FIF_OTHER_BSS |
2866                    FIF_BCN_PRBRESP_PROMISC;
2867
2868         wl->filter_flags = *fflags;
2869
2870         if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2871                 b43legacy_adjust_opmode(dev);
2872         spin_unlock_irqrestore(&wl->irq_lock, flags);
2873 }
2874
2875 /* Locking: wl->mutex */
2876 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2877 {
2878         struct b43legacy_wl *wl = dev->wl;
2879         unsigned long flags;
2880
2881         if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2882                 return;
2883
2884         /* Disable and sync interrupts. We must do this before than
2885          * setting the status to INITIALIZED, as the interrupt handler
2886          * won't care about IRQs then. */
2887         spin_lock_irqsave(&wl->irq_lock, flags);
2888         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2889         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2890         spin_unlock_irqrestore(&wl->irq_lock, flags);
2891         b43legacy_synchronize_irq(dev);
2892
2893         b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2894
2895         mutex_unlock(&wl->mutex);
2896         /* Must unlock as it would otherwise deadlock. No races here.
2897          * Cancel the possibly running self-rearming periodic work. */
2898         cancel_delayed_work_sync(&dev->periodic_work);
2899         mutex_lock(&wl->mutex);
2900
2901         ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
2902
2903         b43legacy_mac_suspend(dev);
2904         free_irq(dev->dev->irq, dev);
2905         b43legacydbg(wl, "Wireless interface stopped\n");
2906 }
2907
2908 /* Locking: wl->mutex */
2909 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2910 {
2911         int err;
2912
2913         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2914
2915         drain_txstatus_queue(dev);
2916         err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2917                           IRQF_SHARED, KBUILD_MODNAME, dev);
2918         if (err) {
2919                 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2920                        dev->dev->irq);
2921                 goto out;
2922         }
2923         /* We are ready to run. */
2924         ieee80211_wake_queues(dev->wl->hw);
2925         b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2926
2927         /* Start data flow (TX/RX) */
2928         b43legacy_mac_enable(dev);
2929         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2930
2931         /* Start maintenance work */
2932         b43legacy_periodic_tasks_setup(dev);
2933
2934         b43legacydbg(dev->wl, "Wireless interface started\n");
2935 out:
2936         return err;
2937 }
2938
2939 /* Get PHY and RADIO versioning numbers */
2940 static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2941 {
2942         struct b43legacy_phy *phy = &dev->phy;
2943         u32 tmp;
2944         u8 analog_type;
2945         u8 phy_type;
2946         u8 phy_rev;
2947         u16 radio_manuf;
2948         u16 radio_ver;
2949         u16 radio_rev;
2950         int unsupported = 0;
2951
2952         /* Get PHY versioning */
2953         tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
2954         analog_type = (tmp & B43legacy_PHYVER_ANALOG)
2955                       >> B43legacy_PHYVER_ANALOG_SHIFT;
2956         phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
2957         phy_rev = (tmp & B43legacy_PHYVER_VERSION);
2958         switch (phy_type) {
2959         case B43legacy_PHYTYPE_B:
2960                 if (phy_rev != 2 && phy_rev != 4
2961                     && phy_rev != 6 && phy_rev != 7)
2962                         unsupported = 1;
2963                 break;
2964         case B43legacy_PHYTYPE_G:
2965                 if (phy_rev > 8)
2966                         unsupported = 1;
2967                 break;
2968         default:
2969                 unsupported = 1;
2970         }
2971         if (unsupported) {
2972                 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
2973                        "(Analog %u, Type %u, Revision %u)\n",
2974                        analog_type, phy_type, phy_rev);
2975                 return -EOPNOTSUPP;
2976         }
2977         b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
2978                analog_type, phy_type, phy_rev);
2979
2980
2981         /* Get RADIO versioning */
2982         if (dev->dev->bus->chip_id == 0x4317) {
2983                 if (dev->dev->bus->chip_rev == 0)
2984                         tmp = 0x3205017F;
2985                 else if (dev->dev->bus->chip_rev == 1)
2986                         tmp = 0x4205017F;
2987                 else
2988                         tmp = 0x5205017F;
2989         } else {
2990                 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2991                                   B43legacy_RADIOCTL_ID);
2992                 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
2993                 tmp <<= 16;
2994            &nbs