b43legacy: Fix error due to MMIO access with SSB unpowered
[pandora-kernel.git] / drivers / net / wireless / b43legacy / main.c
1 /*
2  *
3  *  Broadcom B43legacy wireless driver
4  *
5  *  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6  *  Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
7  *  Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
8  *  Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9  *  Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10  *  Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
11  *
12  *  Some parts of the code in this file are derived from the ipw2200
13  *  driver  Copyright(c) 2003 - 2004 Intel Corporation.
14
15  *  This program is free software; you can redistribute it and/or modify
16  *  it under the terms of the GNU General Public License as published by
17  *  the Free Software Foundation; either version 2 of the License, or
18  *  (at your option) any later version.
19  *
20  *  This program is distributed in the hope that it will be useful,
21  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
22  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  *  GNU General Public License for more details.
24  *
25  *  You should have received a copy of the GNU General Public License
26  *  along with this program; see the file COPYING.  If not, write to
27  *  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28  *  Boston, MA 02110-1301, USA.
29  *
30  */
31
32 #include <linux/delay.h>
33 #include <linux/init.h>
34 #include <linux/module.h>
35 #include <linux/if_arp.h>
36 #include <linux/etherdevice.h>
37 #include <linux/firmware.h>
38 #include <linux/workqueue.h>
39 #include <linux/sched.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/slab.h>
43 #include <net/dst.h>
44 #include <asm/unaligned.h>
45
46 #include "b43legacy.h"
47 #include "main.h"
48 #include "debugfs.h"
49 #include "phy.h"
50 #include "dma.h"
51 #include "pio.h"
52 #include "sysfs.h"
53 #include "xmit.h"
54 #include "radio.h"
55
56
57 MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62
63 MODULE_FIRMWARE("b43legacy/ucode2.fw");
64 MODULE_FIRMWARE("b43legacy/ucode4.fw");
65
66 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
67 static int modparam_pio;
68 module_param_named(pio, modparam_pio, int, 0444);
69 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
70 #elif defined(CONFIG_B43LEGACY_DMA)
71 # define modparam_pio   0
72 #elif defined(CONFIG_B43LEGACY_PIO)
73 # define modparam_pio   1
74 #endif
75
76 static int modparam_bad_frames_preempt;
77 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
78 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
79                  " Preemption");
80
81 static char modparam_fwpostfix[16];
82 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
83 MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
84
85 /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
86 static const struct ssb_device_id b43legacy_ssb_tbl[] = {
87         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
88         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
89         SSB_DEVTABLE_END
90 };
91 MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
92
93
94 /* Channel and ratetables are shared for all devices.
95  * They can't be const, because ieee80211 puts some precalculated
96  * data in there. This data is the same for all devices, so we don't
97  * get concurrency issues */
98 #define RATETAB_ENT(_rateid, _flags) \
99         {                                                               \
100                 .bitrate        = B43legacy_RATE_TO_100KBPS(_rateid),   \
101                 .hw_value       = (_rateid),                            \
102                 .flags          = (_flags),                             \
103         }
104 /*
105  * NOTE: When changing this, sync with xmit.c's
106  *       b43legacy_plcp_get_bitrate_idx_* functions!
107  */
108 static struct ieee80211_rate __b43legacy_ratetable[] = {
109         RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
110         RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
111         RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
112         RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
113         RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
114         RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
115         RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
116         RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
117         RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
118         RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
119         RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
120         RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
121 };
122 #define b43legacy_b_ratetable           (__b43legacy_ratetable + 0)
123 #define b43legacy_b_ratetable_size      4
124 #define b43legacy_g_ratetable           (__b43legacy_ratetable + 0)
125 #define b43legacy_g_ratetable_size      12
126
127 #define CHANTAB_ENT(_chanid, _freq) \
128         {                                                       \
129                 .center_freq    = (_freq),                      \
130                 .hw_value       = (_chanid),                    \
131         }
132 static struct ieee80211_channel b43legacy_bg_chantable[] = {
133         CHANTAB_ENT(1, 2412),
134         CHANTAB_ENT(2, 2417),
135         CHANTAB_ENT(3, 2422),
136         CHANTAB_ENT(4, 2427),
137         CHANTAB_ENT(5, 2432),
138         CHANTAB_ENT(6, 2437),
139         CHANTAB_ENT(7, 2442),
140         CHANTAB_ENT(8, 2447),
141         CHANTAB_ENT(9, 2452),
142         CHANTAB_ENT(10, 2457),
143         CHANTAB_ENT(11, 2462),
144         CHANTAB_ENT(12, 2467),
145         CHANTAB_ENT(13, 2472),
146         CHANTAB_ENT(14, 2484),
147 };
148
149 static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
150         .channels = b43legacy_bg_chantable,
151         .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
152         .bitrates = b43legacy_b_ratetable,
153         .n_bitrates = b43legacy_b_ratetable_size,
154 };
155
156 static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
157         .channels = b43legacy_bg_chantable,
158         .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
159         .bitrates = b43legacy_g_ratetable,
160         .n_bitrates = b43legacy_g_ratetable_size,
161 };
162
163 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
164 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
165 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
166 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
167
168
169 static int b43legacy_ratelimit(struct b43legacy_wl *wl)
170 {
171         if (!wl || !wl->current_dev)
172                 return 1;
173         if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
174                 return 1;
175         /* We are up and running.
176          * Ratelimit the messages to avoid DoS over the net. */
177         return net_ratelimit();
178 }
179
180 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
181 {
182         struct va_format vaf;
183         va_list args;
184
185         if (!b43legacy_ratelimit(wl))
186                 return;
187
188         va_start(args, fmt);
189
190         vaf.fmt = fmt;
191         vaf.va = &args;
192
193         printk(KERN_INFO "b43legacy-%s: %pV",
194                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
195
196         va_end(args);
197 }
198
199 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
200 {
201         struct va_format vaf;
202         va_list args;
203
204         if (!b43legacy_ratelimit(wl))
205                 return;
206
207         va_start(args, fmt);
208
209         vaf.fmt = fmt;
210         vaf.va = &args;
211
212         printk(KERN_ERR "b43legacy-%s ERROR: %pV",
213                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
214
215         va_end(args);
216 }
217
218 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
219 {
220         struct va_format vaf;
221         va_list args;
222
223         if (!b43legacy_ratelimit(wl))
224                 return;
225
226         va_start(args, fmt);
227
228         vaf.fmt = fmt;
229         vaf.va = &args;
230
231         printk(KERN_WARNING "b43legacy-%s warning: %pV",
232                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
233
234         va_end(args);
235 }
236
237 #if B43legacy_DEBUG
238 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
239 {
240         struct va_format vaf;
241         va_list args;
242
243         va_start(args, fmt);
244
245         vaf.fmt = fmt;
246         vaf.va = &args;
247
248         printk(KERN_DEBUG "b43legacy-%s debug: %pV",
249                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
250
251         va_end(args);
252 }
253 #endif /* DEBUG */
254
255 static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
256                                 u32 val)
257 {
258         u32 status;
259
260         B43legacy_WARN_ON(offset % 4 != 0);
261
262         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
263         if (status & B43legacy_MACCTL_BE)
264                 val = swab32(val);
265
266         b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
267         mmiowb();
268         b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
269 }
270
271 static inline
272 void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
273                                 u16 routing, u16 offset)
274 {
275         u32 control;
276
277         /* "offset" is the WORD offset. */
278
279         control = routing;
280         control <<= 16;
281         control |= offset;
282         b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
283 }
284
285 u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
286                        u16 routing, u16 offset)
287 {
288         u32 ret;
289
290         if (routing == B43legacy_SHM_SHARED) {
291                 B43legacy_WARN_ON((offset & 0x0001) != 0);
292                 if (offset & 0x0003) {
293                         /* Unaligned access */
294                         b43legacy_shm_control_word(dev, routing, offset >> 2);
295                         ret = b43legacy_read16(dev,
296                                 B43legacy_MMIO_SHM_DATA_UNALIGNED);
297                         ret <<= 16;
298                         b43legacy_shm_control_word(dev, routing,
299                                                      (offset >> 2) + 1);
300                         ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
301
302                         return ret;
303                 }
304                 offset >>= 2;
305         }
306         b43legacy_shm_control_word(dev, routing, offset);
307         ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
308
309         return ret;
310 }
311
312 u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
313                            u16 routing, u16 offset)
314 {
315         u16 ret;
316
317         if (routing == B43legacy_SHM_SHARED) {
318                 B43legacy_WARN_ON((offset & 0x0001) != 0);
319                 if (offset & 0x0003) {
320                         /* Unaligned access */
321                         b43legacy_shm_control_word(dev, routing, offset >> 2);
322                         ret = b43legacy_read16(dev,
323                                              B43legacy_MMIO_SHM_DATA_UNALIGNED);
324
325                         return ret;
326                 }
327                 offset >>= 2;
328         }
329         b43legacy_shm_control_word(dev, routing, offset);
330         ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
331
332         return ret;
333 }
334
335 void b43legacy_shm_write32(struct b43legacy_wldev *dev,
336                            u16 routing, u16 offset,
337                            u32 value)
338 {
339         if (routing == B43legacy_SHM_SHARED) {
340                 B43legacy_WARN_ON((offset & 0x0001) != 0);
341                 if (offset & 0x0003) {
342                         /* Unaligned access */
343                         b43legacy_shm_control_word(dev, routing, offset >> 2);
344                         mmiowb();
345                         b43legacy_write16(dev,
346                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
347                                           (value >> 16) & 0xffff);
348                         mmiowb();
349                         b43legacy_shm_control_word(dev, routing,
350                                                    (offset >> 2) + 1);
351                         mmiowb();
352                         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
353                                           value & 0xffff);
354                         return;
355                 }
356                 offset >>= 2;
357         }
358         b43legacy_shm_control_word(dev, routing, offset);
359         mmiowb();
360         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
361 }
362
363 void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
364                            u16 value)
365 {
366         if (routing == B43legacy_SHM_SHARED) {
367                 B43legacy_WARN_ON((offset & 0x0001) != 0);
368                 if (offset & 0x0003) {
369                         /* Unaligned access */
370                         b43legacy_shm_control_word(dev, routing, offset >> 2);
371                         mmiowb();
372                         b43legacy_write16(dev,
373                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
374                                           value);
375                         return;
376                 }
377                 offset >>= 2;
378         }
379         b43legacy_shm_control_word(dev, routing, offset);
380         mmiowb();
381         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
382 }
383
384 /* Read HostFlags */
385 u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
386 {
387         u32 ret;
388
389         ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
390                                    B43legacy_SHM_SH_HOSTFHI);
391         ret <<= 16;
392         ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
393                                     B43legacy_SHM_SH_HOSTFLO);
394
395         return ret;
396 }
397
398 /* Write HostFlags */
399 void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
400 {
401         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
402                               B43legacy_SHM_SH_HOSTFLO,
403                               (value & 0x0000FFFF));
404         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
405                               B43legacy_SHM_SH_HOSTFHI,
406                               ((value & 0xFFFF0000) >> 16));
407 }
408
409 void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
410 {
411         /* We need to be careful. As we read the TSF from multiple
412          * registers, we should take care of register overflows.
413          * In theory, the whole tsf read process should be atomic.
414          * We try to be atomic here, by restaring the read process,
415          * if any of the high registers changed (overflew).
416          */
417         if (dev->dev->id.revision >= 3) {
418                 u32 low;
419                 u32 high;
420                 u32 high2;
421
422                 do {
423                         high = b43legacy_read32(dev,
424                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
425                         low = b43legacy_read32(dev,
426                                         B43legacy_MMIO_REV3PLUS_TSF_LOW);
427                         high2 = b43legacy_read32(dev,
428                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
429                 } while (unlikely(high != high2));
430
431                 *tsf = high;
432                 *tsf <<= 32;
433                 *tsf |= low;
434         } else {
435                 u64 tmp;
436                 u16 v0;
437                 u16 v1;
438                 u16 v2;
439                 u16 v3;
440                 u16 test1;
441                 u16 test2;
442                 u16 test3;
443
444                 do {
445                         v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
446                         v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
447                         v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
448                         v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
449
450                         test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
451                         test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
452                         test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
453                 } while (v3 != test3 || v2 != test2 || v1 != test1);
454
455                 *tsf = v3;
456                 *tsf <<= 48;
457                 tmp = v2;
458                 tmp <<= 32;
459                 *tsf |= tmp;
460                 tmp = v1;
461                 tmp <<= 16;
462                 *tsf |= tmp;
463                 *tsf |= v0;
464         }
465 }
466
467 static void b43legacy_time_lock(struct b43legacy_wldev *dev)
468 {
469         u32 status;
470
471         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
472         status |= B43legacy_MACCTL_TBTTHOLD;
473         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
474         mmiowb();
475 }
476
477 static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
478 {
479         u32 status;
480
481         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
482         status &= ~B43legacy_MACCTL_TBTTHOLD;
483         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
484 }
485
486 static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
487 {
488         /* Be careful with the in-progress timer.
489          * First zero out the low register, so we have a full
490          * register-overflow duration to complete the operation.
491          */
492         if (dev->dev->id.revision >= 3) {
493                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
494                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
495
496                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
497                 mmiowb();
498                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
499                                     hi);
500                 mmiowb();
501                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
502                                     lo);
503         } else {
504                 u16 v0 = (tsf & 0x000000000000FFFFULL);
505                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
506                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
507                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
508
509                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
510                 mmiowb();
511                 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
512                 mmiowb();
513                 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
514                 mmiowb();
515                 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
516                 mmiowb();
517                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
518         }
519 }
520
521 void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
522 {
523         b43legacy_time_lock(dev);
524         b43legacy_tsf_write_locked(dev, tsf);
525         b43legacy_time_unlock(dev);
526 }
527
528 static
529 void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
530                              u16 offset, const u8 *mac)
531 {
532         static const u8 zero_addr[ETH_ALEN] = { 0 };
533         u16 data;
534
535         if (!mac)
536                 mac = zero_addr;
537
538         offset |= 0x0020;
539         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
540
541         data = mac[0];
542         data |= mac[1] << 8;
543         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
544         data = mac[2];
545         data |= mac[3] << 8;
546         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
547         data = mac[4];
548         data |= mac[5] << 8;
549         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
550 }
551
552 static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
553 {
554         static const u8 zero_addr[ETH_ALEN] = { 0 };
555         const u8 *mac = dev->wl->mac_addr;
556         const u8 *bssid = dev->wl->bssid;
557         u8 mac_bssid[ETH_ALEN * 2];
558         int i;
559         u32 tmp;
560
561         if (!bssid)
562                 bssid = zero_addr;
563         if (!mac)
564                 mac = zero_addr;
565
566         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
567
568         memcpy(mac_bssid, mac, ETH_ALEN);
569         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
570
571         /* Write our MAC address and BSSID to template ram */
572         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
573                 tmp =  (u32)(mac_bssid[i + 0]);
574                 tmp |= (u32)(mac_bssid[i + 1]) << 8;
575                 tmp |= (u32)(mac_bssid[i + 2]) << 16;
576                 tmp |= (u32)(mac_bssid[i + 3]) << 24;
577                 b43legacy_ram_write(dev, 0x20 + i, tmp);
578                 b43legacy_ram_write(dev, 0x78 + i, tmp);
579                 b43legacy_ram_write(dev, 0x478 + i, tmp);
580         }
581 }
582
583 static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
584 {
585         b43legacy_write_mac_bssid_templates(dev);
586         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
587                                 dev->wl->mac_addr);
588 }
589
590 static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
591                                     u16 slot_time)
592 {
593         /* slot_time is in usec. */
594         if (dev->phy.type != B43legacy_PHYTYPE_G)
595                 return;
596         b43legacy_write16(dev, 0x684, 510 + slot_time);
597         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
598                               slot_time);
599 }
600
601 static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
602 {
603         b43legacy_set_slot_time(dev, 9);
604 }
605
606 static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
607 {
608         b43legacy_set_slot_time(dev, 20);
609 }
610
611 /* Synchronize IRQ top- and bottom-half.
612  * IRQs must be masked before calling this.
613  * This must not be called with the irq_lock held.
614  */
615 static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
616 {
617         synchronize_irq(dev->dev->irq);
618         tasklet_kill(&dev->isr_tasklet);
619 }
620
621 /* DummyTransmission function, as documented on
622  * http://bcm-specs.sipsolutions.net/DummyTransmission
623  */
624 void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
625 {
626         struct b43legacy_phy *phy = &dev->phy;
627         unsigned int i;
628         unsigned int max_loop;
629         u16 value;
630         u32 buffer[5] = {
631                 0x00000000,
632                 0x00D40000,
633                 0x00000000,
634                 0x01000000,
635                 0x00000000,
636         };
637
638         switch (phy->type) {
639         case B43legacy_PHYTYPE_B:
640         case B43legacy_PHYTYPE_G:
641                 max_loop = 0xFA;
642                 buffer[0] = 0x000B846E;
643                 break;
644         default:
645                 B43legacy_BUG_ON(1);
646                 return;
647         }
648
649         for (i = 0; i < 5; i++)
650                 b43legacy_ram_write(dev, i * 4, buffer[i]);
651
652         /* dummy read follows */
653         b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
654
655         b43legacy_write16(dev, 0x0568, 0x0000);
656         b43legacy_write16(dev, 0x07C0, 0x0000);
657         b43legacy_write16(dev, 0x050C, 0x0000);
658         b43legacy_write16(dev, 0x0508, 0x0000);
659         b43legacy_write16(dev, 0x050A, 0x0000);
660         b43legacy_write16(dev, 0x054C, 0x0000);
661         b43legacy_write16(dev, 0x056A, 0x0014);
662         b43legacy_write16(dev, 0x0568, 0x0826);
663         b43legacy_write16(dev, 0x0500, 0x0000);
664         b43legacy_write16(dev, 0x0502, 0x0030);
665
666         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
667                 b43legacy_radio_write16(dev, 0x0051, 0x0017);
668         for (i = 0x00; i < max_loop; i++) {
669                 value = b43legacy_read16(dev, 0x050E);
670                 if (value & 0x0080)
671                         break;
672                 udelay(10);
673         }
674         for (i = 0x00; i < 0x0A; i++) {
675                 value = b43legacy_read16(dev, 0x050E);
676                 if (value & 0x0400)
677                         break;
678                 udelay(10);
679         }
680         for (i = 0x00; i < 0x0A; i++) {
681                 value = b43legacy_read16(dev, 0x0690);
682                 if (!(value & 0x0100))
683                         break;
684                 udelay(10);
685         }
686         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
687                 b43legacy_radio_write16(dev, 0x0051, 0x0037);
688 }
689
690 /* Turn the Analog ON/OFF */
691 static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
692 {
693         b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
694 }
695
696 void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
697 {
698         u32 tmslow;
699         u32 macctl;
700
701         flags |= B43legacy_TMSLOW_PHYCLKEN;
702         flags |= B43legacy_TMSLOW_PHYRESET;
703         ssb_device_enable(dev->dev, flags);
704         msleep(2); /* Wait for the PLL to turn on. */
705
706         /* Now take the PHY out of Reset again */
707         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
708         tmslow |= SSB_TMSLOW_FGC;
709         tmslow &= ~B43legacy_TMSLOW_PHYRESET;
710         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
711         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
712         msleep(1);
713         tmslow &= ~SSB_TMSLOW_FGC;
714         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
715         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
716         msleep(1);
717
718         /* Turn Analog ON */
719         b43legacy_switch_analog(dev, 1);
720
721         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
722         macctl &= ~B43legacy_MACCTL_GMODE;
723         if (flags & B43legacy_TMSLOW_GMODE) {
724                 macctl |= B43legacy_MACCTL_GMODE;
725                 dev->phy.gmode = true;
726         } else
727                 dev->phy.gmode = false;
728         macctl |= B43legacy_MACCTL_IHR_ENABLED;
729         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
730 }
731
732 static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
733 {
734         u32 v0;
735         u32 v1;
736         u16 tmp;
737         struct b43legacy_txstatus stat;
738
739         while (1) {
740                 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
741                 if (!(v0 & 0x00000001))
742                         break;
743                 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
744
745                 stat.cookie = (v0 >> 16);
746                 stat.seq = (v1 & 0x0000FFFF);
747                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
748                 tmp = (v0 & 0x0000FFFF);
749                 stat.frame_count = ((tmp & 0xF000) >> 12);
750                 stat.rts_count = ((tmp & 0x0F00) >> 8);
751                 stat.supp_reason = ((tmp & 0x001C) >> 2);
752                 stat.pm_indicated = !!(tmp & 0x0080);
753                 stat.intermediate = !!(tmp & 0x0040);
754                 stat.for_ampdu = !!(tmp & 0x0020);
755                 stat.acked = !!(tmp & 0x0002);
756
757                 b43legacy_handle_txstatus(dev, &stat);
758         }
759 }
760
761 static void drain_txstatus_queue(struct b43legacy_wldev *dev)
762 {
763         u32 dummy;
764
765         if (dev->dev->id.revision < 5)
766                 return;
767         /* Read all entries from the microcode TXstatus FIFO
768          * and throw them away.
769          */
770         while (1) {
771                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
772                 if (!(dummy & 0x00000001))
773                         break;
774                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
775         }
776 }
777
778 static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
779 {
780         u32 val = 0;
781
782         val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
783         val <<= 16;
784         val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
785
786         return val;
787 }
788
789 static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
790 {
791         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
792                               (jssi & 0x0000FFFF));
793         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
794                               (jssi & 0xFFFF0000) >> 16);
795 }
796
797 static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
798 {
799         b43legacy_jssi_write(dev, 0x7F7F7F7F);
800         b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
801                           b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
802                           | B43legacy_MACCMD_BGNOISE);
803         B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
804                             dev->phy.channel);
805 }
806
807 static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
808 {
809         /* Top half of Link Quality calculation. */
810
811         if (dev->noisecalc.calculation_running)
812                 return;
813         dev->noisecalc.channel_at_start = dev->phy.channel;
814         dev->noisecalc.calculation_running = true;
815         dev->noisecalc.nr_samples = 0;
816
817         b43legacy_generate_noise_sample(dev);
818 }
819
820 static void handle_irq_noise(struct b43legacy_wldev *dev)
821 {
822         struct b43legacy_phy *phy = &dev->phy;
823         u16 tmp;
824         u8 noise[4];
825         u8 i;
826         u8 j;
827         s32 average;
828
829         /* Bottom half of Link Quality calculation. */
830
831         B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
832         if (dev->noisecalc.channel_at_start != phy->channel)
833                 goto drop_calculation;
834         *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
835         if (noise[0] == 0x7F || noise[1] == 0x7F ||
836             noise[2] == 0x7F || noise[3] == 0x7F)
837                 goto generate_new;
838
839         /* Get the noise samples. */
840         B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
841         i = dev->noisecalc.nr_samples;
842         noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
843         noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
844         noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
845         noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
846         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
847         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
848         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
849         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
850         dev->noisecalc.nr_samples++;
851         if (dev->noisecalc.nr_samples == 8) {
852                 /* Calculate the Link Quality by the noise samples. */
853                 average = 0;
854                 for (i = 0; i < 8; i++) {
855                         for (j = 0; j < 4; j++)
856                                 average += dev->noisecalc.samples[i][j];
857                 }
858                 average /= (8 * 4);
859                 average *= 125;
860                 average += 64;
861                 average /= 128;
862                 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
863                                              0x40C);
864                 tmp = (tmp / 128) & 0x1F;
865                 if (tmp >= 8)
866                         average += 2;
867                 else
868                         average -= 25;
869                 if (tmp == 8)
870                         average -= 72;
871                 else
872                         average -= 48;
873
874                 dev->stats.link_noise = average;
875 drop_calculation:
876                 dev->noisecalc.calculation_running = false;
877                 return;
878         }
879 generate_new:
880         b43legacy_generate_noise_sample(dev);
881 }
882
883 static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
884 {
885         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
886                 /* TODO: PS TBTT */
887         } else {
888                 if (1/*FIXME: the last PSpoll frame was sent successfully */)
889                         b43legacy_power_saving_ctl_bits(dev, -1, -1);
890         }
891         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
892                 dev->dfq_valid = true;
893 }
894
895 static void handle_irq_atim_end(struct b43legacy_wldev *dev)
896 {
897         if (dev->dfq_valid) {
898                 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
899                                   b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
900                                   | B43legacy_MACCMD_DFQ_VALID);
901                 dev->dfq_valid = false;
902         }
903 }
904
905 static void handle_irq_pmq(struct b43legacy_wldev *dev)
906 {
907         u32 tmp;
908
909         /* TODO: AP mode. */
910
911         while (1) {
912                 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
913                 if (!(tmp & 0x00000008))
914                         break;
915         }
916         /* 16bit write is odd, but correct. */
917         b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
918 }
919
920 static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
921                                             const u8 *data, u16 size,
922                                             u16 ram_offset,
923                                             u16 shm_size_offset, u8 rate)
924 {
925         u32 i;
926         u32 tmp;
927         struct b43legacy_plcp_hdr4 plcp;
928
929         plcp.data = 0;
930         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
931         b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
932         ram_offset += sizeof(u32);
933         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
934          * So leave the first two bytes of the next write blank.
935          */
936         tmp = (u32)(data[0]) << 16;
937         tmp |= (u32)(data[1]) << 24;
938         b43legacy_ram_write(dev, ram_offset, tmp);
939         ram_offset += sizeof(u32);
940         for (i = 2; i < size; i += sizeof(u32)) {
941                 tmp = (u32)(data[i + 0]);
942                 if (i + 1 < size)
943                         tmp |= (u32)(data[i + 1]) << 8;
944                 if (i + 2 < size)
945                         tmp |= (u32)(data[i + 2]) << 16;
946                 if (i + 3 < size)
947                         tmp |= (u32)(data[i + 3]) << 24;
948                 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
949         }
950         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
951                               size + sizeof(struct b43legacy_plcp_hdr6));
952 }
953
954 /* Convert a b43legacy antenna number value to the PHY TX control value. */
955 static u16 b43legacy_antenna_to_phyctl(int antenna)
956 {
957         switch (antenna) {
958         case B43legacy_ANTENNA0:
959                 return B43legacy_TX4_PHY_ANT0;
960         case B43legacy_ANTENNA1:
961                 return B43legacy_TX4_PHY_ANT1;
962         }
963         return B43legacy_TX4_PHY_ANTLAST;
964 }
965
966 static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
967                                             u16 ram_offset,
968                                             u16 shm_size_offset)
969 {
970
971         unsigned int i, len, variable_len;
972         const struct ieee80211_mgmt *bcn;
973         const u8 *ie;
974         bool tim_found = false;
975         unsigned int rate;
976         u16 ctl;
977         int antenna;
978         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
979
980         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
981         len = min((size_t)dev->wl->current_beacon->len,
982                   0x200 - sizeof(struct b43legacy_plcp_hdr6));
983         rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
984
985         b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
986                                         shm_size_offset, rate);
987
988         /* Write the PHY TX control parameters. */
989         antenna = B43legacy_ANTENNA_DEFAULT;
990         antenna = b43legacy_antenna_to_phyctl(antenna);
991         ctl = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
992                                    B43legacy_SHM_SH_BEACPHYCTL);
993         /* We can't send beacons with short preamble. Would get PHY errors. */
994         ctl &= ~B43legacy_TX4_PHY_SHORTPRMBL;
995         ctl &= ~B43legacy_TX4_PHY_ANT;
996         ctl &= ~B43legacy_TX4_PHY_ENC;
997         ctl |= antenna;
998         ctl |= B43legacy_TX4_PHY_ENC_CCK;
999         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1000                               B43legacy_SHM_SH_BEACPHYCTL, ctl);
1001
1002         /* Find the position of the TIM and the DTIM_period value
1003          * and write them to SHM. */
1004         ie = bcn->u.beacon.variable;
1005         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1006         for (i = 0; i < variable_len - 2; ) {
1007                 uint8_t ie_id, ie_len;
1008
1009                 ie_id = ie[i];
1010                 ie_len = ie[i + 1];
1011                 if (ie_id == 5) {
1012                         u16 tim_position;
1013                         u16 dtim_period;
1014                         /* This is the TIM Information Element */
1015
1016                         /* Check whether the ie_len is in the beacon data range. */
1017                         if (variable_len < ie_len + 2 + i)
1018                                 break;
1019                         /* A valid TIM is at least 4 bytes long. */
1020                         if (ie_len < 4)
1021                                 break;
1022                         tim_found = true;
1023
1024                         tim_position = sizeof(struct b43legacy_plcp_hdr6);
1025                         tim_position += offsetof(struct ieee80211_mgmt,
1026                                                  u.beacon.variable);
1027                         tim_position += i;
1028
1029                         dtim_period = ie[i + 3];
1030
1031                         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1032                                         B43legacy_SHM_SH_TIMPOS, tim_position);
1033                         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1034                                         B43legacy_SHM_SH_DTIMP, dtim_period);
1035                         break;
1036                 }
1037                 i += ie_len + 2;
1038         }
1039         if (!tim_found) {
1040                 b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
1041                               "beacon template packet. AP or IBSS operation "
1042                               "may be broken.\n");
1043         } else
1044                 b43legacydbg(dev->wl, "Updated beacon template\n");
1045 }
1046
1047 static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
1048                                             u16 shm_offset, u16 size,
1049                                             struct ieee80211_rate *rate)
1050 {
1051         struct b43legacy_plcp_hdr4 plcp;
1052         u32 tmp;
1053         __le16 dur;
1054
1055         plcp.data = 0;
1056         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1057         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1058                                                dev->wl->vif,
1059                                                IEEE80211_BAND_2GHZ,
1060                                                size,
1061                                                rate);
1062         /* Write PLCP in two parts and timing for packet transfer */
1063         tmp = le32_to_cpu(plcp.data);
1064         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
1065                               tmp & 0xFFFF);
1066         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
1067                               tmp >> 16);
1068         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
1069                               le16_to_cpu(dur));
1070 }
1071
1072 /* Instead of using custom probe response template, this function
1073  * just patches custom beacon template by:
1074  * 1) Changing packet type
1075  * 2) Patching duration field
1076  * 3) Stripping TIM
1077  */
1078 static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
1079                                                u16 *dest_size,
1080                                                struct ieee80211_rate *rate)
1081 {
1082         const u8 *src_data;
1083         u8 *dest_data;
1084         u16 src_size, elem_size, src_pos, dest_pos;
1085         __le16 dur;
1086         struct ieee80211_hdr *hdr;
1087         size_t ie_start;
1088
1089         src_size = dev->wl->current_beacon->len;
1090         src_data = (const u8 *)dev->wl->current_beacon->data;
1091
1092         /* Get the start offset of the variable IEs in the packet. */
1093         ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1094         B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
1095                                                u.beacon.variable));
1096
1097         if (B43legacy_WARN_ON(src_size < ie_start))
1098                 return NULL;
1099
1100         dest_data = kmalloc(src_size, GFP_ATOMIC);
1101         if (unlikely(!dest_data))
1102                 return NULL;
1103
1104         /* Copy the static data and all Information Elements, except the TIM. */
1105         memcpy(dest_data, src_data, ie_start);
1106         src_pos = ie_start;
1107         dest_pos = ie_start;
1108         for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1109                 elem_size = src_data[src_pos + 1] + 2;
1110                 if (src_data[src_pos] == 5) {
1111                         /* This is the TIM. */
1112                         continue;
1113                 }
1114                 memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
1115                 dest_pos += elem_size;
1116         }
1117         *dest_size = dest_pos;
1118         hdr = (struct ieee80211_hdr *)dest_data;
1119
1120         /* Set the frame control. */
1121         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1122                                          IEEE80211_STYPE_PROBE_RESP);
1123         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1124                                                dev->wl->vif,
1125                                                IEEE80211_BAND_2GHZ,
1126                                                *dest_size,
1127                                                rate);
1128         hdr->duration_id = dur;
1129
1130         return dest_data;
1131 }
1132
1133 static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1134                                                 u16 ram_offset,
1135                                                 u16 shm_size_offset,
1136                                                 struct ieee80211_rate *rate)
1137 {
1138         const u8 *probe_resp_data;
1139         u16 size;
1140
1141         size = dev->wl->current_beacon->len;
1142         probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1143         if (unlikely(!probe_resp_data))
1144                 return;
1145
1146         /* Looks like PLCP headers plus packet timings are stored for
1147          * all possible basic rates
1148          */
1149         b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
1150                                         &b43legacy_b_ratetable[0]);
1151         b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
1152                                         &b43legacy_b_ratetable[1]);
1153         b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
1154                                         &b43legacy_b_ratetable[2]);
1155         b43legacy_write_probe_resp_plcp(dev, 0x350, size,
1156                                         &b43legacy_b_ratetable[3]);
1157
1158         size = min((size_t)size,
1159                    0x200 - sizeof(struct b43legacy_plcp_hdr6));
1160         b43legacy_write_template_common(dev, probe_resp_data,
1161                                         size, ram_offset,
1162                                         shm_size_offset, rate->hw_value);
1163         kfree(probe_resp_data);
1164 }
1165
1166 static void b43legacy_upload_beacon0(struct b43legacy_wldev *dev)
1167 {
1168         struct b43legacy_wl *wl = dev->wl;
1169
1170         if (wl->beacon0_uploaded)
1171                 return;
1172         b43legacy_write_beacon_template(dev, 0x68, 0x18);
1173         /* FIXME: Probe resp upload doesn't really belong here,
1174          *        but we don't use that feature anyway. */
1175         b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
1176                                       &__b43legacy_ratetable[3]);
1177         wl->beacon0_uploaded = true;
1178 }
1179
1180 static void b43legacy_upload_beacon1(struct b43legacy_wldev *dev)
1181 {
1182         struct b43legacy_wl *wl = dev->wl;
1183
1184         if (wl->beacon1_uploaded)
1185                 return;
1186         b43legacy_write_beacon_template(dev, 0x468, 0x1A);
1187         wl->beacon1_uploaded = true;
1188 }
1189
1190 static void handle_irq_beacon(struct b43legacy_wldev *dev)
1191 {
1192         struct b43legacy_wl *wl = dev->wl;
1193         u32 cmd, beacon0_valid, beacon1_valid;
1194
1195         if (!b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1196                 return;
1197
1198         /* This is the bottom half of the asynchronous beacon update. */
1199
1200         /* Ignore interrupt in the future. */
1201         dev->irq_mask &= ~B43legacy_IRQ_BEACON;
1202
1203         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1204         beacon0_valid = (cmd & B43legacy_MACCMD_BEACON0_VALID);
1205         beacon1_valid = (cmd & B43legacy_MACCMD_BEACON1_VALID);
1206
1207         /* Schedule interrupt manually, if busy. */
1208         if (beacon0_valid && beacon1_valid) {
1209                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, B43legacy_IRQ_BEACON);
1210                 dev->irq_mask |= B43legacy_IRQ_BEACON;
1211                 return;
1212         }
1213
1214         if (unlikely(wl->beacon_templates_virgin)) {
1215                 /* We never uploaded a beacon before.
1216                  * Upload both templates now, but only mark one valid. */
1217                 wl->beacon_templates_virgin = false;
1218                 b43legacy_upload_beacon0(dev);
1219                 b43legacy_upload_beacon1(dev);
1220                 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1221                 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1222                 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1223         } else {
1224                 if (!beacon0_valid) {
1225                         b43legacy_upload_beacon0(dev);
1226                         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1227                         cmd |= B43legacy_MACCMD_BEACON0_VALID;
1228                         b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1229                 } else if (!beacon1_valid) {
1230                         b43legacy_upload_beacon1(dev);
1231                         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1232                         cmd |= B43legacy_MACCMD_BEACON1_VALID;
1233                         b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1234                 }
1235         }
1236 }
1237
1238 static void b43legacy_beacon_update_trigger_work(struct work_struct *work)
1239 {
1240         struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
1241                                          beacon_update_trigger);
1242         struct b43legacy_wldev *dev;
1243
1244         mutex_lock(&wl->mutex);
1245         dev = wl->current_dev;
1246         if (likely(dev && (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED))) {
1247                 spin_lock_irq(&wl->irq_lock);
1248                 /* Update beacon right away or defer to IRQ. */
1249                 handle_irq_beacon(dev);
1250                 /* The handler might have updated the IRQ mask. */
1251                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1252                                   dev->irq_mask);
1253                 mmiowb();
1254                 spin_unlock_irq(&wl->irq_lock);
1255         }
1256         mutex_unlock(&wl->mutex);
1257 }
1258
1259 /* Asynchronously update the packet templates in template RAM.
1260  * Locking: Requires wl->irq_lock to be locked. */
1261 static void b43legacy_update_templates(struct b43legacy_wl *wl)
1262 {
1263         struct sk_buff *beacon;
1264         /* This is the top half of the ansynchronous beacon update. The bottom
1265          * half is the beacon IRQ. Beacon update must be asynchronous to avoid
1266          * sending an invalid beacon. This can happen for example, if the
1267          * firmware transmits a beacon while we are updating it. */
1268
1269         /* We could modify the existing beacon and set the aid bit in the TIM
1270          * field, but that would probably require resizing and moving of data
1271          * within the beacon template. Simply request a new beacon and let
1272          * mac80211 do the hard work. */
1273         beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1274         if (unlikely(!beacon))
1275                 return;
1276
1277         if (wl->current_beacon)
1278                 dev_kfree_skb_any(wl->current_beacon);
1279         wl->current_beacon = beacon;
1280         wl->beacon0_uploaded = false;
1281         wl->beacon1_uploaded = false;
1282         ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1283 }
1284
1285 static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1286                                      u16 beacon_int)
1287 {
1288         b43legacy_time_lock(dev);
1289         if (dev->dev->id.revision >= 3) {
1290                 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_REP,
1291                                  (beacon_int << 16));
1292                 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_START,
1293                                  (beacon_int << 10));
1294         } else {
1295                 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1296                 b43legacy_write16(dev, 0x610, beacon_int);
1297         }
1298         b43legacy_time_unlock(dev);
1299         b43legacydbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1300 }
1301
1302 static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1303 {
1304 }
1305
1306 /* Interrupt handler bottom-half */
1307 static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1308 {
1309         u32 reason;
1310         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1311         u32 merged_dma_reason = 0;
1312         int i;
1313         unsigned long flags;
1314
1315         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1316
1317         B43legacy_WARN_ON(b43legacy_status(dev) <
1318                           B43legacy_STAT_INITIALIZED);
1319
1320         reason = dev->irq_reason;
1321         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1322                 dma_reason[i] = dev->dma_reason[i];
1323                 merged_dma_reason |= dma_reason[i];
1324         }
1325
1326         if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1327                 b43legacyerr(dev->wl, "MAC transmission error\n");
1328
1329         if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
1330                 b43legacyerr(dev->wl, "PHY transmission error\n");
1331                 rmb();
1332                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1333                         b43legacyerr(dev->wl, "Too many PHY TX errors, "
1334                                               "restarting the controller\n");
1335                         b43legacy_controller_restart(dev, "PHY TX errors");
1336                 }
1337         }
1338
1339         if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1340                                           B43legacy_DMAIRQ_NONFATALMASK))) {
1341                 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1342                         b43legacyerr(dev->wl, "Fatal DMA error: "
1343                                "0x%08X, 0x%08X, 0x%08X, "
1344                                "0x%08X, 0x%08X, 0x%08X\n",
1345                                dma_reason[0], dma_reason[1],
1346                                dma_reason[2], dma_reason[3],
1347                                dma_reason[4], dma_reason[5]);
1348                         b43legacy_controller_restart(dev, "DMA error");
1349                         mmiowb();
1350                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1351                         return;
1352                 }
1353                 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1354                         b43legacyerr(dev->wl, "DMA error: "
1355                                "0x%08X, 0x%08X, 0x%08X, "
1356                                "0x%08X, 0x%08X, 0x%08X\n",
1357                                dma_reason[0], dma_reason[1],
1358                                dma_reason[2], dma_reason[3],
1359                                dma_reason[4], dma_reason[5]);
1360         }
1361
1362         if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1363                 handle_irq_ucode_debug(dev);
1364         if (reason & B43legacy_IRQ_TBTT_INDI)
1365                 handle_irq_tbtt_indication(dev);
1366         if (reason & B43legacy_IRQ_ATIM_END)
1367                 handle_irq_atim_end(dev);
1368         if (reason & B43legacy_IRQ_BEACON)
1369                 handle_irq_beacon(dev);
1370         if (reason & B43legacy_IRQ_PMQ)
1371                 handle_irq_pmq(dev);
1372         if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1373                 ;/*TODO*/
1374         if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1375                 handle_irq_noise(dev);
1376
1377         /* Check the DMA reason registers for received data. */
1378         if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1379                 if (b43legacy_using_pio(dev))
1380                         b43legacy_pio_rx(dev->pio.queue0);
1381                 else
1382                         b43legacy_dma_rx(dev->dma.rx_ring0);
1383         }
1384         B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1385         B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1386         if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1387                 if (b43legacy_using_pio(dev))
1388                         b43legacy_pio_rx(dev->pio.queue3);
1389                 else
1390                         b43legacy_dma_rx(dev->dma.rx_ring3);
1391         }
1392         B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1393         B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1394
1395         if (reason & B43legacy_IRQ_TX_OK)
1396                 handle_irq_transmit_status(dev);
1397
1398         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1399         mmiowb();
1400         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1401 }
1402
1403 static void pio_irq_workaround(struct b43legacy_wldev *dev,
1404                                u16 base, int queueidx)
1405 {
1406         u16 rxctl;
1407
1408         rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1409         if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1410                 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1411         else
1412                 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1413 }
1414
1415 static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1416 {
1417         if (b43legacy_using_pio(dev) &&
1418             (dev->dev->id.revision < 3) &&
1419             (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1420                 /* Apply a PIO specific workaround to the dma_reasons */
1421                 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1422                 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1423                 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1424                 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1425         }
1426
1427         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1428
1429         b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1430                           dev->dma_reason[0]);
1431         b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1432                           dev->dma_reason[1]);
1433         b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1434                           dev->dma_reason[2]);
1435         b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1436                           dev->dma_reason[3]);
1437         b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1438                           dev->dma_reason[4]);
1439         b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1440                           dev->dma_reason[5]);
1441 }
1442
1443 /* Interrupt handler top-half */
1444 static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1445 {
1446         irqreturn_t ret = IRQ_NONE;
1447         struct b43legacy_wldev *dev = dev_id;
1448         u32 reason;
1449
1450         B43legacy_WARN_ON(!dev);
1451
1452         spin_lock(&dev->wl->irq_lock);
1453
1454         if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
1455                 /* This can only happen on shared IRQ lines. */
1456                 goto out;
1457         reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1458         if (reason == 0xffffffff) /* shared IRQ */
1459                 goto out;
1460         ret = IRQ_HANDLED;
1461         reason &= dev->irq_mask;
1462         if (!reason)
1463                 goto out;
1464
1465         dev->dma_reason[0] = b43legacy_read32(dev,
1466                                               B43legacy_MMIO_DMA0_REASON)
1467                                               & 0x0001DC00;
1468         dev->dma_reason[1] = b43legacy_read32(dev,
1469                                               B43legacy_MMIO_DMA1_REASON)
1470                                               & 0x0000DC00;
1471         dev->dma_reason[2] = b43legacy_read32(dev,
1472                                               B43legacy_MMIO_DMA2_REASON)
1473                                               & 0x0000DC00;
1474         dev->dma_reason[3] = b43legacy_read32(dev,
1475                                               B43legacy_MMIO_DMA3_REASON)
1476                                               & 0x0001DC00;
1477         dev->dma_reason[4] = b43legacy_read32(dev,
1478                                               B43legacy_MMIO_DMA4_REASON)
1479                                               & 0x0000DC00;
1480         dev->dma_reason[5] = b43legacy_read32(dev,
1481                                               B43legacy_MMIO_DMA5_REASON)
1482                                               & 0x0000DC00;
1483
1484         b43legacy_interrupt_ack(dev, reason);
1485         /* Disable all IRQs. They are enabled again in the bottom half. */
1486         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1487         /* Save the reason code and call our bottom half. */
1488         dev->irq_reason = reason;
1489         tasklet_schedule(&dev->isr_tasklet);
1490 out:
1491         mmiowb();
1492         spin_unlock(&dev->wl->irq_lock);
1493
1494         return ret;
1495 }
1496
1497 static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1498 {
1499         release_firmware(dev->fw.ucode);
1500         dev->fw.ucode = NULL;
1501         release_firmware(dev->fw.pcm);
1502         dev->fw.pcm = NULL;
1503         release_firmware(dev->fw.initvals);
1504         dev->fw.initvals = NULL;
1505         release_firmware(dev->fw.initvals_band);
1506         dev->fw.initvals_band = NULL;
1507 }
1508
1509 static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1510 {
1511         b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
1512                      "Drivers/b43#devicefirmware "
1513                      "and download the correct firmware (version 3).\n");
1514 }
1515
1516 static int do_request_fw(struct b43legacy_wldev *dev,
1517                          const char *name,
1518                          const struct firmware **fw)
1519 {
1520         char path[sizeof(modparam_fwpostfix) + 32];
1521         struct b43legacy_fw_header *hdr;
1522         u32 size;
1523         int err;
1524
1525         if (!name)
1526                 return 0;
1527
1528         snprintf(path, ARRAY_SIZE(path),
1529                  "b43legacy%s/%s.fw",
1530                  modparam_fwpostfix, name);
1531         err = request_firmware(fw, path, dev->dev->dev);
1532         if (err) {
1533                 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1534                        "or load failed.\n", path);
1535                 return err;
1536         }
1537         if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1538                 goto err_format;
1539         hdr = (struct b43legacy_fw_header *)((*fw)->data);
1540         switch (hdr->type) {
1541         case B43legacy_FW_TYPE_UCODE:
1542         case B43legacy_FW_TYPE_PCM:
1543                 size = be32_to_cpu(hdr->size);
1544                 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1545                         goto err_format;
1546                 /* fallthrough */
1547         case B43legacy_FW_TYPE_IV:
1548                 if (hdr->ver != 1)
1549                         goto err_format;
1550                 break;
1551         default:
1552                 goto err_format;
1553         }
1554
1555         return err;
1556
1557 err_format:
1558         b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1559         return -EPROTO;
1560 }
1561
1562 static int b43legacy_one_core_attach(struct ssb_device *dev,
1563                                      struct b43legacy_wl *wl);
1564 static void b43legacy_one_core_detach(struct ssb_device *dev);
1565
1566 static void b43legacy_request_firmware(struct work_struct *work)
1567 {
1568         struct b43legacy_wl *wl = container_of(work,
1569                                   struct b43legacy_wl, firmware_load);
1570         struct b43legacy_wldev *dev = wl->current_dev;
1571         struct b43legacy_firmware *fw = &dev->fw;
1572         const u8 rev = dev->dev->id.revision;
1573         const char *filename;
1574         int err;
1575
1576         if (!fw->ucode) {
1577                 if (rev == 2)
1578                         filename = "ucode2";
1579                 else if (rev == 4)
1580                         filename = "ucode4";
1581                 else
1582                         filename = "ucode5";
1583                 err = do_request_fw(dev, filename, &fw->ucode);
1584                 if (err)
1585                         goto err_load;
1586         }
1587         if (!fw->pcm) {
1588                 if (rev < 5)
1589                         filename = "pcm4";
1590                 else
1591                         filename = "pcm5";
1592                 err = do_request_fw(dev, filename, &fw->pcm);
1593                 if (err)
1594                         goto err_load;
1595         }
1596         if (!fw->initvals) {
1597                 switch (dev->phy.type) {
1598                 case B43legacy_PHYTYPE_B:
1599                 case B43legacy_PHYTYPE_G:
1600                         if ((rev >= 5) && (rev <= 10))
1601                                 filename = "b0g0initvals5";
1602                         else if (rev == 2 || rev == 4)
1603                                 filename = "b0g0initvals2";
1604                         else
1605                                 goto err_no_initvals;
1606                         break;
1607                 default:
1608                         goto err_no_initvals;
1609                 }
1610                 err = do_request_fw(dev, filename, &fw->initvals);
1611                 if (err)
1612                         goto err_load;
1613         }
1614         if (!fw->initvals_band) {
1615                 switch (dev->phy.type) {
1616                 case B43legacy_PHYTYPE_B:
1617                 case B43legacy_PHYTYPE_G:
1618                         if ((rev >= 5) && (rev <= 10))
1619                                 filename = "b0g0bsinitvals5";
1620                         else if (rev >= 11)
1621                                 filename = NULL;
1622                         else if (rev == 2 || rev == 4)
1623                                 filename = NULL;
1624                         else
1625                                 goto err_no_initvals;
1626                         break;
1627                 default:
1628                         goto err_no_initvals;
1629                 }
1630                 err = do_request_fw(dev, filename, &fw->initvals_band);
1631                 if (err)
1632                         goto err_load;
1633         }
1634         err = ieee80211_register_hw(wl->hw);
1635         if (err)
1636                 goto err_one_core_detach;
1637         return;
1638
1639 err_one_core_detach:
1640         b43legacy_one_core_detach(dev->dev);
1641         goto error;
1642
1643 err_load:
1644         b43legacy_print_fw_helptext(dev->wl);
1645         goto error;
1646
1647 err_no_initvals:
1648         err = -ENODEV;
1649         b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1650                "core rev %u\n", dev->phy.type, rev);
1651         goto error;
1652
1653 error:
1654         b43legacy_release_firmware(dev);
1655         return;
1656 }
1657
1658 static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1659 {
1660         struct wiphy *wiphy = dev->wl->hw->wiphy;
1661         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1662         const __be32 *data;
1663         unsigned int i;
1664         unsigned int len;
1665         u16 fwrev;
1666         u16 fwpatch;
1667         u16 fwdate;
1668         u16 fwtime;
1669         u32 tmp, macctl;
1670         int err = 0;
1671
1672         /* Jump the microcode PSM to offset 0 */
1673         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1674         B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1675         macctl |= B43legacy_MACCTL_PSM_JMP0;
1676         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1677         /* Zero out all microcode PSM registers and shared memory. */
1678         for (i = 0; i < 64; i++)
1679                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1680         for (i = 0; i < 4096; i += 2)
1681                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1682
1683         /* Upload Microcode. */
1684         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1685         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1686         b43legacy_shm_control_word(dev,
1687                                    B43legacy_SHM_UCODE |
1688                                    B43legacy_SHM_AUTOINC_W,
1689                                    0x0000);
1690         for (i = 0; i < len; i++) {
1691                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1692                                     be32_to_cpu(data[i]));
1693                 udelay(10);
1694         }
1695
1696         if (dev->fw.pcm) {
1697                 /* Upload PCM data. */
1698                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1699                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1700                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1701                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1702                 /* No need for autoinc bit in SHM_HW */
1703                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1704                 for (i = 0; i < len; i++) {
1705                         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1706                                           be32_to_cpu(data[i]));
1707                         udelay(10);
1708                 }
1709         }
1710
1711         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1712                           B43legacy_IRQ_ALL);
1713
1714         /* Start the microcode PSM */
1715         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1716         macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1717         macctl |= B43legacy_MACCTL_PSM_RUN;
1718         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1719
1720         /* Wait for the microcode to load and respond */
1721         i = 0;
1722         while (1) {
1723                 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1724                 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1725                         break;
1726                 i++;
1727                 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1728                         b43legacyerr(dev->wl, "Microcode not responding\n");
1729                         b43legacy_print_fw_helptext(dev->wl);
1730                         err = -ENODEV;
1731                         goto error;
1732                 }
1733                 msleep_interruptible(50);
1734                 if (signal_pending(current)) {
1735                         err = -EINTR;
1736                         goto error;
1737                 }
1738         }
1739         /* dummy read follows */
1740         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1741
1742         /* Get and check the revisions. */
1743         fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1744                                      B43legacy_SHM_SH_UCODEREV);
1745         fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1746                                        B43legacy_SHM_SH_UCODEPATCH);
1747         fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1748                                       B43legacy_SHM_SH_UCODEDATE);
1749         fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1750                                       B43legacy_SHM_SH_UCODETIME);
1751
1752         if (fwrev > 0x128) {
1753                 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1754                              " Only firmware from binary drivers version 3.x"
1755                              " is supported. You must change your firmware"
1756                              " files.\n");
1757                 b43legacy_print_fw_helptext(dev->wl);
1758                 err = -EOPNOTSUPP;
1759                 goto error;
1760         }
1761         b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1762                       "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1763                       (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1764                       (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1765                       fwtime & 0x1F);
1766
1767         dev->fw.rev = fwrev;
1768         dev->fw.patch = fwpatch;
1769
1770         snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
1771                         dev->fw.rev, dev->fw.patch);
1772         wiphy->hw_version = dev->dev->id.coreid;
1773
1774         return 0;
1775
1776 error:
1777         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1778         macctl &= ~B43legacy_MACCTL_PSM_RUN;
1779         macctl |= B43legacy_MACCTL_PSM_JMP0;
1780         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1781
1782         return err;
1783 }
1784
1785 static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1786                                     const struct b43legacy_iv *ivals,
1787                                     size_t count,
1788                                     size_t array_size)
1789 {
1790         const struct b43legacy_iv *iv;
1791         u16 offset;
1792         size_t i;
1793         bool bit32;
1794
1795         BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1796         iv = ivals;
1797         for (i = 0; i < count; i++) {
1798                 if (array_size < sizeof(iv->offset_size))
1799                         goto err_format;
1800                 array_size -= sizeof(iv->offset_size);
1801                 offset = be16_to_cpu(iv->offset_size);
1802                 bit32 = !!(offset & B43legacy_IV_32BIT);
1803                 offset &= B43legacy_IV_OFFSET_MASK;
1804                 if (offset >= 0x1000)
1805                         goto err_format;
1806                 if (bit32) {
1807                         u32 value;
1808
1809                         if (array_size < sizeof(iv->data.d32))
1810                                 goto err_format;
1811                         array_size -= sizeof(iv->data.d32);
1812
1813                         value = get_unaligned_be32(&iv->data.d32);
1814                         b43legacy_write32(dev, offset, value);
1815
1816                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1817                                                         sizeof(__be16) +
1818                                                         sizeof(__be32));
1819                 } else {
1820                         u16 value;
1821
1822                         if (array_size < sizeof(iv->data.d16))
1823                                 goto err_format;
1824                         array_size -= sizeof(iv->data.d16);
1825
1826                         value = be16_to_cpu(iv->data.d16);
1827                         b43legacy_write16(dev, offset, value);
1828
1829                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1830                                                         sizeof(__be16) +
1831                                                         sizeof(__be16));
1832                 }
1833         }
1834         if (array_size)
1835                 goto err_format;
1836
1837         return 0;
1838
1839 err_format:
1840         b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1841         b43legacy_print_fw_helptext(dev->wl);
1842
1843         return -EPROTO;
1844 }
1845
1846 static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1847 {
1848         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1849         const struct b43legacy_fw_header *hdr;
1850         struct b43legacy_firmware *fw = &dev->fw;
1851         const struct b43legacy_iv *ivals;
1852         size_t count;
1853         int err;
1854
1855         hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1856         ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1857         count = be32_to_cpu(hdr->size);
1858         err = b43legacy_write_initvals(dev, ivals, count,
1859                                  fw->initvals->size - hdr_len);
1860         if (err)
1861                 goto out;
1862         if (fw->initvals_band) {
1863                 hdr = (const struct b43legacy_fw_header *)
1864                       (fw->initvals_band->data);
1865                 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1866                         + hdr_len);
1867                 count = be32_to_cpu(hdr->size);
1868                 err = b43legacy_write_initvals(dev, ivals, count,
1869                                          fw->initvals_band->size - hdr_len);
1870                 if (err)
1871                         goto out;
1872         }
1873 out:
1874
1875         return err;
1876 }
1877
1878 /* Initialize the GPIOs
1879  * http://bcm-specs.sipsolutions.net/GPIO
1880  */
1881 static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1882 {
1883         struct ssb_bus *bus = dev->dev->bus;
1884         struct ssb_device *gpiodev, *pcidev = NULL;
1885         u32 mask;
1886         u32 set;
1887
1888         b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1889                           b43legacy_read32(dev,
1890                           B43legacy_MMIO_MACCTL)
1891                           & 0xFFFF3FFF);
1892
1893         b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1894                           b43legacy_read16(dev,
1895                           B43legacy_MMIO_GPIO_MASK)
1896                           | 0x000F);
1897
1898         mask = 0x0000001F;
1899         set = 0x0000000F;
1900         if (dev->dev->bus->chip_id == 0x4301) {
1901                 mask |= 0x0060;
1902                 set |= 0x0060;
1903         }
1904         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
1905                 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1906                                   b43legacy_read16(dev,
1907                                   B43legacy_MMIO_GPIO_MASK)
1908                                   | 0x0200);
1909                 mask |= 0x0200;
1910                 set |= 0x0200;
1911         }
1912         if (dev->dev->id.revision >= 2)
1913                 mask  |= 0x0010; /* FIXME: This is redundant. */
1914
1915 #ifdef CONFIG_SSB_DRIVER_PCICORE
1916         pcidev = bus->pcicore.dev;
1917 #endif
1918         gpiodev = bus->chipco.dev ? : pcidev;
1919         if (!gpiodev)
1920                 return 0;
1921         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1922                     (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1923                      & mask) | set);
1924
1925         return 0;
1926 }
1927
1928 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1929 static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1930 {
1931         struct ssb_bus *bus = dev->dev->bus;
1932         struct ssb_device *gpiodev, *pcidev = NULL;
1933
1934 #ifdef CONFIG_SSB_DRIVER_PCICORE
1935         pcidev = bus->pcicore.dev;
1936 #endif
1937         gpiodev = bus->chipco.dev ? : pcidev;
1938         if (!gpiodev)
1939                 return;
1940         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1941 }
1942
1943 /* http://bcm-specs.sipsolutions.net/EnableMac */
1944 void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1945 {
1946         dev->mac_suspended--;
1947         B43legacy_WARN_ON(dev->mac_suspended < 0);
1948         B43legacy_WARN_ON(irqs_disabled());
1949         if (dev->mac_suspended == 0) {
1950                 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1951                                   b43legacy_read32(dev,
1952                                   B43legacy_MMIO_MACCTL)
1953                                   | B43legacy_MACCTL_ENABLED);
1954                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1955                                   B43legacy_IRQ_MAC_SUSPENDED);
1956                 /* the next two are dummy reads */
1957                 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1958                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1959                 b43legacy_power_saving_ctl_bits(dev, -1, -1);
1960
1961                 /* Re-enable IRQs. */
1962                 spin_lock_irq(&dev->wl->irq_lock);
1963                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1964                                   dev->irq_mask);
1965                 spin_unlock_irq(&dev->wl->irq_lock);
1966         }
1967 }
1968
1969 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1970 void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1971 {
1972         int i;
1973         u32 tmp;
1974
1975         might_sleep();
1976         B43legacy_WARN_ON(irqs_disabled());
1977         B43legacy_WARN_ON(dev->mac_suspended < 0);
1978
1979         if (dev->mac_suspended == 0) {
1980                 /* Mask IRQs before suspending MAC. Otherwise
1981                  * the MAC stays busy and won't suspend. */
1982                 spin_lock_irq(&dev->wl->irq_lock);
1983                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1984                 spin_unlock_irq(&dev->wl->irq_lock);
1985                 b43legacy_synchronize_irq(dev);
1986
1987                 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1988                 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1989                                   b43legacy_read32(dev,
1990                                   B43legacy_MMIO_MACCTL)
1991                                   & ~B43legacy_MACCTL_ENABLED);
1992                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1993                 for (i = 40; i; i--) {
1994                         tmp = b43legacy_read32(dev,
1995                                                B43legacy_MMIO_GEN_IRQ_REASON);
1996                         if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1997                                 goto out;
1998                         msleep(1);
1999                 }
2000                 b43legacyerr(dev->wl, "MAC suspend failed\n");
2001         }
2002 out:
2003         dev->mac_suspended++;
2004 }
2005
2006 static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
2007 {
2008         struct b43legacy_wl *wl = dev->wl;
2009         u32 ctl;
2010         u16 cfp_pretbtt;
2011
2012         ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2013         /* Reset status to STA infrastructure mode. */
2014         ctl &= ~B43legacy_MACCTL_AP;
2015         ctl &= ~B43legacy_MACCTL_KEEP_CTL;
2016         ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
2017         ctl &= ~B43legacy_MACCTL_KEEP_BAD;
2018         ctl &= ~B43legacy_MACCTL_PROMISC;
2019         ctl &= ~B43legacy_MACCTL_BEACPROMISC;
2020         ctl |= B43legacy_MACCTL_INFRA;
2021
2022         if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
2023                 ctl |= B43legacy_MACCTL_AP;
2024         else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))
2025                 ctl &= ~B43legacy_MACCTL_INFRA;
2026
2027         if (wl->filter_flags & FIF_CONTROL)
2028                 ctl |= B43legacy_MACCTL_KEEP_CTL;
2029         if (wl->filter_flags & FIF_FCSFAIL)
2030                 ctl |= B43legacy_MACCTL_KEEP_BAD;
2031         if (wl->filter_flags & FIF_PLCPFAIL)
2032                 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
2033         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2034                 ctl |= B43legacy_MACCTL_PROMISC;
2035         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2036                 ctl |= B43legacy_MACCTL_BEACPROMISC;
2037
2038         /* Workaround: On old hardware the HW-MAC-address-filter
2039          * doesn't work properly, so always run promisc in filter
2040          * it in software. */
2041         if (dev->dev->id.revision <= 4)
2042                 ctl |= B43legacy_MACCTL_PROMISC;
2043
2044         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
2045
2046         cfp_pretbtt = 2;
2047         if ((ctl & B43legacy_MACCTL_INFRA) &&
2048             !(ctl & B43legacy_MACCTL_AP)) {
2049                 if (dev->dev->bus->chip_id == 0x4306 &&
2050                     dev->dev->bus->chip_rev == 3)
2051                         cfp_pretbtt = 100;
2052                 else
2053                         cfp_pretbtt = 50;
2054         }
2055         b43legacy_write16(dev, 0x612, cfp_pretbtt);
2056 }
2057
2058 static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
2059                                         u16 rate,
2060                                         int is_ofdm)
2061 {
2062         u16 offset;
2063
2064         if (is_ofdm) {
2065                 offset = 0x480;
2066                 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2067         } else {
2068                 offset = 0x4C0;
2069                 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2070         }
2071         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
2072                               b43legacy_shm_read16(dev,
2073                               B43legacy_SHM_SHARED, offset));
2074 }
2075
2076 static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
2077 {
2078         switch (dev->phy.type) {
2079         case B43legacy_PHYTYPE_G:
2080                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
2081                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
2082                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
2083                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
2084                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
2085                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
2086                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
2087                 /* fallthrough */
2088         case B43legacy_PHYTYPE_B:
2089                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
2090                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
2091                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
2092                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
2093                 break;
2094         default:
2095                 B43legacy_BUG_ON(1);
2096         }
2097 }
2098
2099 /* Set the TX-Antenna for management frames sent by firmware. */
2100 static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
2101                                           int antenna)
2102 {
2103         u16 ant = 0;
2104         u16 tmp;
2105
2106         switch (antenna) {
2107         case B43legacy_ANTENNA0:
2108                 ant |= B43legacy_TX4_PHY_ANT0;
2109                 break;
2110         case B43legacy_ANTENNA1:
2111                 ant |= B43legacy_TX4_PHY_ANT1;
2112                 break;
2113         case B43legacy_ANTENNA_AUTO:
2114                 ant |= B43legacy_TX4_PHY_ANTLAST;
2115                 break;
2116         default:
2117                 B43legacy_BUG_ON(1);
2118         }
2119
2120         /* FIXME We also need to set the other flags of the PHY control
2121          * field somewhere. */
2122
2123         /* For Beacons */
2124         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2125                                    B43legacy_SHM_SH_BEACPHYCTL);
2126         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2127         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2128                               B43legacy_SHM_SH_BEACPHYCTL, tmp);
2129         /* For ACK/CTS */
2130         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2131                                    B43legacy_SHM_SH_ACKCTSPHYCTL);
2132         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2133         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2134                               B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2135         /* For Probe Resposes */
2136         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2137                                    B43legacy_SHM_SH_PRPHYCTL);
2138         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2139         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2140                               B43legacy_SHM_SH_PRPHYCTL, tmp);
2141 }
2142
2143 /* This is the opposite of b43legacy_chip_init() */
2144 static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2145 {
2146         b43legacy_radio_turn_off(dev, 1);
2147         b43legacy_gpio_cleanup(dev);
2148         /* firmware is released later */
2149 }
2150
2151 /* Initialize the chip
2152  * http://bcm-specs.sipsolutions.net/ChipInit
2153  */
2154 static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2155 {
2156         struct b43legacy_phy *phy = &dev->phy;
2157         int err;
2158         int tmp;
2159         u32 value32, macctl;
2160         u16 value16;
2161
2162         /* Initialize the MAC control */
2163         macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2164         if (dev->phy.gmode)
2165                 macctl |= B43legacy_MACCTL_GMODE;
2166         macctl |= B43legacy_MACCTL_INFRA;
2167         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
2168
2169         err = b43legacy_upload_microcode(dev);
2170         if (err)
2171                 goto out; /* firmware is released later */
2172
2173         err = b43legacy_gpio_init(dev);
2174         if (err)
2175                 goto out; /* firmware is released later */
2176
2177         err = b43legacy_upload_initvals(dev);
2178         if (err)
2179                 goto err_gpio_clean;
2180         b43legacy_radio_turn_on(dev);
2181
2182         b43legacy_write16(dev, 0x03E6, 0x0000);
2183         err = b43legacy_phy_init(dev);
2184         if (err)
2185                 goto err_radio_off;
2186
2187         /* Select initial Interference Mitigation. */
2188         tmp = phy->interfmode;
2189         phy->interfmode = B43legacy_INTERFMODE_NONE;
2190         b43legacy_radio_set_interference_mitigation(dev, tmp);
2191
2192         b43legacy_phy_set_antenna_diversity(dev);
2193         b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2194
2195         if (phy->type == B43legacy_PHYTYPE_B) {
2196                 value16 = b43legacy_read16(dev, 0x005E);
2197                 value16 |= 0x0004;
2198                 b43legacy_write16(dev, 0x005E, value16);
2199         }
2200         b43legacy_write32(dev, 0x0100, 0x01000000);
2201         if (dev->dev->id.revision < 5)
2202                 b43legacy_write32(dev, 0x010C, 0x01000000);
2203
2204         value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2205         value32 &= ~B43legacy_MACCTL_INFRA;
2206         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2207         value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2208         value32 |= B43legacy_MACCTL_INFRA;
2209         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2210
2211         if (b43legacy_using_pio(dev)) {
2212                 b43legacy_write32(dev, 0x0210, 0x00000100);
2213                 b43legacy_write32(dev, 0x0230, 0x00000100);
2214                 b43legacy_write32(dev, 0x0250, 0x00000100);
2215                 b43legacy_write32(dev, 0x0270, 0x00000100);
2216                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2217                                       0x0000);
2218         }
2219
2220         /* Probe Response Timeout value */
2221         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2222         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2223
2224         /* Initially set the wireless operation mode. */
2225         b43legacy_adjust_opmode(dev);
2226
2227         if (dev->dev->id.revision < 3) {
2228                 b43legacy_write16(dev, 0x060E, 0x0000);
2229                 b43legacy_write16(dev, 0x0610, 0x8000);
2230                 b43legacy_write16(dev, 0x0604, 0x0000);
2231                 b43legacy_write16(dev, 0x0606, 0x0200);
2232         } else {
2233                 b43legacy_write32(dev, 0x0188, 0x80000000);
2234                 b43legacy_write32(dev, 0x018C, 0x02000000);
2235         }
2236         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2237         b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2238         b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2239         b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2240         b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2241         b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2242         b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2243
2244         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2245         value32 |= B43legacy_TMSLOW_MACPHYCLKEN;
2246         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2247
2248         b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2249                           dev->dev->bus->chipco.fast_pwrup_delay);
2250
2251         /* PHY TX errors counter. */
2252         atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2253
2254         B43legacy_WARN_ON(err != 0);
2255         b43legacydbg(dev->wl, "Chip initialized\n");
2256 out:
2257         return err;
2258
2259 err_radio_off:
2260         b43legacy_radio_turn_off(dev, 1);
2261 err_gpio_clean:
2262         b43legacy_gpio_cleanup(dev);
2263         goto out;
2264 }
2265
2266 static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2267 {
2268         struct b43legacy_phy *phy = &dev->phy;
2269
2270         if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2271                 return;
2272
2273         b43legacy_mac_suspend(dev);
2274         b43legacy_phy_lo_g_measure(dev);
2275         b43legacy_mac_enable(dev);
2276 }
2277
2278 static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2279 {
2280         b43legacy_phy_lo_mark_all_unused(dev);
2281         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
2282                 b43legacy_mac_suspend(dev);
2283                 b43legacy_calc_nrssi_slope(dev);
2284                 b43legacy_mac_enable(dev);
2285         }
2286 }
2287
2288 static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2289 {
2290         /* Update device statistics. */
2291         b43legacy_calculate_link_quality(dev);
2292 }
2293
2294 static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2295 {
2296         b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
2297
2298         atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2299         wmb();
2300 }
2301
2302 static void do_periodic_work(struct b43legacy_wldev *dev)
2303 {
2304         unsigned int state;
2305
2306         state = dev->periodic_state;
2307         if (state % 8 == 0)
2308                 b43legacy_periodic_every120sec(dev);
2309         if (state % 4 == 0)
2310                 b43legacy_periodic_every60sec(dev);
2311         if (state % 2 == 0)
2312                 b43legacy_periodic_every30sec(dev);
2313         b43legacy_periodic_every15sec(dev);
2314 }
2315
2316 /* Periodic work locking policy:
2317  *      The whole periodic work handler is protected by
2318  *      wl->mutex. If another lock is needed somewhere in the
2319  *      pwork callchain, it's acquired in-place, where it's needed.
2320  */
2321 static void b43legacy_periodic_work_handler(struct work_struct *work)
2322 {
2323         struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2324                                              periodic_work.work);
2325         struct b43legacy_wl *wl = dev->wl;
2326         unsigned long delay;
2327
2328         mutex_lock(&wl->mutex);
2329
2330         if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2331                 goto out;
2332         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2333                 goto out_requeue;
2334
2335         do_periodic_work(dev);
2336
2337         dev->periodic_state++;
2338 out_requeue:
2339         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2340                 delay = msecs_to_jiffies(50);
2341         else
2342                 delay = round_jiffies_relative(HZ * 15);
2343         ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2344 out:
2345         mutex_unlock(&wl->mutex);
2346 }
2347
2348 static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2349 {
2350         struct delayed_work *work = &dev->periodic_work;
2351
2352         dev->periodic_state = 0;
2353         INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
2354         ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
2355 }
2356
2357 /* Validate access to the chip (SHM) */
2358 static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2359 {
2360         u32 value;
2361         u32 shm_backup;
2362
2363         shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2364         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2365         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2366                                  0xAA5555AA)
2367                 goto error;
2368         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2369         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2370                                  0x55AAAA55)
2371                 goto error;
2372         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2373
2374         value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2375         if ((value | B43legacy_MACCTL_GMODE) !=
2376             (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2377                 goto error;
2378
2379         value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2380         if (value)
2381                 goto error;
2382
2383         return 0;
2384 error:
2385         b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2386         return -ENODEV;
2387 }
2388
2389 static void b43legacy_security_init(struct b43legacy_wldev *dev)
2390 {
2391         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2392         B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2393         dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2394                                         0x0056);
2395         /* KTP is a word address, but we address SHM bytewise.
2396          * So multiply by two.
2397          */
2398         dev->ktp *= 2;
2399         if (dev->dev->id.revision >= 5)
2400                 /* Number of RCMTA address slots */
2401                 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2402                                   dev->max_nr_keys - 8);
2403 }
2404
2405 #ifdef CONFIG_B43LEGACY_HWRNG
2406 static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2407 {
2408         struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2409         unsigned long flags;
2410
2411         /* Don't take wl->mutex here, as it could deadlock with
2412          * hwrng internal locking. It's not needed to take
2413          * wl->mutex here, anyway. */
2414
2415         spin_lock_irqsave(&wl->irq_lock, flags);
2416         *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2417         spin_unlock_irqrestore(&wl->irq_lock, flags);
2418
2419         return (sizeof(u16));
2420 }
2421 #endif
2422
2423 static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2424 {
2425 #ifdef CONFIG_B43LEGACY_HWRNG
2426         if (wl->rng_initialized)
2427                 hwrng_unregister(&wl->rng);
2428 #endif
2429 }
2430
2431 static int b43legacy_rng_init(struct b43legacy_wl *wl)
2432 {
2433         int err = 0;
2434
2435 #ifdef CONFIG_B43LEGACY_HWRNG
2436         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2437                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2438         wl->rng.name = wl->rng_name;
2439         wl->rng.data_read = b43legacy_rng_read;
2440         wl->rng.priv = (unsigned long)wl;
2441         wl->rng_initialized = 1;
2442         err = hwrng_register(&wl->rng);
2443         if (err) {
2444                 wl->rng_initialized = 0;
2445                 b43legacyerr(wl, "Failed to register the random "
2446                        "number generator (%d)\n", err);
2447         }
2448
2449 #endif
2450         return err;
2451 }
2452
2453 static void b43legacy_tx_work(struct work_struct *work)
2454 {
2455         struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
2456                                   tx_work);
2457         struct b43legacy_wldev *dev;
2458         struct sk_buff *skb;
2459         int queue_num;
2460         int err = 0;
2461
2462         mutex_lock(&wl->mutex);
2463         dev = wl->current_dev;
2464         if (unlikely(!dev || b43legacy_status(dev) < B43legacy_STAT_STARTED)) {
2465                 mutex_unlock(&wl->mutex);
2466                 return;
2467         }
2468
2469         for (queue_num = 0; queue_num < B43legacy_QOS_QUEUE_NUM; queue_num++) {
2470                 while (skb_queue_len(&wl->tx_queue[queue_num])) {
2471                         skb = skb_dequeue(&wl->tx_queue[queue_num]);
2472                         if (b43legacy_using_pio(dev))
2473                                 err = b43legacy_pio_tx(dev, skb);
2474                         else
2475                                 err = b43legacy_dma_tx(dev, skb);
2476                         if (err == -ENOSPC) {
2477                                 wl->tx_queue_stopped[queue_num] = 1;
2478                                 ieee80211_stop_queue(wl->hw, queue_num);
2479                                 skb_queue_head(&wl->tx_queue[queue_num], skb);
2480                                 break;
2481                         }
2482                         if (unlikely(err))
2483                                 dev_kfree_skb(skb); /* Drop it */
2484                         err = 0;
2485                 }
2486
2487                 if (!err)
2488                         wl->tx_queue_stopped[queue_num] = 0;
2489         }
2490
2491         mutex_unlock(&wl->mutex);
2492 }
2493
2494 static void b43legacy_op_tx(struct ieee80211_hw *hw,
2495                             struct sk_buff *skb)
2496 {
2497         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2498
2499         if (unlikely(skb->len < 2 + 2 + 6)) {
2500                 /* Too short, this can't be a valid frame. */
2501                 dev_kfree_skb_any(skb);
2502                 return;
2503         }
2504         B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags);
2505
2506         skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
2507         if (!wl->tx_queue_stopped[skb->queue_mapping])
2508                 ieee80211_queue_work(wl->hw, &wl->tx_work);
2509         else
2510                 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
2511 }
2512
2513 static int b43legacy_op_conf_tx(struct ieee80211_hw *hw,
2514                                 struct ieee80211_vif *vif, u16 queue,
2515                                 const struct ieee80211_tx_queue_params *params)
2516 {
2517         return 0;
2518 }
2519
2520 static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2521                                   struct ieee80211_low_level_stats *stats)
2522 {
2523         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2524         unsigned long flags;
2525
2526         spin_lock_irqsave(&wl->irq_lock, flags);
2527         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2528         spin_unlock_irqrestore(&wl->irq_lock, flags);
2529
2530         return 0;
2531 }
2532
2533 static const char *phymode_to_string(unsigned int phymode)
2534 {
2535         switch (phymode) {
2536         case B43legacy_PHYMODE_B:
2537                 return "B";
2538         case B43legacy_PHYMODE_G:
2539                 return "G";
2540         default:
2541                 B43legacy_BUG_ON(1);
2542         }
2543         return "";
2544 }
2545
2546 static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2547                                   unsigned int phymode,
2548                                   struct b43legacy_wldev **dev,
2549                                   bool *gmode)
2550 {
2551         struct b43legacy_wldev *d;
2552
2553         list_for_each_entry(d, &wl->devlist, list) {
2554                 if (d->phy.possible_phymodes & phymode) {
2555                         /* Ok, this device supports the PHY-mode.
2556                          * Set the gmode bit. */
2557                         *gmode = true;
2558                         *dev = d;
2559
2560                         return 0;
2561                 }
2562         }
2563
2564         return -ESRCH;
2565 }
2566
2567 static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2568 {
2569         struct ssb_device *sdev = dev->dev;
2570         u32 tmslow;
2571
2572         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2573         tmslow &= ~B43legacy_TMSLOW_GMODE;
2574         tmslow |= B43legacy_TMSLOW_PHYRESET;
2575         tmslow |= SSB_TMSLOW_FGC;
2576         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2577         msleep(1);
2578
2579         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2580         tmslow &= ~SSB_TMSLOW_FGC;
2581         tmslow |= B43legacy_TMSLOW_PHYRESET;
2582         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2583         msleep(1);
2584 }
2585
2586 /* Expects wl->mutex locked */
2587 static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2588                                       unsigned int new_mode)
2589 {
2590         struct b43legacy_wldev *uninitialized_var(up_dev);
2591         struct b43legacy_wldev *down_dev;
2592         int err;
2593         bool gmode = false;
2594         int prev_status;
2595
2596         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2597         if (err) {
2598                 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2599                        phymode_to_string(new_mode));
2600                 return err;
2601         }
2602         if ((up_dev == wl->current_dev) &&
2603             (!!wl->current_dev->phy.gmode == !!gmode))
2604                 /* This device is already running. */
2605                 return 0;
2606         b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2607                phymode_to_string(new_mode));
2608         down_dev = wl->current_dev;
2609
2610         prev_status = b43legacy_status(down_dev);
2611         /* Shutdown the currently running core. */
2612         if (prev_status >= B43legacy_STAT_STARTED)
2613                 b43legacy_wireless_core_stop(down_dev);
2614         if (prev_status >= B43legacy_STAT_INITIALIZED)
2615                 b43legacy_wireless_core_exit(down_dev);
2616
2617         if (down_dev != up_dev)
2618                 /* We switch to a different core, so we put PHY into
2619                  * RESET on the old core. */
2620                 b43legacy_put_phy_into_reset(down_dev);
2621
2622         /* Now start the new core. */
2623         up_dev->phy.gmode = gmode;
2624         if (prev_status >= B43legacy_STAT_INITIALIZED) {
2625                 err = b43legacy_wireless_core_init(up_dev);
2626                 if (err) {
2627                         b43legacyerr(wl, "Fatal: Could not initialize device"
2628                                      " for newly selected %s-PHY mode\n",
2629                                      phymode_to_string(new_mode));
2630                         goto init_failure;
2631                 }
2632         }
2633         if (prev_status >= B43legacy_STAT_STARTED) {
2634                 err = b43legacy_wireless_core_start(up_dev);
2635                 if (err) {
2636                         b43legacyerr(wl, "Fatal: Coult not start device for "
2637                                "newly selected %s-PHY mode\n",
2638                                phymode_to_string(new_mode));
2639                         b43legacy_wireless_core_exit(up_dev);
2640                         goto init_failure;
2641                 }
2642         }
2643         B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2644
2645         b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2646
2647         wl->current_dev = up_dev;
2648
2649         return 0;
2650 init_failure:
2651         /* Whoops, failed to init the new core. No core is operating now. */
2652         wl->current_dev = NULL;
2653         return err;
2654 }
2655
2656 /* Write the short and long frame retry limit values. */
2657 static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2658                                        unsigned int short_retry,
2659                                        unsigned int long_retry)
2660 {
2661         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2662          * the chip-internal counter. */
2663         short_retry = min(short_retry, (unsigned int)0xF);
2664         long_retry = min(long_retry, (unsigned int)0xF);
2665
2666         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2667         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2668 }
2669
2670 static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2671                                    u32 changed)
2672 {
2673         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2674         struct b43legacy_wldev *dev;
2675         struct b43legacy_phy *phy;
2676         struct ieee80211_conf *conf = &hw->conf;
2677         unsigned long flags;
2678         unsigned int new_phymode = 0xFFFF;
2679         int antenna_tx;
2680         int err = 0;
2681
2682         antenna_tx = B43legacy_ANTENNA_DEFAULT;
2683
2684         mutex_lock(&wl->mutex);
2685         dev = wl->current_dev;
2686         phy = &dev->phy;
2687
2688         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2689                 b43legacy_set_retry_limits(dev,
2690                                            conf->short_frame_max_tx_count,
2691                                            conf->long_frame_max_tx_count);
2692         changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
2693         if (!changed)
2694                 goto out_unlock_mutex;
2695
2696         /* Switch the PHY mode (if necessary). */
2697         switch (conf->channel->band) {
2698         case IEEE80211_BAND_2GHZ:
2699                 if (phy->type == B43legacy_PHYTYPE_B)
2700                         new_phymode = B43legacy_PHYMODE_B;
2701                 else
2702                         new_phymode = B43legacy_PHYMODE_G;
2703                 break;
2704         default:
2705                 B43legacy_WARN_ON(1);
2706         }
2707         err = b43legacy_switch_phymode(wl, new_phymode);
2708         if (err)
2709                 goto out_unlock_mutex;
2710
2711         /* Disable IRQs while reconfiguring the device.
2712          * This makes it possible to drop the spinlock throughout
2713          * the reconfiguration process. */
2714         spin_lock_irqsave(&wl->irq_lock, flags);
2715         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2716                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2717                 goto out_unlock_mutex;
2718         }
2719         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2720         spin_unlock_irqrestore(&wl->irq_lock, flags);
2721         b43legacy_synchronize_irq(dev);
2722
2723         /* Switch to the requested channel.
2724          * The firmware takes care of races with the TX handler. */
2725         if (conf->channel->hw_value != phy->channel)
2726                 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
2727
2728         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
2729
2730         /* Adjust the desired TX power level. */
2731         if (conf->power_level != 0) {
2732                 if (conf->power_level != phy->power_level) {
2733                         phy->power_level = conf->power_level;
2734                         b43legacy_phy_xmitpower(dev);
2735                 }
2736         }
2737
2738         /* Antennas for RX and management frame TX. */
2739         b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2740
2741         if (wl->radio_enabled != phy->radio_on) {
2742                 if (wl->radio_enabled) {
2743                         b43legacy_radio_turn_on(dev);
2744                         b43legacyinfo(dev->wl, "Radio turned on by software\n");
2745                         if (!dev->radio_hw_enable)
2746                                 b43legacyinfo(dev->wl, "The hardware RF-kill"
2747                                               " button still turns the radio"
2748                                               " physically off. Press the"
2749                                               " button to turn it on.\n");
2750                 } else {
2751                         b43legacy_radio_turn_off(dev, 0);
2752                         b43legacyinfo(dev->wl, "Radio turned off by"
2753                                       " software\n");
2754                 }
2755         }
2756
2757         spin_lock_irqsave(&wl->irq_lock, flags);
2758         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2759         mmiowb();
2760         spin_unlock_irqrestore(&wl->irq_lock, flags);
2761 out_unlock_mutex:
2762         mutex_unlock(&wl->mutex);
2763
2764         return err;
2765 }
2766
2767 static void b43legacy_update_basic_rates(struct b43legacy_wldev *dev, u32 brates)
2768 {
2769         struct ieee80211_supported_band *sband =
2770                 dev->wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2771         struct ieee80211_rate *rate;
2772         int i;
2773         u16 basic, direct, offset, basic_offset, rateptr;
2774
2775         for (i = 0; i < sband->n_bitrates; i++) {
2776                 rate = &sband->bitrates[i];
2777
2778                 if (b43legacy_is_cck_rate(rate->hw_value)) {
2779                         direct = B43legacy_SHM_SH_CCKDIRECT;
2780                         basic = B43legacy_SHM_SH_CCKBASIC;
2781                         offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2782                         offset &= 0xF;
2783                 } else {
2784                         direct = B43legacy_SHM_SH_OFDMDIRECT;
2785                         basic = B43legacy_SHM_SH_OFDMBASIC;
2786                         offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2787                         offset &= 0xF;
2788                 }
2789
2790                 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
2791
2792                 if (b43legacy_is_cck_rate(rate->hw_value)) {
2793                         basic_offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2794                         basic_offset &= 0xF;
2795                 } else {
2796                         basic_offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2797                         basic_offset &= 0xF;
2798                 }
2799
2800                 /*
2801                  * Get the pointer that we need to point to
2802                  * from the direct map
2803                  */
2804                 rateptr = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2805                                                direct + 2 * basic_offset);
2806                 /* and write it to the basic map */
2807                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2808                                       basic + 2 * offset, rateptr);
2809         }
2810 }
2811
2812 static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw,
2813                                     struct ieee80211_vif *vif,
2814                                     struct ieee80211_bss_conf *conf,
2815                                     u32 changed)
2816 {
2817         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2818         struct b43legacy_wldev *dev;
2819         unsigned long flags;
2820
2821         mutex_lock(&wl->mutex);
2822         B43legacy_WARN_ON(wl->vif != vif);
2823
2824         dev = wl->current_dev;
2825
2826         /* Disable IRQs while reconfiguring the device.
2827          * This makes it possible to drop the spinlock throughout
2828          * the reconfiguration process. */
2829         spin_lock_irqsave(&wl->irq_lock, flags);
2830         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2831                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2832                 goto out_unlock_mutex;
2833         }
2834         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2835
2836         if (changed & BSS_CHANGED_BSSID) {
2837                 b43legacy_synchronize_irq(dev);
2838
2839                 if (conf->bssid)
2840                         memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2841                 else
2842                         memset(wl->bssid, 0, ETH_ALEN);
2843         }
2844
2845         if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2846                 if (changed & BSS_CHANGED_BEACON &&
2847                     (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2848                      b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2849                         b43legacy_update_templates(wl);
2850
2851                 if (changed & BSS_CHANGED_BSSID)
2852                         b43legacy_write_mac_bssid_templates(dev);
2853         }
2854         spin_unlock_irqrestore(&wl->irq_lock, flags);
2855
2856         b43legacy_mac_suspend(dev);
2857
2858         if (changed & BSS_CHANGED_BEACON_INT &&
2859             (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2860              b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2861                 b43legacy_set_beacon_int(dev, conf->beacon_int);
2862
2863         if (changed & BSS_CHANGED_BASIC_RATES)
2864                 b43legacy_update_basic_rates(dev, conf->basic_rates);
2865
2866         if (changed & BSS_CHANGED_ERP_SLOT) {
2867                 if (conf->use_short_slot)
2868                         b43legacy_short_slot_timing_enable(dev);
2869                 else
2870                         b43legacy_short_slot_timing_disable(dev);
2871         }
2872
2873         b43legacy_mac_enable(dev);
2874
2875         spin_lock_irqsave(&wl->irq_lock, flags);
2876         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2877         /* XXX: why? */
2878         mmiowb();
2879         spin_unlock_irqrestore(&wl->irq_lock, flags);
2880  out_unlock_mutex:
2881         mutex_unlock(&wl->mutex);
2882 }
2883
2884 static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2885                                           unsigned int changed,
2886                                           unsigned int *fflags,u64 multicast)
2887 {
2888         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2889         struct b43legacy_wldev *dev = wl->current_dev;
2890         unsigned long flags;
2891
2892         if (!dev) {
2893                 *fflags = 0;
2894                 return;
2895         }
2896
2897         spin_lock_irqsave(&wl->irq_lock, flags);
2898         *fflags &= FIF_PROMISC_IN_BSS |
2899                   FIF_ALLMULTI |
2900                   FIF_FCSFAIL |
2901                   FIF_PLCPFAIL |
2902                   FIF_CONTROL |
2903                   FIF_OTHER_BSS |
2904                   FIF_BCN_PRBRESP_PROMISC;
2905
2906         changed &= FIF_PROMISC_IN_BSS |
2907                    FIF_ALLMULTI |
2908                    FIF_FCSFAIL |
2909                    FIF_PLCPFAIL |
2910                    FIF_CONTROL |
2911                    FIF_OTHER_BSS |
2912                    FIF_BCN_PRBRESP_PROMISC;
2913
2914         wl->filter_flags = *fflags;
2915
2916         if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2917                 b43legacy_adjust_opmode(dev);
2918         spin_unlock_irqrestore(&wl->irq_lock, flags);
2919 }
2920
2921 /* Locking: wl->mutex */
2922 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2923 {
2924         struct b43legacy_wl *wl = dev->wl;
2925         unsigned long flags;
2926         int queue_num;
2927
2928         if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2929                 return;
2930
2931         /* Disable and sync interrupts. We must do this before than
2932          * setting the status to INITIALIZED, as the interrupt handler
2933          * won't care about IRQs then. */
2934         spin_lock_irqsave(&wl->irq_lock, flags);
2935         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2936         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2937         spin_unlock_irqrestore(&wl->irq_lock, flags);
2938         b43legacy_synchronize_irq(dev);
2939
2940         b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2941
2942         mutex_unlock(&wl->mutex);
2943         /* Must unlock as it would otherwise deadlock. No races here.
2944          * Cancel the possibly running self-rearming periodic work. */
2945         cancel_delayed_work_sync(&dev->periodic_work);
2946         cancel_work_sync(&wl->tx_work);
2947         mutex_lock(&wl->mutex);
2948
2949         /* Drain all TX queues. */
2950         for (queue_num = 0; queue_num < B43legacy_QOS_QUEUE_NUM; queue_num++) {
2951                 while (skb_queue_len(&wl->tx_queue[queue_num]))
2952                         dev_kfree_skb(skb_dequeue(&wl->tx_queue[queue_num]));
2953         }
2954
2955 b43legacy_mac_suspend(dev);
2956         free_irq(dev->dev->irq, dev);
2957         b43legacydbg(wl, "Wireless interface stopped\n");
2958 }
2959
2960 /* Locking: wl->mutex */
2961 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2962 {
2963         int err;
2964
2965         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2966
2967         drain_txstatus_queue(dev);
2968         err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2969                           IRQF_SHARED, KBUILD_MODNAME, dev);
2970         if (err) {
2971                 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2972                        dev->dev->irq);
2973                 goto out;
2974         }
2975         /* We are ready to run. */
2976         ieee80211_wake_queues(dev->wl->hw);
2977         b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2978
2979         /* Start data flow (TX/RX) */
2980         b43legacy_mac_enable(dev);
2981         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2982
2983         /* Start maintenance work */
2984         b43legacy_periodic_tasks_setup(dev);
2985
2986         b43legacydbg(dev->wl, "Wireless interface started\n");
2987 out:
2988         return err;
2989 }
2990
2991 /* Get PHY and RADIO versioning numbers */