drivers/net/wireless/b43/phy_a.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11a PHY driver
   5
   6   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
   7   Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
   8   Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
   9   Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
  10   Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  11
  12   This program is free software; you can redistribute it and/or modify
  13   it under the terms of the GNU General Public License as published by
  14   the Free Software Foundation; either version 2 of the License, or
  15   (at your option) any later version.
  16
  17   This program is distributed in the hope that it will be useful,
  18   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20   GNU General Public License for more details.
  21
  22   You should have received a copy of the GNU General Public License
  23   along with this program; see the file COPYING.  If not, write to
  24   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  25   Boston, MA 02110-1301, USA.
  26
  27 */
  28
  29 #include <linux/slab.h>
  30
  31 #include "b43.h"
  32 #include "phy_a.h"
  33 #include "phy_common.h"
  34 #include "wa.h"
  35 #include "tables.h"
  36 #include "main.h"
  37
  38
  39 /* Get the freq, as it has to be written to the device. */
  40 static inline u16 channel2freq_a(u8 channel)
  41 {
  42         B43_WARN_ON(channel > 200);
  43
  44         return (5000 + 5 * channel);
  45 }
  46
  47 static inline u16 freq_r3A_value(u16 frequency)
  48 {
  49         u16 value;
  50
  51         if (frequency < 5091)
  52                 value = 0x0040;
  53         else if (frequency < 5321)
  54                 value = 0x0000;
  55         else if (frequency < 5806)
  56                 value = 0x0080;
  57         else
  58                 value = 0x0040;
  59
  60         return value;
  61 }
  62
  63 #if 0
  64 /* This function converts a TSSI value to dBm in Q5.2 */
  65 static s8 b43_aphy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
  66 {
  67         struct b43_phy *phy = &dev->phy;
  68         struct b43_phy_a *aphy = phy->a;
  69         s8 dbm = 0;
  70         s32 tmp;
  71
  72         tmp = (aphy->tgt_idle_tssi - aphy->cur_idle_tssi + tssi);
  73         tmp += 0x80;
  74         tmp = clamp_val(tmp, 0x00, 0xFF);
  75         dbm = aphy->tssi2dbm[tmp];
  76         //TODO: There's a FIXME on the specs
  77
  78         return dbm;
  79 }
  80 #endif
  81
  82 static void b43_radio_set_tx_iq(struct b43_wldev *dev)
  83 {
  84         static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
  85         static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
  86         u16 tmp = b43_radio_read16(dev, 0x001E);
  87         int i, j;
  88
  89         for (i = 0; i < 5; i++) {
  90                 for (j = 0; j < 5; j++) {
  91                         if (tmp == (data_high[i] << 4 | data_low[j])) {
  92                                 b43_phy_write(dev, 0x0069,
  93                                               (i - j) << 8 | 0x00C0);
  94                                 return;
  95                         }
  96                 }
  97         }
  98 }
  99
 100 static void aphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 101 {
 102         u16 freq, r8, tmp;
 103
 104         freq = channel2freq_a(channel);
 105
 106         r8 = b43_radio_read16(dev, 0x0008);
 107         b43_write16(dev, 0x03F0, freq);
 108         b43_radio_write16(dev, 0x0008, r8);
 109
 110         //TODO: write max channel TX power? to Radio 0x2D
 111         tmp = b43_radio_read16(dev, 0x002E);
 112         tmp &= 0x0080;
 113         //TODO: OR tmp with the Power out estimation for this channel?
 114         b43_radio_write16(dev, 0x002E, tmp);
 115
 116         if (freq >= 4920 && freq <= 5500) {
 117                 /*
 118                  * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
 119                  *    = (freq * 0.025862069
 120                  */
 121                 r8 = 3 * freq / 116;    /* is equal to r8 = freq * 0.025862 */
 122         }
 123         b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
 124         b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
 125         b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
 126         b43_radio_maskset(dev, 0x0022, 0x000F, (r8 << 4));
 127         b43_radio_write16(dev, 0x002A, (r8 << 4));
 128         b43_radio_write16(dev, 0x002B, (r8 << 4));
 129         b43_radio_maskset(dev, 0x0008, 0x00F0, (r8 << 4));
 130         b43_radio_maskset(dev, 0x0029, 0xFF0F, 0x00B0);
 131         b43_radio_write16(dev, 0x0035, 0x00AA);
 132         b43_radio_write16(dev, 0x0036, 0x0085);
 133         b43_radio_maskset(dev, 0x003A, 0xFF20, freq_r3A_value(freq));
 134         b43_radio_mask(dev, 0x003D, 0x00FF);
 135         b43_radio_maskset(dev, 0x0081, 0xFF7F, 0x0080);
 136         b43_radio_mask(dev, 0x0035, 0xFFEF);
 137         b43_radio_maskset(dev, 0x0035, 0xFFEF, 0x0010);
 138         b43_radio_set_tx_iq(dev);
 139         //TODO: TSSI2dbm workaround
 140 //FIXME b43_phy_xmitpower(dev);
 141 }
 142
 143 static void b43_radio_init2060(struct b43_wldev *dev)
 144 {
 145         b43_radio_write16(dev, 0x0004, 0x00C0);
 146         b43_radio_write16(dev, 0x0005, 0x0008);
 147         b43_radio_write16(dev, 0x0009, 0x0040);
 148         b43_radio_write16(dev, 0x0005, 0x00AA);
 149         b43_radio_write16(dev, 0x0032, 0x008F);
 150         b43_radio_write16(dev, 0x0006, 0x008F);
 151         b43_radio_write16(dev, 0x0034, 0x008F);
 152         b43_radio_write16(dev, 0x002C, 0x0007);
 153         b43_radio_write16(dev, 0x0082, 0x0080);
 154         b43_radio_write16(dev, 0x0080, 0x0000);
 155         b43_radio_write16(dev, 0x003F, 0x00DA);
 156         b43_radio_mask(dev, 0x0005, ~0x0008);
 157         b43_radio_mask(dev, 0x0081, ~0x0010);
 158         b43_radio_mask(dev, 0x0081, ~0x0020);
 159         b43_radio_mask(dev, 0x0081, ~0x0020);
 160         msleep(1);              /* delay 400usec */
 161
 162         b43_radio_maskset(dev, 0x0081, ~0x0020, 0x0010);
 163         msleep(1);              /* delay 400usec */
 164
 165         b43_radio_maskset(dev, 0x0005, ~0x0008, 0x0008);
 166         b43_radio_mask(dev, 0x0085, ~0x0010);
 167         b43_radio_mask(dev, 0x0005, ~0x0008);
 168         b43_radio_mask(dev, 0x0081, ~0x0040);
 169         b43_radio_maskset(dev, 0x0081, ~0x0040, 0x0040);
 170         b43_radio_write16(dev, 0x0005,
 171                           (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
 172         b43_phy_write(dev, 0x0063, 0xDDC6);
 173         b43_phy_write(dev, 0x0069, 0x07BE);
 174         b43_phy_write(dev, 0x006A, 0x0000);
 175
 176         aphy_channel_switch(dev, dev->phy.ops->get_default_chan(dev));
 177
 178         msleep(1);
 179 }
 180
 181 static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable)
 182 {
 183         int i;
 184
 185         if (dev->phy.rev < 3) {
 186                 if (enable)
 187                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
 188                                 b43_ofdmtab_write16(dev,
 189                                         B43_OFDMTAB_LNAHPFGAIN1, i, 0xFFF8);
 190                                 b43_ofdmtab_write16(dev,
 191                                         B43_OFDMTAB_WRSSI, i, 0xFFF8);
 192                         }
 193                 else
 194                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
 195                                 b43_ofdmtab_write16(dev,
 196                                         B43_OFDMTAB_LNAHPFGAIN1, i, b43_tab_rssiagc1[i]);
 197                                 b43_ofdmtab_write16(dev,
 198                                         B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc1[i]);
 199                         }
 200         } else {
 201                 if (enable)
 202                         for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++)
 203                                 b43_ofdmtab_write16(dev,
 204                                         B43_OFDMTAB_WRSSI, i, 0x0820);
 205                 else
 206                         for (i = 0; i < B43_TAB_RSSIAGC2_SIZE; i++)
 207                                 b43_ofdmtab_write16(dev,
 208                                         B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc2[i]);
 209         }
 210 }
 211
 212 static void b43_phy_ww(struct b43_wldev *dev)
 213 {
 214         u16 b, curr_s, best_s = 0xFFFF;
 215         int i;
 216
 217         b43_phy_mask(dev, B43_PHY_CRS0, ~B43_PHY_CRS0_EN);
 218         b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000);
 219         b43_phy_maskset(dev, B43_PHY_OFDM(0x82), 0xF0FF, 0x0300);
 220         b43_radio_set(dev, 0x0009, 0x0080);
 221         b43_radio_maskset(dev, 0x0012, 0xFFFC, 0x0002);
 222         b43_wa_initgains(dev);
 223         b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5);
 224         b = b43_phy_read(dev, B43_PHY_PWRDOWN);
 225         b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005);
 226         b43_radio_set(dev, 0x0004, 0x0004);
 227         for (i = 0x10; i <= 0x20; i++) {
 228                 b43_radio_write16(dev, 0x0013, i);
 229                 curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF;
 230                 if (!curr_s) {
 231                         best_s = 0x0000;
 232                         break;
 233                 } else if (curr_s >= 0x0080)
 234                         curr_s = 0x0100 - curr_s;
 235                 if (curr_s < best_s)
 236                         best_s = curr_s;
 237         }
 238         b43_phy_write(dev, B43_PHY_PWRDOWN, b);
 239         b43_radio_mask(dev, 0x0004, 0xFFFB);
 240         b43_radio_write16(dev, 0x0013, best_s);
 241         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC);
 242         b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80);
 243         b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00);
 244         b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);
 245         b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);
 246         b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);
 247         b43_phy_maskset(dev, B43_PHY_OFDM(0xBB), 0xF000, 0x0053);
 248         b43_phy_maskset(dev, B43_PHY_OFDM61, 0xFE1F, 0x0120);
 249         b43_phy_maskset(dev, B43_PHY_OFDM(0x13), 0x0FFF, 0x3000);
 250         b43_phy_maskset(dev, B43_PHY_OFDM(0x14), 0x0FFF, 0x3000);
 251         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);
 252         for (i = 0; i < 6; i++)
 253                 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);
 254         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E);
 255         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011);
 256         b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013);
 257         b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030);
 258         b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);
 259 }
 260
 261 static void hardware_pctl_init_aphy(struct b43_wldev *dev)
 262 {
 263         //TODO
 264 }
 265
 266 void b43_phy_inita(struct b43_wldev *dev)
 267 {
 268         struct b43_phy *phy = &dev->phy;
 269
 270         /* This lowlevel A-PHY init is also called from G-PHY init.
 271          * So we must not access phy->a, if called from G-PHY code.
 272          */
 273         B43_WARN_ON((phy->type != B43_PHYTYPE_A) &&
 274                     (phy->type != B43_PHYTYPE_G));
 275
 276         might_sleep();
 277
 278         if (phy->rev >= 6) {
 279                 if (phy->type == B43_PHYTYPE_A)
 280                         b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x1000);
 281                 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
 282                         b43_phy_set(dev, B43_PHY_ENCORE, 0x0010);
 283                 else
 284                         b43_phy_mask(dev, B43_PHY_ENCORE, ~0x1010);
 285         }
 286
 287         b43_wa_all(dev);
 288
 289         if (phy->type == B43_PHYTYPE_A) {
 290                 if (phy->gmode && (phy->rev < 3))
 291                         b43_phy_set(dev, 0x0034, 0x0001);
 292                 b43_phy_rssiagc(dev, 0);
 293
 294                 b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);
 295
 296                 b43_radio_init2060(dev);
 297
 298                 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
 299                     ((dev->dev->board_type == SSB_BOARD_BU4306) ||
 300                      (dev->dev->board_type == SSB_BOARD_BU4309))) {
 301                         ; //TODO: A PHY LO
 302                 }
 303
 304                 if (phy->rev >= 3)
 305                         b43_phy_ww(dev);
 306
 307                 hardware_pctl_init_aphy(dev);
 308
 309                 //TODO: radar detection
 310         }
 311
 312         if ((phy->type == B43_PHYTYPE_G) &&
 313             (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL)) {
 314                 b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF);
 315         }
 316 }
 317
 318 /* Initialise the TSSI->dBm lookup table */
 319 static int b43_aphy_init_tssi2dbm_table(struct b43_wldev *dev)
 320 {
 321         struct b43_phy *phy = &dev->phy;
 322         struct b43_phy_a *aphy = phy->a;
 323         s16 pab0, pab1, pab2;
 324
 325         pab0 = (s16) (dev->dev->bus_sprom->pa1b0);
 326         pab1 = (s16) (dev->dev->bus_sprom->pa1b1);
 327         pab2 = (s16) (dev->dev->bus_sprom->pa1b2);
 328
 329         if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
 330             pab0 != -1 && pab1 != -1 && pab2 != -1) {
 331                 /* The pabX values are set in SPROM. Use them. */
 332                 if ((s8) dev->dev->bus_sprom->itssi_a != 0 &&
 333                     (s8) dev->dev->bus_sprom->itssi_a != -1)
 334                         aphy->tgt_idle_tssi =
 335                             (s8) (dev->dev->bus_sprom->itssi_a);
 336                 else
 337                         aphy->tgt_idle_tssi = 62;
 338                 aphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
 339                                                                pab1, pab2);
 340                 if (!aphy->tssi2dbm)
 341                         return -ENOMEM;
 342         } else {
 343                 /* pabX values not set in SPROM,
 344                  * but APHY needs a generated table. */
 345                 aphy->tssi2dbm = NULL;
 346                 b43err(dev->wl, "Could not generate tssi2dBm "
 347                        "table (wrong SPROM info)!\n");
 348                 return -ENODEV;
 349         }
 350
 351         return 0;
 352 }
 353
 354 static int b43_aphy_op_allocate(struct b43_wldev *dev)
 355 {
 356         struct b43_phy_a *aphy;
 357         int err;
 358
 359         aphy = kzalloc(sizeof(*aphy), GFP_KERNEL);
 360         if (!aphy)
 361                 return -ENOMEM;
 362         dev->phy.a = aphy;
 363
 364         err = b43_aphy_init_tssi2dbm_table(dev);
 365         if (err)
 366                 goto err_free_aphy;
 367
 368         return 0;
 369
 370 err_free_aphy:
 371         kfree(aphy);
 372         dev->phy.a = NULL;
 373
 374         return err;
 375 }
 376
 377 static void b43_aphy_op_prepare_structs(struct b43_wldev *dev)
 378 {
 379         struct b43_phy *phy = &dev->phy;
 380         struct b43_phy_a *aphy = phy->a;
 381         const void *tssi2dbm;
 382         int tgt_idle_tssi;
 383
 384         /* tssi2dbm table is constant, so it is initialized at alloc time.
 385          * Save a copy of the pointer. */
 386         tssi2dbm = aphy->tssi2dbm;
 387         tgt_idle_tssi = aphy->tgt_idle_tssi;
 388
 389         /* Zero out the whole PHY structure. */
 390         memset(aphy, 0, sizeof(*aphy));
 391
 392         aphy->tssi2dbm = tssi2dbm;
 393         aphy->tgt_idle_tssi = tgt_idle_tssi;
 394
 395         //TODO init struct b43_phy_a
 396
 397 }
 398
 399 static void b43_aphy_op_free(struct b43_wldev *dev)
 400 {
 401         struct b43_phy *phy = &dev->phy;
 402         struct b43_phy_a *aphy = phy->a;
 403
 404         kfree(aphy->tssi2dbm);
 405         aphy->tssi2dbm = NULL;
 406
 407         kfree(aphy);
 408         dev->phy.a = NULL;
 409 }
 410
 411 static int b43_aphy_op_init(struct b43_wldev *dev)
 412 {
 413         b43_phy_inita(dev);
 414
 415         return 0;
 416 }
 417
 418 static inline u16 adjust_phyreg(struct b43_wldev *dev, u16 offset)
 419 {
 420         /* OFDM registers are base-registers for the A-PHY. */
 421         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
 422                 offset &= ~B43_PHYROUTE;
 423                 offset |= B43_PHYROUTE_BASE;
 424         }
 425
 426 #if B43_DEBUG
 427         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
 428                 /* Ext-G registers are only available on G-PHYs */
 429                 b43err(dev->wl, "Invalid EXT-G PHY access at "
 430                        "0x%04X on A-PHY\n", offset);
 431                 dump_stack();
 432         }
 433         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) {
 434                 /* N-BMODE registers are only available on N-PHYs */
 435                 b43err(dev->wl, "Invalid N-BMODE PHY access at "
 436                        "0x%04X on A-PHY\n", offset);
 437                 dump_stack();
 438         }
 439 #endif /* B43_DEBUG */
 440
 441         return offset;
 442 }
 443
 444 static u16 b43_aphy_op_read(struct b43_wldev *dev, u16 reg)
 445 {
 446         reg = adjust_phyreg(dev, reg);
 447         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 448         return b43_read16(dev, B43_MMIO_PHY_DATA);
 449 }
 450
 451 static void b43_aphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 452 {
 453         reg = adjust_phyreg(dev, reg);
 454         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 455         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 456 }
 457
 458 static u16 b43_aphy_op_radio_read(struct b43_wldev *dev, u16 reg)
 459 {
 460         /* Register 1 is a 32-bit register. */
 461         B43_WARN_ON(reg == 1);
 462         /* A-PHY needs 0x40 for read access */
 463         reg |= 0x40;
 464
 465         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 466         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
 467 }
 468
 469 static void b43_aphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
 470 {
 471         /* Register 1 is a 32-bit register. */
 472         B43_WARN_ON(reg == 1);
 473
 474         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 475         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
 476 }
 477
 478 static bool b43_aphy_op_supports_hwpctl(struct b43_wldev *dev)
 479 {
 480         return (dev->phy.rev >= 5);
 481 }
 482
 483 static void b43_aphy_op_software_rfkill(struct b43_wldev *dev,
 484                                         bool blocked)
 485 {
 486         struct b43_phy *phy = &dev->phy;
 487
 488         if (!blocked) {
 489                 if (phy->radio_on)
 490                         return;
 491                 b43_radio_write16(dev, 0x0004, 0x00C0);
 492                 b43_radio_write16(dev, 0x0005, 0x0008);
 493                 b43_phy_mask(dev, 0x0010, 0xFFF7);
 494                 b43_phy_mask(dev, 0x0011, 0xFFF7);
 495                 b43_radio_init2060(dev);
 496         } else {
 497                 b43_radio_write16(dev, 0x0004, 0x00FF);
 498                 b43_radio_write16(dev, 0x0005, 0x00FB);
 499                 b43_phy_set(dev, 0x0010, 0x0008);
 500                 b43_phy_set(dev, 0x0011, 0x0008);
 501         }
 502 }
 503
 504 static int b43_aphy_op_switch_channel(struct b43_wldev *dev,
 505                                       unsigned int new_channel)
 506 {
 507         if (new_channel > 200)
 508                 return -EINVAL;
 509         aphy_channel_switch(dev, new_channel);
 510
 511         return 0;
 512 }
 513
 514 static unsigned int b43_aphy_op_get_default_chan(struct b43_wldev *dev)
 515 {
 516         return 36; /* Default to channel 36 */
 517 }
 518
 519 static void b43_aphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
 520 {//TODO
 521         struct b43_phy *phy = &dev->phy;
 522         u16 tmp;
 523         int autodiv = 0;
 524
 525         if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
 526                 autodiv = 1;
 527
 528         b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP);
 529
 530         b43_phy_maskset(dev, B43_PHY_BBANDCFG, ~B43_PHY_BBANDCFG_RXANT,
 531                         (autodiv ? B43_ANTENNA_AUTO1 : antenna) <<
 532                         B43_PHY_BBANDCFG_RXANT_SHIFT);
 533
 534         if (autodiv) {
 535                 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
 536                 if (antenna == B43_ANTENNA_AUTO1)
 537                         tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
 538                 else
 539                         tmp |= B43_PHY_ANTDWELL_AUTODIV1;
 540                 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
 541         }
 542         if (phy->rev < 3)
 543                 b43_phy_maskset(dev, B43_PHY_ANTDWELL, 0xFF00, 0x24);
 544         else {
 545                 b43_phy_set(dev, B43_PHY_OFDM61, 0x10);
 546                 if (phy->rev == 3) {
 547                         b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT, 0x1D);
 548                         b43_phy_write(dev, B43_PHY_ADIVRELATED, 8);
 549                 } else {
 550                         b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT, 0x3A);
 551                         b43_phy_maskset(dev, B43_PHY_ADIVRELATED, 0xFF00, 8);
 552                 }
 553         }
 554
 555         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP);
 556 }
 557
 558 static void b43_aphy_op_adjust_txpower(struct b43_wldev *dev)
 559 {//TODO
 560 }
 561
 562 static enum b43_txpwr_result b43_aphy_op_recalc_txpower(struct b43_wldev *dev,
 563                                                         bool ignore_tssi)
 564 {//TODO
 565         return B43_TXPWR_RES_DONE;
 566 }
 567
 568 static void b43_aphy_op_pwork_15sec(struct b43_wldev *dev)
 569 {//TODO
 570 }
 571
 572 static void b43_aphy_op_pwork_60sec(struct b43_wldev *dev)
 573 {//TODO
 574 }
 575
 576 const struct b43_phy_operations b43_phyops_a = {
 577         .allocate               = b43_aphy_op_allocate,
 578         .free                   = b43_aphy_op_free,
 579         .prepare_structs        = b43_aphy_op_prepare_structs,
 580         .init                   = b43_aphy_op_init,
 581         .phy_read               = b43_aphy_op_read,
 582         .phy_write              = b43_aphy_op_write,
 583         .radio_read             = b43_aphy_op_radio_read,
 584         .radio_write            = b43_aphy_op_radio_write,
 585         .supports_hwpctl        = b43_aphy_op_supports_hwpctl,
 586         .software_rfkill        = b43_aphy_op_software_rfkill,
 587         .switch_analog          = b43_phyop_switch_analog_generic,
 588         .switch_channel         = b43_aphy_op_switch_channel,
 589         .get_default_chan       = b43_aphy_op_get_default_chan,
 590         .set_rx_antenna         = b43_aphy_op_set_rx_antenna,
 591         .recalc_txpower         = b43_aphy_op_recalc_txpower,
 592         .adjust_txpower         = b43_aphy_op_adjust_txpower,
 593         .pwork_15sec            = b43_aphy_op_pwork_15sec,
 594         .pwork_60sec            = b43_aphy_op_pwork_60sec,
 595 };