drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20 #include "hw.h"
  21
  22 #define ATH_PCI_VERSION "0.1"
  23
  24 static char *dev_info = "ath9k";
  25
  26 MODULE_AUTHOR("Atheros Communications");
  27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  29 MODULE_LICENSE("Dual BSD/GPL");
  30
  31 /* We use the hw_value as an index into our private channel structure */
  32
  33 #define CHAN2G(_freq, _idx)  { \
  34         .center_freq = (_freq), \
  35         .hw_value = (_idx), \
  36         .max_power = 30, \
  37 }
  38
  39 #define CHAN5G(_freq, _idx) { \
  40         .band = IEEE80211_BAND_5GHZ, \
  41         .center_freq = (_freq), \
  42         .hw_value = (_idx), \
  43         .max_power = 30, \
  44 }
  45
  46 /* Some 2 GHz radios are actually tunable on 2312-2732
  47  * on 5 MHz steps, we support the channels which we know
  48  * we have calibration data for all cards though to make
  49  * this static */
  50 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  51         CHAN2G(2412, 0), /* Channel 1 */
  52         CHAN2G(2417, 1), /* Channel 2 */
  53         CHAN2G(2422, 2), /* Channel 3 */
  54         CHAN2G(2427, 3), /* Channel 4 */
  55         CHAN2G(2432, 4), /* Channel 5 */
  56         CHAN2G(2437, 5), /* Channel 6 */
  57         CHAN2G(2442, 6), /* Channel 7 */
  58         CHAN2G(2447, 7), /* Channel 8 */
  59         CHAN2G(2452, 8), /* Channel 9 */
  60         CHAN2G(2457, 9), /* Channel 10 */
  61         CHAN2G(2462, 10), /* Channel 11 */
  62         CHAN2G(2467, 11), /* Channel 12 */
  63         CHAN2G(2472, 12), /* Channel 13 */
  64         CHAN2G(2484, 13), /* Channel 14 */
  65 };
  66
  67 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  68  * on 5 MHz steps, we support the channels which we know
  69  * we have calibration data for all cards though to make
  70  * this static */
  71 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  72         /* _We_ call this UNII 1 */
  73         CHAN5G(5180, 14), /* Channel 36 */
  74         CHAN5G(5200, 15), /* Channel 40 */
  75         CHAN5G(5220, 16), /* Channel 44 */
  76         CHAN5G(5240, 17), /* Channel 48 */
  77         /* _We_ call this UNII 2 */
  78         CHAN5G(5260, 18), /* Channel 52 */
  79         CHAN5G(5280, 19), /* Channel 56 */
  80         CHAN5G(5300, 20), /* Channel 60 */
  81         CHAN5G(5320, 21), /* Channel 64 */
  82         /* _We_ call this "Middle band" */
  83         CHAN5G(5500, 22), /* Channel 100 */
  84         CHAN5G(5520, 23), /* Channel 104 */
  85         CHAN5G(5540, 24), /* Channel 108 */
  86         CHAN5G(5560, 25), /* Channel 112 */
  87         CHAN5G(5580, 26), /* Channel 116 */
  88         CHAN5G(5600, 27), /* Channel 120 */
  89         CHAN5G(5620, 28), /* Channel 124 */
  90         CHAN5G(5640, 29), /* Channel 128 */
  91         CHAN5G(5660, 30), /* Channel 132 */
  92         CHAN5G(5680, 31), /* Channel 136 */
  93         CHAN5G(5700, 32), /* Channel 140 */
  94         /* _We_ call this UNII 3 */
  95         CHAN5G(5745, 33), /* Channel 149 */
  96         CHAN5G(5765, 34), /* Channel 153 */
  97         CHAN5G(5785, 35), /* Channel 157 */
  98         CHAN5G(5805, 36), /* Channel 161 */
  99         CHAN5G(5825, 37), /* Channel 165 */
 100 };
 101
 102 static void ath_cache_conf_rate(struct ath_softc *sc,
 103                                 struct ieee80211_conf *conf)
 104 {
 105         switch (conf->channel->band) {
 106         case IEEE80211_BAND_2GHZ:
 107                 if (conf_is_ht20(conf))
 108                         sc->cur_rate_table =
 109                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 110                 else if (conf_is_ht40_minus(conf))
 111                         sc->cur_rate_table =
 112                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 113                 else if (conf_is_ht40_plus(conf))
 114                         sc->cur_rate_table =
 115                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 116                 else
 117                         sc->cur_rate_table =
 118                           sc->hw_rate_table[ATH9K_MODE_11G];
 119                 break;
 120         case IEEE80211_BAND_5GHZ:
 121                 if (conf_is_ht20(conf))
 122                         sc->cur_rate_table =
 123                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 124                 else if (conf_is_ht40_minus(conf))
 125                         sc->cur_rate_table =
 126                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 127                 else if (conf_is_ht40_plus(conf))
 128                         sc->cur_rate_table =
 129                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 130                 else
 131                         sc->cur_rate_table =
 132                           sc->hw_rate_table[ATH9K_MODE_11A];
 133                 break;
 134         default:
 135                 BUG_ON(1);
 136                 break;
 137         }
 138 }
 139
 140 static void ath_update_txpow(struct ath_softc *sc)
 141 {
 142         struct ath_hal *ah = sc->sc_ah;
 143         u32 txpow;
 144
 145         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 146                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 147                 /* read back in case value is clamped */
 148                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 149                 sc->sc_curtxpow = txpow;
 150         }
 151 }
 152
 153 static u8 parse_mpdudensity(u8 mpdudensity)
 154 {
 155         /*
 156          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 157          *   0 for no restriction
 158          *   1 for 1/4 us
 159          *   2 for 1/2 us
 160          *   3 for 1 us
 161          *   4 for 2 us
 162          *   5 for 4 us
 163          *   6 for 8 us
 164          *   7 for 16 us
 165          */
 166         switch (mpdudensity) {
 167         case 0:
 168                 return 0;
 169         case 1:
 170         case 2:
 171         case 3:
 172                 /* Our lower layer calculations limit our precision to
 173                    1 microsecond */
 174                 return 1;
 175         case 4:
 176                 return 2;
 177         case 5:
 178                 return 4;
 179         case 6:
 180                 return 8;
 181         case 7:
 182                 return 16;
 183         default:
 184                 return 0;
 185         }
 186 }
 187
 188 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 189 {
 190         struct ath_rate_table *rate_table = NULL;
 191         struct ieee80211_supported_band *sband;
 192         struct ieee80211_rate *rate;
 193         int i, maxrates;
 194
 195         switch (band) {
 196         case IEEE80211_BAND_2GHZ:
 197                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 198                 break;
 199         case IEEE80211_BAND_5GHZ:
 200                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 201                 break;
 202         default:
 203                 break;
 204         }
 205
 206         if (rate_table == NULL)
 207                 return;
 208
 209         sband = &sc->sbands[band];
 210         rate = sc->rates[band];
 211
 212         if (rate_table->rate_cnt > ATH_RATE_MAX)
 213                 maxrates = ATH_RATE_MAX;
 214         else
 215                 maxrates = rate_table->rate_cnt;
 216
 217         for (i = 0; i < maxrates; i++) {
 218                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 219                 rate[i].hw_value = rate_table->info[i].ratecode;
 220                 sband->n_bitrates++;
 221                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 222                         rate[i].bitrate / 10, rate[i].hw_value);
 223         }
 224 }
 225
 226 /*
 227  * Set/change channels.  If the channel is really being changed, it's done
 228  * by reseting the chip.  To accomplish this we must first cleanup any pending
 229  * DMA, then restart stuff.
 230 */
 231 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 232 {
 233         struct ath_hal *ah = sc->sc_ah;
 234         bool fastcc = true, stopped;
 235         struct ieee80211_hw *hw = sc->hw;
 236         struct ieee80211_channel *channel = hw->conf.channel;
 237         int r;
 238
 239         if (sc->sc_flags & SC_OP_INVALID)
 240                 return -EIO;
 241
 242         ath9k_ps_wakeup(sc);
 243
 244         /*
 245          * This is only performed if the channel settings have
 246          * actually changed.
 247          *
 248          * To switch channels clear any pending DMA operations;
 249          * wait long enough for the RX fifo to drain, reset the
 250          * hardware at the new frequency, and then re-enable
 251          * the relevant bits of the h/w.
 252          */
 253         ath9k_hw_set_interrupts(ah, 0);
 254         ath_drain_all_txq(sc, false);
 255         stopped = ath_stoprecv(sc);
 256
 257         /* XXX: do not flush receive queue here. We don't want
 258          * to flush data frames already in queue because of
 259          * changing channel. */
 260
 261         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 262                 fastcc = false;
 263
 264         DPRINTF(sc, ATH_DBG_CONFIG,
 265                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 266                 sc->sc_ah->ah_curchan->channel,
 267                 channel->center_freq, sc->tx_chan_width);
 268
 269         spin_lock_bh(&sc->sc_resetlock);
 270
 271         r = ath9k_hw_reset(ah, hchan, fastcc);
 272         if (r) {
 273                 DPRINTF(sc, ATH_DBG_FATAL,
 274                         "Unable to reset channel (%u Mhz) "
 275                         "reset status %u\n",
 276                         channel->center_freq, r);
 277                 spin_unlock_bh(&sc->sc_resetlock);
 278                 return r;
 279         }
 280         spin_unlock_bh(&sc->sc_resetlock);
 281
 282         sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 283         sc->sc_flags &= ~SC_OP_FULL_RESET;
 284
 285         if (ath_startrecv(sc) != 0) {
 286                 DPRINTF(sc, ATH_DBG_FATAL,
 287                         "Unable to restart recv logic\n");
 288                 return -EIO;
 289         }
 290
 291         ath_cache_conf_rate(sc, &hw->conf);
 292         ath_update_txpow(sc);
 293         ath9k_hw_set_interrupts(ah, sc->sc_imask);
 294         ath9k_ps_restore(sc);
 295         return 0;
 296 }
 297
 298 /*
 299  *  This routine performs the periodic noise floor calibration function
 300  *  that is used to adjust and optimize the chip performance.  This
 301  *  takes environmental changes (location, temperature) into account.
 302  *  When the task is complete, it reschedules itself depending on the
 303  *  appropriate interval that was calculated.
 304  */
 305 static void ath_ani_calibrate(unsigned long data)
 306 {
 307         struct ath_softc *sc;
 308         struct ath_hal *ah;
 309         bool longcal = false;
 310         bool shortcal = false;
 311         bool aniflag = false;
 312         unsigned int timestamp = jiffies_to_msecs(jiffies);
 313         u32 cal_interval;
 314
 315         sc = (struct ath_softc *)data;
 316         ah = sc->sc_ah;
 317
 318         /*
 319         * don't calibrate when we're scanning.
 320         * we are most likely not on our home channel.
 321         */
 322         if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
 323                 return;
 324
 325         /* Long calibration runs independently of short calibration. */
 326         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 327                 longcal = true;
 328                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 329                 sc->sc_ani.sc_longcal_timer = timestamp;
 330         }
 331
 332         /* Short calibration applies only while sc_caldone is false */
 333         if (!sc->sc_ani.sc_caldone) {
 334                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 335                     ATH_SHORT_CALINTERVAL) {
 336                         shortcal = true;
 337                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 338                         sc->sc_ani.sc_shortcal_timer = timestamp;
 339                         sc->sc_ani.sc_resetcal_timer = timestamp;
 340                 }
 341         } else {
 342                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 343                     ATH_RESTART_CALINTERVAL) {
 344                         sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
 345                         if (sc->sc_ani.sc_caldone)
 346                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 347                 }
 348         }
 349
 350         /* Verify whether we must check ANI */
 351         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 352            ATH_ANI_POLLINTERVAL) {
 353                 aniflag = true;
 354                 sc->sc_ani.sc_checkani_timer = timestamp;
 355         }
 356
 357         /* Skip all processing if there's nothing to do. */
 358         if (longcal || shortcal || aniflag) {
 359                 /* Call ANI routine if necessary */
 360                 if (aniflag)
 361                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 362                                              ah->ah_curchan);
 363
 364                 /* Perform calibration if necessary */
 365                 if (longcal || shortcal) {
 366                         bool iscaldone = false;
 367
 368                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 369                                                sc->sc_rx_chainmask, longcal,
 370                                                &iscaldone)) {
 371                                 if (longcal)
 372                                         sc->sc_ani.sc_noise_floor =
 373                                                 ath9k_hw_getchan_noise(ah,
 374                                                                ah->ah_curchan);
 375
 376                                 DPRINTF(sc, ATH_DBG_ANI,
 377                                         "calibrate chan %u/%x nf: %d\n",
 378                                         ah->ah_curchan->channel,
 379                                         ah->ah_curchan->channelFlags,
 380                                         sc->sc_ani.sc_noise_floor);
 381                         } else {
 382                                 DPRINTF(sc, ATH_DBG_ANY,
 383                                         "calibrate chan %u/%x failed\n",
 384                                         ah->ah_curchan->channel,
 385                                         ah->ah_curchan->channelFlags);
 386                         }
 387                         sc->sc_ani.sc_caldone = iscaldone;
 388                 }
 389         }
 390
 391         /*
 392         * Set timer interval based on previous results.
 393         * The interval must be the shortest necessary to satisfy ANI,
 394         * short calibration and long calibration.
 395         */
 396         cal_interval = ATH_LONG_CALINTERVAL;
 397         if (sc->sc_ah->ah_config.enable_ani)
 398                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 399         if (!sc->sc_ani.sc_caldone)
 400                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 401
 402         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 403 }
 404
 405 /*
 406  * Update tx/rx chainmask. For legacy association,
 407  * hard code chainmask to 1x1, for 11n association, use
 408  * the chainmask configuration, for bt coexistence, use
 409  * the chainmask configuration even in legacy mode.
 410  */
 411 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 412 {
 413         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 414         if (is_ht ||
 415             (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 416                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 417                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 418         } else {
 419                 sc->sc_tx_chainmask = 1;
 420                 sc->sc_rx_chainmask = 1;
 421         }
 422
 423         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 424                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 425 }
 426
 427 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 428 {
 429         struct ath_node *an;
 430
 431         an = (struct ath_node *)sta->drv_priv;
 432
 433         if (sc->sc_flags & SC_OP_TXAGGR)
 434                 ath_tx_node_init(sc, an);
 435
 436         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 437                              sta->ht_cap.ampdu_factor);
 438         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 439 }
 440
 441 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 442 {
 443         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 444
 445         if (sc->sc_flags & SC_OP_TXAGGR)
 446                 ath_tx_node_cleanup(sc, an);
 447 }
 448
 449 static void ath9k_tasklet(unsigned long data)
 450 {
 451         struct ath_softc *sc = (struct ath_softc *)data;
 452         u32 status = sc->sc_intrstatus;
 453
 454         if (status & ATH9K_INT_FATAL) {
 455                 /* need a chip reset */
 456                 ath_reset(sc, false);
 457                 return;
 458         } else {
 459
 460                 if (status &
 461                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 462                         spin_lock_bh(&sc->rx.rxflushlock);
 463                         ath_rx_tasklet(sc, 0);
 464                         spin_unlock_bh(&sc->rx.rxflushlock);
 465                 }
 466                 /* XXX: optimize this */
 467                 if (status & ATH9K_INT_TX)
 468                         ath_tx_tasklet(sc);
 469         }
 470
 471         /* re-enable hardware interrupt */
 472         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 473 }
 474
 475 irqreturn_t ath_isr(int irq, void *dev)
 476 {
 477         struct ath_softc *sc = dev;
 478         struct ath_hal *ah = sc->sc_ah;
 479         enum ath9k_int status;
 480         bool sched = false;
 481
 482         do {
 483                 if (sc->sc_flags & SC_OP_INVALID) {
 484                         /*
 485                          * The hardware is not ready/present, don't
 486                          * touch anything. Note this can happen early
 487                          * on if the IRQ is shared.
 488                          */
 489                         return IRQ_NONE;
 490                 }
 491                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 492                         return IRQ_NONE;
 493                 }
 494
 495                 /*
 496                  * Figure out the reason(s) for the interrupt.  Note
 497                  * that the hal returns a pseudo-ISR that may include
 498                  * bits we haven't explicitly enabled so we mask the
 499                  * value to insure we only process bits we requested.
 500                  */
 501                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 502
 503                 status &= sc->sc_imask; /* discard unasked-for bits */
 504
 505                 /*
 506                  * If there are no status bits set, then this interrupt was not
 507                  * for me (should have been caught above).
 508                  */
 509                 if (!status)
 510                         return IRQ_NONE;
 511
 512                 sc->sc_intrstatus = status;
 513
 514                 if (status & ATH9K_INT_FATAL) {
 515                         /* need a chip reset */
 516                         sched = true;
 517                 } else if (status & ATH9K_INT_RXORN) {
 518                         /* need a chip reset */
 519                         sched = true;
 520                 } else {
 521                         if (status & ATH9K_INT_SWBA) {
 522                                 /* schedule a tasklet for beacon handling */
 523                                 tasklet_schedule(&sc->bcon_tasklet);
 524                         }
 525                         if (status & ATH9K_INT_RXEOL) {
 526                                 /*
 527                                  * NB: the hardware should re-read the link when
 528                                  *     RXE bit is written, but it doesn't work
 529                                  *     at least on older hardware revs.
 530                                  */
 531                                 sched = true;
 532                         }
 533
 534                         if (status & ATH9K_INT_TXURN)
 535                                 /* bump tx trigger level */
 536                                 ath9k_hw_updatetxtriglevel(ah, true);
 537                         /* XXX: optimize this */
 538                         if (status & ATH9K_INT_RX)
 539                                 sched = true;
 540                         if (status & ATH9K_INT_TX)
 541                                 sched = true;
 542                         if (status & ATH9K_INT_BMISS)
 543                                 sched = true;
 544                         /* carrier sense timeout */
 545                         if (status & ATH9K_INT_CST)
 546                                 sched = true;
 547                         if (status & ATH9K_INT_MIB) {
 548                                 /*
 549                                  * Disable interrupts until we service the MIB
 550                                  * interrupt; otherwise it will continue to
 551                                  * fire.
 552                                  */
 553                                 ath9k_hw_set_interrupts(ah, 0);
 554                                 /*
 555                                  * Let the hal handle the event. We assume
 556                                  * it will clear whatever condition caused
 557                                  * the interrupt.
 558                                  */
 559                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 560                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 561                         }
 562                         if (status & ATH9K_INT_TIM_TIMER) {
 563                                 if (!(ah->ah_caps.hw_caps &
 564                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 565                                         /* Clear RxAbort bit so that we can
 566                                          * receive frames */
 567                                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
 568                                         ath9k_hw_setrxabort(ah, 0);
 569                                         sched = true;
 570                                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 571                                 }
 572                         }
 573                 }
 574         } while (0);
 575
 576         ath_debug_stat_interrupt(sc, status);
 577
 578         if (sched) {
 579                 /* turn off every interrupt except SWBA */
 580                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 581                 tasklet_schedule(&sc->intr_tq);
 582         }
 583
 584         return IRQ_HANDLED;
 585 }
 586
 587 static u32 ath_get_extchanmode(struct ath_softc *sc,
 588                                struct ieee80211_channel *chan,
 589                                enum nl80211_channel_type channel_type)
 590 {
 591         u32 chanmode = 0;
 592
 593         switch (chan->band) {
 594         case IEEE80211_BAND_2GHZ:
 595                 switch(channel_type) {
 596                 case NL80211_CHAN_NO_HT:
 597                 case NL80211_CHAN_HT20:
 598                         chanmode = CHANNEL_G_HT20;
 599                         break;
 600                 case NL80211_CHAN_HT40PLUS:
 601                         chanmode = CHANNEL_G_HT40PLUS;
 602                         break;
 603                 case NL80211_CHAN_HT40MINUS:
 604                         chanmode = CHANNEL_G_HT40MINUS;
 605                         break;
 606                 }
 607                 break;
 608         case IEEE80211_BAND_5GHZ:
 609                 switch(channel_type) {
 610                 case NL80211_CHAN_NO_HT:
 611                 case NL80211_CHAN_HT20:
 612                         chanmode = CHANNEL_A_HT20;
 613                         break;
 614                 case NL80211_CHAN_HT40PLUS:
 615                         chanmode = CHANNEL_A_HT40PLUS;
 616                         break;
 617                 case NL80211_CHAN_HT40MINUS:
 618                         chanmode = CHANNEL_A_HT40MINUS;
 619                         break;
 620                 }
 621                 break;
 622         default:
 623                 break;
 624         }
 625
 626         return chanmode;
 627 }
 628
 629 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 630                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 631 {
 632         bool status;
 633
 634         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 635                 keyix, hk, mac, false);
 636
 637         return status != false;
 638 }
 639
 640 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 641                            struct ath9k_keyval *hk,
 642                            const u8 *addr)
 643 {
 644         const u8 *key_rxmic;
 645         const u8 *key_txmic;
 646
 647         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 648         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 649
 650         if (addr == NULL) {
 651                 /* Group key installation */
 652                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 653                 return ath_keyset(sc, keyix, hk, addr);
 654         }
 655         if (!sc->sc_splitmic) {
 656                 /*
 657                  * data key goes at first index,
 658                  * the hal handles the MIC keys at index+64.
 659                  */
 660                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 661                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 662                 return ath_keyset(sc, keyix, hk, addr);
 663         }
 664         /*
 665          * TX key goes at first index, RX key at +32.
 666          * The hal handles the MIC keys at index+64.
 667          */
 668         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 669         if (!ath_keyset(sc, keyix, hk, NULL)) {
 670                 /* Txmic entry failed. No need to proceed further */
 671                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 672                         "Setting TX MIC Key Failed\n");
 673                 return 0;
 674         }
 675
 676         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 677         /* XXX delete tx key on failure? */
 678         return ath_keyset(sc, keyix + 32, hk, addr);
 679 }
 680
 681 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 682 {
 683         int i;
 684
 685         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 686                 if (test_bit(i, sc->sc_keymap) ||
 687                     test_bit(i + 64, sc->sc_keymap))
 688                         continue; /* At least one part of TKIP key allocated */
 689                 if (sc->sc_splitmic &&
 690                     (test_bit(i + 32, sc->sc_keymap) ||
 691                      test_bit(i + 64 + 32, sc->sc_keymap)))
 692                         continue; /* At least one part of TKIP key allocated */
 693
 694                 /* Found a free slot for a TKIP key */
 695                 return i;
 696         }
 697         return -1;
 698 }
 699
 700 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 701 {
 702         int i;
 703
 704         /* First, try to find slots that would not be available for TKIP. */
 705         if (sc->sc_splitmic) {
 706                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
 707                         if (!test_bit(i, sc->sc_keymap) &&
 708                             (test_bit(i + 32, sc->sc_keymap) ||
 709                              test_bit(i + 64, sc->sc_keymap) ||
 710                              test_bit(i + 64 + 32, sc->sc_keymap)))
 711                                 return i;
 712                         if (!test_bit(i + 32, sc->sc_keymap) &&
 713                             (test_bit(i, sc->sc_keymap) ||
 714                              test_bit(i + 64, sc->sc_keymap) ||
 715                              test_bit(i + 64 + 32, sc->sc_keymap)))
 716                                 return i + 32;
 717                         if (!test_bit(i + 64, sc->sc_keymap) &&
 718                             (test_bit(i , sc->sc_keymap) ||
 719                              test_bit(i + 32, sc->sc_keymap) ||
 720                              test_bit(i + 64 + 32, sc->sc_keymap)))
 721                                 return i + 64;
 722                         if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
 723                             (test_bit(i, sc->sc_keymap) ||
 724                              test_bit(i + 32, sc->sc_keymap) ||
 725                              test_bit(i + 64, sc->sc_keymap)))
 726                                 return i + 64 + 32;
 727                 }
 728         } else {
 729                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 730                         if (!test_bit(i, sc->sc_keymap) &&
 731                             test_bit(i + 64, sc->sc_keymap))
 732                                 return i;
 733                         if (test_bit(i, sc->sc_keymap) &&
 734                             !test_bit(i + 64, sc->sc_keymap))
 735                                 return i + 64;
 736                 }
 737         }
 738
 739         /* No partially used TKIP slots, pick any available slot */
 740         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
 741                 /* Do not allow slots that could be needed for TKIP group keys
 742                  * to be used. This limitation could be removed if we know that
 743                  * TKIP will not be used. */
 744                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 745                         continue;
 746                 if (sc->sc_splitmic) {
 747                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 748                                 continue;
 749                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 750                                 continue;
 751                 }
 752
 753                 if (!test_bit(i, sc->sc_keymap))
 754                         return i; /* Found a free slot for a key */
 755         }
 756
 757         /* No free slot found */
 758         return -1;
 759 }
 760
 761 static int ath_key_config(struct ath_softc *sc,
 762                           struct ieee80211_sta *sta,
 763                           struct ieee80211_key_conf *key)
 764 {
 765         struct ath9k_keyval hk;
 766         const u8 *mac = NULL;
 767         int ret = 0;
 768         int idx;
 769
 770         memset(&hk, 0, sizeof(hk));
 771
 772         switch (key->alg) {
 773         case ALG_WEP:
 774                 hk.kv_type = ATH9K_CIPHER_WEP;
 775                 break;
 776         case ALG_TKIP:
 777                 hk.kv_type = ATH9K_CIPHER_TKIP;
 778                 break;
 779         case ALG_CCMP:
 780                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 781                 break;
 782         default:
 783                 return -EOPNOTSUPP;
 784         }
 785
 786         hk.kv_len = key->keylen;
 787         memcpy(hk.kv_val, key->key, key->keylen);
 788
 789         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 790                 /* For now, use the default keys for broadcast keys. This may
 791                  * need to change with virtual interfaces. */
 792                 idx = key->keyidx;
 793         } else if (key->keyidx) {
 794                 struct ieee80211_vif *vif;
 795
 796                 if (WARN_ON(!sta))
 797                         return -EOPNOTSUPP;
 798                 mac = sta->addr;
 799
 800                 vif = sc->sc_vaps[0];
 801                 if (vif->type != NL80211_IFTYPE_AP) {
 802                         /* Only keyidx 0 should be used with unicast key, but
 803                          * allow this for client mode for now. */
 804                         idx = key->keyidx;
 805                 } else
 806                         return -EIO;
 807         } else {
 808                 if (WARN_ON(!sta))
 809                         return -EOPNOTSUPP;
 810                 mac = sta->addr;
 811
 812                 if (key->alg == ALG_TKIP)
 813                         idx = ath_reserve_key_cache_slot_tkip(sc);
 814                 else
 815                         idx = ath_reserve_key_cache_slot(sc);
 816                 if (idx < 0)
 817                         return -ENOSPC; /* no free key cache entries */
 818         }
 819
 820         if (key->alg == ALG_TKIP)
 821                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
 822         else
 823                 ret = ath_keyset(sc, idx, &hk, mac);
 824
 825         if (!ret)
 826                 return -EIO;
 827
 828         set_bit(idx, sc->sc_keymap);
 829         if (key->alg == ALG_TKIP) {
 830                 set_bit(idx + 64, sc->sc_keymap);
 831                 if (sc->sc_splitmic) {
 832                         set_bit(idx + 32, sc->sc_keymap);
 833                         set_bit(idx + 64 + 32, sc->sc_keymap);
 834                 }
 835         }
 836
 837         return idx;
 838 }
 839
 840 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 841 {
 842         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 843         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 844                 return;
 845
 846         clear_bit(key->hw_key_idx, sc->sc_keymap);
 847         if (key->alg != ALG_TKIP)
 848                 return;
 849
 850         clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
 851         if (sc->sc_splitmic) {
 852                 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
 853                 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
 854         }
 855 }
 856
 857 static void setup_ht_cap(struct ath_softc *sc,
 858                          struct ieee80211_sta_ht_cap *ht_info)
 859 {
 860 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 861 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 862
 863         ht_info->ht_supported = true;
 864         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 865                        IEEE80211_HT_CAP_SM_PS |
 866                        IEEE80211_HT_CAP_SGI_40 |
 867                        IEEE80211_HT_CAP_DSSSCCK40;
 868
 869         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 870         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 871
 872         /* set up supported mcs set */
 873         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 874
 875         switch(sc->sc_rx_chainmask) {
 876         case 1:
 877                 ht_info->mcs.rx_mask[0] = 0xff;
 878                 break;
 879         case 5:
 880         case 7:
 881         default:
 882                 ht_info->mcs.rx_mask[0] = 0xff;
 883                 ht_info->mcs.rx_mask[1] = 0xff;
 884                 break;
 885         }
 886
 887         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 888 }
 889
 890 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 891                                  struct ieee80211_vif *vif,
 892                                  struct ieee80211_bss_conf *bss_conf)
 893 {
 894         struct ath_vap *avp = (void *)vif->drv_priv;
 895
 896         if (bss_conf->assoc) {
 897                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 898                         bss_conf->aid, sc->sc_curbssid);
 899
 900                 /* New association, store aid */
 901                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 902                         sc->sc_curaid = bss_conf->aid;
 903                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 904                                                sc->sc_curaid);
 905                 }
 906
 907                 /* Configure the beacon */
 908                 ath_beacon_config(sc, 0);
 909                 sc->sc_flags |= SC_OP_BEACONS;
 910
 911                 /* Reset rssi stats */
 912                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 913                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 914                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 915                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 916
 917                 /* Start ANI */
 918                 mod_timer(&sc->sc_ani.timer,
 919                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 920
 921         } else {
 922                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 923                 sc->sc_curaid = 0;
 924         }
 925 }
 926
 927 /********************************/
 928 /*       LED functions          */
 929 /********************************/
 930
 931 static void ath_led_brightness(struct led_classdev *led_cdev,
 932                                enum led_brightness brightness)
 933 {
 934         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 935         struct ath_softc *sc = led->sc;
 936
 937         switch (brightness) {
 938         case LED_OFF:
 939                 if (led->led_type == ATH_LED_ASSOC ||
 940                     led->led_type == ATH_LED_RADIO)
 941                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 942                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 943                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 944                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 945                 break;
 946         case LED_FULL:
 947                 if (led->led_type == ATH_LED_ASSOC)
 948                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 949                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 950                 break;
 951         default:
 952                 break;
 953         }
 954 }
 955
 956 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 957                             char *trigger)
 958 {
 959         int ret;
 960
 961         led->sc = sc;
 962         led->led_cdev.name = led->name;
 963         led->led_cdev.default_trigger = trigger;
 964         led->led_cdev.brightness_set = ath_led_brightness;
 965
 966         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 967         if (ret)
 968                 DPRINTF(sc, ATH_DBG_FATAL,
 969                         "Failed to register led:%s", led->name);
 970         else
 971                 led->registered = 1;
 972         return ret;
 973 }
 974
 975 static void ath_unregister_led(struct ath_led *led)
 976 {
 977         if (led->registered) {
 978                 led_classdev_unregister(&led->led_cdev);
 979                 led->registered = 0;
 980         }
 981 }
 982
 983 static void ath_deinit_leds(struct ath_softc *sc)
 984 {
 985         ath_unregister_led(&sc->assoc_led);
 986         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 987         ath_unregister_led(&sc->tx_led);
 988         ath_unregister_led(&sc->rx_led);
 989         ath_unregister_led(&sc->radio_led);
 990         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 991 }
 992
 993 static void ath_init_leds(struct ath_softc *sc)
 994 {
 995         char *trigger;
 996         int ret;
 997
 998         /* Configure gpio 1 for output */
 999         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1000                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1001         /* LED off, active low */
1002         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1003
1004         trigger = ieee80211_get_radio_led_name(sc->hw);
1005         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1006                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1007         ret = ath_register_led(sc, &sc->radio_led, trigger);
1008         sc->radio_led.led_type = ATH_LED_RADIO;
1009         if (ret)
1010                 goto fail;
1011
1012         trigger = ieee80211_get_assoc_led_name(sc->hw);
1013         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1014                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1015         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1016         sc->assoc_led.led_type = ATH_LED_ASSOC;
1017         if (ret)
1018                 goto fail;
1019
1020         trigger = ieee80211_get_tx_led_name(sc->hw);
1021         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1022                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1023         ret = ath_register_led(sc, &sc->tx_led, trigger);
1024         sc->tx_led.led_type = ATH_LED_TX;
1025         if (ret)
1026                 goto fail;
1027
1028         trigger = ieee80211_get_rx_led_name(sc->hw);
1029         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1030                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1031         ret = ath_register_led(sc, &sc->rx_led, trigger);
1032         sc->rx_led.led_type = ATH_LED_RX;
1033         if (ret)
1034                 goto fail;
1035
1036         return;
1037
1038 fail:
1039         ath_deinit_leds(sc);
1040 }
1041
1042 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1043
1044 /*******************/
1045 /*      Rfkill     */
1046 /*******************/
1047
1048 static void ath_radio_enable(struct ath_softc *sc)
1049 {
1050         struct ath_hal *ah = sc->sc_ah;
1051         struct ieee80211_channel *channel = sc->hw->conf.channel;
1052         int r;
1053
1054         ath9k_ps_wakeup(sc);
1055         spin_lock_bh(&sc->sc_resetlock);
1056
1057         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1058
1059         if (r) {
1060                 DPRINTF(sc, ATH_DBG_FATAL,
1061                         "Unable to reset channel %u (%uMhz) ",
1062                         "reset status %u\n",
1063                         channel->center_freq, r);
1064         }
1065         spin_unlock_bh(&sc->sc_resetlock);
1066
1067         ath_update_txpow(sc);
1068         if (ath_startrecv(sc) != 0) {
1069                 DPRINTF(sc, ATH_DBG_FATAL,
1070                         "Unable to restart recv logic\n");
1071                 return;
1072         }
1073
1074         if (sc->sc_flags & SC_OP_BEACONS)
1075                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1076
1077         /* Re-Enable  interrupts */
1078         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1079
1080         /* Enable LED */
1081         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1082                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1083         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1084
1085         ieee80211_wake_queues(sc->hw);
1086         ath9k_ps_restore(sc);
1087 }
1088
1089 static void ath_radio_disable(struct ath_softc *sc)
1090 {
1091         struct ath_hal *ah = sc->sc_ah;
1092         struct ieee80211_channel *channel = sc->hw->conf.channel;
1093         int r;
1094
1095         ath9k_ps_wakeup(sc);
1096         ieee80211_stop_queues(sc->hw);
1097
1098         /* Disable LED */
1099         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1100         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1101
1102         /* Disable interrupts */
1103         ath9k_hw_set_interrupts(ah, 0);
1104
1105         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1106         ath_stoprecv(sc);               /* turn off frame recv */
1107         ath_flushrecv(sc);              /* flush recv queue */
1108
1109         spin_lock_bh(&sc->sc_resetlock);
1110         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1111         if (r) {
1112                 DPRINTF(sc, ATH_DBG_FATAL,
1113                         "Unable to reset channel %u (%uMhz) "
1114                         "reset status %u\n",
1115                         channel->center_freq, r);
1116         }
1117         spin_unlock_bh(&sc->sc_resetlock);
1118
1119         ath9k_hw_phy_disable(ah);
1120         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1121         ath9k_ps_restore(sc);
1122 }
1123
1124 static bool ath_is_rfkill_set(struct ath_softc *sc)
1125 {
1126         struct ath_hal *ah = sc->sc_ah;
1127
1128         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1129                                   ah->ah_rfkill_polarity;
1130 }
1131
1132 /* h/w rfkill poll function */
1133 static void ath_rfkill_poll(struct work_struct *work)
1134 {
1135         struct ath_softc *sc = container_of(work, struct ath_softc,
1136                                             rf_kill.rfkill_poll.work);
1137         bool radio_on;
1138
1139         if (sc->sc_flags & SC_OP_INVALID)
1140                 return;
1141
1142         radio_on = !ath_is_rfkill_set(sc);
1143
1144         /*
1145          * enable/disable radio only when there is a
1146          * state change in RF switch
1147          */
1148         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1149                 enum rfkill_state state;
1150
1151                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1152                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1153                                 : RFKILL_STATE_HARD_BLOCKED;
1154                 } else if (radio_on) {
1155                         ath_radio_enable(sc);
1156                         state = RFKILL_STATE_UNBLOCKED;
1157                 } else {
1158                         ath_radio_disable(sc);
1159                         state = RFKILL_STATE_HARD_BLOCKED;
1160                 }
1161
1162                 if (state == RFKILL_STATE_HARD_BLOCKED)
1163                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1164                 else
1165                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1166
1167                 rfkill_force_state(sc->rf_kill.rfkill, state);
1168         }
1169
1170         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1171                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1172 }
1173
1174 /* s/w rfkill handler */
1175 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1176 {
1177         struct ath_softc *sc = data;
1178
1179         switch (state) {
1180         case RFKILL_STATE_SOFT_BLOCKED:
1181                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1182                     SC_OP_RFKILL_SW_BLOCKED)))
1183                         ath_radio_disable(sc);
1184                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1185                 return 0;
1186         case RFKILL_STATE_UNBLOCKED:
1187                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1188                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1189                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1190                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1191                                         "radio as it is disabled by h/w\n");
1192                                 return -EPERM;
1193                         }
1194                         ath_radio_enable(sc);
1195                 }
1196                 return 0;
1197         default:
1198                 return -EINVAL;
1199         }
1200 }
1201
1202 /* Init s/w rfkill */
1203 static int ath_init_sw_rfkill(struct ath_softc *sc)
1204 {
1205         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1206                                              RFKILL_TYPE_WLAN);
1207         if (!sc->rf_kill.rfkill) {
1208                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1209                 return -ENOMEM;
1210         }
1211
1212         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1213                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1214         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1215         sc->rf_kill.rfkill->data = sc;
1216         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1217         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1218         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1219
1220         return 0;
1221 }
1222
1223 /* Deinitialize rfkill */
1224 static void ath_deinit_rfkill(struct ath_softc *sc)
1225 {
1226         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1227                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1228
1229         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1230                 rfkill_unregister(sc->rf_kill.rfkill);
1231                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1232                 sc->rf_kill.rfkill = NULL;
1233         }
1234 }
1235
1236 static int ath_start_rfkill_poll(struct ath_softc *sc)
1237 {
1238         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1239                 queue_delayed_work(sc->hw->workqueue,
1240                                    &sc->rf_kill.rfkill_poll, 0);
1241
1242         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1243                 if (rfkill_register(sc->rf_kill.rfkill)) {
1244                         DPRINTF(sc, ATH_DBG_FATAL,
1245                                 "Unable to register rfkill\n");
1246                         rfkill_free(sc->rf_kill.rfkill);
1247
1248                         /* Deinitialize the device */
1249                         ath_cleanup(sc);
1250                         return -EIO;
1251                 } else {
1252                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1253                 }
1254         }
1255
1256         return 0;
1257 }
1258 #endif /* CONFIG_RFKILL */
1259
1260 void ath_cleanup(struct ath_softc *sc)
1261 {
1262         ath_detach(sc);
1263         free_irq(sc->irq, sc);
1264         ath_bus_cleanup(sc);
1265         ieee80211_free_hw(sc->hw);
1266 }
1267
1268 void ath_detach(struct ath_softc *sc)
1269 {
1270         struct ieee80211_hw *hw = sc->hw;
1271         int i = 0;
1272
1273         ath9k_ps_wakeup(sc);
1274
1275         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1276
1277 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1278         ath_deinit_rfkill(sc);
1279 #endif
1280         ath_deinit_leds(sc);
1281
1282         ieee80211_unregister_hw(hw);
1283         ath_rx_cleanup(sc);
1284         ath_tx_cleanup(sc);
1285
1286         tasklet_kill(&sc->intr_tq);
1287         tasklet_kill(&sc->bcon_tasklet);
1288
1289         if (!(sc->sc_flags & SC_OP_INVALID))
1290                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1291
1292         /* cleanup tx queues */
1293         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1294                 if (ATH_TXQ_SETUP(sc, i))
1295                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1296
1297         ath9k_hw_detach(sc->sc_ah);
1298         ath9k_exit_debug(sc);
1299         ath9k_ps_restore(sc);
1300 }
1301
1302 static int ath_init(u16 devid, struct ath_softc *sc)
1303 {
1304         struct ath_hal *ah = NULL;
1305         int status;
1306         int error = 0, i;
1307         int csz = 0;
1308
1309         /* XXX: hardware will not be ready until ath_open() being called */
1310         sc->sc_flags |= SC_OP_INVALID;
1311
1312         if (ath9k_init_debug(sc) < 0)
1313                 printk(KERN_ERR "Unable to create debugfs files\n");
1314
1315         spin_lock_init(&sc->sc_resetlock);
1316         mutex_init(&sc->mutex);
1317         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1318         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1319                      (unsigned long)sc);
1320
1321         /*
1322          * Cache line size is used to size and align various
1323          * structures used to communicate with the hardware.
1324          */
1325         ath_read_cachesize(sc, &csz);
1326         /* XXX assert csz is non-zero */
1327         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1328
1329         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1330         if (ah == NULL) {
1331                 DPRINTF(sc, ATH_DBG_FATAL,
1332                         "Unable to attach hardware; HAL status %d\n", status);
1333                 error = -ENXIO;
1334                 goto bad;
1335         }
1336         sc->sc_ah = ah;
1337
1338         /* Get the hardware key cache size. */
1339         sc->sc_keymax = ah->ah_caps.keycache_size;
1340         if (sc->sc_keymax > ATH_KEYMAX) {
1341                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1342                         "Warning, using only %u entries in %u key cache\n",
1343                         ATH_KEYMAX, sc->sc_keymax);
1344                 sc->sc_keymax = ATH_KEYMAX;
1345         }
1346
1347         /*
1348          * Reset the key cache since some parts do not
1349          * reset the contents on initial power up.
1350          */
1351         for (i = 0; i < sc->sc_keymax; i++)
1352                 ath9k_hw_keyreset(ah, (u16) i);
1353
1354         if (ath9k_regd_init(sc->sc_ah))
1355                 goto bad;
1356
1357         /* default to MONITOR mode */
1358         sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1359
1360         /* Setup rate tables */
1361
1362         ath_rate_attach(sc);
1363         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1364         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1365
1366         /*
1367          * Allocate hardware transmit queues: one queue for
1368          * beacon frames and one data queue for each QoS
1369          * priority.  Note that the hal handles reseting
1370          * these queues at the needed time.
1371          */
1372         sc->beacon.beaconq = ath_beaconq_setup(ah);
1373         if (sc->beacon.beaconq == -1) {
1374                 DPRINTF(sc, ATH_DBG_FATAL,
1375                         "Unable to setup a beacon xmit queue\n");
1376                 error = -EIO;
1377                 goto bad2;
1378         }
1379         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1380         if (sc->beacon.cabq == NULL) {
1381                 DPRINTF(sc, ATH_DBG_FATAL,
1382                         "Unable to setup CAB xmit queue\n");
1383                 error = -EIO;
1384                 goto bad2;
1385         }
1386
1387         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1388         ath_cabq_update(sc);
1389
1390         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1391                 sc->tx.hwq_map[i] = -1;
1392
1393         /* Setup data queues */
1394         /* NB: ensure BK queue is the lowest priority h/w queue */
1395         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1396                 DPRINTF(sc, ATH_DBG_FATAL,
1397                         "Unable to setup xmit queue for BK traffic\n");
1398                 error = -EIO;
1399                 goto bad2;
1400         }
1401
1402         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1403                 DPRINTF(sc, ATH_DBG_FATAL,
1404                         "Unable to setup xmit queue for BE traffic\n");
1405                 error = -EIO;
1406                 goto bad2;
1407         }
1408         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1409                 DPRINTF(sc, ATH_DBG_FATAL,
1410                         "Unable to setup xmit queue for VI traffic\n");
1411                 error = -EIO;
1412                 goto bad2;
1413         }
1414         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1415                 DPRINTF(sc, ATH_DBG_FATAL,
1416                         "Unable to setup xmit queue for VO traffic\n");
1417                 error = -EIO;
1418                 goto bad2;
1419         }
1420
1421         /* Initializes the noise floor to a reasonable default value.
1422          * Later on this will be updated during ANI processing. */
1423
1424         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1425         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1426
1427         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1428                                    ATH9K_CIPHER_TKIP, NULL)) {
1429                 /*
1430                  * Whether we should enable h/w TKIP MIC.
1431                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1432                  * report WMM capable, so it's always safe to turn on
1433                  * TKIP MIC in this case.
1434                  */
1435                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1436                                        0, 1, NULL);
1437         }
1438
1439         /*
1440          * Check whether the separate key cache entries
1441          * are required to handle both tx+rx MIC keys.
1442          * With split mic keys the number of stations is limited
1443          * to 27 otherwise 59.
1444          */
1445         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1446                                    ATH9K_CIPHER_TKIP, NULL)
1447             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1448                                       ATH9K_CIPHER_MIC, NULL)
1449             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1450                                       0, NULL))
1451                 sc->sc_splitmic = 1;
1452
1453         /* turn on mcast key search if possible */
1454         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1455                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1456                                              1, NULL);
1457
1458         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1459         sc->sc_config.txpowlimit_override = 0;
1460
1461         /* 11n Capabilities */
1462         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1463                 sc->sc_flags |= SC_OP_TXAGGR;
1464                 sc->sc_flags |= SC_OP_RXAGGR;
1465         }
1466
1467         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1468         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1469
1470         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1471         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1472
1473         ath9k_hw_getmac(ah, sc->sc_myaddr);
1474         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1475                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1476                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1477                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1478         }
1479
1480         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1481
1482         /* initialize beacon slots */
1483         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1484                 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1485
1486         /* save MISC configurations */
1487         sc->sc_config.swBeaconProcess = 1;
1488
1489         /* setup channels and rates */
1490
1491         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1492         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1493                 sc->rates[IEEE80211_BAND_2GHZ];
1494         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1495         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1496                 ARRAY_SIZE(ath9k_2ghz_chantable);
1497
1498         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1499                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1500                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1501                         sc->rates[IEEE80211_BAND_5GHZ];
1502                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1503                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1504                         ARRAY_SIZE(ath9k_5ghz_chantable);
1505         }
1506
1507         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1508                 ath9k_hw_btcoex_enable(sc->sc_ah);
1509
1510         return 0;
1511 bad2:
1512         /* cleanup tx queues */
1513         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1514                 if (ATH_TXQ_SETUP(sc, i))
1515                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1516 bad:
1517         if (ah)
1518                 ath9k_hw_detach(ah);
1519
1520         return error;
1521 }
1522
1523 int ath_attach(u16 devid, struct ath_softc *sc)
1524 {
1525         struct ieee80211_hw *hw = sc->hw;
1526         int error = 0;
1527
1528         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1529
1530         error = ath_init(devid, sc);
1531         if (error != 0)
1532                 return error;
1533
1534         /* get mac address from hardware and set in mac80211 */
1535
1536         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1537
1538         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1539                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1540                 IEEE80211_HW_SIGNAL_DBM |
1541                 IEEE80211_HW_AMPDU_AGGREGATION |
1542                 IEEE80211_HW_SUPPORTS_PS |
1543                 IEEE80211_HW_PS_NULLFUNC_STACK;
1544
1545         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1546                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1547
1548         hw->wiphy->interface_modes =
1549                 BIT(NL80211_IFTYPE_AP) |
1550                 BIT(NL80211_IFTYPE_STATION) |
1551                 BIT(NL80211_IFTYPE_ADHOC);
1552
1553         hw->wiphy->reg_notifier = ath9k_reg_notifier;
1554         hw->wiphy->strict_regulatory = true;
1555
1556         hw->queues = 4;
1557         hw->max_rates = 4;
1558         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1559         hw->sta_data_size = sizeof(struct ath_node);
1560         hw->vif_data_size = sizeof(struct ath_vap);
1561
1562         hw->rate_control_algorithm = "ath9k_rate_control";
1563
1564         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1565                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1566                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1567                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1568         }
1569
1570         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1571         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1572                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1573                         &sc->sbands[IEEE80211_BAND_5GHZ];
1574
1575         /* initialize tx/rx engine */
1576         error = ath_tx_init(sc, ATH_TXBUF);
1577         if (error != 0)
1578                 goto detach;
1579
1580         error = ath_rx_init(sc, ATH_RXBUF);
1581         if (error != 0)
1582                 goto detach;
1583
1584 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1585         /* Initialze h/w Rfkill */
1586         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1587                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1588
1589         /* Initialize s/w rfkill */
1590         if (ath_init_sw_rfkill(sc))
1591                 goto detach;
1592 #endif
1593
1594         if (ath9k_is_world_regd(sc->sc_ah)) {
1595                 /* Anything applied here (prior to wiphy registratoin) gets
1596                  * saved on the wiphy orig_* parameters */
1597                 const struct ieee80211_regdomain *regd =
1598                         ath9k_world_regdomain(sc->sc_ah);
1599                 hw->wiphy->custom_regulatory = true;
1600                 hw->wiphy->strict_regulatory = false;
1601                 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1602                 ath9k_reg_apply_radar_flags(hw->wiphy);
1603                 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1604         } else {
1605                 /* This gets applied in the case of the absense of CRDA,
1606                  * its our own custom world regulatory domain, similar to
1607                  * cfg80211's but we enable passive scanning */
1608                 const struct ieee80211_regdomain *regd =
1609                         ath9k_default_world_regdomain();
1610                 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1611                 ath9k_reg_apply_radar_flags(hw->wiphy);
1612                 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1613         }
1614
1615         error = ieee80211_register_hw(hw);
1616
1617         if (!ath9k_is_world_regd(sc->sc_ah))
1618                 regulatory_hint(hw->wiphy, sc->sc_ah->alpha2);
1619
1620         /* Initialize LED control */
1621         ath_init_leds(sc);
1622
1623
1624         return 0;
1625 detach:
1626         ath_detach(sc);
1627         return error;
1628 }
1629
1630 int ath_reset(struct ath_softc *sc, bool retry_tx)
1631 {
1632         struct ath_hal *ah = sc->sc_ah;
1633         struct ieee80211_hw *hw = sc->hw;
1634         int r;
1635
1636         ath9k_hw_set_interrupts(ah, 0);
1637         ath_drain_all_txq(sc, retry_tx);
1638         ath_stoprecv(sc);
1639         ath_flushrecv(sc);
1640
1641         spin_lock_bh(&sc->sc_resetlock);
1642         r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1643         if (r)
1644                 DPRINTF(sc, ATH_DBG_FATAL,
1645                         "Unable to reset hardware; reset status %u\n", r);
1646         spin_unlock_bh(&sc->sc_resetlock);
1647
1648         if (ath_startrecv(sc) != 0)
1649                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1650
1651         /*
1652          * We may be doing a reset in response to a request
1653          * that changes the channel so update any state that
1654          * might change as a result.
1655          */
1656         ath_cache_conf_rate(sc, &hw->conf);
1657
1658         ath_update_txpow(sc);
1659
1660         if (sc->sc_flags & SC_OP_BEACONS)
1661                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1662
1663         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1664
1665         if (retry_tx) {
1666                 int i;
1667                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1668                         if (ATH_TXQ_SETUP(sc, i)) {
1669                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1670                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1671                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1672                         }
1673                 }
1674         }
1675
1676         return r;
1677 }
1678
1679 /*
1680  *  This function will allocate both the DMA descriptor structure, and the
1681  *  buffers it contains.  These are used to contain the descriptors used
1682  *  by the system.
1683 */
1684 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1685                       struct list_head *head, const char *name,
1686                       int nbuf, int ndesc)
1687 {
1688 #define DS2PHYS(_dd, _ds)                                               \
1689         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1690 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1691 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1692
1693         struct ath_desc *ds;
1694         struct ath_buf *bf;
1695         int i, bsize, error;
1696
1697         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1698                 name, nbuf, ndesc);
1699
1700         /* ath_desc must be a multiple of DWORDs */
1701         if ((sizeof(struct ath_desc) % 4) != 0) {
1702                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1703                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1704                 error = -ENOMEM;
1705                 goto fail;
1706         }
1707
1708         dd->dd_name = name;
1709         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1710
1711         /*
1712          * Need additional DMA memory because we can't use
1713          * descriptors that cross the 4K page boundary. Assume
1714          * one skipped descriptor per 4K page.
1715          */
1716         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1717                 u32 ndesc_skipped =
1718                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1719                 u32 dma_len;
1720
1721                 while (ndesc_skipped) {
1722                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1723                         dd->dd_desc_len += dma_len;
1724
1725                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1726                 };
1727         }
1728
1729         /* allocate descriptors */
1730         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1731                                          &dd->dd_desc_paddr, GFP_ATOMIC);
1732         if (dd->dd_desc == NULL) {
1733                 error = -ENOMEM;
1734                 goto fail;
1735         }
1736         ds = dd->dd_desc;
1737         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1738                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1739                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1740
1741         /* allocate buffers */
1742         bsize = sizeof(struct ath_buf) * nbuf;
1743         bf = kmalloc(bsize, GFP_KERNEL);
1744         if (bf == NULL) {
1745                 error = -ENOMEM;
1746                 goto fail2;
1747         }
1748         memset(bf, 0, bsize);
1749         dd->dd_bufptr = bf;
1750
1751         INIT_LIST_HEAD(head);
1752         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1753                 bf->bf_desc = ds;
1754                 bf->bf_daddr = DS2PHYS(dd, ds);
1755
1756                 if (!(sc->sc_ah->ah_caps.hw_caps &
1757                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1758                         /*
1759                          * Skip descriptor addresses which can cause 4KB
1760                          * boundary crossing (addr + length) with a 32 dword
1761                          * descriptor fetch.
1762                          */
1763                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1764                                 ASSERT((caddr_t) bf->bf_desc <
1765                                        ((caddr_t) dd->dd_desc +
1766                                         dd->dd_desc_len));
1767
1768                                 ds += ndesc;
1769                                 bf->bf_desc = ds;
1770                                 bf->bf_daddr = DS2PHYS(dd, ds);
1771                         }
1772                 }
1773                 list_add_tail(&bf->list, head);
1774         }
1775         return 0;
1776 fail2:
1777         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1778                           dd->dd_desc_paddr);
1779 fail:
1780         memset(dd, 0, sizeof(*dd));
1781         return error;
1782 #undef ATH_DESC_4KB_BOUND_CHECK
1783 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1784 #undef DS2PHYS
1785 }
1786
1787 void ath_descdma_cleanup(struct ath_softc *sc,
1788                          struct ath_descdma *dd,
1789                          struct list_head *head)
1790 {
1791         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1792                           dd->dd_desc_paddr);
1793
1794         INIT_LIST_HEAD(head);
1795         kfree(dd->dd_bufptr);
1796         memset(dd, 0, sizeof(*dd));
1797 }
1798
1799 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1800 {
1801         int qnum;
1802
1803         switch (queue) {
1804         case 0:
1805                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1806                 break;
1807         case 1:
1808                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1809                 break;
1810         case 2:
1811                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1812                 break;
1813         case 3:
1814                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1815                 break;
1816         default:
1817                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1818                 break;
1819         }
1820
1821         return qnum;
1822 }
1823
1824 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1825 {
1826         int qnum;
1827
1828         switch (queue) {
1829         case ATH9K_WME_AC_VO:
1830                 qnum = 0;
1831                 break;
1832         case ATH9K_WME_AC_VI:
1833                 qnum = 1;
1834                 break;
1835         case ATH9K_WME_AC_BE:
1836                 qnum = 2;
1837                 break;
1838         case ATH9K_WME_AC_BK:
1839                 qnum = 3;
1840                 break;
1841         default:
1842                 qnum = -1;
1843                 break;
1844         }
1845
1846         return qnum;
1847 }
1848
1849 /* XXX: Remove me once we don't depend on ath9k_channel for all
1850  * this redundant data */
1851 static void ath9k_update_ichannel(struct ath_softc *sc,
1852                           struct ath9k_channel *ichan)
1853 {
1854         struct ieee80211_hw *hw = sc->hw;
1855         struct ieee80211_channel *chan = hw->conf.channel;
1856         struct ieee80211_conf *conf = &hw->conf;
1857
1858         ichan->channel = chan->center_freq;
1859         ichan->chan = chan;
1860
1861         if (chan->band == IEEE80211_BAND_2GHZ) {
1862                 ichan->chanmode = CHANNEL_G;
1863                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1864         } else {
1865                 ichan->chanmode = CHANNEL_A;
1866                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1867         }
1868
1869         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1870
1871         if (conf_is_ht(conf)) {
1872                 if (conf_is_ht40(conf))
1873                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1874
1875                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1876                                             conf->channel_type);
1877         }
1878 }
1879
1880 /**********************/
1881 /* mac80211 callbacks */
1882 /**********************/
1883
1884 static int ath9k_start(struct ieee80211_hw *hw)
1885 {
1886         struct ath_softc *sc = hw->priv;
1887         struct ieee80211_channel *curchan = hw->conf.channel;
1888         struct ath9k_channel *init_channel;
1889         int r, pos;
1890
1891         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1892                 "initial channel: %d MHz\n", curchan->center_freq);
1893
1894         /* setup initial channel */
1895
1896         pos = curchan->hw_value;
1897
1898         init_channel = &sc->sc_ah->ah_channels[pos];
1899         ath9k_update_ichannel(sc, init_channel);
1900
1901         /* Reset SERDES registers */
1902         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1903
1904         /*
1905          * The basic interface to setting the hardware in a good
1906          * state is ``reset''.  On return the hardware is known to
1907          * be powered up and with interrupts disabled.  This must
1908          * be followed by initialization of the appropriate bits
1909          * and then setup of the interrupt mask.
1910          */
1911         spin_lock_bh(&sc->sc_resetlock);
1912         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1913         if (r) {
1914                 DPRINTF(sc, ATH_DBG_FATAL,
1915                         "Unable to reset hardware; reset status %u "
1916                         "(freq %u MHz)\n", r,
1917                         curchan->center_freq);
1918                 spin_unlock_bh(&sc->sc_resetlock);
1919                 return r;
1920         }
1921         spin_unlock_bh(&sc->sc_resetlock);
1922
1923         /*
1924          * This is needed only to setup initial state
1925          * but it's best done after a reset.
1926          */
1927         ath_update_txpow(sc);
1928
1929         /*
1930          * Setup the hardware after reset:
1931          * The receive engine is set going.
1932          * Frame transmit is handled entirely
1933          * in the frame output path; there's nothing to do
1934          * here except setup the interrupt mask.
1935          */
1936         if (ath_startrecv(sc) != 0) {
1937                 DPRINTF(sc, ATH_DBG_FATAL,
1938                         "Unable to start recv logic\n");
1939                 return -EIO;
1940         }
1941
1942         /* Setup our intr mask. */
1943         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1944                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1945                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1946
1947         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1948                 sc->sc_imask |= ATH9K_INT_GTT;
1949
1950         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1951                 sc->sc_imask |= ATH9K_INT_CST;
1952
1953         /*
1954          * Enable MIB interrupts when there are hardware phy counters.
1955          * Note we only do this (at the moment) for station mode.
1956          */
1957         if (ath9k_hw_phycounters(sc->sc_ah) &&
1958             ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1959              (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1960                 sc->sc_imask |= ATH9K_INT_MIB;
1961         /*
1962          * Some hardware processes the TIM IE and fires an
1963          * interrupt when the TIM bit is set.  For hardware
1964          * that does, if not overridden by configuration,
1965          * enable the TIM interrupt when operating as station.
1966          */
1967         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1968             (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1969             !sc->sc_config.swBeaconProcess)
1970                 sc->sc_imask |= ATH9K_INT_TIM;
1971
1972         ath_cache_conf_rate(sc, &hw->conf);
1973
1974         sc->sc_flags &= ~SC_OP_INVALID;
1975
1976         /* Disable BMISS interrupt when we're not associated */
1977         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1978         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1979
1980         ieee80211_wake_queues(sc->hw);
1981
1982 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1983         r = ath_start_rfkill_poll(sc);
1984 #endif
1985         return r;
1986 }
1987
1988 static int ath9k_tx(struct ieee80211_hw *hw,
1989                     struct sk_buff *skb)
1990 {
1991         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1992         struct ath_softc *sc = hw->priv;
1993         struct ath_tx_control txctl;
1994         int hdrlen, padsize;
1995
1996         memset(&txctl, 0, sizeof(struct ath_tx_control));
1997
1998         /*
1999          * As a temporary workaround, assign seq# here; this will likely need
2000          * to be cleaned up to work better with Beacon transmission and virtual
2001          * BSSes.
2002          */
2003         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2004                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2005                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2006                         sc->tx.seq_no += 0x10;
2007                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2008                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2009         }
2010
2011         /* Add the padding after the header if this is not already done */
2012         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2013         if (hdrlen & 3) {
2014                 padsize = hdrlen % 4;
2015                 if (skb_headroom(skb) < padsize)
2016                         return -1;
2017                 skb_push(skb, padsize);
2018                 memmove(skb->data, skb->data + padsize, hdrlen);
2019         }
2020
2021         /* Check if a tx queue is available */
2022
2023         txctl.txq = ath_test_get_txq(sc, skb);
2024         if (!txctl.txq)
2025                 goto exit;
2026
2027         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2028
2029         if (ath_tx_start(sc, skb, &txctl) != 0) {
2030                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2031                 goto exit;
2032         }
2033
2034         return 0;
2035 exit:
2036         dev_kfree_skb_any(skb);
2037         return 0;
2038 }
2039
2040 static void ath9k_stop(struct ieee80211_hw *hw)
2041 {
2042         struct ath_softc *sc = hw->priv;
2043
2044         if (sc->sc_flags & SC_OP_INVALID) {
2045                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2046                 return;
2047         }
2048
2049         DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2050
2051         ieee80211_stop_queues(sc->hw);
2052
2053         /* make sure h/w will not generate any interrupt
2054          * before setting the invalid flag. */
2055         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2056
2057         if (!(sc->sc_flags & SC_OP_INVALID)) {
2058                 ath_drain_all_txq(sc, false);
2059                 ath_stoprecv(sc);
2060                 ath9k_hw_phy_disable(sc->sc_ah);
2061         } else
2062                 sc->rx.rxlink = NULL;
2063
2064 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2065         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2066                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2067 #endif
2068         /* disable HAL and put h/w to sleep */
2069         ath9k_hw_disable(sc->sc_ah);
2070         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2071
2072         sc->sc_flags |= SC_OP_INVALID;
2073
2074         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2075 }
2076
2077 static int ath9k_add_interface(struct ieee80211_hw *hw,
2078                                struct ieee80211_if_init_conf *conf)
2079 {
2080         struct ath_softc *sc = hw->priv;
2081         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2082         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2083
2084         /* Support only vap for now */
2085
2086         if (sc->sc_nvaps)
2087                 return -ENOBUFS;
2088
2089         switch (conf->type) {
2090         case NL80211_IFTYPE_STATION:
2091                 ic_opmode = NL80211_IFTYPE_STATION;
2092                 break;
2093         case NL80211_IFTYPE_ADHOC:
2094                 ic_opmode = NL80211_IFTYPE_ADHOC;
2095                 break;
2096         case NL80211_IFTYPE_AP:
2097                 ic_opmode = NL80211_IFTYPE_AP;
2098                 break;
2099         default:
2100                 DPRINTF(sc, ATH_DBG_FATAL,
2101                         "Interface type %d not yet supported\n", conf->type);
2102                 return -EOPNOTSUPP;
2103         }
2104
2105         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2106
2107         /* Set the VAP opmode */
2108         avp->av_opmode = ic_opmode;
2109         avp->av_bslot = -1;
2110
2111         if (ic_opmode == NL80211_IFTYPE_AP)
2112                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2113
2114         sc->sc_vaps[0] = conf->vif;
2115         sc->sc_nvaps++;
2116
2117         /* Set the device opmode */
2118         sc->sc_ah->ah_opmode = ic_opmode;
2119
2120         if (conf->type == NL80211_IFTYPE_AP) {
2121                 /* TODO: is this a suitable place to start ANI for AP mode? */
2122                 /* Start ANI */
2123                 mod_timer(&sc->sc_ani.timer,
2124                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2125         }
2126
2127         return 0;
2128 }
2129
2130 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2131                                    struct ieee80211_if_init_conf *conf)
2132 {
2133         struct ath_softc *sc = hw->priv;
2134         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2135
2136         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2137
2138         /* Stop ANI */
2139         del_timer_sync(&sc->sc_ani.timer);
2140
2141         /* Reclaim beacon resources */
2142         if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2143             sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2144                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2145                 ath_beacon_return(sc, avp);
2146         }
2147
2148         sc->sc_flags &= ~SC_OP_BEACONS;
2149
2150         sc->sc_vaps[0] = NULL;
2151         sc->sc_nvaps--;
2152 }
2153
2154 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2155 {
2156         struct ath_softc *sc = hw->priv;
2157         struct ieee80211_conf *conf = &hw->conf;
2158
2159         mutex_lock(&sc->mutex);
2160         if (changed & IEEE80211_CONF_CHANGE_PS) {
2161                 if (conf->flags & IEEE80211_CONF_PS) {
2162                         if ((sc->sc_imask & ATH9K_INT_TIM_TIMER) == 0) {
2163                                 sc->sc_imask |= ATH9K_INT_TIM_TIMER;
2164                                 ath9k_hw_set_interrupts(sc->sc_ah,
2165                                                 sc->sc_imask);
2166                         }
2167                         ath9k_hw_setrxabort(sc->sc_ah, 1);
2168                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2169                 } else {
2170                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2171                         ath9k_hw_setrxabort(sc->sc_ah, 0);
2172                         sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2173                         if (sc->sc_imask & ATH9K_INT_TIM_TIMER) {
2174                                 sc->sc_imask &= ~ATH9K_INT_TIM_TIMER;
2175                                 ath9k_hw_set_interrupts(sc->sc_ah,
2176                                                 sc->sc_imask);
2177                         }
2178                 }
2179         }
2180
2181         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2182                 struct ieee80211_channel *curchan = hw->conf.channel;
2183                 int pos = curchan->hw_value;
2184
2185                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2186                         curchan->center_freq);
2187
2188                 /* XXX: remove me eventualy */
2189                 ath9k_update_ichannel(sc, &sc->sc_ah->ah_channels[pos]);
2190
2191                 ath_update_chainmask(sc, conf_is_ht(conf));
2192
2193                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2194                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2195                         mutex_unlock(&sc->mutex);
2196                         return -EINVAL;
2197                 }
2198         }
2199
2200         if (changed & IEEE80211_CONF_CHANGE_POWER)
2201                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2202
2203         mutex_unlock(&sc->mutex);
2204         return 0;
2205 }
2206
2207 static int ath9k_config_interface(struct ieee80211_hw *hw,
2208                                   struct ieee80211_vif *vif,
2209                                   struct ieee80211_if_conf *conf)
2210 {
2211         struct ath_softc *sc = hw->priv;
2212         struct ath_hal *ah = sc->sc_ah;
2213         struct ath_vap *avp = (void *)vif->drv_priv;
2214         u32 rfilt = 0;
2215         int error, i;
2216
2217         /* TODO: Need to decide which hw opmode to use for multi-interface
2218          * cases */
2219         if (vif->type == NL80211_IFTYPE_AP &&
2220             ah->ah_opmode != NL80211_IFTYPE_AP) {
2221                 ah->ah_opmode = NL80211_IFTYPE_STATION;
2222                 ath9k_hw_setopmode(ah);
2223                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2224                 /* Request full reset to get hw opmode changed properly */
2225                 sc->sc_flags |= SC_OP_FULL_RESET;
2226         }
2227
2228         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2229             !is_zero_ether_addr(conf->bssid)) {
2230                 switch (vif->type) {
2231                 case NL80211_IFTYPE_STATION:
2232                 case NL80211_IFTYPE_ADHOC:
2233                         /* Set BSSID */
2234                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2235                         sc->sc_curaid = 0;
2236                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2237                                                sc->sc_curaid);
2238
2239                         /* Set aggregation protection mode parameters */
2240                         sc->sc_config.ath_aggr_prot = 0;
2241
2242                         DPRINTF(sc, ATH_DBG_CONFIG,
2243                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2244                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2245
2246                         /* need to reconfigure the beacon */
2247                         sc->sc_flags &= ~SC_OP_BEACONS ;
2248
2249                         break;
2250                 default:
2251                         break;
2252                 }
2253         }
2254
2255         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2256             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2257              (vif->type == NL80211_IFTYPE_AP))) {
2258                 /*
2259                  * Allocate and setup the beacon frame.
2260                  *
2261                  * Stop any previous beacon DMA.  This may be
2262                  * necessary, for example, when an ibss merge
2263                  * causes reconfiguration; we may be called
2264                  * with beacon transmission active.
2265                  */
2266                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2267
2268                 error = ath_beacon_alloc(sc, 0);
2269                 if (error != 0)
2270                         return error;
2271
2272                 ath_beacon_sync(sc, 0);
2273         }
2274
2275         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2276         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2277                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2278                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2279                                 ath9k_hw_keysetmac(sc->sc_ah,
2280                                                    (u16)i,
2281                                                    sc->sc_curbssid);
2282         }
2283
2284         /* Only legacy IBSS for now */
2285         if (vif->type == NL80211_IFTYPE_ADHOC)
2286                 ath_update_chainmask(sc, 0);
2287
2288         return 0;
2289 }
2290
2291 #define SUPPORTED_FILTERS                       \
2292         (FIF_PROMISC_IN_BSS |                   \
2293         FIF_ALLMULTI |                          \
2294         FIF_CONTROL |                           \
2295         FIF_OTHER_BSS |                         \
2296         FIF_BCN_PRBRESP_PROMISC |               \
2297         FIF_FCSFAIL)
2298
2299 /* FIXME: sc->sc_full_reset ? */
2300 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2301                                    unsigned int changed_flags,
2302                                    unsigned int *total_flags,
2303                                    int mc_count,
2304                                    struct dev_mc_list *mclist)
2305 {
2306         struct ath_softc *sc = hw->priv;
2307         u32 rfilt;
2308
2309         changed_flags &= SUPPORTED_FILTERS;
2310         *total_flags &= SUPPORTED_FILTERS;
2311
2312         sc->rx.rxfilter = *total_flags;
2313         rfilt = ath_calcrxfilter(sc);
2314         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2315
2316         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2317                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2318                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2319         }
2320
2321         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2322 }
2323
2324 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2325                              struct ieee80211_vif *vif,
2326                              enum sta_notify_cmd cmd,
2327                              struct ieee80211_sta *sta)
2328 {
2329         struct ath_softc *sc = hw->priv;
2330
2331         switch (cmd) {
2332         case STA_NOTIFY_ADD:
2333                 ath_node_attach(sc, sta);
2334                 break;
2335         case STA_NOTIFY_REMOVE:
2336                 ath_node_detach(sc, sta);
2337                 break;
2338         default:
2339                 break;
2340         }
2341 }
2342
2343 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2344                          u16 queue,
2345                          const struct ieee80211_tx_queue_params *params)
2346 {
2347         struct ath_softc *sc = hw->priv;
2348         struct ath9k_tx_queue_info qi;
2349         int ret = 0, qnum;
2350
2351         if (queue >= WME_NUM_AC)
2352                 return 0;
2353
2354         qi.tqi_aifs = params->aifs;
2355         qi.tqi_cwmin = params->cw_min;
2356         qi.tqi_cwmax = params->cw_max;
2357         qi.tqi_burstTime = params->txop;
2358         qnum = ath_get_hal_qnum(queue, sc);
2359
2360         DPRINTF(sc, ATH_DBG_CONFIG,
2361                 "Configure tx [queue/halq] [%d/%d],  "
2362                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2363                 queue, qnum, params->aifs, params->cw_min,
2364                 params->cw_max, params->txop);
2365
2366         ret = ath_txq_update(sc, qnum, &qi);
2367         if (ret)
2368                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2369
2370         return ret;
2371 }
2372
2373 static int ath9k_set_key(struct ieee80211_hw *hw,
2374                          enum set_key_cmd cmd,
2375                          struct ieee80211_vif *vif,
2376                          struct ieee80211_sta *sta,
2377                          struct ieee80211_key_conf *key)
2378 {
2379         struct ath_softc *sc = hw->priv;
2380         int ret = 0;
2381
2382         ath9k_ps_wakeup(sc);
2383         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2384
2385         switch (cmd) {
2386         case SET_KEY:
2387                 ret = ath_key_config(sc, sta, key);
2388                 if (ret >= 0) {
2389                         key->hw_key_idx = ret;
2390                         /* push IV and Michael MIC generation to stack */
2391                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2392                         if (key->alg == ALG_TKIP)
2393                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2394                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2395                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2396                         ret = 0;
2397                 }
2398                 break;
2399         case DISABLE_KEY:
2400                 ath_key_delete(sc, key);
2401                 break;
2402         default:
2403                 ret = -EINVAL;
2404         }
2405
2406         ath9k_ps_restore(sc);
2407         return ret;
2408 }
2409
2410 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2411                                    struct ieee80211_vif *vif,
2412                                    struct ieee80211_bss_conf *bss_conf,
2413                                    u32 changed)
2414 {
2415         struct ath_softc *sc = hw->priv;
2416
2417         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2418                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2419                         bss_conf->use_short_preamble);
2420                 if (bss_conf->use_short_preamble)
2421                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2422                 else
2423                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2424         }
2425
2426         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2427                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2428                         bss_conf->use_cts_prot);
2429                 if (bss_conf->use_cts_prot &&
2430                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2431                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2432                 else
2433                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2434         }
2435
2436         if (changed & BSS_CHANGED_ASSOC) {
2437                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2438                         bss_conf->assoc);
2439                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2440         }
2441 }
2442
2443 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2444 {
2445         u64 tsf;
2446         struct ath_softc *sc = hw->priv;
2447         struct ath_hal *ah = sc->sc_ah;
2448
2449         tsf = ath9k_hw_gettsf64(ah);
2450
2451         return tsf;
2452 }
2453
2454 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2455 {
2456         struct ath_softc *sc = hw->priv;
2457         struct ath_hal *ah = sc->sc_ah;
2458
2459         ath9k_hw_settsf64(ah, tsf);
2460 }
2461
2462 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2463 {
2464         struct ath_softc *sc = hw->priv;
2465         struct ath_hal *ah = sc->sc_ah;
2466
2467         ath9k_hw_reset_tsf(ah);
2468 }
2469
2470 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2471                        enum ieee80211_ampdu_mlme_action action,
2472                        struct ieee80211_sta *sta,
2473                        u16 tid, u16 *ssn)
2474 {
2475         struct ath_softc *sc = hw->priv;
2476         int ret = 0;
2477
2478         switch (action) {
2479         case IEEE80211_AMPDU_RX_START:
2480                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2481                         ret = -ENOTSUPP;
2482                 break;
2483         case IEEE80211_AMPDU_RX_STOP:
2484                 break;
2485         case IEEE80211_AMPDU_TX_START:
2486                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2487                 if (ret < 0)
2488                         DPRINTF(sc, ATH_DBG_FATAL,
2489                                 "Unable to start TX aggregation\n");
2490                 else
2491                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2492                 break;
2493         case IEEE80211_AMPDU_TX_STOP:
2494                 ret = ath_tx_aggr_stop(sc, sta, tid);
2495                 if (ret < 0)
2496                         DPRINTF(sc, ATH_DBG_FATAL,
2497                                 "Unable to stop TX aggregation\n");
2498
2499                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2500                 break;
2501         case IEEE80211_AMPDU_TX_RESUME:
2502                 ath_tx_aggr_resume(sc, sta, tid);
2503                 break;
2504         default:
2505                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2506         }
2507
2508         return ret;
2509 }
2510
2511 struct ieee80211_ops ath9k_ops = {
2512         .tx                 = ath9k_tx,
2513         .start              = ath9k_start,
2514         .stop               = ath9k_stop,
2515         .add_interface      = ath9k_add_interface,
2516         .remove_interface   = ath9k_remove_interface,
2517         .config             = ath9k_config,
2518         .config_interface   = ath9k_config_interface,
2519         .configure_filter   = ath9k_configure_filter,
2520         .sta_notify         = ath9k_sta_notify,
2521         .conf_tx            = ath9k_conf_tx,
2522         .bss_info_changed   = ath9k_bss_info_changed,
2523         .set_key            = ath9k_set_key,
2524         .get_tsf            = ath9k_get_tsf,
2525         .set_tsf            = ath9k_set_tsf,
2526         .reset_tsf          = ath9k_reset_tsf,
2527         .ampdu_action       = ath9k_ampdu_action,
2528 };
2529
2530 static struct {
2531         u32 version;
2532         const char * name;
2533 } ath_mac_bb_names[] = {
2534         { AR_SREV_VERSION_5416_PCI,     "5416" },
2535         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2536         { AR_SREV_VERSION_9100,         "9100" },
2537         { AR_SREV_VERSION_9160,         "9160" },
2538         { AR_SREV_VERSION_9280,         "9280" },
2539         { AR_SREV_VERSION_9285,         "9285" }
2540 };
2541
2542 static struct {
2543         u16 version;
2544         const char * name;
2545 } ath_rf_names[] = {
2546         { 0,                            "5133" },
2547         { AR_RAD5133_SREV_MAJOR,        "5133" },
2548         { AR_RAD5122_SREV_MAJOR,        "5122" },
2549         { AR_RAD2133_SREV_MAJOR,        "2133" },
2550         { AR_RAD2122_SREV_MAJOR,        "2122" }
2551 };
2552
2553 /*
2554  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2555  */
2556 const char *
2557 ath_mac_bb_name(u32 mac_bb_version)
2558 {
2559         int i;
2560
2561         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2562                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2563                         return ath_mac_bb_names[i].name;
2564                 }
2565         }
2566
2567         return "????";
2568 }
2569
2570 /*
2571  * Return the RF name. "????" is returned if the RF is unknown.
2572  */
2573 const char *
2574 ath_rf_name(u16 rf_version)
2575 {
2576         int i;
2577
2578         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2579                 if (ath_rf_names[i].version == rf_version) {
2580                         return ath_rf_names[i].name;
2581                 }
2582         }
2583
2584         return "????";
2585 }
2586
2587 static int __init ath9k_init(void)
2588 {
2589         int error;
2590
2591         /* Register rate control algorithm */
2592         error = ath_rate_control_register();
2593         if (error != 0) {
2594                 printk(KERN_ERR
2595                         "ath9k: Unable to register rate control "
2596                         "algorithm: %d\n",
2597                         error);
2598                 goto err_out;
2599         }
2600
2601         error = ath_pci_init();
2602         if (error < 0) {
2603                 printk(KERN_ERR
2604                         "ath9k: No PCI devices found, driver not installed.\n");
2605                 error = -ENODEV;
2606                 goto err_rate_unregister;
2607         }
2608
2609         error = ath_ahb_init();
2610         if (error < 0) {
2611                 error = -ENODEV;
2612                 goto err_pci_exit;
2613         }
2614
2615         return 0;
2616
2617  err_pci_exit:
2618         ath_pci_exit();
2619
2620  err_rate_unregister:
2621         ath_rate_control_unregister();
2622  err_out:
2623         return error;
2624 }
2625 module_init(ath9k_init);
2626
2627 static void __exit ath9k_exit(void)
2628 {
2629         ath_ahb_exit();
2630         ath_pci_exit();
2631         ath_rate_control_unregister();
2632         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2633 }
2634 module_exit(ath9k_exit);