drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20 #include "hw.h"
  21
  22 #define ATH_PCI_VERSION "0.1"
  23
  24 static char *dev_info = "ath9k";
  25
  26 MODULE_AUTHOR("Atheros Communications");
  27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  29 MODULE_LICENSE("Dual BSD/GPL");
  30
  31 static void ath_cache_conf_rate(struct ath_softc *sc,
  32                                 struct ieee80211_conf *conf)
  33 {
  34         switch (conf->channel->band) {
  35         case IEEE80211_BAND_2GHZ:
  36                 if (conf_is_ht20(conf))
  37                         sc->cur_rate_table =
  38                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
  39                 else if (conf_is_ht40_minus(conf))
  40                         sc->cur_rate_table =
  41                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
  42                 else if (conf_is_ht40_plus(conf))
  43                         sc->cur_rate_table =
  44                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
  45                 else
  46                         sc->cur_rate_table =
  47                           sc->hw_rate_table[ATH9K_MODE_11G];
  48                 break;
  49         case IEEE80211_BAND_5GHZ:
  50                 if (conf_is_ht20(conf))
  51                         sc->cur_rate_table =
  52                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
  53                 else if (conf_is_ht40_minus(conf))
  54                         sc->cur_rate_table =
  55                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
  56                 else if (conf_is_ht40_plus(conf))
  57                         sc->cur_rate_table =
  58                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
  59                 else
  60                         sc->cur_rate_table =
  61                           sc->hw_rate_table[ATH9K_MODE_11A];
  62                 break;
  63         default:
  64                 BUG_ON(1);
  65                 break;
  66         }
  67 }
  68
  69 static void ath_update_txpow(struct ath_softc *sc)
  70 {
  71         struct ath_hal *ah = sc->sc_ah;
  72         u32 txpow;
  73
  74         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
  75                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
  76                 /* read back in case value is clamped */
  77                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
  78                 sc->sc_curtxpow = txpow;
  79         }
  80 }
  81
  82 static u8 parse_mpdudensity(u8 mpdudensity)
  83 {
  84         /*
  85          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  86          *   0 for no restriction
  87          *   1 for 1/4 us
  88          *   2 for 1/2 us
  89          *   3 for 1 us
  90          *   4 for 2 us
  91          *   5 for 4 us
  92          *   6 for 8 us
  93          *   7 for 16 us
  94          */
  95         switch (mpdudensity) {
  96         case 0:
  97                 return 0;
  98         case 1:
  99         case 2:
 100         case 3:
 101                 /* Our lower layer calculations limit our precision to
 102                    1 microsecond */
 103                 return 1;
 104         case 4:
 105                 return 2;
 106         case 5:
 107                 return 4;
 108         case 6:
 109                 return 8;
 110         case 7:
 111                 return 16;
 112         default:
 113                 return 0;
 114         }
 115 }
 116
 117 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 118 {
 119         struct ath_rate_table *rate_table = NULL;
 120         struct ieee80211_supported_band *sband;
 121         struct ieee80211_rate *rate;
 122         int i, maxrates;
 123
 124         switch (band) {
 125         case IEEE80211_BAND_2GHZ:
 126                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 127                 break;
 128         case IEEE80211_BAND_5GHZ:
 129                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 130                 break;
 131         default:
 132                 break;
 133         }
 134
 135         if (rate_table == NULL)
 136                 return;
 137
 138         sband = &sc->sbands[band];
 139         rate = sc->rates[band];
 140
 141         if (rate_table->rate_cnt > ATH_RATE_MAX)
 142                 maxrates = ATH_RATE_MAX;
 143         else
 144                 maxrates = rate_table->rate_cnt;
 145
 146         for (i = 0; i < maxrates; i++) {
 147                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 148                 rate[i].hw_value = rate_table->info[i].ratecode;
 149                 sband->n_bitrates++;
 150                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 151                         rate[i].bitrate / 10, rate[i].hw_value);
 152         }
 153 }
 154
 155 static int ath_setup_channels(struct ath_softc *sc)
 156 {
 157         struct ath_hal *ah = sc->sc_ah;
 158         int nchan, i, a = 0, b = 0;
 159         u8 regclassids[ATH_REGCLASSIDS_MAX];
 160         u32 nregclass = 0;
 161         struct ieee80211_supported_band *band_2ghz;
 162         struct ieee80211_supported_band *band_5ghz;
 163         struct ieee80211_channel *chan_2ghz;
 164         struct ieee80211_channel *chan_5ghz;
 165         struct ath9k_channel *c;
 166
 167         /* Fill in ah->ah_channels */
 168         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 169                                       regclassids, ATH_REGCLASSIDS_MAX,
 170                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 171                 u32 rd = ah->ah_currentRD;
 172                 DPRINTF(sc, ATH_DBG_FATAL,
 173                         "Unable to collect channel list; "
 174                         "regdomain likely %u country code %u\n",
 175                         rd, CTRY_DEFAULT);
 176                 return -EINVAL;
 177         }
 178
 179         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 180         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 181         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 182         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 183
 184         for (i = 0; i < nchan; i++) {
 185                 c = &ah->ah_channels[i];
 186                 if (IS_CHAN_2GHZ(c)) {
 187                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 188                         chan_2ghz[a].center_freq = c->channel;
 189                         chan_2ghz[a].max_power = c->maxTxPower;
 190                         c->chan = &chan_2ghz[a];
 191
 192                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 193                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 194                         if (c->channelFlags & CHANNEL_PASSIVE)
 195                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 196
 197                         band_2ghz->n_channels = ++a;
 198
 199                         DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
 200                                 "channelFlags: 0x%x\n",
 201                                 c->channel, c->channelFlags);
 202                 } else if (IS_CHAN_5GHZ(c)) {
 203                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 204                         chan_5ghz[b].center_freq = c->channel;
 205                         chan_5ghz[b].max_power = c->maxTxPower;
 206                         c->chan = &chan_5ghz[a];
 207
 208                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 209                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 210                         if (c->channelFlags & CHANNEL_PASSIVE)
 211                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 212
 213                         band_5ghz->n_channels = ++b;
 214
 215                         DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
 216                                 "channelFlags: 0x%x\n",
 217                                 c->channel, c->channelFlags);
 218                 }
 219         }
 220
 221         return 0;
 222 }
 223
 224 /*
 225  * Set/change channels.  If the channel is really being changed, it's done
 226  * by reseting the chip.  To accomplish this we must first cleanup any pending
 227  * DMA, then restart stuff.
 228 */
 229 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 230 {
 231         struct ath_hal *ah = sc->sc_ah;
 232         bool fastcc = true, stopped;
 233         struct ieee80211_hw *hw = sc->hw;
 234         struct ieee80211_channel *channel = hw->conf.channel;
 235         int r;
 236
 237         if (sc->sc_flags & SC_OP_INVALID)
 238                 return -EIO;
 239
 240         /*
 241          * This is only performed if the channel settings have
 242          * actually changed.
 243          *
 244          * To switch channels clear any pending DMA operations;
 245          * wait long enough for the RX fifo to drain, reset the
 246          * hardware at the new frequency, and then re-enable
 247          * the relevant bits of the h/w.
 248          */
 249         ath9k_hw_set_interrupts(ah, 0);
 250         ath_draintxq(sc, false);
 251         stopped = ath_stoprecv(sc);
 252
 253         /* XXX: do not flush receive queue here. We don't want
 254          * to flush data frames already in queue because of
 255          * changing channel. */
 256
 257         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 258                 fastcc = false;
 259
 260         DPRINTF(sc, ATH_DBG_CONFIG,
 261                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 262                 sc->sc_ah->ah_curchan->channel,
 263                 channel->center_freq, sc->tx_chan_width);
 264
 265         spin_lock_bh(&sc->sc_resetlock);
 266
 267         r = ath9k_hw_reset(ah, hchan, fastcc);
 268         if (r) {
 269                 DPRINTF(sc, ATH_DBG_FATAL,
 270                         "Unable to reset channel (%u Mhz) "
 271                         "reset status %u\n",
 272                         channel->center_freq, r);
 273                 spin_unlock_bh(&sc->sc_resetlock);
 274                 return r;
 275         }
 276         spin_unlock_bh(&sc->sc_resetlock);
 277
 278         sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 279         sc->sc_flags &= ~SC_OP_FULL_RESET;
 280
 281         if (ath_startrecv(sc) != 0) {
 282                 DPRINTF(sc, ATH_DBG_FATAL,
 283                         "Unable to restart recv logic\n");
 284                 return -EIO;
 285         }
 286
 287         ath_cache_conf_rate(sc, &hw->conf);
 288         ath_update_txpow(sc);
 289         ath9k_hw_set_interrupts(ah, sc->sc_imask);
 290         return 0;
 291 }
 292
 293 /*
 294  *  This routine performs the periodic noise floor calibration function
 295  *  that is used to adjust and optimize the chip performance.  This
 296  *  takes environmental changes (location, temperature) into account.
 297  *  When the task is complete, it reschedules itself depending on the
 298  *  appropriate interval that was calculated.
 299  */
 300 static void ath_ani_calibrate(unsigned long data)
 301 {
 302         struct ath_softc *sc;
 303         struct ath_hal *ah;
 304         bool longcal = false;
 305         bool shortcal = false;
 306         bool aniflag = false;
 307         unsigned int timestamp = jiffies_to_msecs(jiffies);
 308         u32 cal_interval;
 309
 310         sc = (struct ath_softc *)data;
 311         ah = sc->sc_ah;
 312
 313         /*
 314         * don't calibrate when we're scanning.
 315         * we are most likely not on our home channel.
 316         */
 317         if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
 318                 return;
 319
 320         /* Long calibration runs independently of short calibration. */
 321         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 322                 longcal = true;
 323                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 324                 sc->sc_ani.sc_longcal_timer = timestamp;
 325         }
 326
 327         /* Short calibration applies only while sc_caldone is false */
 328         if (!sc->sc_ani.sc_caldone) {
 329                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 330                     ATH_SHORT_CALINTERVAL) {
 331                         shortcal = true;
 332                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 333                         sc->sc_ani.sc_shortcal_timer = timestamp;
 334                         sc->sc_ani.sc_resetcal_timer = timestamp;
 335                 }
 336         } else {
 337                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 338                     ATH_RESTART_CALINTERVAL) {
 339                         sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
 340                         if (sc->sc_ani.sc_caldone)
 341                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 342                 }
 343         }
 344
 345         /* Verify whether we must check ANI */
 346         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 347            ATH_ANI_POLLINTERVAL) {
 348                 aniflag = true;
 349                 sc->sc_ani.sc_checkani_timer = timestamp;
 350         }
 351
 352         /* Skip all processing if there's nothing to do. */
 353         if (longcal || shortcal || aniflag) {
 354                 /* Call ANI routine if necessary */
 355                 if (aniflag)
 356                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 357                                              ah->ah_curchan);
 358
 359                 /* Perform calibration if necessary */
 360                 if (longcal || shortcal) {
 361                         bool iscaldone = false;
 362
 363                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 364                                                sc->sc_rx_chainmask, longcal,
 365                                                &iscaldone)) {
 366                                 if (longcal)
 367                                         sc->sc_ani.sc_noise_floor =
 368                                                 ath9k_hw_getchan_noise(ah,
 369                                                                ah->ah_curchan);
 370
 371                                 DPRINTF(sc, ATH_DBG_ANI,
 372                                         "calibrate chan %u/%x nf: %d\n",
 373                                         ah->ah_curchan->channel,
 374                                         ah->ah_curchan->channelFlags,
 375                                         sc->sc_ani.sc_noise_floor);
 376                         } else {
 377                                 DPRINTF(sc, ATH_DBG_ANY,
 378                                         "calibrate chan %u/%x failed\n",
 379                                         ah->ah_curchan->channel,
 380                                         ah->ah_curchan->channelFlags);
 381                         }
 382                         sc->sc_ani.sc_caldone = iscaldone;
 383                 }
 384         }
 385
 386         /*
 387         * Set timer interval based on previous results.
 388         * The interval must be the shortest necessary to satisfy ANI,
 389         * short calibration and long calibration.
 390         */
 391         cal_interval = ATH_LONG_CALINTERVAL;
 392         if (sc->sc_ah->ah_config.enable_ani)
 393                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 394         if (!sc->sc_ani.sc_caldone)
 395                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 396
 397         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 398 }
 399
 400 /*
 401  * Update tx/rx chainmask. For legacy association,
 402  * hard code chainmask to 1x1, for 11n association, use
 403  * the chainmask configuration, for bt coexistence, use
 404  * the chainmask configuration even in legacy mode.
 405  */
 406 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 407 {
 408         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 409         if (is_ht ||
 410             (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 411                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 412                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 413         } else {
 414                 sc->sc_tx_chainmask = 1;
 415                 sc->sc_rx_chainmask = 1;
 416         }
 417
 418         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 419                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 420 }
 421
 422 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 423 {
 424         struct ath_node *an;
 425
 426         an = (struct ath_node *)sta->drv_priv;
 427
 428         if (sc->sc_flags & SC_OP_TXAGGR)
 429                 ath_tx_node_init(sc, an);
 430
 431         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 432                              sta->ht_cap.ampdu_factor);
 433         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 434 }
 435
 436 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 437 {
 438         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 439
 440         if (sc->sc_flags & SC_OP_TXAGGR)
 441                 ath_tx_node_cleanup(sc, an);
 442 }
 443
 444 static void ath9k_tasklet(unsigned long data)
 445 {
 446         struct ath_softc *sc = (struct ath_softc *)data;
 447         u32 status = sc->sc_intrstatus;
 448
 449         if (status & ATH9K_INT_FATAL) {
 450                 /* need a chip reset */
 451                 ath_reset(sc, false);
 452                 return;
 453         } else {
 454
 455                 if (status &
 456                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 457                         spin_lock_bh(&sc->rx.rxflushlock);
 458                         ath_rx_tasklet(sc, 0);
 459                         spin_unlock_bh(&sc->rx.rxflushlock);
 460                 }
 461                 /* XXX: optimize this */
 462                 if (status & ATH9K_INT_TX)
 463                         ath_tx_tasklet(sc);
 464         }
 465
 466         /* re-enable hardware interrupt */
 467         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 468 }
 469
 470 irqreturn_t ath_isr(int irq, void *dev)
 471 {
 472         struct ath_softc *sc = dev;
 473         struct ath_hal *ah = sc->sc_ah;
 474         enum ath9k_int status;
 475         bool sched = false;
 476
 477         do {
 478                 if (sc->sc_flags & SC_OP_INVALID) {
 479                         /*
 480                          * The hardware is not ready/present, don't
 481                          * touch anything. Note this can happen early
 482                          * on if the IRQ is shared.
 483                          */
 484                         return IRQ_NONE;
 485                 }
 486                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 487                         return IRQ_NONE;
 488                 }
 489
 490                 /*
 491                  * Figure out the reason(s) for the interrupt.  Note
 492                  * that the hal returns a pseudo-ISR that may include
 493                  * bits we haven't explicitly enabled so we mask the
 494                  * value to insure we only process bits we requested.
 495                  */
 496                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 497
 498                 status &= sc->sc_imask; /* discard unasked-for bits */
 499
 500                 /*
 501                  * If there are no status bits set, then this interrupt was not
 502                  * for me (should have been caught above).
 503                  */
 504                 if (!status)
 505                         return IRQ_NONE;
 506
 507                 sc->sc_intrstatus = status;
 508
 509                 if (status & ATH9K_INT_FATAL) {
 510                         /* need a chip reset */
 511                         sched = true;
 512                 } else if (status & ATH9K_INT_RXORN) {
 513                         /* need a chip reset */
 514                         sched = true;
 515                 } else {
 516                         if (status & ATH9K_INT_SWBA) {
 517                                 /* schedule a tasklet for beacon handling */
 518                                 tasklet_schedule(&sc->bcon_tasklet);
 519                         }
 520                         if (status & ATH9K_INT_RXEOL) {
 521                                 /*
 522                                  * NB: the hardware should re-read the link when
 523                                  *     RXE bit is written, but it doesn't work
 524                                  *     at least on older hardware revs.
 525                                  */
 526                                 sched = true;
 527                         }
 528
 529                         if (status & ATH9K_INT_TXURN)
 530                                 /* bump tx trigger level */
 531                                 ath9k_hw_updatetxtriglevel(ah, true);
 532                         /* XXX: optimize this */
 533                         if (status & ATH9K_INT_RX)
 534                                 sched = true;
 535                         if (status & ATH9K_INT_TX)
 536                                 sched = true;
 537                         if (status & ATH9K_INT_BMISS)
 538                                 sched = true;
 539                         /* carrier sense timeout */
 540                         if (status & ATH9K_INT_CST)
 541                                 sched = true;
 542                         if (status & ATH9K_INT_MIB) {
 543                                 /*
 544                                  * Disable interrupts until we service the MIB
 545                                  * interrupt; otherwise it will continue to
 546                                  * fire.
 547                                  */
 548                                 ath9k_hw_set_interrupts(ah, 0);
 549                                 /*
 550                                  * Let the hal handle the event. We assume
 551                                  * it will clear whatever condition caused
 552                                  * the interrupt.
 553                                  */
 554                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 555                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 556                         }
 557                         if (status & ATH9K_INT_TIM_TIMER) {
 558                                 if (!(ah->ah_caps.hw_caps &
 559                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 560                                         /* Clear RxAbort bit so that we can
 561                                          * receive frames */
 562                                         ath9k_hw_setrxabort(ah, 0);
 563                                         sched = true;
 564                                 }
 565                         }
 566                 }
 567         } while (0);
 568
 569         ath_debug_stat_interrupt(sc, status);
 570
 571         if (sched) {
 572                 /* turn off every interrupt except SWBA */
 573                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 574                 tasklet_schedule(&sc->intr_tq);
 575         }
 576
 577         return IRQ_HANDLED;
 578 }
 579
 580 static int ath_get_channel(struct ath_softc *sc,
 581                            struct ieee80211_channel *chan)
 582 {
 583         int i;
 584
 585         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 586                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 587                         return i;
 588         }
 589
 590         return -1;
 591 }
 592
 593 static u32 ath_get_extchanmode(struct ath_softc *sc,
 594                                struct ieee80211_channel *chan,
 595                                enum nl80211_channel_type channel_type)
 596 {
 597         u32 chanmode = 0;
 598
 599         switch (chan->band) {
 600         case IEEE80211_BAND_2GHZ:
 601                 switch(channel_type) {
 602                 case NL80211_CHAN_NO_HT:
 603                 case NL80211_CHAN_HT20:
 604                         chanmode = CHANNEL_G_HT20;
 605                         break;
 606                 case NL80211_CHAN_HT40PLUS:
 607                         chanmode = CHANNEL_G_HT40PLUS;
 608                         break;
 609                 case NL80211_CHAN_HT40MINUS:
 610                         chanmode = CHANNEL_G_HT40MINUS;
 611                         break;
 612                 }
 613                 break;
 614         case IEEE80211_BAND_5GHZ:
 615                 switch(channel_type) {
 616                 case NL80211_CHAN_NO_HT:
 617                 case NL80211_CHAN_HT20:
 618                         chanmode = CHANNEL_A_HT20;
 619                         break;
 620                 case NL80211_CHAN_HT40PLUS:
 621                         chanmode = CHANNEL_A_HT40PLUS;
 622                         break;
 623                 case NL80211_CHAN_HT40MINUS:
 624                         chanmode = CHANNEL_A_HT40MINUS;
 625                         break;
 626                 }
 627                 break;
 628         default:
 629                 break;
 630         }
 631
 632         return chanmode;
 633 }
 634
 635 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 636                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 637 {
 638         bool status;
 639
 640         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 641                 keyix, hk, mac, false);
 642
 643         return status != false;
 644 }
 645
 646 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 647                            struct ath9k_keyval *hk,
 648                            const u8 *addr)
 649 {
 650         const u8 *key_rxmic;
 651         const u8 *key_txmic;
 652
 653         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 654         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 655
 656         if (addr == NULL) {
 657                 /* Group key installation */
 658                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 659                 return ath_keyset(sc, keyix, hk, addr);
 660         }
 661         if (!sc->sc_splitmic) {
 662                 /*
 663                  * data key goes at first index,
 664                  * the hal handles the MIC keys at index+64.
 665                  */
 666                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 667                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 668                 return ath_keyset(sc, keyix, hk, addr);
 669         }
 670         /*
 671          * TX key goes at first index, RX key at +32.
 672          * The hal handles the MIC keys at index+64.
 673          */
 674         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 675         if (!ath_keyset(sc, keyix, hk, NULL)) {
 676                 /* Txmic entry failed. No need to proceed further */
 677                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 678                         "Setting TX MIC Key Failed\n");
 679                 return 0;
 680         }
 681
 682         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 683         /* XXX delete tx key on failure? */
 684         return ath_keyset(sc, keyix + 32, hk, addr);
 685 }
 686
 687 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 688 {
 689         int i;
 690
 691         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 692                 if (test_bit(i, sc->sc_keymap) ||
 693                     test_bit(i + 64, sc->sc_keymap))
 694                         continue; /* At least one part of TKIP key allocated */
 695                 if (sc->sc_splitmic &&
 696                     (test_bit(i + 32, sc->sc_keymap) ||
 697                      test_bit(i + 64 + 32, sc->sc_keymap)))
 698                         continue; /* At least one part of TKIP key allocated */
 699
 700                 /* Found a free slot for a TKIP key */
 701                 return i;
 702         }
 703         return -1;
 704 }
 705
 706 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 707 {
 708         int i;
 709
 710         /* First, try to find slots that would not be available for TKIP. */
 711         if (sc->sc_splitmic) {
 712                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
 713                         if (!test_bit(i, sc->sc_keymap) &&
 714                             (test_bit(i + 32, sc->sc_keymap) ||
 715                              test_bit(i + 64, sc->sc_keymap) ||
 716                              test_bit(i + 64 + 32, sc->sc_keymap)))
 717                                 return i;
 718                         if (!test_bit(i + 32, sc->sc_keymap) &&
 719                             (test_bit(i, sc->sc_keymap) ||
 720                              test_bit(i + 64, sc->sc_keymap) ||
 721                              test_bit(i + 64 + 32, sc->sc_keymap)))
 722                                 return i + 32;
 723                         if (!test_bit(i + 64, sc->sc_keymap) &&
 724                             (test_bit(i , sc->sc_keymap) ||
 725                              test_bit(i + 32, sc->sc_keymap) ||
 726                              test_bit(i + 64 + 32, sc->sc_keymap)))
 727                                 return i + 64;
 728                         if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
 729                             (test_bit(i, sc->sc_keymap) ||
 730                              test_bit(i + 32, sc->sc_keymap) ||
 731                              test_bit(i + 64, sc->sc_keymap)))
 732                                 return i + 64 + 32;
 733                 }
 734         } else {
 735                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 736                         if (!test_bit(i, sc->sc_keymap) &&
 737                             test_bit(i + 64, sc->sc_keymap))
 738                                 return i;
 739                         if (test_bit(i, sc->sc_keymap) &&
 740                             !test_bit(i + 64, sc->sc_keymap))
 741                                 return i + 64;
 742                 }
 743         }
 744
 745         /* No partially used TKIP slots, pick any available slot */
 746         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
 747                 /* Do not allow slots that could be needed for TKIP group keys
 748                  * to be used. This limitation could be removed if we know that
 749                  * TKIP will not be used. */
 750                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 751                         continue;
 752                 if (sc->sc_splitmic) {
 753                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 754                                 continue;
 755                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 756                                 continue;
 757                 }
 758
 759                 if (!test_bit(i, sc->sc_keymap))
 760                         return i; /* Found a free slot for a key */
 761         }
 762
 763         /* No free slot found */
 764         return -1;
 765 }
 766
 767 static int ath_key_config(struct ath_softc *sc,
 768                           struct ieee80211_sta *sta,
 769                           struct ieee80211_key_conf *key)
 770 {
 771         struct ath9k_keyval hk;
 772         const u8 *mac = NULL;
 773         int ret = 0;
 774         int idx;
 775
 776         memset(&hk, 0, sizeof(hk));
 777
 778         switch (key->alg) {
 779         case ALG_WEP:
 780                 hk.kv_type = ATH9K_CIPHER_WEP;
 781                 break;
 782         case ALG_TKIP:
 783                 hk.kv_type = ATH9K_CIPHER_TKIP;
 784                 break;
 785         case ALG_CCMP:
 786                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 787                 break;
 788         default:
 789                 return -EOPNOTSUPP;
 790         }
 791
 792         hk.kv_len = key->keylen;
 793         memcpy(hk.kv_val, key->key, key->keylen);
 794
 795         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 796                 /* For now, use the default keys for broadcast keys. This may
 797                  * need to change with virtual interfaces. */
 798                 idx = key->keyidx;
 799         } else if (key->keyidx) {
 800                 struct ieee80211_vif *vif;
 801
 802                 if (WARN_ON(!sta))
 803                         return -EOPNOTSUPP;
 804                 mac = sta->addr;
 805
 806                 vif = sc->sc_vaps[0];
 807                 if (vif->type != NL80211_IFTYPE_AP) {
 808                         /* Only keyidx 0 should be used with unicast key, but
 809                          * allow this for client mode for now. */
 810                         idx = key->keyidx;
 811                 } else
 812                         return -EIO;
 813         } else {
 814                 if (WARN_ON(!sta))
 815                         return -EOPNOTSUPP;
 816                 mac = sta->addr;
 817
 818                 if (key->alg == ALG_TKIP)
 819                         idx = ath_reserve_key_cache_slot_tkip(sc);
 820                 else
 821                         idx = ath_reserve_key_cache_slot(sc);
 822                 if (idx < 0)
 823                         return -ENOSPC; /* no free key cache entries */
 824         }
 825
 826         if (key->alg == ALG_TKIP)
 827                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
 828         else
 829                 ret = ath_keyset(sc, idx, &hk, mac);
 830
 831         if (!ret)
 832                 return -EIO;
 833
 834         set_bit(idx, sc->sc_keymap);
 835         if (key->alg == ALG_TKIP) {
 836                 set_bit(idx + 64, sc->sc_keymap);
 837                 if (sc->sc_splitmic) {
 838                         set_bit(idx + 32, sc->sc_keymap);
 839                         set_bit(idx + 64 + 32, sc->sc_keymap);
 840                 }
 841         }
 842
 843         return idx;
 844 }
 845
 846 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 847 {
 848         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 849         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 850                 return;
 851
 852         clear_bit(key->hw_key_idx, sc->sc_keymap);
 853         if (key->alg != ALG_TKIP)
 854                 return;
 855
 856         clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
 857         if (sc->sc_splitmic) {
 858                 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
 859                 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
 860         }
 861 }
 862
 863 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 864 {
 865 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 866 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 867
 868         ht_info->ht_supported = true;
 869         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 870                        IEEE80211_HT_CAP_SM_PS |
 871                        IEEE80211_HT_CAP_SGI_40 |
 872                        IEEE80211_HT_CAP_DSSSCCK40;
 873
 874         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 875         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 876         /* set up supported mcs set */
 877         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 878         ht_info->mcs.rx_mask[0] = 0xff;
 879         ht_info->mcs.rx_mask[1] = 0xff;
 880         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 881 }
 882
 883 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 884                                  struct ieee80211_vif *vif,
 885                                  struct ieee80211_bss_conf *bss_conf)
 886 {
 887         struct ath_vap *avp = (void *)vif->drv_priv;
 888
 889         if (bss_conf->assoc) {
 890                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 891                         bss_conf->aid, sc->sc_curbssid);
 892
 893                 /* New association, store aid */
 894                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 895                         sc->sc_curaid = bss_conf->aid;
 896                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 897                                                sc->sc_curaid);
 898                 }
 899
 900                 /* Configure the beacon */
 901                 ath_beacon_config(sc, 0);
 902                 sc->sc_flags |= SC_OP_BEACONS;
 903
 904                 /* Reset rssi stats */
 905                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 906                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 907                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 908                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 909
 910                 /* Start ANI */
 911                 mod_timer(&sc->sc_ani.timer,
 912                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 913
 914         } else {
 915                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 916                 sc->sc_curaid = 0;
 917         }
 918 }
 919
 920 /********************************/
 921 /*       LED functions          */
 922 /********************************/
 923
 924 static void ath_led_brightness(struct led_classdev *led_cdev,
 925                                enum led_brightness brightness)
 926 {
 927         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 928         struct ath_softc *sc = led->sc;
 929
 930         switch (brightness) {
 931         case LED_OFF:
 932                 if (led->led_type == ATH_LED_ASSOC ||
 933                     led->led_type == ATH_LED_RADIO)
 934                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 935                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 936                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 937                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 938                 break;
 939         case LED_FULL:
 940                 if (led->led_type == ATH_LED_ASSOC)
 941                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 942                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 943                 break;
 944         default:
 945                 break;
 946         }
 947 }
 948
 949 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 950                             char *trigger)
 951 {
 952         int ret;
 953
 954         led->sc = sc;
 955         led->led_cdev.name = led->name;
 956         led->led_cdev.default_trigger = trigger;
 957         led->led_cdev.brightness_set = ath_led_brightness;
 958
 959         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 960         if (ret)
 961                 DPRINTF(sc, ATH_DBG_FATAL,
 962                         "Failed to register led:%s", led->name);
 963         else
 964                 led->registered = 1;
 965         return ret;
 966 }
 967
 968 static void ath_unregister_led(struct ath_led *led)
 969 {
 970         if (led->registered) {
 971                 led_classdev_unregister(&led->led_cdev);
 972                 led->registered = 0;
 973         }
 974 }
 975
 976 static void ath_deinit_leds(struct ath_softc *sc)
 977 {
 978         ath_unregister_led(&sc->assoc_led);
 979         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 980         ath_unregister_led(&sc->tx_led);
 981         ath_unregister_led(&sc->rx_led);
 982         ath_unregister_led(&sc->radio_led);
 983         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 984 }
 985
 986 static void ath_init_leds(struct ath_softc *sc)
 987 {
 988         char *trigger;
 989         int ret;
 990
 991         /* Configure gpio 1 for output */
 992         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
 993                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 994         /* LED off, active low */
 995         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 996
 997         trigger = ieee80211_get_radio_led_name(sc->hw);
 998         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
 999                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1000         ret = ath_register_led(sc, &sc->radio_led, trigger);
1001         sc->radio_led.led_type = ATH_LED_RADIO;
1002         if (ret)
1003                 goto fail;
1004
1005         trigger = ieee80211_get_assoc_led_name(sc->hw);
1006         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1007                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1008         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1009         sc->assoc_led.led_type = ATH_LED_ASSOC;
1010         if (ret)
1011                 goto fail;
1012
1013         trigger = ieee80211_get_tx_led_name(sc->hw);
1014         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1015                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1016         ret = ath_register_led(sc, &sc->tx_led, trigger);
1017         sc->tx_led.led_type = ATH_LED_TX;
1018         if (ret)
1019                 goto fail;
1020
1021         trigger = ieee80211_get_rx_led_name(sc->hw);
1022         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1023                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1024         ret = ath_register_led(sc, &sc->rx_led, trigger);
1025         sc->rx_led.led_type = ATH_LED_RX;
1026         if (ret)
1027                 goto fail;
1028
1029         return;
1030
1031 fail:
1032         ath_deinit_leds(sc);
1033 }
1034
1035 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1036
1037 /*******************/
1038 /*      Rfkill     */
1039 /*******************/
1040
1041 static void ath_radio_enable(struct ath_softc *sc)
1042 {
1043         struct ath_hal *ah = sc->sc_ah;
1044         struct ieee80211_channel *channel = sc->hw->conf.channel;
1045         int r;
1046
1047         spin_lock_bh(&sc->sc_resetlock);
1048
1049         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1050
1051         if (r) {
1052                 DPRINTF(sc, ATH_DBG_FATAL,
1053                         "Unable to reset channel %u (%uMhz) ",
1054                         "reset status %u\n",
1055                         channel->center_freq, r);
1056         }
1057         spin_unlock_bh(&sc->sc_resetlock);
1058
1059         ath_update_txpow(sc);
1060         if (ath_startrecv(sc) != 0) {
1061                 DPRINTF(sc, ATH_DBG_FATAL,
1062                         "Unable to restart recv logic\n");
1063                 return;
1064         }
1065
1066         if (sc->sc_flags & SC_OP_BEACONS)
1067                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1068
1069         /* Re-Enable  interrupts */
1070         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1071
1072         /* Enable LED */
1073         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1074                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1075         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1076
1077         ieee80211_wake_queues(sc->hw);
1078 }
1079
1080 static void ath_radio_disable(struct ath_softc *sc)
1081 {
1082         struct ath_hal *ah = sc->sc_ah;
1083         struct ieee80211_channel *channel = sc->hw->conf.channel;
1084         int r;
1085
1086         ieee80211_stop_queues(sc->hw);
1087
1088         /* Disable LED */
1089         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1090         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1091
1092         /* Disable interrupts */
1093         ath9k_hw_set_interrupts(ah, 0);
1094
1095         ath_draintxq(sc, false);        /* clear pending tx frames */
1096         ath_stoprecv(sc);               /* turn off frame recv */
1097         ath_flushrecv(sc);              /* flush recv queue */
1098
1099         spin_lock_bh(&sc->sc_resetlock);
1100         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1101         if (r) {
1102                 DPRINTF(sc, ATH_DBG_FATAL,
1103                         "Unable to reset channel %u (%uMhz) "
1104                         "reset status %u\n",
1105                         channel->center_freq, r);
1106         }
1107         spin_unlock_bh(&sc->sc_resetlock);
1108
1109         ath9k_hw_phy_disable(ah);
1110         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1111 }
1112
1113 static bool ath_is_rfkill_set(struct ath_softc *sc)
1114 {
1115         struct ath_hal *ah = sc->sc_ah;
1116
1117         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1118                                   ah->ah_rfkill_polarity;
1119 }
1120
1121 /* h/w rfkill poll function */
1122 static void ath_rfkill_poll(struct work_struct *work)
1123 {
1124         struct ath_softc *sc = container_of(work, struct ath_softc,
1125                                             rf_kill.rfkill_poll.work);
1126         bool radio_on;
1127
1128         if (sc->sc_flags & SC_OP_INVALID)
1129                 return;
1130
1131         radio_on = !ath_is_rfkill_set(sc);
1132
1133         /*
1134          * enable/disable radio only when there is a
1135          * state change in RF switch
1136          */
1137         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1138                 enum rfkill_state state;
1139
1140                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1141                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1142                                 : RFKILL_STATE_HARD_BLOCKED;
1143                 } else if (radio_on) {
1144                         ath_radio_enable(sc);
1145                         state = RFKILL_STATE_UNBLOCKED;
1146                 } else {
1147                         ath_radio_disable(sc);
1148                         state = RFKILL_STATE_HARD_BLOCKED;
1149                 }
1150
1151                 if (state == RFKILL_STATE_HARD_BLOCKED)
1152                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1153                 else
1154                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1155
1156                 rfkill_force_state(sc->rf_kill.rfkill, state);
1157         }
1158
1159         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1160                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1161 }
1162
1163 /* s/w rfkill handler */
1164 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1165 {
1166         struct ath_softc *sc = data;
1167
1168         switch (state) {
1169         case RFKILL_STATE_SOFT_BLOCKED:
1170                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1171                     SC_OP_RFKILL_SW_BLOCKED)))
1172                         ath_radio_disable(sc);
1173                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1174                 return 0;
1175         case RFKILL_STATE_UNBLOCKED:
1176                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1177                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1178                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1179                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1180                                         "radio as it is disabled by h/w\n");
1181                                 return -EPERM;
1182                         }
1183                         ath_radio_enable(sc);
1184                 }
1185                 return 0;
1186         default:
1187                 return -EINVAL;
1188         }
1189 }
1190
1191 /* Init s/w rfkill */
1192 static int ath_init_sw_rfkill(struct ath_softc *sc)
1193 {
1194         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1195                                              RFKILL_TYPE_WLAN);
1196         if (!sc->rf_kill.rfkill) {
1197                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1198                 return -ENOMEM;
1199         }
1200
1201         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1202                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1203         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1204         sc->rf_kill.rfkill->data = sc;
1205         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1206         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1207         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1208
1209         return 0;
1210 }
1211
1212 /* Deinitialize rfkill */
1213 static void ath_deinit_rfkill(struct ath_softc *sc)
1214 {
1215         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1216                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1217
1218         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1219                 rfkill_unregister(sc->rf_kill.rfkill);
1220                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1221                 sc->rf_kill.rfkill = NULL;
1222         }
1223 }
1224
1225 static int ath_start_rfkill_poll(struct ath_softc *sc)
1226 {
1227         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1228                 queue_delayed_work(sc->hw->workqueue,
1229                                    &sc->rf_kill.rfkill_poll, 0);
1230
1231         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1232                 if (rfkill_register(sc->rf_kill.rfkill)) {
1233                         DPRINTF(sc, ATH_DBG_FATAL,
1234                                 "Unable to register rfkill\n");
1235                         rfkill_free(sc->rf_kill.rfkill);
1236
1237                         /* Deinitialize the device */
1238                         ath_cleanup(sc);
1239                         return -EIO;
1240                 } else {
1241                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1242                 }
1243         }
1244
1245         return 0;
1246 }
1247 #endif /* CONFIG_RFKILL */
1248
1249 void ath_cleanup(struct ath_softc *sc)
1250 {
1251         ath_detach(sc);
1252         free_irq(sc->irq, sc);
1253         ath_bus_cleanup(sc);
1254         ieee80211_free_hw(sc->hw);
1255 }
1256
1257 void ath_detach(struct ath_softc *sc)
1258 {
1259         struct ieee80211_hw *hw = sc->hw;
1260         int i = 0;
1261
1262         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1263
1264 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1265         ath_deinit_rfkill(sc);
1266 #endif
1267         ath_deinit_leds(sc);
1268
1269         ieee80211_unregister_hw(hw);
1270         ath_rx_cleanup(sc);
1271         ath_tx_cleanup(sc);
1272
1273         tasklet_kill(&sc->intr_tq);
1274         tasklet_kill(&sc->bcon_tasklet);
1275
1276         if (!(sc->sc_flags & SC_OP_INVALID))
1277                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1278
1279         /* cleanup tx queues */
1280         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1281                 if (ATH_TXQ_SETUP(sc, i))
1282                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1283
1284         ath9k_hw_detach(sc->sc_ah);
1285         ath9k_exit_debug(sc);
1286 }
1287
1288 static int ath_init(u16 devid, struct ath_softc *sc)
1289 {
1290         struct ath_hal *ah = NULL;
1291         int status;
1292         int error = 0, i;
1293         int csz = 0;
1294
1295         /* XXX: hardware will not be ready until ath_open() being called */
1296         sc->sc_flags |= SC_OP_INVALID;
1297
1298         if (ath9k_init_debug(sc) < 0)
1299                 printk(KERN_ERR "Unable to create debugfs files\n");
1300
1301         spin_lock_init(&sc->sc_resetlock);
1302         mutex_init(&sc->mutex);
1303         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1304         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1305                      (unsigned long)sc);
1306
1307         /*
1308          * Cache line size is used to size and align various
1309          * structures used to communicate with the hardware.
1310          */
1311         ath_read_cachesize(sc, &csz);
1312         /* XXX assert csz is non-zero */
1313         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1314
1315         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1316         if (ah == NULL) {
1317                 DPRINTF(sc, ATH_DBG_FATAL,
1318                         "Unable to attach hardware; HAL status %d\n", status);
1319                 error = -ENXIO;
1320                 goto bad;
1321         }
1322         sc->sc_ah = ah;
1323
1324         /* Get the hardware key cache size. */
1325         sc->sc_keymax = ah->ah_caps.keycache_size;
1326         if (sc->sc_keymax > ATH_KEYMAX) {
1327                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1328                         "Warning, using only %u entries in %u key cache\n",
1329                         ATH_KEYMAX, sc->sc_keymax);
1330                 sc->sc_keymax = ATH_KEYMAX;
1331         }
1332
1333         /*
1334          * Reset the key cache since some parts do not
1335          * reset the contents on initial power up.
1336          */
1337         for (i = 0; i < sc->sc_keymax; i++)
1338                 ath9k_hw_keyreset(ah, (u16) i);
1339
1340         /* Collect the channel list using the default country code */
1341
1342         error = ath_setup_channels(sc);
1343         if (error)
1344                 goto bad;
1345
1346         /* default to MONITOR mode */
1347         sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1348
1349
1350         /* Setup rate tables */
1351
1352         ath_rate_attach(sc);
1353         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1354         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1355
1356         /*
1357          * Allocate hardware transmit queues: one queue for
1358          * beacon frames and one data queue for each QoS
1359          * priority.  Note that the hal handles reseting
1360          * these queues at the needed time.
1361          */
1362         sc->beacon.beaconq = ath_beaconq_setup(ah);
1363         if (sc->beacon.beaconq == -1) {
1364                 DPRINTF(sc, ATH_DBG_FATAL,
1365                         "Unable to setup a beacon xmit queue\n");
1366                 error = -EIO;
1367                 goto bad2;
1368         }
1369         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1370         if (sc->beacon.cabq == NULL) {
1371                 DPRINTF(sc, ATH_DBG_FATAL,
1372                         "Unable to setup CAB xmit queue\n");
1373                 error = -EIO;
1374                 goto bad2;
1375         }
1376
1377         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1378         ath_cabq_update(sc);
1379
1380         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1381                 sc->tx.hwq_map[i] = -1;
1382
1383         /* Setup data queues */
1384         /* NB: ensure BK queue is the lowest priority h/w queue */
1385         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1386                 DPRINTF(sc, ATH_DBG_FATAL,
1387                         "Unable to setup xmit queue for BK traffic\n");
1388                 error = -EIO;
1389                 goto bad2;
1390         }
1391
1392         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1393                 DPRINTF(sc, ATH_DBG_FATAL,
1394                         "Unable to setup xmit queue for BE traffic\n");
1395                 error = -EIO;
1396                 goto bad2;
1397         }
1398         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1399                 DPRINTF(sc, ATH_DBG_FATAL,
1400                         "Unable to setup xmit queue for VI traffic\n");
1401                 error = -EIO;
1402                 goto bad2;
1403         }
1404         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1405                 DPRINTF(sc, ATH_DBG_FATAL,
1406                         "Unable to setup xmit queue for VO traffic\n");
1407                 error = -EIO;
1408                 goto bad2;
1409         }
1410
1411         /* Initializes the noise floor to a reasonable default value.
1412          * Later on this will be updated during ANI processing. */
1413
1414         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1415         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1416
1417         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1418                                    ATH9K_CIPHER_TKIP, NULL)) {
1419                 /*
1420                  * Whether we should enable h/w TKIP MIC.
1421                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1422                  * report WMM capable, so it's always safe to turn on
1423                  * TKIP MIC in this case.
1424                  */
1425                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1426                                        0, 1, NULL);
1427         }
1428
1429         /*
1430          * Check whether the separate key cache entries
1431          * are required to handle both tx+rx MIC keys.
1432          * With split mic keys the number of stations is limited
1433          * to 27 otherwise 59.
1434          */
1435         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1436                                    ATH9K_CIPHER_TKIP, NULL)
1437             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1438                                       ATH9K_CIPHER_MIC, NULL)
1439             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1440                                       0, NULL))
1441                 sc->sc_splitmic = 1;
1442
1443         /* turn on mcast key search if possible */
1444         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1445                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1446                                              1, NULL);
1447
1448         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1449         sc->sc_config.txpowlimit_override = 0;
1450
1451         /* 11n Capabilities */
1452         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1453                 sc->sc_flags |= SC_OP_TXAGGR;
1454                 sc->sc_flags |= SC_OP_RXAGGR;
1455         }
1456
1457         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1458         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1459
1460         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1461         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1462
1463         ath9k_hw_getmac(ah, sc->sc_myaddr);
1464         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1465                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1466                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1467                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1468         }
1469
1470         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1471
1472         /* initialize beacon slots */
1473         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1474                 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1475
1476         /* save MISC configurations */
1477         sc->sc_config.swBeaconProcess = 1;
1478
1479         /* setup channels and rates */
1480
1481         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1482                 sc->channels[IEEE80211_BAND_2GHZ];
1483         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1484                 sc->rates[IEEE80211_BAND_2GHZ];
1485         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1486
1487         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1488                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1489                         sc->channels[IEEE80211_BAND_5GHZ];
1490                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1491                         sc->rates[IEEE80211_BAND_5GHZ];
1492                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1493         }
1494
1495         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1496                 ath9k_hw_btcoex_enable(sc->sc_ah);
1497
1498         return 0;
1499 bad2:
1500         /* cleanup tx queues */
1501         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1502                 if (ATH_TXQ_SETUP(sc, i))
1503                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1504 bad:
1505         if (ah)
1506                 ath9k_hw_detach(ah);
1507
1508         return error;
1509 }
1510
1511 int ath_attach(u16 devid, struct ath_softc *sc)
1512 {
1513         struct ieee80211_hw *hw = sc->hw;
1514         int error = 0;
1515
1516         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1517
1518         error = ath_init(devid, sc);
1519         if (error != 0)
1520                 return error;
1521
1522         /* get mac address from hardware and set in mac80211 */
1523
1524         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1525
1526         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1527                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1528                 IEEE80211_HW_SIGNAL_DBM |
1529                 IEEE80211_HW_AMPDU_AGGREGATION;
1530
1531         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1532                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1533
1534         hw->wiphy->interface_modes =
1535                 BIT(NL80211_IFTYPE_AP) |
1536                 BIT(NL80211_IFTYPE_STATION) |
1537                 BIT(NL80211_IFTYPE_ADHOC);
1538
1539         hw->queues = 4;
1540         hw->max_rates = 4;
1541         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1542         hw->sta_data_size = sizeof(struct ath_node);
1543         hw->vif_data_size = sizeof(struct ath_vap);
1544
1545         hw->rate_control_algorithm = "ath9k_rate_control";
1546
1547         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1548                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1549                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1550                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1551         }
1552
1553         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1554         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1555                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1556                         &sc->sbands[IEEE80211_BAND_5GHZ];
1557
1558         /* initialize tx/rx engine */
1559         error = ath_tx_init(sc, ATH_TXBUF);
1560         if (error != 0)
1561                 goto detach;
1562
1563         error = ath_rx_init(sc, ATH_RXBUF);
1564         if (error != 0)
1565                 goto detach;
1566
1567 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1568         /* Initialze h/w Rfkill */
1569         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1570                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1571
1572         /* Initialize s/w rfkill */
1573         if (ath_init_sw_rfkill(sc))
1574                 goto detach;
1575 #endif
1576
1577         error = ieee80211_register_hw(hw);
1578
1579         /* Initialize LED control */
1580         ath_init_leds(sc);
1581
1582         return 0;
1583 detach:
1584         ath_detach(sc);
1585         return error;
1586 }
1587
1588 int ath_reset(struct ath_softc *sc, bool retry_tx)
1589 {
1590         struct ath_hal *ah = sc->sc_ah;
1591         struct ieee80211_hw *hw = sc->hw;
1592         int r;
1593
1594         ath9k_hw_set_interrupts(ah, 0);
1595         ath_draintxq(sc, retry_tx);
1596         ath_stoprecv(sc);
1597         ath_flushrecv(sc);
1598
1599         spin_lock_bh(&sc->sc_resetlock);
1600         r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1601         if (r)
1602                 DPRINTF(sc, ATH_DBG_FATAL,
1603                         "Unable to reset hardware; reset status %u\n", r);
1604         spin_unlock_bh(&sc->sc_resetlock);
1605
1606         if (ath_startrecv(sc) != 0)
1607                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1608
1609         /*
1610          * We may be doing a reset in response to a request
1611          * that changes the channel so update any state that
1612          * might change as a result.
1613          */
1614         ath_cache_conf_rate(sc, &hw->conf);
1615
1616         ath_update_txpow(sc);
1617
1618         if (sc->sc_flags & SC_OP_BEACONS)
1619                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1620
1621         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1622
1623         if (retry_tx) {
1624                 int i;
1625                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1626                         if (ATH_TXQ_SETUP(sc, i)) {
1627                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1628                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1629                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1630                         }
1631                 }
1632         }
1633
1634         return r;
1635 }
1636
1637 /*
1638  *  This function will allocate both the DMA descriptor structure, and the
1639  *  buffers it contains.  These are used to contain the descriptors used
1640  *  by the system.
1641 */
1642 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1643                       struct list_head *head, const char *name,
1644                       int nbuf, int ndesc)
1645 {
1646 #define DS2PHYS(_dd, _ds)                                               \
1647         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1648 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1649 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1650
1651         struct ath_desc *ds;
1652         struct ath_buf *bf;
1653         int i, bsize, error;
1654
1655         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1656                 name, nbuf, ndesc);
1657
1658         /* ath_desc must be a multiple of DWORDs */
1659         if ((sizeof(struct ath_desc) % 4) != 0) {
1660                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1661                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1662                 error = -ENOMEM;
1663                 goto fail;
1664         }
1665
1666         dd->dd_name = name;
1667         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1668
1669         /*
1670          * Need additional DMA memory because we can't use
1671          * descriptors that cross the 4K page boundary. Assume
1672          * one skipped descriptor per 4K page.
1673          */
1674         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1675                 u32 ndesc_skipped =
1676                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1677                 u32 dma_len;
1678
1679                 while (ndesc_skipped) {
1680                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1681                         dd->dd_desc_len += dma_len;
1682
1683                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1684                 };
1685         }
1686
1687         /* allocate descriptors */
1688         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1689                                          &dd->dd_desc_paddr, GFP_ATOMIC);
1690         if (dd->dd_desc == NULL) {
1691                 error = -ENOMEM;
1692                 goto fail;
1693         }
1694         ds = dd->dd_desc;
1695         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1696                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1697                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1698
1699         /* allocate buffers */
1700         bsize = sizeof(struct ath_buf) * nbuf;
1701         bf = kmalloc(bsize, GFP_KERNEL);
1702         if (bf == NULL) {
1703                 error = -ENOMEM;
1704                 goto fail2;
1705         }
1706         memset(bf, 0, bsize);
1707         dd->dd_bufptr = bf;
1708
1709         INIT_LIST_HEAD(head);
1710         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1711                 bf->bf_desc = ds;
1712                 bf->bf_daddr = DS2PHYS(dd, ds);
1713
1714                 if (!(sc->sc_ah->ah_caps.hw_caps &
1715                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1716                         /*
1717                          * Skip descriptor addresses which can cause 4KB
1718                          * boundary crossing (addr + length) with a 32 dword
1719                          * descriptor fetch.
1720                          */
1721                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1722                                 ASSERT((caddr_t) bf->bf_desc <
1723                                        ((caddr_t) dd->dd_desc +
1724                                         dd->dd_desc_len));
1725
1726                                 ds += ndesc;
1727                                 bf->bf_desc = ds;
1728                                 bf->bf_daddr = DS2PHYS(dd, ds);
1729                         }
1730                 }
1731                 list_add_tail(&bf->list, head);
1732         }
1733         return 0;
1734 fail2:
1735         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1736                           dd->dd_desc_paddr);
1737 fail:
1738         memset(dd, 0, sizeof(*dd));
1739         return error;
1740 #undef ATH_DESC_4KB_BOUND_CHECK
1741 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1742 #undef DS2PHYS
1743 }
1744
1745 void ath_descdma_cleanup(struct ath_softc *sc,
1746                          struct ath_descdma *dd,
1747                          struct list_head *head)
1748 {
1749         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1750                           dd->dd_desc_paddr);
1751
1752         INIT_LIST_HEAD(head);
1753         kfree(dd->dd_bufptr);
1754         memset(dd, 0, sizeof(*dd));
1755 }
1756
1757 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1758 {
1759         int qnum;
1760
1761         switch (queue) {
1762         case 0:
1763                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1764                 break;
1765         case 1:
1766                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1767                 break;
1768         case 2:
1769                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1770                 break;
1771         case 3:
1772                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1773                 break;
1774         default:
1775                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1776                 break;
1777         }
1778
1779         return qnum;
1780 }
1781
1782 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1783 {
1784         int qnum;
1785
1786         switch (queue) {
1787         case ATH9K_WME_AC_VO:
1788                 qnum = 0;
1789                 break;
1790         case ATH9K_WME_AC_VI:
1791                 qnum = 1;
1792                 break;
1793         case ATH9K_WME_AC_BE:
1794                 qnum = 2;
1795                 break;
1796         case ATH9K_WME_AC_BK:
1797                 qnum = 3;
1798                 break;
1799         default:
1800                 qnum = -1;
1801                 break;
1802         }
1803
1804         return qnum;
1805 }
1806
1807 /**********************/
1808 /* mac80211 callbacks */
1809 /**********************/
1810
1811 static int ath9k_start(struct ieee80211_hw *hw)
1812 {
1813         struct ath_softc *sc = hw->priv;
1814         struct ieee80211_channel *curchan = hw->conf.channel;
1815         struct ath9k_channel *init_channel;
1816         int r, pos;
1817
1818         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1819                 "initial channel: %d MHz\n", curchan->center_freq);
1820
1821         /* setup initial channel */
1822
1823         pos = ath_get_channel(sc, curchan);
1824         if (pos == -1) {
1825                 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1826                 return -EINVAL;
1827         }
1828
1829         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1830         sc->sc_ah->ah_channels[pos].chanmode =
1831                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1832         init_channel = &sc->sc_ah->ah_channels[pos];
1833
1834         /* Reset SERDES registers */
1835         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1836
1837         /*
1838          * The basic interface to setting the hardware in a good
1839          * state is ``reset''.  On return the hardware is known to
1840          * be powered up and with interrupts disabled.  This must
1841          * be followed by initialization of the appropriate bits
1842          * and then setup of the interrupt mask.
1843          */
1844         spin_lock_bh(&sc->sc_resetlock);
1845         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1846         if (r) {
1847                 DPRINTF(sc, ATH_DBG_FATAL,
1848                         "Unable to reset hardware; reset status %u "
1849                         "(freq %u MHz)\n", r,
1850                         curchan->center_freq);
1851                 spin_unlock_bh(&sc->sc_resetlock);
1852                 return r;
1853         }
1854         spin_unlock_bh(&sc->sc_resetlock);
1855
1856         /*
1857          * This is needed only to setup initial state
1858          * but it's best done after a reset.
1859          */
1860         ath_update_txpow(sc);
1861
1862         /*
1863          * Setup the hardware after reset:
1864          * The receive engine is set going.
1865          * Frame transmit is handled entirely
1866          * in the frame output path; there's nothing to do
1867          * here except setup the interrupt mask.
1868          */
1869         if (ath_startrecv(sc) != 0) {
1870                 DPRINTF(sc, ATH_DBG_FATAL,
1871                         "Unable to start recv logic\n");
1872                 return -EIO;
1873         }
1874
1875         /* Setup our intr mask. */
1876         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1877                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1878                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1879
1880         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1881                 sc->sc_imask |= ATH9K_INT_GTT;
1882
1883         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1884                 sc->sc_imask |= ATH9K_INT_CST;
1885
1886         /*
1887          * Enable MIB interrupts when there are hardware phy counters.
1888          * Note we only do this (at the moment) for station mode.
1889          */
1890         if (ath9k_hw_phycounters(sc->sc_ah) &&
1891             ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1892              (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1893                 sc->sc_imask |= ATH9K_INT_MIB;
1894         /*
1895          * Some hardware processes the TIM IE and fires an
1896          * interrupt when the TIM bit is set.  For hardware
1897          * that does, if not overridden by configuration,
1898          * enable the TIM interrupt when operating as station.
1899          */
1900         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1901             (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1902             !sc->sc_config.swBeaconProcess)
1903                 sc->sc_imask |= ATH9K_INT_TIM;
1904
1905         ath_cache_conf_rate(sc, &hw->conf);
1906
1907         sc->sc_flags &= ~SC_OP_INVALID;
1908
1909         /* Disable BMISS interrupt when we're not associated */
1910         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1911         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1912
1913         ieee80211_wake_queues(sc->hw);
1914
1915 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1916         r = ath_start_rfkill_poll(sc);
1917 #endif
1918         return r;
1919 }
1920
1921 static int ath9k_tx(struct ieee80211_hw *hw,
1922                     struct sk_buff *skb)
1923 {
1924         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1925         struct ath_softc *sc = hw->priv;
1926         struct ath_tx_control txctl;
1927         int hdrlen, padsize;
1928
1929         memset(&txctl, 0, sizeof(struct ath_tx_control));
1930
1931         /*
1932          * As a temporary workaround, assign seq# here; this will likely need
1933          * to be cleaned up to work better with Beacon transmission and virtual
1934          * BSSes.
1935          */
1936         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1937                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1938                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1939                         sc->tx.seq_no += 0x10;
1940                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1941                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1942         }
1943
1944         /* Add the padding after the header if this is not already done */
1945         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1946         if (hdrlen & 3) {
1947                 padsize = hdrlen % 4;
1948                 if (skb_headroom(skb) < padsize)
1949                         return -1;
1950                 skb_push(skb, padsize);
1951                 memmove(skb->data, skb->data + padsize, hdrlen);
1952         }
1953
1954         /* Check if a tx queue is available */
1955
1956         txctl.txq = ath_test_get_txq(sc, skb);
1957         if (!txctl.txq)
1958                 goto exit;
1959
1960         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
1961
1962         if (ath_tx_start(sc, skb, &txctl) != 0) {
1963                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
1964                 goto exit;
1965         }
1966
1967         return 0;
1968 exit:
1969         dev_kfree_skb_any(skb);
1970         return 0;
1971 }
1972
1973 static void ath9k_stop(struct ieee80211_hw *hw)
1974 {
1975         struct ath_softc *sc = hw->priv;
1976
1977         if (sc->sc_flags & SC_OP_INVALID) {
1978                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
1979                 return;
1980         }
1981
1982         DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
1983
1984         ieee80211_stop_queues(sc->hw);
1985
1986         /* make sure h/w will not generate any interrupt
1987          * before setting the invalid flag. */
1988         ath9k_hw_set_interrupts(sc->sc_ah, 0);
1989
1990         if (!(sc->sc_flags & SC_OP_INVALID)) {
1991                 ath_draintxq(sc, false);
1992                 ath_stoprecv(sc);
1993                 ath9k_hw_phy_disable(sc->sc_ah);
1994         } else
1995                 sc->rx.rxlink = NULL;
1996
1997 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1998         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1999                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2000 #endif
2001         /* disable HAL and put h/w to sleep */
2002         ath9k_hw_disable(sc->sc_ah);
2003         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2004
2005         sc->sc_flags |= SC_OP_INVALID;
2006
2007         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2008 }
2009
2010 static int ath9k_add_interface(struct ieee80211_hw *hw,
2011                                struct ieee80211_if_init_conf *conf)
2012 {
2013         struct ath_softc *sc = hw->priv;
2014         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2015         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2016
2017         /* Support only vap for now */
2018
2019         if (sc->sc_nvaps)
2020                 return -ENOBUFS;
2021
2022         switch (conf->type) {
2023         case NL80211_IFTYPE_STATION:
2024                 ic_opmode = NL80211_IFTYPE_STATION;
2025                 break;
2026         case NL80211_IFTYPE_ADHOC:
2027                 ic_opmode = NL80211_IFTYPE_ADHOC;
2028                 break;
2029         case NL80211_IFTYPE_AP:
2030                 ic_opmode = NL80211_IFTYPE_AP;
2031                 break;
2032         default:
2033                 DPRINTF(sc, ATH_DBG_FATAL,
2034                         "Interface type %d not yet supported\n", conf->type);
2035                 return -EOPNOTSUPP;
2036         }
2037
2038         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2039
2040         /* Set the VAP opmode */
2041         avp->av_opmode = ic_opmode;
2042         avp->av_bslot = -1;
2043
2044         if (ic_opmode == NL80211_IFTYPE_AP)
2045                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2046
2047         sc->sc_vaps[0] = conf->vif;
2048         sc->sc_nvaps++;
2049
2050         /* Set the device opmode */
2051         sc->sc_ah->ah_opmode = ic_opmode;
2052
2053         if (conf->type == NL80211_IFTYPE_AP) {
2054                 /* TODO: is this a suitable place to start ANI for AP mode? */
2055                 /* Start ANI */
2056                 mod_timer(&sc->sc_ani.timer,
2057                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2058         }
2059
2060         return 0;
2061 }
2062
2063 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2064                                    struct ieee80211_if_init_conf *conf)
2065 {
2066         struct ath_softc *sc = hw->priv;
2067         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2068
2069         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2070
2071         /* Stop ANI */
2072         del_timer_sync(&sc->sc_ani.timer);
2073
2074         /* Reclaim beacon resources */
2075         if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2076             sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2077                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2078                 ath_beacon_return(sc, avp);
2079         }
2080
2081         sc->sc_flags &= ~SC_OP_BEACONS;
2082
2083         sc->sc_vaps[0] = NULL;
2084         sc->sc_nvaps--;
2085 }
2086
2087 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2088 {
2089         struct ath_softc *sc = hw->priv;
2090         struct ieee80211_conf *conf = &hw->conf;
2091
2092         mutex_lock(&sc->mutex);
2093         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2094                 struct ieee80211_channel *curchan = hw->conf.channel;
2095                 int pos;
2096
2097                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2098                         curchan->center_freq);
2099
2100                 pos = ath_get_channel(sc, curchan);
2101                 if (pos == -1) {
2102                         DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2103                                 curchan->center_freq);
2104                         mutex_unlock(&sc->mutex);
2105                         return -EINVAL;
2106                 }
2107
2108                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2109                 sc->sc_ah->ah_channels[pos].chanmode =
2110                         (curchan->band == IEEE80211_BAND_2GHZ) ?
2111                         CHANNEL_G : CHANNEL_A;
2112
2113                 if (conf_is_ht(conf)) {
2114                         if (conf_is_ht40(conf))
2115                                 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2116
2117                         sc->sc_ah->ah_channels[pos].chanmode =
2118                                 ath_get_extchanmode(sc, curchan,
2119                                                     conf->channel_type);
2120                 }
2121
2122                 ath_update_chainmask(sc, conf_is_ht(conf));
2123
2124                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2125                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2126                         mutex_unlock(&sc->mutex);
2127                         return -EINVAL;
2128                 }
2129         }
2130
2131         if (changed & IEEE80211_CONF_CHANGE_POWER)
2132                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2133
2134         mutex_unlock(&sc->mutex);
2135         return 0;
2136 }
2137
2138 static int ath9k_config_interface(struct ieee80211_hw *hw,
2139                                   struct ieee80211_vif *vif,
2140                                   struct ieee80211_if_conf *conf)
2141 {
2142         struct ath_softc *sc = hw->priv;
2143         struct ath_hal *ah = sc->sc_ah;
2144         struct ath_vap *avp = (void *)vif->drv_priv;
2145         u32 rfilt = 0;
2146         int error, i;
2147
2148         /* TODO: Need to decide which hw opmode to use for multi-interface
2149          * cases */
2150         if (vif->type == NL80211_IFTYPE_AP &&
2151             ah->ah_opmode != NL80211_IFTYPE_AP) {
2152                 ah->ah_opmode = NL80211_IFTYPE_STATION;
2153                 ath9k_hw_setopmode(ah);
2154                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2155                 /* Request full reset to get hw opmode changed properly */
2156                 sc->sc_flags |= SC_OP_FULL_RESET;
2157         }
2158
2159         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2160             !is_zero_ether_addr(conf->bssid)) {
2161                 switch (vif->type) {
2162                 case NL80211_IFTYPE_STATION:
2163                 case NL80211_IFTYPE_ADHOC:
2164                         /* Set BSSID */
2165                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2166                         sc->sc_curaid = 0;
2167                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2168                                                sc->sc_curaid);
2169
2170                         /* Set aggregation protection mode parameters */
2171                         sc->sc_config.ath_aggr_prot = 0;
2172
2173                         DPRINTF(sc, ATH_DBG_CONFIG,
2174                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2175                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2176
2177                         /* need to reconfigure the beacon */
2178                         sc->sc_flags &= ~SC_OP_BEACONS ;
2179
2180                         break;
2181                 default:
2182                         break;
2183                 }
2184         }
2185
2186         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2187             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2188              (vif->type == NL80211_IFTYPE_AP))) {
2189                 /*
2190                  * Allocate and setup the beacon frame.
2191                  *
2192                  * Stop any previous beacon DMA.  This may be
2193                  * necessary, for example, when an ibss merge
2194                  * causes reconfiguration; we may be called
2195                  * with beacon transmission active.
2196                  */
2197                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2198
2199                 error = ath_beacon_alloc(sc, 0);
2200                 if (error != 0)
2201                         return error;
2202
2203                 ath_beacon_sync(sc, 0);
2204         }
2205
2206         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2207         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2208                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2209                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2210                                 ath9k_hw_keysetmac(sc->sc_ah,
2211                                                    (u16)i,
2212                                                    sc->sc_curbssid);
2213         }
2214
2215         /* Only legacy IBSS for now */
2216         if (vif->type == NL80211_IFTYPE_ADHOC)
2217                 ath_update_chainmask(sc, 0);
2218
2219         return 0;
2220 }
2221
2222 #define SUPPORTED_FILTERS                       \
2223         (FIF_PROMISC_IN_BSS |                   \
2224         FIF_ALLMULTI |                          \
2225         FIF_CONTROL |                           \
2226         FIF_OTHER_BSS |                         \
2227         FIF_BCN_PRBRESP_PROMISC |               \
2228         FIF_FCSFAIL)
2229
2230 /* FIXME: sc->sc_full_reset ? */
2231 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2232                                    unsigned int changed_flags,
2233                                    unsigned int *total_flags,
2234                                    int mc_count,
2235                                    struct dev_mc_list *mclist)
2236 {
2237         struct ath_softc *sc = hw->priv;
2238         u32 rfilt;
2239
2240         changed_flags &= SUPPORTED_FILTERS;
2241         *total_flags &= SUPPORTED_FILTERS;
2242
2243         sc->rx.rxfilter = *total_flags;
2244         rfilt = ath_calcrxfilter(sc);
2245         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2246
2247         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2248                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2249                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2250         }
2251
2252         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2253 }
2254
2255 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2256                              struct ieee80211_vif *vif,
2257                              enum sta_notify_cmd cmd,
2258                              struct ieee80211_sta *sta)
2259 {
2260         struct ath_softc *sc = hw->priv;
2261
2262         switch (cmd) {
2263         case STA_NOTIFY_ADD:
2264                 ath_node_attach(sc, sta);
2265                 break;
2266         case STA_NOTIFY_REMOVE:
2267                 ath_node_detach(sc, sta);
2268                 break;
2269         default:
2270                 break;
2271         }
2272 }
2273
2274 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2275                          u16 queue,
2276                          const struct ieee80211_tx_queue_params *params)
2277 {
2278         struct ath_softc *sc = hw->priv;
2279         struct ath9k_tx_queue_info qi;
2280         int ret = 0, qnum;
2281
2282         if (queue >= WME_NUM_AC)
2283                 return 0;
2284
2285         qi.tqi_aifs = params->aifs;
2286         qi.tqi_cwmin = params->cw_min;
2287         qi.tqi_cwmax = params->cw_max;
2288         qi.tqi_burstTime = params->txop;
2289         qnum = ath_get_hal_qnum(queue, sc);
2290
2291         DPRINTF(sc, ATH_DBG_CONFIG,
2292                 "Configure tx [queue/halq] [%d/%d],  "
2293                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2294                 queue, qnum, params->aifs, params->cw_min,
2295                 params->cw_max, params->txop);
2296
2297         ret = ath_txq_update(sc, qnum, &qi);
2298         if (ret)
2299                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2300
2301         return ret;
2302 }
2303
2304 static int ath9k_set_key(struct ieee80211_hw *hw,
2305                          enum set_key_cmd cmd,
2306                          struct ieee80211_vif *vif,
2307                          struct ieee80211_sta *sta,
2308                          struct ieee80211_key_conf *key)
2309 {
2310         struct ath_softc *sc = hw->priv;
2311         int ret = 0;
2312
2313         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2314
2315         switch (cmd) {
2316         case SET_KEY:
2317                 ret = ath_key_config(sc, sta, key);
2318                 if (ret >= 0) {
2319                         key->hw_key_idx = ret;
2320                         /* push IV and Michael MIC generation to stack */
2321                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2322                         if (key->alg == ALG_TKIP)
2323                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2324                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2325                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2326                         ret = 0;
2327                 }
2328                 break;
2329         case DISABLE_KEY:
2330                 ath_key_delete(sc, key);
2331                 break;
2332         default:
2333                 ret = -EINVAL;
2334         }
2335
2336         return ret;
2337 }
2338
2339 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2340                                    struct ieee80211_vif *vif,
2341                                    struct ieee80211_bss_conf *bss_conf,
2342                                    u32 changed)
2343 {
2344         struct ath_softc *sc = hw->priv;
2345
2346         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2347                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2348                         bss_conf->use_short_preamble);
2349                 if (bss_conf->use_short_preamble)
2350                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2351                 else
2352                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2353         }
2354
2355         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2356                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2357                         bss_conf->use_cts_prot);
2358                 if (bss_conf->use_cts_prot &&
2359                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2360                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2361                 else
2362                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2363         }
2364
2365         if (changed & BSS_CHANGED_ASSOC) {
2366                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2367                         bss_conf->assoc);
2368                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2369         }
2370 }
2371
2372 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2373 {
2374         u64 tsf;
2375         struct ath_softc *sc = hw->priv;
2376         struct ath_hal *ah = sc->sc_ah;
2377
2378         tsf = ath9k_hw_gettsf64(ah);
2379
2380         return tsf;
2381 }
2382
2383 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2384 {
2385         struct ath_softc *sc = hw->priv;
2386         struct ath_hal *ah = sc->sc_ah;
2387
2388         ath9k_hw_reset_tsf(ah);
2389 }
2390
2391 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2392                        enum ieee80211_ampdu_mlme_action action,
2393                        struct ieee80211_sta *sta,
2394                        u16 tid, u16 *ssn)
2395 {
2396         struct ath_softc *sc = hw->priv;
2397         int ret = 0;
2398
2399         switch (action) {
2400         case IEEE80211_AMPDU_RX_START:
2401                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2402                         ret = -ENOTSUPP;
2403                 break;
2404         case IEEE80211_AMPDU_RX_STOP:
2405                 break;
2406         case IEEE80211_AMPDU_TX_START:
2407                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2408                 if (ret < 0)
2409                         DPRINTF(sc, ATH_DBG_FATAL,
2410                                 "Unable to start TX aggregation\n");
2411                 else
2412                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2413                 break;
2414         case IEEE80211_AMPDU_TX_STOP:
2415                 ret = ath_tx_aggr_stop(sc, sta, tid);
2416                 if (ret < 0)
2417                         DPRINTF(sc, ATH_DBG_FATAL,
2418                                 "Unable to stop TX aggregation\n");
2419
2420                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2421                 break;
2422         case IEEE80211_AMPDU_TX_RESUME:
2423                 ath_tx_aggr_resume(sc, sta, tid);
2424                 break;
2425         default:
2426                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2427         }
2428
2429         return ret;
2430 }
2431
2432 struct ieee80211_ops ath9k_ops = {
2433         .tx                 = ath9k_tx,
2434         .start              = ath9k_start,
2435         .stop               = ath9k_stop,
2436         .add_interface      = ath9k_add_interface,
2437         .remove_interface   = ath9k_remove_interface,
2438         .config             = ath9k_config,
2439         .config_interface   = ath9k_config_interface,
2440         .configure_filter   = ath9k_configure_filter,
2441         .sta_notify         = ath9k_sta_notify,
2442         .conf_tx            = ath9k_conf_tx,
2443         .bss_info_changed   = ath9k_bss_info_changed,
2444         .set_key            = ath9k_set_key,
2445         .get_tsf            = ath9k_get_tsf,
2446         .reset_tsf          = ath9k_reset_tsf,
2447         .ampdu_action       = ath9k_ampdu_action,
2448 };
2449
2450 static struct {
2451         u32 version;
2452         const char * name;
2453 } ath_mac_bb_names[] = {
2454         { AR_SREV_VERSION_5416_PCI,     "5416" },
2455         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2456         { AR_SREV_VERSION_9100,         "9100" },
2457         { AR_SREV_VERSION_9160,         "9160" },
2458         { AR_SREV_VERSION_9280,         "9280" },
2459         { AR_SREV_VERSION_9285,         "9285" }
2460 };
2461
2462 static struct {
2463         u16 version;
2464         const char * name;
2465 } ath_rf_names[] = {
2466         { 0,                            "5133" },
2467         { AR_RAD5133_SREV_MAJOR,        "5133" },
2468         { AR_RAD5122_SREV_MAJOR,        "5122" },
2469         { AR_RAD2133_SREV_MAJOR,        "2133" },
2470         { AR_RAD2122_SREV_MAJOR,        "2122" }
2471 };
2472
2473 /*
2474  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2475  */
2476 const char *
2477 ath_mac_bb_name(u32 mac_bb_version)
2478 {
2479         int i;
2480
2481         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2482                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2483                         return ath_mac_bb_names[i].name;
2484                 }
2485         }
2486
2487         return "????";
2488 }
2489
2490 /*
2491  * Return the RF name. "????" is returned if the RF is unknown.
2492  */
2493 const char *
2494 ath_rf_name(u16 rf_version)
2495 {
2496         int i;
2497
2498         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2499                 if (ath_rf_names[i].version == rf_version) {
2500                         return ath_rf_names[i].name;
2501                 }
2502         }
2503
2504         return "????";
2505 }
2506
2507 static int __init ath9k_init(void)
2508 {
2509         int error;
2510
2511         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2512
2513         /* Register rate control algorithm */
2514         error = ath_rate_control_register();
2515         if (error != 0) {
2516                 printk(KERN_ERR
2517                         "Unable to register rate control algorithm: %d\n",
2518                         error);
2519                 goto err_out;
2520         }
2521
2522         error = ath_pci_init();
2523         if (error < 0) {
2524                 printk(KERN_ERR
2525                         "ath_pci: No devices found, driver not installed.\n");
2526                 error = -ENODEV;
2527                 goto err_rate_unregister;
2528         }
2529
2530         return 0;
2531
2532  err_rate_unregister:
2533         ath_rate_control_unregister();
2534  err_out:
2535         return error;
2536 }
2537 module_init(ath9k_init);
2538
2539 static void __exit ath9k_exit(void)
2540 {
2541         ath_pci_exit();
2542         ath_rate_control_unregister();
2543         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2544 }
2545 module_exit(ath9k_exit);