drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "core.h"
  21 #include "hw.h"
  22 #include "reg.h"
  23 #include "phy.h"
  24 #include "initvals.h"
  25
  26 static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
  27
  28 extern struct hal_percal_data iq_cal_multi_sample;
  29 extern struct hal_percal_data iq_cal_single_sample;
  30 extern struct hal_percal_data adc_gain_cal_multi_sample;
  31 extern struct hal_percal_data adc_gain_cal_single_sample;
  32 extern struct hal_percal_data adc_dc_cal_multi_sample;
  33 extern struct hal_percal_data adc_dc_cal_single_sample;
  34 extern struct hal_percal_data adc_init_dc_cal;
  35
  36 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
  37 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
  38                               enum ath9k_ht_macmode macmode);
  39 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
  40                               struct ar5416_eeprom *pEepData,
  41                               u32 reg, u32 value);
  42 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  43 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  44
  45 /********************/
  46 /* Helper Functions */
  47 /********************/
  48
  49 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
  50 {
  51         if (ah->ah_curchan != NULL)
  52                 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
  53         else
  54                 return clks / CLOCK_RATE[ATH9K_MODE_11B];
  55 }
  56
  57 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
  58 {
  59         struct ath9k_channel *chan = ah->ah_curchan;
  60
  61         if (chan && IS_CHAN_HT40(chan))
  62                 return ath9k_hw_mac_usec(ah, clks) / 2;
  63         else
  64                 return ath9k_hw_mac_usec(ah, clks);
  65 }
  66
  67 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
  68 {
  69         if (ah->ah_curchan != NULL)
  70                 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
  71                         ah->ah_curchan)];
  72         else
  73                 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
  74 }
  75
  76 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
  77 {
  78         struct ath9k_channel *chan = ah->ah_curchan;
  79
  80         if (chan && IS_CHAN_HT40(chan))
  81                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  82         else
  83                 return ath9k_hw_mac_clks(ah, usecs);
  84 }
  85
  86 enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
  87                                const struct ath9k_channel *chan)
  88 {
  89         if (IS_CHAN_B(chan))
  90                 return ATH9K_MODE_11B;
  91         if (IS_CHAN_G(chan))
  92                 return ATH9K_MODE_11G;
  93
  94         return ATH9K_MODE_11A;
  95 }
  96
  97 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
  98 {
  99         int i;
 100
 101         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
 102                 if ((REG_READ(ah, reg) & mask) == val)
 103                         return true;
 104
 105                 udelay(AH_TIME_QUANTUM);
 106         }
 107
 108         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 109                 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 110                 reg, REG_READ(ah, reg), mask, val);
 111
 112         return false;
 113 }
 114
 115 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 116 {
 117         u32 retval;
 118         int i;
 119
 120         for (i = 0, retval = 0; i < n; i++) {
 121                 retval = (retval << 1) | (val & 1);
 122                 val >>= 1;
 123         }
 124         return retval;
 125 }
 126
 127 bool ath9k_get_channel_edges(struct ath_hal *ah,
 128                              u16 flags, u16 *low,
 129                              u16 *high)
 130 {
 131         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
 132
 133         if (flags & CHANNEL_5GHZ) {
 134                 *low = pCap->low_5ghz_chan;
 135                 *high = pCap->high_5ghz_chan;
 136                 return true;
 137         }
 138         if ((flags & CHANNEL_2GHZ)) {
 139                 *low = pCap->low_2ghz_chan;
 140                 *high = pCap->high_2ghz_chan;
 141                 return true;
 142         }
 143         return false;
 144 }
 145
 146 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
 147                            struct ath_rate_table *rates,
 148                            u32 frameLen, u16 rateix,
 149                            bool shortPreamble)
 150 {
 151         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 152         u32 kbps;
 153
 154         kbps = rates->info[rateix].ratekbps;
 155
 156         if (kbps == 0)
 157                 return 0;
 158
 159         switch (rates->info[rateix].phy) {
 160         case WLAN_RC_PHY_CCK:
 161                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 162                 if (shortPreamble && rates->info[rateix].short_preamble)
 163                         phyTime >>= 1;
 164                 numBits = frameLen << 3;
 165                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 166                 break;
 167         case WLAN_RC_PHY_OFDM:
 168                 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
 169                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 170                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 171                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 172                         txTime = OFDM_SIFS_TIME_QUARTER
 173                                 + OFDM_PREAMBLE_TIME_QUARTER
 174                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 175                 } else if (ah->ah_curchan &&
 176                            IS_CHAN_HALF_RATE(ah->ah_curchan)) {
 177                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 178                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 179                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 180                         txTime = OFDM_SIFS_TIME_HALF +
 181                                 OFDM_PREAMBLE_TIME_HALF
 182                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 183                 } else {
 184                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 185                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 186                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 187                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 188                                 + (numSymbols * OFDM_SYMBOL_TIME);
 189                 }
 190                 break;
 191         default:
 192                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 193                         "Unknown phy %u (rate ix %u)\n",
 194                         rates->info[rateix].phy, rateix);
 195                 txTime = 0;
 196                 break;
 197         }
 198
 199         return txTime;
 200 }
 201
 202 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
 203 {
 204         if (flags & CHANNEL_2GHZ) {
 205                 if (freq == 2484)
 206                         return 14;
 207                 if (freq < 2484)
 208                         return (freq - 2407) / 5;
 209                 else
 210                         return 15 + ((freq - 2512) / 20);
 211         } else if (flags & CHANNEL_5GHZ) {
 212                 if (ath9k_regd_is_public_safety_sku(ah) &&
 213                     IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
 214                         return ((freq * 10) +
 215                                 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
 216                 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
 217                         return (freq - 4000) / 5;
 218                 } else {
 219                         return (freq - 5000) / 5;
 220                 }
 221         } else {
 222                 if (freq == 2484)
 223                         return 14;
 224                 if (freq < 2484)
 225                         return (freq - 2407) / 5;
 226                 if (freq < 5000) {
 227                         if (ath9k_regd_is_public_safety_sku(ah)
 228                             && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
 229                                 return ((freq * 10) +
 230                                         (((freq % 5) ==
 231                                           2) ? 5 : 0) - 49400) / 5;
 232                         } else if (freq > 4900) {
 233                                 return (freq - 4000) / 5;
 234                         } else {
 235                                 return 15 + ((freq - 2512) / 20);
 236                         }
 237                 }
 238                 return (freq - 5000) / 5;
 239         }
 240 }
 241
 242 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
 243                                   struct ath9k_channel *chan,
 244                                   struct chan_centers *centers)
 245 {
 246         int8_t extoff;
 247         struct ath_hal_5416 *ahp = AH5416(ah);
 248
 249         if (!IS_CHAN_HT40(chan)) {
 250                 centers->ctl_center = centers->ext_center =
 251                         centers->synth_center = chan->channel;
 252                 return;
 253         }
 254
 255         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 256             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 257                 centers->synth_center =
 258                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 259                 extoff = 1;
 260         } else {
 261                 centers->synth_center =
 262                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 263                 extoff = -1;
 264         }
 265
 266         centers->ctl_center =
 267                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 268         centers->ext_center =
 269                 centers->synth_center + (extoff *
 270                          ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 271                           HT40_CHANNEL_CENTER_SHIFT : 15));
 272
 273 }
 274
 275 /******************/
 276 /* Chip Revisions */
 277 /******************/
 278
 279 static void ath9k_hw_read_revisions(struct ath_hal *ah)
 280 {
 281         u32 val;
 282
 283         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 284
 285         if (val == 0xFF) {
 286                 val = REG_READ(ah, AR_SREV);
 287                 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 288                 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
 289                 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 290         } else {
 291                 if (!AR_SREV_9100(ah))
 292                         ah->ah_macVersion = MS(val, AR_SREV_VERSION);
 293
 294                 ah->ah_macRev = val & AR_SREV_REVISION;
 295
 296                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
 297                         ah->ah_isPciExpress = true;
 298         }
 299 }
 300
 301 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
 302 {
 303         u32 val;
 304         int i;
 305
 306         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 307
 308         for (i = 0; i < 8; i++)
 309                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 310         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 311         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 312
 313         return ath9k_hw_reverse_bits(val, 8);
 314 }
 315
 316 /************************************/
 317 /* HW Attach, Detach, Init Routines */
 318 /************************************/
 319
 320 static void ath9k_hw_disablepcie(struct ath_hal *ah)
 321 {
 322         if (!AR_SREV_9100(ah))
 323                 return;
 324
 325         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 326         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 327         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 328         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 329         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 330         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 331         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 332         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 333         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 334
 335         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 336 }
 337
 338 static bool ath9k_hw_chip_test(struct ath_hal *ah)
 339 {
 340         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 341         u32 regHold[2];
 342         u32 patternData[4] = { 0x55555555,
 343                                0xaaaaaaaa,
 344                                0x66666666,
 345                                0x99999999 };
 346         int i, j;
 347
 348         for (i = 0; i < 2; i++) {
 349                 u32 addr = regAddr[i];
 350                 u32 wrData, rdData;
 351
 352                 regHold[i] = REG_READ(ah, addr);
 353                 for (j = 0; j < 0x100; j++) {
 354                         wrData = (j << 16) | j;
 355                         REG_WRITE(ah, addr, wrData);
 356                         rdData = REG_READ(ah, addr);
 357                         if (rdData != wrData) {
 358                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 359                                         "address test failed "
 360                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 361                                         addr, wrData, rdData);
 362                                 return false;
 363                         }
 364                 }
 365                 for (j = 0; j < 4; j++) {
 366                         wrData = patternData[j];
 367                         REG_WRITE(ah, addr, wrData);
 368                         rdData = REG_READ(ah, addr);
 369                         if (wrData != rdData) {
 370                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 371                                         "address test failed "
 372                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 373                                         addr, wrData, rdData);
 374                                 return false;
 375                         }
 376                 }
 377                 REG_WRITE(ah, regAddr[i], regHold[i]);
 378         }
 379         udelay(100);
 380         return true;
 381 }
 382
 383 static const char *ath9k_hw_devname(u16 devid)
 384 {
 385         switch (devid) {
 386         case AR5416_DEVID_PCI:
 387                 return "Atheros 5416";
 388         case AR5416_DEVID_PCIE:
 389                 return "Atheros 5418";
 390         case AR9160_DEVID_PCI:
 391                 return "Atheros 9160";
 392         case AR9280_DEVID_PCI:
 393         case AR9280_DEVID_PCIE:
 394                 return "Atheros 9280";
 395         }
 396
 397         return NULL;
 398 }
 399
 400 static void ath9k_hw_set_defaults(struct ath_hal *ah)
 401 {
 402         int i;
 403
 404         ah->ah_config.dma_beacon_response_time = 2;
 405         ah->ah_config.sw_beacon_response_time = 10;
 406         ah->ah_config.additional_swba_backoff = 0;
 407         ah->ah_config.ack_6mb = 0x0;
 408         ah->ah_config.cwm_ignore_extcca = 0;
 409         ah->ah_config.pcie_powersave_enable = 0;
 410         ah->ah_config.pcie_l1skp_enable = 0;
 411         ah->ah_config.pcie_clock_req = 0;
 412         ah->ah_config.pcie_power_reset = 0x100;
 413         ah->ah_config.pcie_restore = 0;
 414         ah->ah_config.pcie_waen = 0;
 415         ah->ah_config.analog_shiftreg = 1;
 416         ah->ah_config.ht_enable = 1;
 417         ah->ah_config.ofdm_trig_low = 200;
 418         ah->ah_config.ofdm_trig_high = 500;
 419         ah->ah_config.cck_trig_high = 200;
 420         ah->ah_config.cck_trig_low = 100;
 421         ah->ah_config.enable_ani = 1;
 422         ah->ah_config.noise_immunity_level = 4;
 423         ah->ah_config.ofdm_weaksignal_det = 1;
 424         ah->ah_config.cck_weaksignal_thr = 0;
 425         ah->ah_config.spur_immunity_level = 2;
 426         ah->ah_config.firstep_level = 0;
 427         ah->ah_config.rssi_thr_high = 40;
 428         ah->ah_config.rssi_thr_low = 7;
 429         ah->ah_config.diversity_control = 0;
 430         ah->ah_config.antenna_switch_swap = 0;
 431
 432         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 433                 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
 434                 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
 435         }
 436
 437         ah->ah_config.intr_mitigation = 1;
 438 }
 439
 440 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
 441                                               struct ath_softc *sc,
 442                                               void __iomem *mem,
 443                                               int *status)
 444 {
 445         static const u8 defbssidmask[ETH_ALEN] =
 446                 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 447         struct ath_hal_5416 *ahp;
 448         struct ath_hal *ah;
 449
 450         ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
 451         if (ahp == NULL) {
 452                 DPRINTF(sc, ATH_DBG_FATAL,
 453                         "Cannot allocate memory for state block\n");
 454                 *status = -ENOMEM;
 455                 return NULL;
 456         }
 457
 458         ah = &ahp->ah;
 459         ah->ah_sc = sc;
 460         ah->ah_sh = mem;
 461         ah->ah_magic = AR5416_MAGIC;
 462         ah->ah_countryCode = CTRY_DEFAULT;
 463         ah->ah_devid = devid;
 464         ah->ah_subvendorid = 0;
 465
 466         ah->ah_flags = 0;
 467         if ((devid == AR5416_AR9100_DEVID))
 468                 ah->ah_macVersion = AR_SREV_VERSION_9100;
 469         if (!AR_SREV_9100(ah))
 470                 ah->ah_flags = AH_USE_EEPROM;
 471
 472         ah->ah_powerLimit = MAX_RATE_POWER;
 473         ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
 474         ahp->ah_atimWindow = 0;
 475         ahp->ah_diversityControl = ah->ah_config.diversity_control;
 476         ahp->ah_antennaSwitchSwap =
 477                 ah->ah_config.antenna_switch_swap;
 478         ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 479         ahp->ah_beaconInterval = 100;
 480         ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
 481         ahp->ah_slottime = (u32) -1;
 482         ahp->ah_acktimeout = (u32) -1;
 483         ahp->ah_ctstimeout = (u32) -1;
 484         ahp->ah_globaltxtimeout = (u32) -1;
 485         memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
 486
 487         ahp->ah_gBeaconRate = 0;
 488
 489         return ahp;
 490 }
 491
 492 static int ath9k_hw_rfattach(struct ath_hal *ah)
 493 {
 494         bool rfStatus = false;
 495         int ecode = 0;
 496
 497         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 498         if (!rfStatus) {
 499                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 500                         "RF setup failed, status %u\n", ecode);
 501                 return ecode;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static int ath9k_hw_rf_claim(struct ath_hal *ah)
 508 {
 509         u32 val;
 510
 511         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 512
 513         val = ath9k_hw_get_radiorev(ah);
 514         switch (val & AR_RADIO_SREV_MAJOR) {
 515         case 0:
 516                 val = AR_RAD5133_SREV_MAJOR;
 517                 break;
 518         case AR_RAD5133_SREV_MAJOR:
 519         case AR_RAD5122_SREV_MAJOR:
 520         case AR_RAD2133_SREV_MAJOR:
 521         case AR_RAD2122_SREV_MAJOR:
 522                 break;
 523         default:
 524                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 525                         "5G Radio Chip Rev 0x%02X is not "
 526                         "supported by this driver\n",
 527                         ah->ah_analog5GhzRev);
 528                 return -EOPNOTSUPP;
 529         }
 530
 531         ah->ah_analog5GhzRev = val;
 532
 533         return 0;
 534 }
 535
 536 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
 537 {
 538         u32 sum;
 539         int i;
 540         u16 eeval;
 541         struct ath_hal_5416 *ahp = AH5416(ah);
 542
 543         sum = 0;
 544         for (i = 0; i < 3; i++) {
 545                 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
 546                 sum += eeval;
 547                 ahp->ah_macaddr[2 * i] = eeval >> 8;
 548                 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
 549         }
 550         if (sum == 0 || sum == 0xffff * 3) {
 551                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 552                         "mac address read failed: %pM\n",
 553                         ahp->ah_macaddr);
 554                 return -EADDRNOTAVAIL;
 555         }
 556
 557         return 0;
 558 }
 559
 560 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
 561 {
 562         u32 rxgain_type;
 563         struct ath_hal_5416 *ahp = AH5416(ah);
 564
 565         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 566                 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
 567
 568                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 569                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 570                         ar9280Modes_backoff_13db_rxgain_9280_2,
 571                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 572                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 573                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 574                         ar9280Modes_backoff_23db_rxgain_9280_2,
 575                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 576                 else
 577                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 578                         ar9280Modes_original_rxgain_9280_2,
 579                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 580         } else
 581                 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 582                         ar9280Modes_original_rxgain_9280_2,
 583                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 584 }
 585
 586 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
 587 {
 588         u32 txgain_type;
 589         struct ath_hal_5416 *ahp = AH5416(ah);
 590
 591         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 592                 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
 593
 594                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 595                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 596                         ar9280Modes_high_power_tx_gain_9280_2,
 597                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 598                 else
 599                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 600                         ar9280Modes_original_tx_gain_9280_2,
 601                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 602         } else
 603                 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 604                 ar9280Modes_original_tx_gain_9280_2,
 605                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 606 }
 607
 608 static int ath9k_hw_post_attach(struct ath_hal *ah)
 609 {
 610         int ecode;
 611
 612         if (!ath9k_hw_chip_test(ah)) {
 613                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 614                         "hardware self-test failed\n");
 615                 return -ENODEV;
 616         }
 617
 618         ecode = ath9k_hw_rf_claim(ah);
 619         if (ecode != 0)
 620                 return ecode;
 621
 622         ecode = ath9k_hw_eeprom_attach(ah);
 623         if (ecode != 0)
 624                 return ecode;
 625         ecode = ath9k_hw_rfattach(ah);
 626         if (ecode != 0)
 627                 return ecode;
 628
 629         if (!AR_SREV_9100(ah)) {
 630                 ath9k_hw_ani_setup(ah);
 631                 ath9k_hw_ani_attach(ah);
 632         }
 633
 634         return 0;
 635 }
 636
 637 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 638                                           void __iomem *mem, int *status)
 639 {
 640         struct ath_hal_5416 *ahp;
 641         struct ath_hal *ah;
 642         int ecode;
 643         u32 i, j;
 644
 645         ahp = ath9k_hw_newstate(devid, sc, mem, status);
 646         if (ahp == NULL)
 647                 return NULL;
 648
 649         ah = &ahp->ah;
 650
 651         ath9k_hw_set_defaults(ah);
 652
 653         if (ah->ah_config.intr_mitigation != 0)
 654                 ahp->ah_intrMitigation = true;
 655
 656         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 657                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
 658                 ecode = -EIO;
 659                 goto bad;
 660         }
 661
 662         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 663                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
 664                 ecode = -EIO;
 665                 goto bad;
 666         }
 667
 668         if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
 669                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
 670                         ah->ah_config.serialize_regmode =
 671                                 SER_REG_MODE_ON;
 672                 } else {
 673                         ah->ah_config.serialize_regmode =
 674                                 SER_REG_MODE_OFF;
 675                 }
 676         }
 677
 678         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 679                 "serialize_regmode is %d\n",
 680                 ah->ah_config.serialize_regmode);
 681
 682         if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
 683             (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
 684             (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
 685             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
 686                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 687                         "Mac Chip Rev 0x%02x.%x is not supported by "
 688                         "this driver\n", ah->ah_macVersion, ah->ah_macRev);
 689                 ecode = -EOPNOTSUPP;
 690                 goto bad;
 691         }
 692
 693         if (AR_SREV_9100(ah)) {
 694                 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 695                 ahp->ah_suppCals = IQ_MISMATCH_CAL;
 696                 ah->ah_isPciExpress = false;
 697         }
 698         ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 699
 700         if (AR_SREV_9160_10_OR_LATER(ah)) {
 701                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 702                         ahp->ah_iqCalData.calData = &iq_cal_single_sample;
 703                         ahp->ah_adcGainCalData.calData =
 704                                 &adc_gain_cal_single_sample;
 705                         ahp->ah_adcDcCalData.calData =
 706                                 &adc_dc_cal_single_sample;
 707                         ahp->ah_adcDcCalInitData.calData =
 708                                 &adc_init_dc_cal;
 709                 } else {
 710                         ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 711                         ahp->ah_adcGainCalData.calData =
 712                                 &adc_gain_cal_multi_sample;
 713                         ahp->ah_adcDcCalData.calData =
 714                                 &adc_dc_cal_multi_sample;
 715                         ahp->ah_adcDcCalInitData.calData =
 716                                 &adc_init_dc_cal;
 717                 }
 718                 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 719         }
 720
 721         if (AR_SREV_9160(ah)) {
 722                 ah->ah_config.enable_ani = 1;
 723                 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
 724                                         ATH9K_ANI_FIRSTEP_LEVEL);
 725         } else {
 726                 ahp->ah_ani_function = ATH9K_ANI_ALL;
 727                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 728                         ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 729                 }
 730         }
 731
 732         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 733                 "This Mac Chip Rev 0x%02x.%x is \n",
 734                 ah->ah_macVersion, ah->ah_macRev);
 735
 736         if (AR_SREV_9280_20_OR_LATER(ah)) {
 737                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
 738                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 739                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
 740                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 741
 742                 if (ah->ah_config.pcie_clock_req) {
 743                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 744                                ar9280PciePhy_clkreq_off_L1_9280,
 745                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 746                 } else {
 747                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 748                                ar9280PciePhy_clkreq_always_on_L1_9280,
 749                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 750                 }
 751                 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
 752                                ar9280Modes_fast_clock_9280_2,
 753                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 754         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 755                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
 756                                ARRAY_SIZE(ar9280Modes_9280), 6);
 757                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
 758                                ARRAY_SIZE(ar9280Common_9280), 2);
 759         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 760                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
 761                                ARRAY_SIZE(ar5416Modes_9160), 6);
 762                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
 763                                ARRAY_SIZE(ar5416Common_9160), 2);
 764                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
 765                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 766                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
 767                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 768                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
 769                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 770                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
 771                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 772                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
 773                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 774                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
 775                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 776                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
 777                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 778                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
 779                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 780                 if (AR_SREV_9160_11(ah)) {
 781                         INIT_INI_ARRAY(&ahp->ah_iniAddac,
 782                                        ar5416Addac_91601_1,
 783                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 784                 } else {
 785                         INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
 786                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 787                 }
 788         } else if (AR_SREV_9100_OR_LATER(ah)) {
 789                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
 790                                ARRAY_SIZE(ar5416Modes_9100), 6);
 791                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
 792                                ARRAY_SIZE(ar5416Common_9100), 2);
 793                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
 794                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 795                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
 796                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 797                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
 798                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 799                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
 800                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 801                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
 802                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 803                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
 804                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 805                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
 806                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 807                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
 808                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 809                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
 810                                ARRAY_SIZE(ar5416Addac_9100), 2);
 811         } else {
 812                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
 813                                ARRAY_SIZE(ar5416Modes), 6);
 814                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
 815                                ARRAY_SIZE(ar5416Common), 2);
 816                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
 817                                ARRAY_SIZE(ar5416Bank0), 2);
 818                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
 819                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 820                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
 821                                ARRAY_SIZE(ar5416Bank1), 2);
 822                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
 823                                ARRAY_SIZE(ar5416Bank2), 2);
 824                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
 825                                ARRAY_SIZE(ar5416Bank3), 3);
 826                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
 827                                ARRAY_SIZE(ar5416Bank6), 3);
 828                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
 829                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 830                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
 831                                ARRAY_SIZE(ar5416Bank7), 2);
 832                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
 833                                ARRAY_SIZE(ar5416Addac), 2);
 834         }
 835
 836         if (ah->ah_isPciExpress)
 837                 ath9k_hw_configpcipowersave(ah, 0);
 838         else
 839                 ath9k_hw_disablepcie(ah);
 840
 841         ecode = ath9k_hw_post_attach(ah);
 842         if (ecode != 0)
 843                 goto bad;
 844
 845         /* rxgain table */
 846         if (AR_SREV_9280_20_OR_LATER(ah))
 847                 ath9k_hw_init_rxgain_ini(ah);
 848
 849         /* txgain table */
 850         if (AR_SREV_9280_20_OR_LATER(ah))
 851                 ath9k_hw_init_txgain_ini(ah);
 852
 853         if (ah->ah_devid == AR9280_DEVID_PCI) {
 854                 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
 855                         u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
 856
 857                         for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
 858                                 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
 859
 860                                 INI_RA(&ahp->ah_iniModes, i, j) =
 861                                         ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
 862                                                            reg, val);
 863                         }
 864                 }
 865         }
 866
 867         if (!ath9k_hw_fill_cap_info(ah)) {
 868                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 869                         "failed ath9k_hw_fill_cap_info\n");
 870                 ecode = -EINVAL;
 871                 goto bad;
 872         }
 873
 874         ecode = ath9k_hw_init_macaddr(ah);
 875         if (ecode != 0) {
 876                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 877                         "failed initializing mac address\n");
 878                 goto bad;
 879         }
 880
 881         if (AR_SREV_9285(ah))
 882                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
 883         else
 884                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
 885
 886         ath9k_init_nfcal_hist_buffer(ah);
 887
 888         return ah;
 889 bad:
 890         if (ahp)
 891                 ath9k_hw_detach((struct ath_hal *) ahp);
 892         if (status)
 893                 *status = ecode;
 894
 895         return NULL;
 896 }
 897
 898 static void ath9k_hw_init_bb(struct ath_hal *ah,
 899                              struct ath9k_channel *chan)
 900 {
 901         u32 synthDelay;
 902
 903         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 904         if (IS_CHAN_B(chan))
 905                 synthDelay = (4 * synthDelay) / 22;
 906         else
 907                 synthDelay /= 10;
 908
 909         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 910
 911         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 912 }
 913
 914 static void ath9k_hw_init_qos(struct ath_hal *ah)
 915 {
 916         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 917         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 918
 919         REG_WRITE(ah, AR_QOS_NO_ACK,
 920                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 921                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 922                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 923
 924         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 925         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 926         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 927         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 928         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 929 }
 930
 931 static void ath9k_hw_init_pll(struct ath_hal *ah,
 932                               struct ath9k_channel *chan)
 933 {
 934         u32 pll;
 935
 936         if (AR_SREV_9100(ah)) {
 937                 if (chan && IS_CHAN_5GHZ(chan))
 938                         pll = 0x1450;
 939                 else
 940                         pll = 0x1458;
 941         } else {
 942                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 943                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 944
 945                         if (chan && IS_CHAN_HALF_RATE(chan))
 946                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 947                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 948                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 949
 950                         if (chan && IS_CHAN_5GHZ(chan)) {
 951                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 952
 953
 954                                 if (AR_SREV_9280_20(ah)) {
 955                                         if (((chan->channel % 20) == 0)
 956                                             || ((chan->channel % 10) == 0))
 957                                                 pll = 0x2850;
 958                                         else
 959                                                 pll = 0x142c;
 960                                 }
 961                         } else {
 962                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 963                         }
 964
 965                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 966
 967                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 968
 969                         if (chan && IS_CHAN_HALF_RATE(chan))
 970                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 971                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 972                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 973
 974                         if (chan && IS_CHAN_5GHZ(chan))
 975                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
 976                         else
 977                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
 978                 } else {
 979                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
 980
 981                         if (chan && IS_CHAN_HALF_RATE(chan))
 982                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
 983                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 984                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
 985
 986                         if (chan && IS_CHAN_5GHZ(chan))
 987                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
 988                         else
 989                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
 990                 }
 991         }
 992         REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
 993
 994         udelay(RTC_PLL_SETTLE_DELAY);
 995
 996         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 997 }
 998
 999 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1000 {
1001         struct ath_hal_5416 *ahp = AH5416(ah);
1002         int rx_chainmask, tx_chainmask;
1003
1004         rx_chainmask = ahp->ah_rxchainmask;
1005         tx_chainmask = ahp->ah_txchainmask;
1006
1007         switch (rx_chainmask) {
1008         case 0x5:
1009                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1010                             AR_PHY_SWAP_ALT_CHAIN);
1011         case 0x3:
1012                 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1013                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1014                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1015                         break;
1016                 }
1017         case 0x1:
1018         case 0x2:
1019                 if (!AR_SREV_9280(ah))
1020                         break;
1021         case 0x7:
1022                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1023                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1024                 break;
1025         default:
1026                 break;
1027         }
1028
1029         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1030         if (tx_chainmask == 0x5) {
1031                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1032                             AR_PHY_SWAP_ALT_CHAIN);
1033         }
1034         if (AR_SREV_9100(ah))
1035                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1036                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1037 }
1038
1039 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1040                                           enum nl80211_iftype opmode)
1041 {
1042         struct ath_hal_5416 *ahp = AH5416(ah);
1043
1044         ahp->ah_maskReg = AR_IMR_TXERR |
1045                 AR_IMR_TXURN |
1046                 AR_IMR_RXERR |
1047                 AR_IMR_RXORN |
1048                 AR_IMR_BCNMISC;
1049
1050         if (ahp->ah_intrMitigation)
1051                 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1052         else
1053                 ahp->ah_maskReg |= AR_IMR_RXOK;
1054
1055         ahp->ah_maskReg |= AR_IMR_TXOK;
1056
1057         if (opmode == NL80211_IFTYPE_AP)
1058                 ahp->ah_maskReg |= AR_IMR_MIB;
1059
1060         REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1061         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1062
1063         if (!AR_SREV_9100(ah)) {
1064                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1065                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1066                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1067         }
1068 }
1069
1070 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1071 {
1072         struct ath_hal_5416 *ahp = AH5416(ah);
1073
1074         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1075                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1076                 ahp->ah_acktimeout = (u32) -1;
1077                 return false;
1078         } else {
1079                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1080                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1081                 ahp->ah_acktimeout = us;
1082                 return true;
1083         }
1084 }
1085
1086 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1087 {
1088         struct ath_hal_5416 *ahp = AH5416(ah);
1089
1090         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1091                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1092                 ahp->ah_ctstimeout = (u32) -1;
1093                 return false;
1094         } else {
1095                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1096                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1097                 ahp->ah_ctstimeout = us;
1098                 return true;
1099         }
1100 }
1101
1102 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1103 {
1104         struct ath_hal_5416 *ahp = AH5416(ah);
1105
1106         if (tu > 0xFFFF) {
1107                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1108                         "bad global tx timeout %u\n", tu);
1109                 ahp->ah_globaltxtimeout = (u32) -1;
1110                 return false;
1111         } else {
1112                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1113                 ahp->ah_globaltxtimeout = tu;
1114                 return true;
1115         }
1116 }
1117
1118 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1119 {
1120         struct ath_hal_5416 *ahp = AH5416(ah);
1121
1122         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1123                 ahp->ah_miscMode);
1124
1125         if (ahp->ah_miscMode != 0)
1126                 REG_WRITE(ah, AR_PCU_MISC,
1127                           REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1128         if (ahp->ah_slottime != (u32) -1)
1129                 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1130         if (ahp->ah_acktimeout != (u32) -1)
1131                 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1132         if (ahp->ah_ctstimeout != (u32) -1)
1133                 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1134         if (ahp->ah_globaltxtimeout != (u32) -1)
1135                 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1136 }
1137
1138 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1139 {
1140         return vendorid == ATHEROS_VENDOR_ID ?
1141                 ath9k_hw_devname(devid) : NULL;
1142 }
1143
1144 void ath9k_hw_detach(struct ath_hal *ah)
1145 {
1146         if (!AR_SREV_9100(ah))
1147                 ath9k_hw_ani_detach(ah);
1148
1149         ath9k_hw_rfdetach(ah);
1150         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1151         kfree(ah);
1152 }
1153
1154 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1155                                 void __iomem *mem, int *error)
1156 {
1157         struct ath_hal *ah = NULL;
1158
1159         switch (devid) {
1160         case AR5416_DEVID_PCI:
1161         case AR5416_DEVID_PCIE:
1162         case AR9160_DEVID_PCI:
1163         case AR9280_DEVID_PCI:
1164         case AR9280_DEVID_PCIE:
1165                 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1166                 break;
1167         default:
1168                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1169                         "devid=0x%x not supported.\n", devid);
1170                 ah = NULL;
1171                 *error = -ENXIO;
1172                 break;
1173         }
1174
1175         return ah;
1176 }
1177
1178 /*******/
1179 /* INI */
1180 /*******/
1181
1182 static void ath9k_hw_override_ini(struct ath_hal *ah,
1183                                   struct ath9k_channel *chan)
1184 {
1185         if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1186             AR_SREV_9280_10_OR_LATER(ah))
1187                 return;
1188
1189         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1190 }
1191
1192 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1193                               struct ar5416_eeprom *pEepData,
1194                               u32 reg, u32 value)
1195 {
1196         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1197
1198         switch (ah->ah_devid) {
1199         case AR9280_DEVID_PCI:
1200                 if (reg == 0x7894) {
1201                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1202                                 "ini VAL: %x  EEPROM: %x\n", value,
1203                                 (pBase->version & 0xff));
1204
1205                         if ((pBase->version & 0xff) > 0x0a) {
1206                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1207                                         "PWDCLKIND: %d\n",
1208                                         pBase->pwdclkind);
1209                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1210                                 value |= AR_AN_TOP2_PWDCLKIND &
1211                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1212                         } else {
1213                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1214                                         "PWDCLKIND Earlier Rev\n");
1215                         }
1216
1217                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1218                                 "final ini VAL: %x\n", value);
1219                 }
1220                 break;
1221         }
1222
1223         return value;
1224 }
1225
1226 static int ath9k_hw_process_ini(struct ath_hal *ah,
1227                                 struct ath9k_channel *chan,
1228                                 enum ath9k_ht_macmode macmode)
1229 {
1230         int i, regWrites = 0;
1231         struct ath_hal_5416 *ahp = AH5416(ah);
1232         u32 modesIndex, freqIndex;
1233         int status;
1234
1235         switch (chan->chanmode) {
1236         case CHANNEL_A:
1237         case CHANNEL_A_HT20:
1238                 modesIndex = 1;
1239                 freqIndex = 1;
1240                 break;
1241         case CHANNEL_A_HT40PLUS:
1242         case CHANNEL_A_HT40MINUS:
1243                 modesIndex = 2;
1244                 freqIndex = 1;
1245                 break;
1246         case CHANNEL_G:
1247         case CHANNEL_G_HT20:
1248         case CHANNEL_B:
1249                 modesIndex = 4;
1250                 freqIndex = 2;
1251                 break;
1252         case CHANNEL_G_HT40PLUS:
1253         case CHANNEL_G_HT40MINUS:
1254                 modesIndex = 3;
1255                 freqIndex = 2;
1256                 break;
1257
1258         default:
1259                 return -EINVAL;
1260         }
1261
1262         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1263
1264         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1265
1266         ath9k_hw_set_addac(ah, chan);
1267
1268         if (AR_SREV_5416_V22_OR_LATER(ah)) {
1269                 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1270         } else {
1271                 struct ar5416IniArray temp;
1272                 u32 addacSize =
1273                         sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1274                         ahp->ah_iniAddac.ia_columns;
1275
1276                 memcpy(ahp->ah_addac5416_21,
1277                        ahp->ah_iniAddac.ia_array, addacSize);
1278
1279                 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1280
1281                 temp.ia_array = ahp->ah_addac5416_21;
1282                 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1283                 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1284                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1285         }
1286
1287         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1288
1289         for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1290                 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1291                 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1292
1293                 REG_WRITE(ah, reg, val);
1294
1295                 if (reg >= 0x7800 && reg < 0x78a0
1296                     && ah->ah_config.analog_shiftreg) {
1297                         udelay(100);
1298                 }
1299
1300                 DO_DELAY(regWrites);
1301         }
1302
1303         if (AR_SREV_9280_20_OR_LATER(ah))
1304                 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1305
1306         if (AR_SREV_9280_20_OR_LATER(ah))
1307                 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1308
1309         for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1310                 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1311                 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1312
1313                 REG_WRITE(ah, reg, val);
1314
1315                 if (reg >= 0x7800 && reg < 0x78a0
1316                     && ah->ah_config.analog_shiftreg) {
1317                         udelay(100);
1318                 }
1319
1320                 DO_DELAY(regWrites);
1321         }
1322
1323         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1324
1325         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1326                 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1327                                 regWrites);
1328         }
1329
1330         ath9k_hw_override_ini(ah, chan);
1331         ath9k_hw_set_regs(ah, chan, macmode);
1332         ath9k_hw_init_chain_masks(ah);
1333
1334         status = ath9k_hw_set_txpower(ah, chan,
1335                                       ath9k_regd_get_ctl(ah, chan),
1336                                       ath9k_regd_get_antenna_allowed(ah,
1337                                                                      chan),
1338                                       chan->maxRegTxPower * 2,
1339                                       min((u32) MAX_RATE_POWER,
1340                                           (u32) ah->ah_powerLimit));
1341         if (status != 0) {
1342                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1343                         "error init'ing transmit power\n");
1344                 return -EIO;
1345         }
1346
1347         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1348                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1349                         "ar5416SetRfRegs failed\n");
1350                 return -EIO;
1351         }
1352
1353         return 0;
1354 }
1355
1356 /****************************************/
1357 /* Reset and Channel Switching Routines */
1358 /****************************************/
1359
1360 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1361 {
1362         u32 rfMode = 0;
1363
1364         if (chan == NULL)
1365                 return;
1366
1367         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1368                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1369
1370         if (!AR_SREV_9280_10_OR_LATER(ah))
1371                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1372                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1373
1374         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1375                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1376
1377         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1378 }
1379
1380 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1381 {
1382         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1383 }
1384
1385 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1386 {
1387         u32 regval;
1388
1389         regval = REG_READ(ah, AR_AHB_MODE);
1390         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1391
1392         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1393         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1394
1395         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1396
1397         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1398         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1399
1400         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1401
1402         if (AR_SREV_9285(ah)) {
1403                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1404                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1405         } else {
1406                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1407                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1408         }
1409 }
1410
1411 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1412 {
1413         u32 val;
1414
1415         val = REG_READ(ah, AR_STA_ID1);
1416         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1417         switch (opmode) {
1418         case NL80211_IFTYPE_AP:
1419                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1420                           | AR_STA_ID1_KSRCH_MODE);
1421                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1422                 break;
1423         case NL80211_IFTYPE_ADHOC:
1424                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1425                           | AR_STA_ID1_KSRCH_MODE);
1426                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1427                 break;
1428         case NL80211_IFTYPE_STATION:
1429         case NL80211_IFTYPE_MONITOR:
1430                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1431                 break;
1432         }
1433 }
1434
1435 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1436                                                  u32 coef_scaled,
1437                                                  u32 *coef_mantissa,
1438                                                  u32 *coef_exponent)
1439 {
1440         u32 coef_exp, coef_man;
1441
1442         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1443                 if ((coef_scaled >> coef_exp) & 0x1)
1444                         break;
1445
1446         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1447
1448         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1449
1450         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1451         *coef_exponent = coef_exp - 16;
1452 }
1453
1454 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1455                                      struct ath9k_channel *chan)
1456 {
1457         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1458         u32 clockMhzScaled = 0x64000000;
1459         struct chan_centers centers;
1460
1461         if (IS_CHAN_HALF_RATE(chan))
1462                 clockMhzScaled = clockMhzScaled >> 1;
1463         else if (IS_CHAN_QUARTER_RATE(chan))
1464                 clockMhzScaled = clockMhzScaled >> 2;
1465
1466         ath9k_hw_get_channel_centers(ah, chan, &centers);
1467         coef_scaled = clockMhzScaled / centers.synth_center;
1468
1469         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1470                                       &ds_coef_exp);
1471
1472         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1473                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1474         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1475                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1476
1477         coef_scaled = (9 * coef_scaled) / 10;
1478
1479         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1480                                       &ds_coef_exp);
1481
1482         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1483                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1484         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1485                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1486 }
1487
1488 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1489 {
1490         u32 rst_flags;
1491         u32 tmpReg;
1492
1493         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1494                   AR_RTC_FORCE_WAKE_ON_INT);
1495
1496         if (AR_SREV_9100(ah)) {
1497                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1498                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1499         } else {
1500                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1501                 if (tmpReg &
1502                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1503                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1504                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1505                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1506                 } else {
1507                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1508                 }
1509
1510                 rst_flags = AR_RTC_RC_MAC_WARM;
1511                 if (type == ATH9K_RESET_COLD)
1512                         rst_flags |= AR_RTC_RC_MAC_COLD;
1513         }
1514
1515         REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1516         udelay(50);
1517
1518         REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1519         if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1520                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1521                         "RTC stuck in MAC reset\n");
1522                 return false;
1523         }
1524
1525         if (!AR_SREV_9100(ah))
1526                 REG_WRITE(ah, AR_RC, 0);
1527
1528         ath9k_hw_init_pll(ah, NULL);
1529
1530         if (AR_SREV_9100(ah))
1531                 udelay(50);
1532
1533         return true;
1534 }
1535
1536 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1537 {
1538         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1539                   AR_RTC_FORCE_WAKE_ON_INT);
1540
1541         REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1542         REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1543
1544         if (!ath9k_hw_wait(ah,
1545                            AR_RTC_STATUS,
1546                            AR_RTC_STATUS_M,
1547                            AR_RTC_STATUS_ON)) {
1548                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1549                 return false;
1550         }
1551
1552         ath9k_hw_read_revisions(ah);
1553
1554         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1555 }
1556
1557 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1558 {
1559         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1560                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1561
1562         switch (type) {
1563         case ATH9K_RESET_POWER_ON:
1564                 return ath9k_hw_set_reset_power_on(ah);
1565                 break;
1566         case ATH9K_RESET_WARM:
1567         case ATH9K_RESET_COLD:
1568                 return ath9k_hw_set_reset(ah, type);
1569                 break;
1570         default:
1571                 return false;
1572         }
1573 }
1574
1575 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1576                               enum ath9k_ht_macmode macmode)
1577 {
1578         u32 phymode;
1579         struct ath_hal_5416 *ahp = AH5416(ah);
1580
1581         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1582                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1583
1584         if (IS_CHAN_HT40(chan)) {
1585                 phymode |= AR_PHY_FC_DYN2040_EN;
1586
1587                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1588                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1589                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1590
1591                 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1592                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1593         }
1594         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1595
1596         ath9k_hw_set11nmac2040(ah, macmode);
1597
1598         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1599         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1600 }
1601
1602 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1603                                 struct ath9k_channel *chan)
1604 {
1605         struct ath_hal_5416 *ahp = AH5416(ah);
1606
1607         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1608                 return false;
1609
1610         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1611                 return false;
1612
1613         ahp->ah_chipFullSleep = false;
1614
1615         ath9k_hw_init_pll(ah, chan);
1616
1617         ath9k_hw_set_rfmode(ah, chan);
1618
1619         return true;
1620 }
1621
1622 static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1623                                                  struct ath9k_channel *chan)
1624 {
1625         if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1626                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1627                         "invalid channel %u/0x%x; not marked as "
1628                         "2GHz or 5GHz\n", chan->channel, chan->channelFlags);
1629                 return NULL;
1630         }
1631
1632         if (!IS_CHAN_OFDM(chan) &&
1633             !IS_CHAN_B(chan) &&
1634             !IS_CHAN_HT20(chan) &&
1635             !IS_CHAN_HT40(chan)) {
1636                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1637                         "invalid channel %u/0x%x; not marked as "
1638                         "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1639                         chan->channel, chan->channelFlags);
1640                 return NULL;
1641         }
1642
1643         return ath9k_regd_check_channel(ah, chan);
1644 }
1645
1646 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1647                                     struct ath9k_channel *chan,
1648                                     enum ath9k_ht_macmode macmode)
1649 {
1650         u32 synthDelay, qnum;
1651
1652         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1653                 if (ath9k_hw_numtxpending(ah, qnum)) {
1654                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1655                                 "Transmit frames pending on queue %d\n", qnum);
1656                         return false;
1657                 }
1658         }
1659
1660         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1661         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1662                            AR_PHY_RFBUS_GRANT_EN)) {
1663                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1664                         "Could not kill baseband RX\n");
1665                 return false;
1666         }
1667
1668         ath9k_hw_set_regs(ah, chan, macmode);
1669
1670         if (AR_SREV_9280_10_OR_LATER(ah)) {
1671                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1672                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1673                                 "failed to set channel\n");
1674                         return false;
1675                 }
1676         } else {
1677                 if (!(ath9k_hw_set_channel(ah, chan))) {
1678                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1679                                 "failed to set channel\n");
1680                         return false;
1681                 }
1682         }
1683
1684         if (ath9k_hw_set_txpower(ah, chan,
1685                                  ath9k_regd_get_ctl(ah, chan),
1686                                  ath9k_regd_get_antenna_allowed(ah, chan),
1687                                  chan->maxRegTxPower * 2,
1688                                  min((u32) MAX_RATE_POWER,
1689                                      (u32) ah->ah_powerLimit)) != 0) {
1690                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1691                         "error init'ing transmit power\n");
1692                 return false;
1693         }
1694
1695         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1696         if (IS_CHAN_B(chan))
1697                 synthDelay = (4 * synthDelay) / 22;
1698         else
1699                 synthDelay /= 10;
1700
1701         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1702
1703         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1704
1705         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1706                 ath9k_hw_set_delta_slope(ah, chan);
1707
1708         if (AR_SREV_9280_10_OR_LATER(ah))
1709                 ath9k_hw_9280_spur_mitigate(ah, chan);
1710         else
1711                 ath9k_hw_spur_mitigate(ah, chan);
1712
1713         if (!chan->oneTimeCalsDone)
1714                 chan->oneTimeCalsDone = true;
1715
1716         return true;
1717 }
1718
1719 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1720 {
1721         int bb_spur = AR_NO_SPUR;
1722         int freq;
1723         int bin, cur_bin;
1724         int bb_spur_off, spur_subchannel_sd;
1725         int spur_freq_sd;
1726         int spur_delta_phase;
1727         int denominator;
1728         int upper, lower, cur_vit_mask;
1729         int tmp, newVal;
1730         int i;
1731         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1732                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1733         };
1734         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1735                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1736         };
1737         int inc[4] = { 0, 100, 0, 0 };
1738         struct chan_centers centers;
1739
1740         int8_t mask_m[123];
1741         int8_t mask_p[123];
1742         int8_t mask_amt;
1743         int tmp_mask;
1744         int cur_bb_spur;
1745         bool is2GHz = IS_CHAN_2GHZ(chan);
1746
1747         memset(&mask_m, 0, sizeof(int8_t) * 123);
1748         memset(&mask_p, 0, sizeof(int8_t) * 123);
1749
1750         ath9k_hw_get_channel_centers(ah, chan, &centers);
1751         freq = centers.synth_center;
1752
1753         ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1754         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1755                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1756
1757                 if (is2GHz)
1758                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1759                 else
1760                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1761
1762                 if (AR_NO_SPUR == cur_bb_spur)
1763                         break;
1764                 cur_bb_spur = cur_bb_spur - freq;
1765
1766                 if (IS_CHAN_HT40(chan)) {
1767                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1768                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1769                                 bb_spur = cur_bb_spur;
1770                                 break;
1771                         }
1772                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1773                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1774                         bb_spur = cur_bb_spur;
1775                         break;
1776                 }
1777         }
1778
1779         if (AR_NO_SPUR == bb_spur) {
1780                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1781                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1782                 return;
1783         } else {
1784                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1785                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1786         }
1787
1788         bin = bb_spur * 320;
1789
1790         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1791
1792         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1793                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1794                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1795                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1796         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1797
1798         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1799                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1800                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1801                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1802                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1803         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1804
1805         if (IS_CHAN_HT40(chan)) {
1806                 if (bb_spur < 0) {
1807                         spur_subchannel_sd = 1;
1808                         bb_spur_off = bb_spur + 10;
1809                 } else {
1810                         spur_subchannel_sd = 0;
1811                         bb_spur_off = bb_spur - 10;
1812                 }
1813         } else {
1814                 spur_subchannel_sd = 0;
1815                 bb_spur_off = bb_spur;
1816         }
1817
1818         if (IS_CHAN_HT40(chan))
1819                 spur_delta_phase =
1820                         ((bb_spur * 262144) /
1821                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1822         else
1823                 spur_delta_phase =
1824                         ((bb_spur * 524288) /
1825                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1826
1827         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1828         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1829
1830         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1831                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1832                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1833         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1834
1835         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1836         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1837
1838         cur_bin = -6000;
1839         upper = bin + 100;
1840         lower = bin - 100;
1841
1842         for (i = 0; i < 4; i++) {
1843                 int pilot_mask = 0;
1844                 int chan_mask = 0;
1845                 int bp = 0;
1846                 for (bp = 0; bp < 30; bp++) {
1847                         if ((cur_bin > lower) && (cur_bin < upper)) {
1848                                 pilot_mask = pilot_mask | 0x1 << bp;
1849                                 chan_mask = chan_mask | 0x1 << bp;
1850                         }
1851                         cur_bin += 100;
1852                 }
1853                 cur_bin += inc[i];
1854                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1855                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1856         }
1857
1858         cur_vit_mask = 6100;
1859         upper = bin + 120;
1860         lower = bin - 120;
1861
1862         for (i = 0; i < 123; i++) {
1863                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1864
1865                         /* workaround for gcc bug #37014 */
1866                         volatile int tmp = abs(cur_vit_mask - bin);
1867
1868                         if (tmp < 75)
1869                                 mask_amt = 1;
1870                         else
1871                                 mask_amt = 0;
1872                         if (cur_vit_mask < 0)
1873                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1874                         else
1875                                 mask_p[cur_vit_mask / 100] = mask_amt;
1876                 }
1877                 cur_vit_mask -= 100;
1878         }
1879
1880         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1881                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1882                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1883                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1884                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1885                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1886                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1887                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1888         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1889         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1890
1891         tmp_mask = (mask_m[31] << 28)
1892                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1893                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1894                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1895                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1896                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1897                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1898                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1899         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1900         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1901
1902         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1903                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1904                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1905                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1906                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1907                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1908                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1909                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1910         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1911         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1912
1913         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1914                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1915                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1916                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1917                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1918                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1919                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1920                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1921         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1922         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1923
1924         tmp_mask = (mask_p[15] << 28)
1925                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1926                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1927                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1928                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1929                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1930                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1931                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1932         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1933         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1934
1935         tmp_mask = (mask_p[30] << 28)
1936                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1937                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1938                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1939                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1940                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1941                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1942                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1943         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1944         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1945
1946         tmp_mask = (mask_p[45] << 28)
1947                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1948                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1949                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1950                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1951                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1952                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1953                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1954         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1955         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1956
1957         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1958                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1959                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1960                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1961                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1962                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1963                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1964                 | (mask_p[47] << 2) | (mask_p[46] << 0);
1965         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1966         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1967 }
1968
1969 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1970 {
1971         int bb_spur = AR_NO_SPUR;
1972         int bin, cur_bin;
1973         int spur_freq_sd;
1974         int spur_delta_phase;
1975         int denominator;
1976         int upper, lower, cur_vit_mask;
1977         int tmp, new;
1978         int i;
1979         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1980                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1981         };
1982         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1983                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1984         };
1985         int inc[4] = { 0, 100, 0, 0 };
1986
1987         int8_t mask_m[123];
1988         int8_t mask_p[123];
1989         int8_t mask_amt;
1990         int tmp_mask;
1991         int cur_bb_spur;
1992         bool is2GHz = IS_CHAN_2GHZ(chan);
1993
1994         memset(&mask_m, 0, sizeof(int8_t) * 123);
1995         memset(&mask_p, 0, sizeof(int8_t) * 123);
1996
1997         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1998                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1999                 if (AR_NO_SPUR == cur_bb_spur)
2000                         break;
2001                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2002                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2003                         bb_spur = cur_bb_spur;
2004                         break;
2005                 }
2006         }
2007
2008         if (AR_NO_SPUR == bb_spur)
2009                 return;
2010
2011         bin = bb_spur * 32;
2012
2013         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2014         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2015                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2016                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2017                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2018
2019         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2020
2021         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2022                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2023                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2024                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2025                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2026         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2027
2028         spur_delta_phase = ((bb_spur * 524288) / 100) &
2029                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2030
2031         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2032         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2033
2034         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2035                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2036                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2037         REG_WRITE(ah, AR_PHY_TIMING11, new);
2038
2039         cur_bin = -6000;
2040         upper = bin + 100;
2041         lower = bin - 100;
2042
2043         for (i = 0; i < 4; i++) {
2044                 int pilot_mask = 0;
2045                 int chan_mask = 0;
2046                 int bp = 0;
2047                 for (bp = 0; bp < 30; bp++) {
2048                         if ((cur_bin > lower) && (cur_bin < upper)) {
2049                                 pilot_mask = pilot_mask | 0x1 << bp;
2050                                 chan_mask = chan_mask | 0x1 << bp;
2051                         }
2052                         cur_bin += 100;
2053                 }
2054                 cur_bin += inc[i];
2055                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2056                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2057         }
2058
2059         cur_vit_mask = 6100;
2060         upper = bin + 120;
2061         lower = bin - 120;
2062
2063         for (i = 0; i < 123; i++) {
2064                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2065
2066                         /* workaround for gcc bug #37014 */
2067                         volatile int tmp = abs(cur_vit_mask - bin);
2068
2069                         if (tmp < 75)
2070                                 mask_amt = 1;
2071                         else
2072                                 mask_amt = 0;
2073                         if (cur_vit_mask < 0)
2074                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2075                         else
2076                                 mask_p[cur_vit_mask / 100] = mask_amt;
2077                 }
2078                 cur_vit_mask -= 100;
2079         }
2080
2081         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2082                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2083                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2084                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2085                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2086                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2087                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2088                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2089         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2090         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2091
2092         tmp_mask = (mask_m[31] << 28)
2093                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2094                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2095                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2096                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2097                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2098                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2099                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2100         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2101         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2102
2103         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2104                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2105                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2106                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2107                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2108                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2109                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2110                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2111         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2112         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2113
2114         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2115                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2116                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2117                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2118                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2119                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2120                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2121                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2122         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2123         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2124
2125         tmp_mask = (mask_p[15] << 28)
2126                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2127                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2128                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2129                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2130                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2131                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2132                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2133         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2134         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2135
2136         tmp_mask = (mask_p[30] << 28)
2137                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2138                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2139                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2140                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2141                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2142                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2143                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2144         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2145         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2146
2147         tmp_mask = (mask_p[45] << 28)
2148                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2149                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2150                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2151                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2152                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2153                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2154                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2155         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2156         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2157
2158         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2159                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2160                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2161                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2162                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2163                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2164                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2165                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2166         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2167         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2168 }
2169
2170 bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2171                     enum ath9k_ht_macmode macmode,
2172                     u8 txchainmask, u8 rxchainmask,
2173                     enum ath9k_ht_extprotspacing extprotspacing,
2174                     bool bChannelChange, int *status)
2175 {
2176         u32 saveLedState;
2177         struct ath_hal_5416 *ahp = AH5416(ah);
2178         struct ath9k_channel *curchan = ah->ah_curchan;
2179         u32 saveDefAntenna;
2180         u32 macStaId1;
2181         int ecode;
2182         int i, rx_chainmask;
2183
2184         ahp->ah_extprotspacing = extprotspacing;
2185         ahp->ah_txchainmask = txchainmask;
2186         ahp->ah_rxchainmask = rxchainmask;
2187
2188         if (AR_SREV_9280(ah)) {
2189                 ahp->ah_txchainmask &= 0x3;
2190                 ahp->ah_rxchainmask &= 0x3;
2191         }
2192
2193         if (ath9k_hw_check_chan(ah, chan) == NULL) {
2194                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2195                         "invalid channel %u/0x%x; no mapping\n",
2196                         chan->channel, chan->channelFlags);
2197                 ecode = -EINVAL;
2198                 goto bad;
2199         }
2200
2201         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
2202                 ecode = -EIO;
2203                 goto bad;
2204         }
2205
2206         if (curchan)
2207                 ath9k_hw_getnf(ah, curchan);
2208
2209         if (bChannelChange &&
2210             (ahp->ah_chipFullSleep != true) &&
2211             (ah->ah_curchan != NULL) &&
2212             (chan->channel != ah->ah_curchan->channel) &&
2213             ((chan->channelFlags & CHANNEL_ALL) ==
2214              (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2215             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2216                                    !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2217
2218                 if (ath9k_hw_channel_change(ah, chan, macmode)) {
2219                         ath9k_hw_loadnf(ah, ah->ah_curchan);
2220                         ath9k_hw_start_nfcal(ah);
2221                         return true;
2222                 }
2223         }
2224
2225         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2226         if (saveDefAntenna == 0)
2227                 saveDefAntenna = 1;
2228
2229         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2230
2231         saveLedState = REG_READ(ah, AR_CFG_LED) &
2232                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2233                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2234
2235         ath9k_hw_mark_phy_inactive(ah);
2236
2237         if (!ath9k_hw_chip_reset(ah, chan)) {
2238                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2239                 ecode = -EINVAL;
2240                 goto bad;
2241         }
2242
2243         if (AR_SREV_9280(ah)) {
2244                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2245                             AR_GPIO_JTAG_DISABLE);
2246
2247                 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2248                         if (IS_CHAN_5GHZ(chan))
2249                                 ath9k_hw_set_gpio(ah, 9, 0);
2250                         else
2251                                 ath9k_hw_set_gpio(ah, 9, 1);
2252                 }
2253                 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2254         }
2255
2256         ecode = ath9k_hw_process_ini(ah, chan, macmode);
2257         if (ecode != 0) {
2258                 ecode = -EINVAL;
2259                 goto bad;
2260         }
2261
2262         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2263                 ath9k_hw_set_delta_slope(ah, chan);
2264
2265         if (AR_SREV_9280_10_OR_LATER(ah))
2266                 ath9k_hw_9280_spur_mitigate(ah, chan);
2267         else
2268                 ath9k_hw_spur_mitigate(ah, chan);
2269
2270         if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2271                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2272                         "error setting board options\n");
2273                 ecode = -EIO;
2274                 goto bad;
2275         }
2276
2277         ath9k_hw_decrease_chain_power(ah, chan);
2278
2279         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2280         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2281                   | macStaId1
2282                   | AR_STA_ID1_RTS_USE_DEF
2283                   | (ah->ah_config.
2284                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2285                   | ahp->ah_staId1Defaults);
2286         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2287
2288         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2289         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2290
2291         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2292
2293         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2294         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2295                   ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2296
2297         REG_WRITE(ah, AR_ISR, ~0);
2298
2299         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2300
2301         if (AR_SREV_9280_10_OR_LATER(ah)) {
2302                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
2303                         ecode = -EIO;
2304                         goto bad;
2305                 }
2306         } else {
2307                 if (!(ath9k_hw_set_channel(ah, chan))) {
2308                         ecode = -EIO;
2309                         goto bad;
2310                 }
2311         }
2312
2313         for (i = 0; i < AR_NUM_DCU; i++)
2314                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2315
2316         ahp->ah_intrTxqs = 0;
2317         for (i = 0; i < ah->ah_caps.total_queues; i++)
2318                 ath9k_hw_resettxqueue(ah, i);
2319
2320         ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2321         ath9k_hw_init_qos(ah);
2322
2323 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2324         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2325                 ath9k_enable_rfkill(ah);
2326 #endif
2327         ath9k_hw_init_user_settings(ah);
2328
2329         REG_WRITE(ah, AR_STA_ID1,
2330                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2331
2332         ath9k_hw_set_dma(ah);
2333
2334         REG_WRITE(ah, AR_OBS, 8);
2335
2336         if (ahp->ah_intrMitigation) {
2337
2338                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2339                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2340         }
2341
2342         ath9k_hw_init_bb(ah, chan);
2343
2344         if (!ath9k_hw_init_cal(ah, chan)){
2345                 ecode = -EIO;;
2346                 goto bad;
2347         }
2348
2349         rx_chainmask = ahp->ah_rxchainmask;
2350         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2351                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2352                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2353         }
2354
2355         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2356
2357         if (AR_SREV_9100(ah)) {
2358                 u32 mask;
2359                 mask = REG_READ(ah, AR_CFG);
2360                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2361                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2362                                 "CFG Byte Swap Set 0x%x\n", mask);
2363                 } else {
2364                         mask =
2365                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2366                         REG_WRITE(ah, AR_CFG, mask);
2367                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2368                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2369                 }
2370         } else {
2371 #ifdef __BIG_ENDIAN
2372                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2373 #endif
2374         }
2375
2376         return true;
2377 bad:
2378         if (status)
2379                 *status = ecode;
2380         return false;
2381 }
2382
2383 /************************/
2384 /* Key Cache Management */
2385 /************************/
2386
2387 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2388 {
2389         u32 keyType;
2390
2391         if (entry >= ah->ah_caps.keycache_size) {
2392                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2393                         "entry %u out of range\n", entry);
2394                 return false;
2395         }
2396
2397         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2398
2399         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2400         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2401         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2402         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2403         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2404         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2405         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2406         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2407
2408         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2409                 u16 micentry = entry + 64;
2410
2411                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2412                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2413                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2414                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2415
2416         }
2417
2418         if (ah->ah_curchan == NULL)
2419                 return true;
2420
2421         return true;
2422 }
2423
2424 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2425 {
2426         u32 macHi, macLo;
2427
2428         if (entry >= ah->ah_caps.keycache_size) {
2429                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2430                         "entry %u out of range\n", entry);
2431                 return false;
2432         }
2433
2434         if (mac != NULL) {
2435                 macHi = (mac[5] << 8) | mac[4];
2436                 macLo = (mac[3] << 24) |
2437                         (mac[2] << 16) |
2438                         (mac[1] << 8) |
2439                         mac[0];
2440                 macLo >>= 1;
2441                 macLo |= (macHi & 1) << 31;
2442                 macHi >>= 1;
2443         } else {
2444                 macLo = macHi = 0;
2445         }
2446         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2447         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2448
2449         return true;
2450 }
2451
2452 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2453                                  const struct ath9k_keyval *k,
2454                                  const u8 *mac, int xorKey)
2455 {
2456         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2457         u32 key0, key1, key2, key3, key4;
2458         u32 keyType;
2459         u32 xorMask = xorKey ?
2460                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2461                  | ATH9K_KEY_XOR) : 0;
2462         struct ath_hal_5416 *ahp = AH5416(ah);
2463
2464         if (entry >= pCap->keycache_size) {
2465                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2466                         "entry %u out of range\n", entry);
2467                 return false;
2468         }
2469
2470         switch (k->kv_type) {
2471         case ATH9K_CIPHER_AES_OCB:
2472                 keyType = AR_KEYTABLE_TYPE_AES;
2473                 break;
2474         case ATH9K_CIPHER_AES_CCM:
2475                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2476                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2477                                 "AES-CCM not supported by mac rev 0x%x\n",
2478                                 ah->ah_macRev);
2479                         return false;
2480                 }
2481                 keyType = AR_KEYTABLE_TYPE_CCM;
2482                 break;
2483         case ATH9K_CIPHER_TKIP:
2484                 keyType = AR_KEYTABLE_TYPE_TKIP;
2485                 if (ATH9K_IS_MIC_ENABLED(ah)
2486                     && entry + 64 >= pCap->keycache_size) {
2487                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2488                                 "entry %u inappropriate for TKIP\n", entry);
2489                         return false;
2490                 }
2491                 break;
2492         case ATH9K_CIPHER_WEP:
2493                 if (k->kv_len < LEN_WEP40) {
2494                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2495                                 "WEP key length %u too small\n", k->kv_len);
2496                         return false;
2497                 }
2498                 if (k->kv_len <= LEN_WEP40)
2499                         keyType = AR_KEYTABLE_TYPE_40;
2500                 else if (k->kv_len <= LEN_WEP104)
2501                         keyType = AR_KEYTABLE_TYPE_104;
2502                 else
2503                         keyType = AR_KEYTABLE_TYPE_128;
2504                 break;
2505         case ATH9K_CIPHER_CLR:
2506                 keyType = AR_KEYTABLE_TYPE_CLR;
2507                 break;
2508         default:
2509                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2510                         "cipher %u not supported\n", k->kv_type);
2511                 return false;
2512         }
2513
2514         key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2515         key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2516         key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2517         key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2518         key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2519         if (k->kv_len <= LEN_WEP104)
2520                 key4 &= 0xff;
2521
2522         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2523                 u16 micentry = entry + 64;
2524
2525                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2526                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2527                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2528                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2529                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2530                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2531                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2532
2533                 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2534                         u32 mic0, mic1, mic2, mic3, mic4;
2535
2536                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2537                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2538                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2539                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2540                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2541                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2542                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2543                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2544                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2545                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2546                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2547                                   AR_KEYTABLE_TYPE_CLR);
2548
2549                 } else {
2550                         u32 mic0, mic2;
2551
2552                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2553                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2554                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2555                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2556                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2557                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2558                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2559                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2560                                   AR_KEYTABLE_TYPE_CLR);
2561                 }
2562                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2563                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2564                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2565                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2566         } else {
2567                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2568                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2569                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2570                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2571                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2572                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2573
2574                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2575         }
2576
2577         if (ah->ah_curchan == NULL)
2578                 return true;
2579
2580         return true;
2581 }
2582
2583 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2584 {
2585         if (entry < ah->ah_caps.keycache_size) {
2586                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2587                 if (val & AR_KEYTABLE_VALID)
2588                         return true;
2589         }
2590         return false;
2591 }
2592
2593 /******************************/
2594 /* Power Management (Chipset) */
2595 /******************************/
2596
2597 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2598 {
2599         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2600         if (setChip) {
2601                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2602                             AR_RTC_FORCE_WAKE_EN);
2603                 if (!AR_SREV_9100(ah))
2604                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2605
2606                 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2607                             AR_RTC_RESET_EN);
2608         }
2609 }
2610
2611 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2612 {
2613         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2614         if (setChip) {
2615                 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2616
2617                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2618                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2619                                   AR_RTC_FORCE_WAKE_ON_INT);
2620                 } else {
2621                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2622                                     AR_RTC_FORCE_WAKE_EN);
2623                 }
2624         }
2625 }
2626
2627 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2628                                      int setChip)
2629 {
2630         u32 val;
2631         int i;
2632
2633         if (setChip) {
2634                 if ((REG_READ(ah, AR_RTC_STATUS) &
2635                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2636                         if (ath9k_hw_set_reset_reg(ah,
2637                                            ATH9K_RESET_POWER_ON) != true) {
2638                                 return false;
2639                         }
2640                 }
2641                 if (AR_SREV_9100(ah))
2642                         REG_SET_BIT(ah, AR_RTC_RESET,
2643                                     AR_RTC_RESET_EN);
2644
2645                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2646                             AR_RTC_FORCE_WAKE_EN);
2647                 udelay(50);
2648
2649                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2650                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2651                         if (val == AR_RTC_STATUS_ON)
2652                                 break;
2653                         udelay(50);
2654                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2655                                     AR_RTC_FORCE_WAKE_EN);
2656                 }
2657                 if (i == 0) {
2658                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2659                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2660                         return false;
2661                 }
2662         }
2663
2664         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2665
2666         return true;
2667 }
2668
2669 bool ath9k_hw_setpower(struct ath_hal *ah,
2670                        enum ath9k_power_mode mode)
2671 {
2672         struct ath_hal_5416 *ahp = AH5416(ah);
2673         static const char *modes[] = {
2674                 "AWAKE",
2675                 "FULL-SLEEP",
2676                 "NETWORK SLEEP",
2677                 "UNDEFINED"
2678         };
2679         int status = true, setChip = true;
2680
2681         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2682                 modes[ahp->ah_powerMode], modes[mode],
2683                 setChip ? "set chip " : "");
2684
2685         switch (mode) {
2686         case ATH9K_PM_AWAKE:
2687                 status = ath9k_hw_set_power_awake(ah, setChip);
2688                 break;
2689         case ATH9K_PM_FULL_SLEEP:
2690                 ath9k_set_power_sleep(ah, setChip);
2691                 ahp->ah_chipFullSleep = true;
2692                 break;
2693         case ATH9K_PM_NETWORK_SLEEP:
2694                 ath9k_set_power_network_sleep(ah, setChip);
2695                 break;
2696         default:
2697                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2698                         "Unknown power mode %u\n", mode);
2699                 return false;
2700         }
2701         ahp->ah_powerMode = mode;
2702
2703         return status;
2704 }
2705
2706 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2707 {
2708         struct ath_hal_5416 *ahp = AH5416(ah);
2709         u8 i;
2710
2711         if (ah->ah_isPciExpress != true)
2712                 return;
2713
2714         if (ah->ah_config.pcie_powersave_enable == 2)
2715                 return;
2716
2717         if (restore)
2718                 return;
2719
2720         if (AR_SREV_9280_20_OR_LATER(ah)) {
2721                 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2722                         REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2723                                   INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2724                 }
2725                 udelay(1000);
2726         } else if (AR_SREV_9280(ah) &&
2727                    (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2728                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2729                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2730
2731                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2732                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2733                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2734
2735                 if (ah->ah_config.pcie_clock_req)
2736                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2737                 else
2738                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2739
2740                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2741                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2742                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2743
2744                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2745
2746                 udelay(1000);
2747         } else {
2748                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2749                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2750                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2751                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2752                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2753                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2754                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2755                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2756                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2757                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2758         }
2759
2760         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2761
2762         if (ah->ah_config.pcie_waen) {
2763                 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2764         } else {
2765                 if (AR_SREV_9280(ah))
2766                         REG_WRITE(ah, AR_WA, 0x0040073f);
2767                 else
2768                         REG_WRITE(ah, AR_WA, 0x0000073f);
2769         }
2770 }
2771
2772 /**********************/
2773 /* Interrupt Handling */
2774 /**********************/
2775
2776 bool ath9k_hw_intrpend(struct ath_hal *ah)
2777 {
2778         u32 host_isr;
2779
2780         if (AR_SREV_9100(ah))
2781                 return true;
2782
2783         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2784         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2785                 return true;
2786
2787         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2788         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2789             && (host_isr != AR_INTR_SPURIOUS))
2790                 return true;
2791
2792         return false;
2793 }
2794
2795 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2796 {
2797         u32 isr = 0;
2798         u32 mask2 = 0;
2799         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2800         u32 sync_cause = 0;
2801         bool fatal_int = false;
2802         struct ath_hal_5416 *ahp = AH5416(ah);
2803
2804         if (!AR_SREV_9100(ah)) {
2805                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2806                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2807                             == AR_RTC_STATUS_ON) {
2808                                 isr = REG_READ(ah, AR_ISR);
2809                         }
2810                 }
2811
2812                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2813                         AR_INTR_SYNC_DEFAULT;
2814
2815                 *masked = 0;
2816
2817                 if (!isr && !sync_cause)
2818                         return false;
2819         } else {
2820                 *masked = 0;
2821                 isr = REG_READ(ah, AR_ISR);
2822         }
2823
2824         if (isr) {
2825                 if (isr & AR_ISR_BCNMISC) {
2826                         u32 isr2;
2827                         isr2 = REG_READ(ah, AR_ISR_S2);
2828                         if (isr2 & AR_ISR_S2_TIM)
2829                                 mask2 |= ATH9K_INT_TIM;
2830                         if (isr2 & AR_ISR_S2_DTIM)
2831                                 mask2 |= ATH9K_INT_DTIM;
2832                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2833                                 mask2 |= ATH9K_INT_DTIMSYNC;
2834                         if (isr2 & (AR_ISR_S2_CABEND))
2835                                 mask2 |= ATH9K_INT_CABEND;
2836                         if (isr2 & AR_ISR_S2_GTT)
2837                                 mask2 |= ATH9K_INT_GTT;
2838                         if (isr2 & AR_ISR_S2_CST)
2839                                 mask2 |= ATH9K_INT_CST;
2840                 }
2841
2842                 isr = REG_READ(ah, AR_ISR_RAC);
2843                 if (isr == 0xffffffff) {
2844                         *masked = 0;
2845                         return false;
2846                 }
2847
2848                 *masked = isr & ATH9K_INT_COMMON;
2849
2850                 if (ahp->ah_intrMitigation) {
2851                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2852                                 *masked |= ATH9K_INT_RX;
2853                 }
2854
2855                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2856                         *masked |= ATH9K_INT_RX;
2857                 if (isr &
2858                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2859                      AR_ISR_TXEOL)) {
2860                         u32 s0_s, s1_s;
2861
2862                         *masked |= ATH9K_INT_TX;
2863
2864                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2865                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2866                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2867
2868                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2869                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2870                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2871                 }
2872
2873                 if (isr & AR_ISR_RXORN) {
2874                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2875                                 "receive FIFO overrun interrupt\n");
2876                 }
2877
2878                 if (!AR_SREV_9100(ah)) {
2879                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2880                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2881                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2882                                         *masked |= ATH9K_INT_TIM_TIMER;
2883                         }
2884                 }
2885
2886                 *masked |= mask2;
2887         }
2888
2889         if (AR_SREV_9100(ah))
2890                 return true;
2891
2892         if (sync_cause) {
2893                 fatal_int =
2894                         (sync_cause &
2895                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2896                         ? true : false;
2897
2898                 if (fatal_int) {
2899                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2900                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2901                                         "received PCI FATAL interrupt\n");
2902                         }
2903                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2904                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2905                                         "received PCI PERR interrupt\n");
2906                         }
2907                 }
2908                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2909                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2910                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2911                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2912                         REG_WRITE(ah, AR_RC, 0);
2913                         *masked |= ATH9K_INT_FATAL;
2914                 }
2915                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2916                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2917                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2918                 }
2919
2920                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2921                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2922         }
2923
2924         return true;
2925 }
2926
2927 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2928 {
2929         return AH5416(ah)->ah_maskReg;
2930 }
2931
2932 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2933 {
2934         struct ath_hal_5416 *ahp = AH5416(ah);
2935         u32 omask = ahp->ah_maskReg;
2936         u32 mask, mask2;
2937         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2938
2939         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2940
2941         if (omask & ATH9K_INT_GLOBAL) {
2942                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2943                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2944                 (void) REG_READ(ah, AR_IER);
2945                 if (!AR_SREV_9100(ah)) {
2946                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2947                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2948
2949                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2950                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2951                 }
2952         }
2953
2954         mask = ints & ATH9K_INT_COMMON;
2955         mask2 = 0;
2956
2957         if (ints & ATH9K_INT_TX) {
2958                 if (ahp->ah_txOkInterruptMask)
2959                         mask |= AR_IMR_TXOK;
2960                 if (ahp->ah_txDescInterruptMask)
2961                         mask |= AR_IMR_TXDESC;
2962                 if (ahp->ah_txErrInterruptMask)
2963                         mask |= AR_IMR_TXERR;
2964                 if (ahp->ah_txEolInterruptMask)
2965                         mask |= AR_IMR_TXEOL;
2966         }
2967         if (ints & ATH9K_INT_RX) {
2968                 mask |= AR_IMR_RXERR;
2969                 if (ahp->ah_intrMitigation)
2970                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2971                 else
2972                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2973                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2974                         mask |= AR_IMR_GENTMR;
2975         }
2976
2977         if (ints & (ATH9K_INT_BMISC)) {
2978                 mask |= AR_IMR_BCNMISC;
2979                 if (ints & ATH9K_INT_TIM)
2980                         mask2 |= AR_IMR_S2_TIM;
2981                 if (ints & ATH9K_INT_DTIM)
2982                         mask2 |= AR_IMR_S2_DTIM;
2983                 if (ints & ATH9K_INT_DTIMSYNC)
2984                         mask2 |= AR_IMR_S2_DTIMSYNC;
2985                 if (ints & ATH9K_INT_CABEND)
2986                         mask2 |= (AR_IMR_S2_CABEND);
2987         }
2988
2989         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2990                 mask |= AR_IMR_BCNMISC;
2991                 if (ints & ATH9K_INT_GTT)
2992                         mask2 |= AR_IMR_S2_GTT;
2993                 if (ints & ATH9K_INT_CST)
2994                         mask2 |= AR_IMR_S2_CST;
2995         }
2996
2997         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2998         REG_WRITE(ah, AR_IMR, mask);
2999         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3000                                            AR_IMR_S2_DTIM |
3001                                            AR_IMR_S2_DTIMSYNC |
3002                                            AR_IMR_S2_CABEND |
3003                                            AR_IMR_S2_CABTO |
3004                                            AR_IMR_S2_TSFOOR |
3005                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3006         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3007         ahp->ah_maskReg = ints;
3008
3009         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3010                 if (ints & ATH9K_INT_TIM_TIMER)
3011                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3012                 else
3013                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3014         }
3015
3016         if (ints & ATH9K_INT_GLOBAL) {
3017                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3018                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3019                 if (!AR_SREV_9100(ah)) {
3020                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3021                                   AR_INTR_MAC_IRQ);
3022                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3023
3024
3025                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3026                                   AR_INTR_SYNC_DEFAULT);
3027                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3028                                   AR_INTR_SYNC_DEFAULT);
3029                 }
3030                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3031                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3032         }
3033
3034         return omask;
3035 }
3036
3037 /*******************/
3038 /* Beacon Handling */
3039 /*******************/
3040
3041 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3042 {
3043         struct ath_hal_5416 *ahp = AH5416(ah);
3044         int flags = 0;
3045
3046         ahp->ah_beaconInterval = beacon_period;
3047
3048         switch (ah->ah_opmode) {
3049         case NL80211_IFTYPE_STATION:
3050         case NL80211_IFTYPE_MONITOR:
3051                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3052                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3053                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3054                 flags |= AR_TBTT_TIMER_EN;
3055                 break;
3056         case NL80211_IFTYPE_ADHOC:
3057                 REG_SET_BIT(ah, AR_TXCFG,
3058                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3059                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3060                           TU_TO_USEC(next_beacon +
3061                                      (ahp->ah_atimWindow ? ahp->
3062                                       ah_atimWindow : 1)));
3063                 flags |= AR_NDP_TIMER_EN;
3064         case NL80211_IFTYPE_AP:
3065                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3066                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3067                           TU_TO_USEC(next_beacon -
3068                                      ah->ah_config.
3069                                      dma_beacon_response_time));
3070                 REG_WRITE(ah, AR_NEXT_SWBA,
3071                           TU_TO_USEC(next_beacon -
3072                                      ah->ah_config.
3073                                      sw_beacon_response_time));
3074                 flags |=
3075                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3076                 break;
3077         default:
3078                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3079                         "%s: unsupported opmode: %d\n",
3080                         __func__, ah->ah_opmode);
3081                 return;
3082                 break;
3083         }
3084
3085         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3086         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3087         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3088         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3089
3090         beacon_period &= ~ATH9K_BEACON_ENA;
3091         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3092                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3093                 ath9k_hw_reset_tsf(ah);
3094         }
3095
3096         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3097 }
3098
3099 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3100                                     const struct ath9k_beacon_state *bs)
3101 {
3102         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3103         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3104
3105         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3106
3107         REG_WRITE(ah, AR_BEACON_PERIOD,
3108                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3109         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3110                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3111
3112         REG_RMW_FIELD(ah, AR_RSSI_THR,
3113                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3114
3115         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3116
3117         if (bs->bs_sleepduration > beaconintval)
3118                 beaconintval = bs->bs_sleepduration;
3119
3120         dtimperiod = bs->bs_dtimperiod;
3121         if (bs->bs_sleepduration > dtimperiod)
3122                 dtimperiod = bs->bs_sleepduration;
3123
3124         if (beaconintval == dtimperiod)
3125                 nextTbtt = bs->bs_nextdtim;
3126         else
3127                 nextTbtt = bs->bs_nexttbtt;
3128
3129         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3130         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3131         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3132         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3133
3134         REG_WRITE(ah, AR_NEXT_DTIM,
3135                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3136         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3137
3138         REG_WRITE(ah, AR_SLEEP1,
3139                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3140                   | AR_SLEEP1_ASSUME_DTIM);
3141
3142         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3143                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3144         else
3145                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3146
3147         REG_WRITE(ah, AR_SLEEP2,
3148                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3149
3150         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3151         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3152
3153         REG_SET_BIT(ah, AR_TIMER_MODE,
3154                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3155                     AR_DTIM_TIMER_EN);
3156
3157 }
3158
3159 /*******************/
3160 /* HW Capabilities */
3161 /*******************/
3162
3163 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3164 {
3165         struct ath_hal_5416 *ahp = AH5416(ah);
3166         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3167         u16 capField = 0, eeval;
3168
3169         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3170
3171         ah->ah_currentRD = eeval;
3172
3173         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3174         ah->ah_currentRDExt = eeval;
3175
3176         capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3177
3178         if (ah->ah_opmode != NL80211_IFTYPE_AP &&
3179             ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3180                 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3181                         ah->ah_currentRD += 5;
3182                 else if (ah->ah_currentRD == 0x41)
3183                         ah->ah_currentRD = 0x43;
3184                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3185                         "regdomain mapped to 0x%x\n", ah->ah_currentRD);
3186         }
3187
3188         eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3189         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3190
3191         if (eeval & AR5416_OPFLAGS_11A) {
3192                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3193                 if (ah->ah_config.ht_enable) {
3194                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3195                                 set_bit(ATH9K_MODE_11NA_HT20,
3196                                         pCap->wireless_modes);
3197                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3198                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3199                                         pCap->wireless_modes);
3200                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3201                                         pCap->wireless_modes);
3202                         }
3203                 }
3204         }
3205
3206         if (eeval & AR5416_OPFLAGS_11G) {
3207                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3208                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3209                 if (ah->ah_config.ht_enable) {
3210                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3211                                 set_bit(ATH9K_MODE_11NG_HT20,
3212                                         pCap->wireless_modes);
3213                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3214                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3215                                         pCap->wireless_modes);
3216                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3217                                         pCap->wireless_modes);
3218                         }
3219                 }
3220         }
3221
3222         pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3223         if ((ah->ah_isPciExpress)
3224             || (eeval & AR5416_OPFLAGS_11A)) {
3225                 pCap->rx_chainmask =
3226                         ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3227         } else {
3228                 pCap->rx_chainmask =
3229                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3230         }
3231
3232         if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3233                 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3234
3235         pCap->low_2ghz_chan = 2312;
3236         pCap->high_2ghz_chan = 2732;
3237
3238         pCap->low_5ghz_chan = 4920;
3239         pCap->high_5ghz_chan = 6100;
3240
3241         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3242         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3243         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3244
3245         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3246         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3247         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3248
3249         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3250
3251         if (ah->ah_config.ht_enable)
3252                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3253         else
3254                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3255
3256         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3257         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3258         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3259         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3260
3261         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3262                 pCap->total_queues =
3263                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3264         else
3265                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3266
3267         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3268                 pCap->keycache_size =
3269                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3270         else
3271                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3272
3273         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3274         pCap->num_mr_retries = 4;
3275         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3276
3277         if (AR_SREV_9280_10_OR_LATER(ah))
3278                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3279         else
3280                 pCap->num_gpio_pins = AR_NUM_GPIO;
3281
3282         if (AR_SREV_9280_10_OR_LATER(ah)) {
3283                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3284                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3285         } else {
3286                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3287                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3288         }
3289
3290         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3291                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3292                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3293         } else {
3294                 pCap->rts_aggr_limit = (8 * 1024);
3295         }
3296
3297         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3298
3299 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3300         ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3301         if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3302                 ah->ah_rfkill_gpio =
3303                         MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3304                 ah->ah_rfkill_polarity =
3305                         MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3306
3307                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3308         }
3309 #endif
3310
3311         if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3312             (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3313             (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3314             (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3315             (ah->ah_macVersion == AR_SREV_VERSION_9280))
3316                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3317         else
3318                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3319
3320         if (AR_SREV_9280(ah))
3321                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3322         else
3323                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3324
3325         if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3326                 pCap->reg_cap =
3327                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3328                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3329                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3330                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3331         } else {
3332                 pCap->reg_cap =
3333                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3334                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3335         }
3336
3337         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3338
3339         pCap->num_antcfg_5ghz =
3340                 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_5GHZ);
3341         pCap->num_antcfg_2ghz =
3342                 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_2GHZ);
3343
3344         return true;
3345 }
3346
3347 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3348                             u32 capability, u32 *result)
3349 {
3350         struct ath_hal_5416 *ahp = AH5416(ah);
3351         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3352
3353         switch (type) {
3354         case ATH9K_CAP_CIPHER:
3355                 switch (capability) {
3356                 case ATH9K_CIPHER_AES_CCM:
3357                 case ATH9K_CIPHER_AES_OCB:
3358                 case ATH9K_CIPHER_TKIP:
3359                 case ATH9K_CIPHER_WEP:
3360                 case ATH9K_CIPHER_MIC:
3361                 case ATH9K_CIPHER_CLR:
3362                         return true;
3363                 default:
3364                         return false;
3365                 }
3366         case ATH9K_CAP_TKIP_MIC:
3367                 switch (capability) {
3368                 case 0:
3369                         return true;
3370                 case 1:
3371                         return (ahp->ah_staId1Defaults &
3372                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3373                         false;
3374                 }
3375         case ATH9K_CAP_TKIP_SPLIT:
3376                 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3377                         false : true;
3378         case ATH9K_CAP_WME_TKIPMIC:
3379                 return 0;
3380         case ATH9K_CAP_PHYCOUNTERS:
3381                 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3382         case ATH9K_CAP_DIVERSITY:
3383                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3384                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3385                         true : false;
3386         case ATH9K_CAP_PHYDIAG:
3387                 return true;
3388         case ATH9K_CAP_MCAST_KEYSRCH:
3389                 switch (capability) {
3390                 case 0:
3391                         return true;
3392                 case 1:
3393                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3394                                 return false;
3395                         } else {
3396                                 return (ahp->ah_staId1Defaults &
3397                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3398                                         false;
3399                         }
3400                 }
3401                 return false;
3402         case ATH9K_CAP_TSF_ADJUST:
3403                 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3404                         true : false;
3405         case ATH9K_CAP_RFSILENT:
3406                 if (capability == 3)
3407                         return false;
3408         case ATH9K_CAP_ANT_CFG_2GHZ:
3409                 *result = pCap->num_antcfg_2ghz;
3410                 return true;
3411         case ATH9K_CAP_ANT_CFG_5GHZ:
3412                 *result = pCap->num_antcfg_5ghz;
3413                 return true;
3414         case ATH9K_CAP_TXPOW:
3415                 switch (capability) {
3416                 case 0:
3417                         return 0;
3418                 case 1:
3419                         *result = ah->ah_powerLimit;
3420                         return 0;
3421                 case 2:
3422                         *result = ah->ah_maxPowerLevel;
3423                         return 0;
3424                 case 3:
3425                         *result = ah->ah_tpScale;
3426                         return 0;
3427                 }
3428                 return false;
3429         default:
3430                 return false;
3431         }
3432 }
3433
3434 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3435                             u32 capability, u32 setting, int *status)
3436 {
3437         struct ath_hal_5416 *ahp = AH5416(ah);
3438         u32 v;
3439
3440         switch (type) {
3441         case ATH9K_CAP_TKIP_MIC:
3442                 if (setting)
3443                         ahp->ah_staId1Defaults |=
3444                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3445                 else
3446                         ahp->ah_staId1Defaults &=
3447                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3448                 return true;
3449         case ATH9K_CAP_DIVERSITY:
3450                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3451                 if (setting)
3452                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3453                 else
3454                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3455                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3456                 return true;
3457         case ATH9K_CAP_MCAST_KEYSRCH:
3458                 if (setting)
3459                         ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3460                 else
3461                         ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3462                 return true;
3463         case ATH9K_CAP_TSF_ADJUST:
3464                 if (setting)
3465                         ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3466                 else
3467                         ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3468                 return true;
3469         default:
3470                 return false;
3471         }
3472 }
3473
3474 /****************************/
3475 /* GPIO / RFKILL / Antennae */
3476 /****************************/
3477
3478 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3479                                          u32 gpio, u32 type)
3480 {
3481         int addr;
3482         u32 gpio_shift, tmp;
3483
3484         if (gpio > 11)
3485                 addr = AR_GPIO_OUTPUT_MUX3;
3486         else if (gpio > 5)
3487                 addr = AR_GPIO_OUTPUT_MUX2;
3488         else
3489                 addr = AR_GPIO_OUTPUT_MUX1;
3490
3491         gpio_shift = (gpio % 6) * 5;
3492
3493         if (AR_SREV_9280_20_OR_LATER(ah)
3494             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3495                 REG_RMW(ah, addr, (type << gpio_shift),
3496                         (0x1f << gpio_shift));
3497         } else {
3498                 tmp = REG_READ(ah, addr);
3499                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3500                 tmp &= ~(0x1f << gpio_shift);
3501                 tmp |= (type << gpio_shift);
3502                 REG_WRITE(ah, addr, tmp);
3503         }
3504 }
3505
3506 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3507 {
3508         u32 gpio_shift;
3509
3510         ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3511
3512         gpio_shift = gpio << 1;
3513
3514         REG_RMW(ah,
3515                 AR_GPIO_OE_OUT,
3516                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3517                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3518 }
3519
3520 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3521 {
3522         if (gpio >= ah->ah_caps.num_gpio_pins)
3523                 return 0xffffffff;
3524
3525         if (AR_SREV_9280_10_OR_LATER(ah)) {
3526                 return (MS
3527                         (REG_READ(ah, AR_GPIO_IN_OUT),
3528                          AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
3529         } else {
3530                 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
3531                         AR_GPIO_BIT(gpio)) != 0;
3532         }
3533 }
3534
3535 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3536                          u32 ah_signal_type)
3537 {
3538         u32 gpio_shift;
3539
3540         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3541
3542         gpio_shift = 2 * gpio;
3543
3544         REG_RMW(ah,
3545                 AR_GPIO_OE_OUT,
3546                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3547                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3548 }
3549
3550 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3551 {
3552         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3553                 AR_GPIO_BIT(gpio));
3554 }
3555
3556 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3557 void ath9k_enable_rfkill(struct ath_hal *ah)
3558 {
3559         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3560                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3561
3562         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3563                     AR_GPIO_INPUT_MUX2_RFSILENT);
3564
3565         ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3566         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3567 }
3568 #endif
3569
3570 int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
3571 {
3572         struct ath9k_channel *chan = ah->ah_curchan;
3573         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3574         u16 ant_config;
3575         u32 halNumAntConfig;
3576
3577         halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3578                 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
3579
3580         if (cfg < halNumAntConfig) {
3581                 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3582                                                      cfg, &ant_config)) {
3583                         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3584                         return 0;
3585                 }
3586         }
3587
3588         return -EINVAL;
3589 }
3590
3591 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3592 {
3593         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3594 }
3595
3596 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3597 {
3598         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3599 }
3600
3601 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3602                                enum ath9k_ant_setting settings,
3603                                struct ath9k_channel *chan,
3604                                u8 *tx_chainmask,
3605                                u8 *rx_chainmask,
3606                                u8 *antenna_cfgd)
3607 {
3608         struct ath_hal_5416 *ahp = AH5416(ah);
3609         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3610
3611         if (AR_SREV_9280(ah)) {
3612                 if (!tx_chainmask_cfg) {
3613
3614                         tx_chainmask_cfg = *tx_chainmask;
3615                         rx_chainmask_cfg = *rx_chainmask;
3616                 }
3617
3618                 switch (settings) {
3619                 case ATH9K_ANT_FIXED_A:
3620                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3621                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3622                         *antenna_cfgd = true;
3623                         break;
3624                 case ATH9K_ANT_FIXED_B:
3625                         if (ah->ah_caps.tx_chainmask >
3626                             ATH9K_ANTENNA1_CHAINMASK) {
3627                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3628                         }
3629                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3630                         *antenna_cfgd = true;
3631                         break;
3632                 case ATH9K_ANT_VARIABLE:
3633                         *tx_chainmask = tx_chainmask_cfg;
3634                         *rx_chainmask = rx_chainmask_cfg;
3635                         *antenna_cfgd = true;
3636                         break;
3637                 default:
3638                         break;
3639                 }
3640         } else {
3641                 ahp->ah_diversityControl = settings;
3642         }
3643
3644         return true;
3645 }
3646
3647 /*********************/
3648 /* General Operation */
3649 /*********************/
3650
3651 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3652 {
3653         u32 bits = REG_READ(ah, AR_RX_FILTER);
3654         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3655
3656         if (phybits & AR_PHY_ERR_RADAR)
3657                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3658         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3659                 bits |= ATH9K_RX_FILTER_PHYERR;
3660
3661         return bits;
3662 }
3663
3664 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3665 {
3666         u32 phybits;
3667
3668         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3669         phybits = 0;
3670         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3671                 phybits |= AR_PHY_ERR_RADAR;
3672         if (bits & ATH9K_RX_FILTER_PHYERR)
3673                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3674         REG_WRITE(ah, AR_PHY_ERR, phybits);
3675
3676         if (phybits)
3677                 REG_WRITE(ah, AR_RXCFG,
3678                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3679         else
3680                 REG_WRITE(ah, AR_RXCFG,
3681                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3682 }
3683
3684 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3685 {
3686         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3687 }
3688
3689 bool ath9k_hw_disable(struct ath_hal *ah)
3690 {
3691         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3692                 return false;
3693
3694         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3695 }
3696
3697 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3698 {
3699         struct ath9k_channel *chan = ah->ah_curchan;
3700
3701         ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3702
3703         if (ath9k_hw_set_txpower(ah, chan,
3704                                  ath9k_regd_get_ctl(ah, chan),
3705                                  ath9k_regd_get_antenna_allowed(ah, chan),
3706                                  chan->maxRegTxPower * 2,
3707                                  min((u32) MAX_RATE_POWER,
3708                                      (u32) ah->ah_powerLimit)) != 0)
3709                 return false;
3710
3711         return true;
3712 }
3713
3714 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
3715 {
3716         struct ath_hal_5416 *ahp = AH5416(ah);
3717
3718         memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3719 }
3720
3721 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3722 {
3723         struct ath_hal_5416 *ahp = AH5416(ah);
3724
3725         memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3726
3727         return true;
3728 }
3729
3730 void ath9k_hw_setopmode(struct ath_hal *ah)
3731 {
3732         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3733 }
3734
3735 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3736 {
3737         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3738         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3739 }
3740
3741 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
3742 {
3743         struct ath_hal_5416 *ahp = AH5416(ah);
3744
3745         memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3746 }
3747
3748 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
3749 {
3750         struct ath_hal_5416 *ahp = AH5416(ah);
3751
3752         memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
3753
3754         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3755         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3756
3757         return true;
3758 }
3759
3760 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3761 {
3762         struct ath_hal_5416 *ahp = AH5416(ah);
3763
3764         memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3765         ahp->ah_assocId = assocId;
3766
3767         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3768         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3769                   ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3770 }
3771
3772 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3773 {
3774         u64 tsf;
3775
3776         tsf = REG_READ(ah, AR_TSF_U32);
3777         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3778
3779         return tsf;
3780 }
3781
3782 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3783 {
3784         int count;
3785
3786         count = 0;
3787         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3788                 count++;
3789                 if (count > 10) {
3790                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3791                                 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3792                         break;
3793                 }
3794                 udelay(10);
3795         }
3796         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3797 }
3798
3799 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3800 {
3801         struct ath_hal_5416 *ahp = AH5416(ah);
3802
3803         if (setting)
3804                 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3805         else
3806                 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3807
3808         return true;
3809 }
3810
3811 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3812 {
3813         struct ath_hal_5416 *ahp = AH5416(ah);
3814
3815         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3816                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3817                 ahp->ah_slottime = (u32) -1;
3818                 return false;
3819         } else {
3820                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3821                 ahp->ah_slottime = us;
3822                 return true;
3823         }
3824 }
3825
3826 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3827 {
3828         u32 macmode;
3829
3830         if (mode == ATH9K_HT_MACMODE_2040 &&
3831             !ah->ah_config.cwm_ignore_extcca)
3832                 macmode = AR_2040_JOINED_RX_CLEAR;
3833         else
3834                 macmode = 0;
3835
3836         REG_WRITE(ah, AR_2040_MODE, macmode);
3837 }