drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "core.h"
  21 #include "hw.h"
  22 #include "reg.h"
  23 #include "phy.h"
  24 #include "initvals.h"
  25
  26 static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
  27
  28 extern struct hal_percal_data iq_cal_multi_sample;
  29 extern struct hal_percal_data iq_cal_single_sample;
  30 extern struct hal_percal_data adc_gain_cal_multi_sample;
  31 extern struct hal_percal_data adc_gain_cal_single_sample;
  32 extern struct hal_percal_data adc_dc_cal_multi_sample;
  33 extern struct hal_percal_data adc_dc_cal_single_sample;
  34 extern struct hal_percal_data adc_init_dc_cal;
  35
  36 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
  37 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
  38                               enum ath9k_ht_macmode macmode);
  39 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
  40                               struct ar5416_eeprom_def *pEepData,
  41                               u32 reg, u32 value);
  42 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  43 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  44
  45 /********************/
  46 /* Helper Functions */
  47 /********************/
  48
  49 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
  50 {
  51         if (ah->ah_curchan != NULL)
  52                 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
  53         else
  54                 return clks / CLOCK_RATE[ATH9K_MODE_11B];
  55 }
  56
  57 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
  58 {
  59         struct ath9k_channel *chan = ah->ah_curchan;
  60
  61         if (chan && IS_CHAN_HT40(chan))
  62                 return ath9k_hw_mac_usec(ah, clks) / 2;
  63         else
  64                 return ath9k_hw_mac_usec(ah, clks);
  65 }
  66
  67 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
  68 {
  69         if (ah->ah_curchan != NULL)
  70                 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
  71                         ah->ah_curchan)];
  72         else
  73                 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
  74 }
  75
  76 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
  77 {
  78         struct ath9k_channel *chan = ah->ah_curchan;
  79
  80         if (chan && IS_CHAN_HT40(chan))
  81                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  82         else
  83                 return ath9k_hw_mac_clks(ah, usecs);
  84 }
  85
  86 enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
  87                                const struct ath9k_channel *chan)
  88 {
  89         if (IS_CHAN_B(chan))
  90                 return ATH9K_MODE_11B;
  91         if (IS_CHAN_G(chan))
  92                 return ATH9K_MODE_11G;
  93
  94         return ATH9K_MODE_11A;
  95 }
  96
  97 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
  98 {
  99         int i;
 100
 101         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
 102                 if ((REG_READ(ah, reg) & mask) == val)
 103                         return true;
 104
 105                 udelay(AH_TIME_QUANTUM);
 106         }
 107
 108         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 109                 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 110                 reg, REG_READ(ah, reg), mask, val);
 111
 112         return false;
 113 }
 114
 115 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 116 {
 117         u32 retval;
 118         int i;
 119
 120         for (i = 0, retval = 0; i < n; i++) {
 121                 retval = (retval << 1) | (val & 1);
 122                 val >>= 1;
 123         }
 124         return retval;
 125 }
 126
 127 bool ath9k_get_channel_edges(struct ath_hal *ah,
 128                              u16 flags, u16 *low,
 129                              u16 *high)
 130 {
 131         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
 132
 133         if (flags & CHANNEL_5GHZ) {
 134                 *low = pCap->low_5ghz_chan;
 135                 *high = pCap->high_5ghz_chan;
 136                 return true;
 137         }
 138         if ((flags & CHANNEL_2GHZ)) {
 139                 *low = pCap->low_2ghz_chan;
 140                 *high = pCap->high_2ghz_chan;
 141                 return true;
 142         }
 143         return false;
 144 }
 145
 146 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
 147                            struct ath_rate_table *rates,
 148                            u32 frameLen, u16 rateix,
 149                            bool shortPreamble)
 150 {
 151         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 152         u32 kbps;
 153
 154         kbps = rates->info[rateix].ratekbps;
 155
 156         if (kbps == 0)
 157                 return 0;
 158
 159         switch (rates->info[rateix].phy) {
 160         case WLAN_RC_PHY_CCK:
 161                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 162                 if (shortPreamble && rates->info[rateix].short_preamble)
 163                         phyTime >>= 1;
 164                 numBits = frameLen << 3;
 165                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 166                 break;
 167         case WLAN_RC_PHY_OFDM:
 168                 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
 169                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 170                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 171                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 172                         txTime = OFDM_SIFS_TIME_QUARTER
 173                                 + OFDM_PREAMBLE_TIME_QUARTER
 174                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 175                 } else if (ah->ah_curchan &&
 176                            IS_CHAN_HALF_RATE(ah->ah_curchan)) {
 177                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 178                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 179                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 180                         txTime = OFDM_SIFS_TIME_HALF +
 181                                 OFDM_PREAMBLE_TIME_HALF
 182                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 183                 } else {
 184                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 185                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 186                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 187                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 188                                 + (numSymbols * OFDM_SYMBOL_TIME);
 189                 }
 190                 break;
 191         default:
 192                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 193                         "Unknown phy %u (rate ix %u)\n",
 194                         rates->info[rateix].phy, rateix);
 195                 txTime = 0;
 196                 break;
 197         }
 198
 199         return txTime;
 200 }
 201
 202 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
 203 {
 204         if (flags & CHANNEL_2GHZ) {
 205                 if (freq == 2484)
 206                         return 14;
 207                 if (freq < 2484)
 208                         return (freq - 2407) / 5;
 209                 else
 210                         return 15 + ((freq - 2512) / 20);
 211         } else if (flags & CHANNEL_5GHZ) {
 212                 if (ath9k_regd_is_public_safety_sku(ah) &&
 213                     IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
 214                         return ((freq * 10) +
 215                                 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
 216                 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
 217                         return (freq - 4000) / 5;
 218                 } else {
 219                         return (freq - 5000) / 5;
 220                 }
 221         } else {
 222                 if (freq == 2484)
 223                         return 14;
 224                 if (freq < 2484)
 225                         return (freq - 2407) / 5;
 226                 if (freq < 5000) {
 227                         if (ath9k_regd_is_public_safety_sku(ah)
 228                             && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
 229                                 return ((freq * 10) +
 230                                         (((freq % 5) ==
 231                                           2) ? 5 : 0) - 49400) / 5;
 232                         } else if (freq > 4900) {
 233                                 return (freq - 4000) / 5;
 234                         } else {
 235                                 return 15 + ((freq - 2512) / 20);
 236                         }
 237                 }
 238                 return (freq - 5000) / 5;
 239         }
 240 }
 241
 242 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
 243                                   struct ath9k_channel *chan,
 244                                   struct chan_centers *centers)
 245 {
 246         int8_t extoff;
 247         struct ath_hal_5416 *ahp = AH5416(ah);
 248
 249         if (!IS_CHAN_HT40(chan)) {
 250                 centers->ctl_center = centers->ext_center =
 251                         centers->synth_center = chan->channel;
 252                 return;
 253         }
 254
 255         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 256             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 257                 centers->synth_center =
 258                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 259                 extoff = 1;
 260         } else {
 261                 centers->synth_center =
 262                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 263                 extoff = -1;
 264         }
 265
 266         centers->ctl_center =
 267                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 268         centers->ext_center =
 269                 centers->synth_center + (extoff *
 270                          ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 271                           HT40_CHANNEL_CENTER_SHIFT : 15));
 272
 273 }
 274
 275 /******************/
 276 /* Chip Revisions */
 277 /******************/
 278
 279 static void ath9k_hw_read_revisions(struct ath_hal *ah)
 280 {
 281         u32 val;
 282
 283         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 284
 285         if (val == 0xFF) {
 286                 val = REG_READ(ah, AR_SREV);
 287                 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 288                 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
 289                 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 290         } else {
 291                 if (!AR_SREV_9100(ah))
 292                         ah->ah_macVersion = MS(val, AR_SREV_VERSION);
 293
 294                 ah->ah_macRev = val & AR_SREV_REVISION;
 295
 296                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
 297                         ah->ah_isPciExpress = true;
 298         }
 299 }
 300
 301 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
 302 {
 303         u32 val;
 304         int i;
 305
 306         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 307
 308         for (i = 0; i < 8; i++)
 309                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 310         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 311         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 312
 313         return ath9k_hw_reverse_bits(val, 8);
 314 }
 315
 316 /************************************/
 317 /* HW Attach, Detach, Init Routines */
 318 /************************************/
 319
 320 static void ath9k_hw_disablepcie(struct ath_hal *ah)
 321 {
 322         if (!AR_SREV_9100(ah))
 323                 return;
 324
 325         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 326         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 327         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 328         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 329         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 330         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 331         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 332         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 333         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 334
 335         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 336 }
 337
 338 static bool ath9k_hw_chip_test(struct ath_hal *ah)
 339 {
 340         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 341         u32 regHold[2];
 342         u32 patternData[4] = { 0x55555555,
 343                                0xaaaaaaaa,
 344                                0x66666666,
 345                                0x99999999 };
 346         int i, j;
 347
 348         for (i = 0; i < 2; i++) {
 349                 u32 addr = regAddr[i];
 350                 u32 wrData, rdData;
 351
 352                 regHold[i] = REG_READ(ah, addr);
 353                 for (j = 0; j < 0x100; j++) {
 354                         wrData = (j << 16) | j;
 355                         REG_WRITE(ah, addr, wrData);
 356                         rdData = REG_READ(ah, addr);
 357                         if (rdData != wrData) {
 358                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 359                                         "address test failed "
 360                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 361                                         addr, wrData, rdData);
 362                                 return false;
 363                         }
 364                 }
 365                 for (j = 0; j < 4; j++) {
 366                         wrData = patternData[j];
 367                         REG_WRITE(ah, addr, wrData);
 368                         rdData = REG_READ(ah, addr);
 369                         if (wrData != rdData) {
 370                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 371                                         "address test failed "
 372                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 373                                         addr, wrData, rdData);
 374                                 return false;
 375                         }
 376                 }
 377                 REG_WRITE(ah, regAddr[i], regHold[i]);
 378         }
 379         udelay(100);
 380         return true;
 381 }
 382
 383 static const char *ath9k_hw_devname(u16 devid)
 384 {
 385         switch (devid) {
 386         case AR5416_DEVID_PCI:
 387                 return "Atheros 5416";
 388         case AR5416_DEVID_PCIE:
 389                 return "Atheros 5418";
 390         case AR9160_DEVID_PCI:
 391                 return "Atheros 9160";
 392         case AR9280_DEVID_PCI:
 393         case AR9280_DEVID_PCIE:
 394                 return "Atheros 9280";
 395         case AR9285_DEVID_PCIE:
 396                 return "Atheros 9285";
 397         }
 398
 399         return NULL;
 400 }
 401
 402 static void ath9k_hw_set_defaults(struct ath_hal *ah)
 403 {
 404         int i;
 405
 406         ah->ah_config.dma_beacon_response_time = 2;
 407         ah->ah_config.sw_beacon_response_time = 10;
 408         ah->ah_config.additional_swba_backoff = 0;
 409         ah->ah_config.ack_6mb = 0x0;
 410         ah->ah_config.cwm_ignore_extcca = 0;
 411         ah->ah_config.pcie_powersave_enable = 0;
 412         ah->ah_config.pcie_l1skp_enable = 0;
 413         ah->ah_config.pcie_clock_req = 0;
 414         ah->ah_config.pcie_power_reset = 0x100;
 415         ah->ah_config.pcie_restore = 0;
 416         ah->ah_config.pcie_waen = 0;
 417         ah->ah_config.analog_shiftreg = 1;
 418         ah->ah_config.ht_enable = 1;
 419         ah->ah_config.ofdm_trig_low = 200;
 420         ah->ah_config.ofdm_trig_high = 500;
 421         ah->ah_config.cck_trig_high = 200;
 422         ah->ah_config.cck_trig_low = 100;
 423         ah->ah_config.enable_ani = 1;
 424         ah->ah_config.noise_immunity_level = 4;
 425         ah->ah_config.ofdm_weaksignal_det = 1;
 426         ah->ah_config.cck_weaksignal_thr = 0;
 427         ah->ah_config.spur_immunity_level = 2;
 428         ah->ah_config.firstep_level = 0;
 429         ah->ah_config.rssi_thr_high = 40;
 430         ah->ah_config.rssi_thr_low = 7;
 431         ah->ah_config.diversity_control = 0;
 432         ah->ah_config.antenna_switch_swap = 0;
 433
 434         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 435                 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
 436                 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
 437         }
 438
 439         ah->ah_config.intr_mitigation = 1;
 440 }
 441
 442 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
 443                                               struct ath_softc *sc,
 444                                               void __iomem *mem,
 445                                               int *status)
 446 {
 447         static const u8 defbssidmask[ETH_ALEN] =
 448                 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 449         struct ath_hal_5416 *ahp;
 450         struct ath_hal *ah;
 451
 452         ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
 453         if (ahp == NULL) {
 454                 DPRINTF(sc, ATH_DBG_FATAL,
 455                         "Cannot allocate memory for state block\n");
 456                 *status = -ENOMEM;
 457                 return NULL;
 458         }
 459
 460         ah = &ahp->ah;
 461         ah->ah_sc = sc;
 462         ah->ah_sh = mem;
 463         ah->ah_magic = AR5416_MAGIC;
 464         ah->ah_countryCode = CTRY_DEFAULT;
 465         ah->ah_devid = devid;
 466         ah->ah_subvendorid = 0;
 467
 468         ah->ah_flags = 0;
 469         if ((devid == AR5416_AR9100_DEVID))
 470                 ah->ah_macVersion = AR_SREV_VERSION_9100;
 471         if (!AR_SREV_9100(ah))
 472                 ah->ah_flags = AH_USE_EEPROM;
 473
 474         ah->ah_powerLimit = MAX_RATE_POWER;
 475         ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
 476         ahp->ah_atimWindow = 0;
 477         ahp->ah_diversityControl = ah->ah_config.diversity_control;
 478         ahp->ah_antennaSwitchSwap =
 479                 ah->ah_config.antenna_switch_swap;
 480         ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 481         ahp->ah_beaconInterval = 100;
 482         ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
 483         ahp->ah_slottime = (u32) -1;
 484         ahp->ah_acktimeout = (u32) -1;
 485         ahp->ah_ctstimeout = (u32) -1;
 486         ahp->ah_globaltxtimeout = (u32) -1;
 487         memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
 488
 489         ahp->ah_gBeaconRate = 0;
 490
 491         return ahp;
 492 }
 493
 494 static int ath9k_hw_rfattach(struct ath_hal *ah)
 495 {
 496         bool rfStatus = false;
 497         int ecode = 0;
 498
 499         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 500         if (!rfStatus) {
 501                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 502                         "RF setup failed, status %u\n", ecode);
 503                 return ecode;
 504         }
 505
 506         return 0;
 507 }
 508
 509 static int ath9k_hw_rf_claim(struct ath_hal *ah)
 510 {
 511         u32 val;
 512
 513         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 514
 515         val = ath9k_hw_get_radiorev(ah);
 516         switch (val & AR_RADIO_SREV_MAJOR) {
 517         case 0:
 518                 val = AR_RAD5133_SREV_MAJOR;
 519                 break;
 520         case AR_RAD5133_SREV_MAJOR:
 521         case AR_RAD5122_SREV_MAJOR:
 522         case AR_RAD2133_SREV_MAJOR:
 523         case AR_RAD2122_SREV_MAJOR:
 524                 break;
 525         default:
 526                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 527                         "5G Radio Chip Rev 0x%02X is not "
 528                         "supported by this driver\n",
 529                         ah->ah_analog5GhzRev);
 530                 return -EOPNOTSUPP;
 531         }
 532
 533         ah->ah_analog5GhzRev = val;
 534
 535         return 0;
 536 }
 537
 538 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
 539 {
 540         u32 sum;
 541         int i;
 542         u16 eeval;
 543         struct ath_hal_5416 *ahp = AH5416(ah);
 544
 545         sum = 0;
 546         for (i = 0; i < 3; i++) {
 547                 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
 548                 sum += eeval;
 549                 ahp->ah_macaddr[2 * i] = eeval >> 8;
 550                 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
 551         }
 552         if (sum == 0 || sum == 0xffff * 3) {
 553                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 554                         "mac address read failed: %pM\n",
 555                         ahp->ah_macaddr);
 556                 return -EADDRNOTAVAIL;
 557         }
 558
 559         return 0;
 560 }
 561
 562 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
 563 {
 564         u32 rxgain_type;
 565         struct ath_hal_5416 *ahp = AH5416(ah);
 566
 567         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 568                 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
 569
 570                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 571                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 572                         ar9280Modes_backoff_13db_rxgain_9280_2,
 573                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 574                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 575                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 576                         ar9280Modes_backoff_23db_rxgain_9280_2,
 577                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 578                 else
 579                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 580                         ar9280Modes_original_rxgain_9280_2,
 581                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 582         } else
 583                 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 584                         ar9280Modes_original_rxgain_9280_2,
 585                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 586 }
 587
 588 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
 589 {
 590         u32 txgain_type;
 591         struct ath_hal_5416 *ahp = AH5416(ah);
 592
 593         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 594                 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
 595
 596                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 597                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 598                         ar9280Modes_high_power_tx_gain_9280_2,
 599                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 600                 else
 601                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 602                         ar9280Modes_original_tx_gain_9280_2,
 603                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 604         } else
 605                 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 606                 ar9280Modes_original_tx_gain_9280_2,
 607                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 608 }
 609
 610 static int ath9k_hw_post_attach(struct ath_hal *ah)
 611 {
 612         int ecode;
 613
 614         if (!ath9k_hw_chip_test(ah)) {
 615                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 616                         "hardware self-test failed\n");
 617                 return -ENODEV;
 618         }
 619
 620         ecode = ath9k_hw_rf_claim(ah);
 621         if (ecode != 0)
 622                 return ecode;
 623
 624         ecode = ath9k_hw_eeprom_attach(ah);
 625         if (ecode != 0)
 626                 return ecode;
 627         ecode = ath9k_hw_rfattach(ah);
 628         if (ecode != 0)
 629                 return ecode;
 630
 631         if (!AR_SREV_9100(ah)) {
 632                 ath9k_hw_ani_setup(ah);
 633                 ath9k_hw_ani_attach(ah);
 634         }
 635
 636         return 0;
 637 }
 638
 639 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 640                                           void __iomem *mem, int *status)
 641 {
 642         struct ath_hal_5416 *ahp;
 643         struct ath_hal *ah;
 644         int ecode;
 645         u32 i, j;
 646
 647         ahp = ath9k_hw_newstate(devid, sc, mem, status);
 648         if (ahp == NULL)
 649                 return NULL;
 650
 651         ah = &ahp->ah;
 652
 653         ath9k_hw_set_defaults(ah);
 654
 655         if (ah->ah_config.intr_mitigation != 0)
 656                 ahp->ah_intrMitigation = true;
 657
 658         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 659                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
 660                 ecode = -EIO;
 661                 goto bad;
 662         }
 663
 664         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 665                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
 666                 ecode = -EIO;
 667                 goto bad;
 668         }
 669
 670         if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
 671                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
 672                         ah->ah_config.serialize_regmode =
 673                                 SER_REG_MODE_ON;
 674                 } else {
 675                         ah->ah_config.serialize_regmode =
 676                                 SER_REG_MODE_OFF;
 677                 }
 678         }
 679
 680         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 681                 "serialize_regmode is %d\n",
 682                 ah->ah_config.serialize_regmode);
 683
 684         if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
 685             (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
 686             (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
 687             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
 688                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 689                         "Mac Chip Rev 0x%02x.%x is not supported by "
 690                         "this driver\n", ah->ah_macVersion, ah->ah_macRev);
 691                 ecode = -EOPNOTSUPP;
 692                 goto bad;
 693         }
 694
 695         if (AR_SREV_9100(ah)) {
 696                 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 697                 ahp->ah_suppCals = IQ_MISMATCH_CAL;
 698                 ah->ah_isPciExpress = false;
 699         }
 700         ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 701
 702         if (AR_SREV_9160_10_OR_LATER(ah)) {
 703                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 704                         ahp->ah_iqCalData.calData = &iq_cal_single_sample;
 705                         ahp->ah_adcGainCalData.calData =
 706                                 &adc_gain_cal_single_sample;
 707                         ahp->ah_adcDcCalData.calData =
 708                                 &adc_dc_cal_single_sample;
 709                         ahp->ah_adcDcCalInitData.calData =
 710                                 &adc_init_dc_cal;
 711                 } else {
 712                         ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 713                         ahp->ah_adcGainCalData.calData =
 714                                 &adc_gain_cal_multi_sample;
 715                         ahp->ah_adcDcCalData.calData =
 716                                 &adc_dc_cal_multi_sample;
 717                         ahp->ah_adcDcCalInitData.calData =
 718                                 &adc_init_dc_cal;
 719                 }
 720                 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 721         }
 722
 723         if (AR_SREV_9160(ah)) {
 724                 ah->ah_config.enable_ani = 1;
 725                 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
 726                                         ATH9K_ANI_FIRSTEP_LEVEL);
 727         } else {
 728                 ahp->ah_ani_function = ATH9K_ANI_ALL;
 729                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 730                         ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 731                 }
 732         }
 733
 734         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 735                 "This Mac Chip Rev 0x%02x.%x is \n",
 736                 ah->ah_macVersion, ah->ah_macRev);
 737
 738         if (AR_SREV_9285_12_OR_LATER(ah)) {
 739                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
 740                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 741                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
 742                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 743
 744                 if (ah->ah_config.pcie_clock_req) {
 745                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 746                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 747                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 748                 } else {
 749                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 750                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 751                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 752                                   2);
 753                 }
 754         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 755                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
 756                                ARRAY_SIZE(ar9285Modes_9285), 6);
 757                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
 758                                ARRAY_SIZE(ar9285Common_9285), 2);
 759
 760                 if (ah->ah_config.pcie_clock_req) {
 761                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 762                         ar9285PciePhy_clkreq_off_L1_9285,
 763                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 764                 } else {
 765                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 766                         ar9285PciePhy_clkreq_always_on_L1_9285,
 767                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 768                 }
 769         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 770                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
 771                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 772                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
 773                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 774
 775                 if (ah->ah_config.pcie_clock_req) {
 776                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 777                                ar9280PciePhy_clkreq_off_L1_9280,
 778                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 779                 } else {
 780                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 781                                ar9280PciePhy_clkreq_always_on_L1_9280,
 782                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 783                 }
 784                 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
 785                                ar9280Modes_fast_clock_9280_2,
 786                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 787         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 788                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
 789                                ARRAY_SIZE(ar9280Modes_9280), 6);
 790                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
 791                                ARRAY_SIZE(ar9280Common_9280), 2);
 792         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 793                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
 794                                ARRAY_SIZE(ar5416Modes_9160), 6);
 795                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
 796                                ARRAY_SIZE(ar5416Common_9160), 2);
 797                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
 798                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 799                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
 800                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 801                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
 802                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 803                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
 804                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 805                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
 806                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 807                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
 808                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 809                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
 810                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 811                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
 812                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 813                 if (AR_SREV_9160_11(ah)) {
 814                         INIT_INI_ARRAY(&ahp->ah_iniAddac,
 815                                        ar5416Addac_91601_1,
 816                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 817                 } else {
 818                         INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
 819                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 820                 }
 821         } else if (AR_SREV_9100_OR_LATER(ah)) {
 822                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
 823                                ARRAY_SIZE(ar5416Modes_9100), 6);
 824                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
 825                                ARRAY_SIZE(ar5416Common_9100), 2);
 826                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
 827                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 828                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
 829                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 830                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
 831                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 832                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
 833                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 834                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
 835                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 836                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
 837                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 838                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
 839                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 840                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
 841                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 842                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
 843                                ARRAY_SIZE(ar5416Addac_9100), 2);
 844         } else {
 845                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
 846                                ARRAY_SIZE(ar5416Modes), 6);
 847                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
 848                                ARRAY_SIZE(ar5416Common), 2);
 849                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
 850                                ARRAY_SIZE(ar5416Bank0), 2);
 851                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
 852                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 853                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
 854                                ARRAY_SIZE(ar5416Bank1), 2);
 855                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
 856                                ARRAY_SIZE(ar5416Bank2), 2);
 857                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
 858                                ARRAY_SIZE(ar5416Bank3), 3);
 859                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
 860                                ARRAY_SIZE(ar5416Bank6), 3);
 861                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
 862                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 863                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
 864                                ARRAY_SIZE(ar5416Bank7), 2);
 865                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
 866                                ARRAY_SIZE(ar5416Addac), 2);
 867         }
 868
 869         if (ah->ah_isPciExpress)
 870                 ath9k_hw_configpcipowersave(ah, 0);
 871         else
 872                 ath9k_hw_disablepcie(ah);
 873
 874         ecode = ath9k_hw_post_attach(ah);
 875         if (ecode != 0)
 876                 goto bad;
 877
 878         /* rxgain table */
 879         if (AR_SREV_9280_20(ah))
 880                 ath9k_hw_init_rxgain_ini(ah);
 881
 882         /* txgain table */
 883         if (AR_SREV_9280_20(ah))
 884                 ath9k_hw_init_txgain_ini(ah);
 885
 886         if (ah->ah_devid == AR9280_DEVID_PCI) {
 887                 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
 888                         u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
 889
 890                         for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
 891                                 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
 892
 893                                 INI_RA(&ahp->ah_iniModes, i, j) =
 894                                         ath9k_hw_ini_fixup(ah,
 895                                                            &ahp->ah_eeprom.def,
 896                                                            reg, val);
 897                         }
 898                 }
 899         }
 900
 901         if (!ath9k_hw_fill_cap_info(ah)) {
 902                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 903                         "failed ath9k_hw_fill_cap_info\n");
 904                 ecode = -EINVAL;
 905                 goto bad;
 906         }
 907
 908         ecode = ath9k_hw_init_macaddr(ah);
 909         if (ecode != 0) {
 910                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 911                         "failed initializing mac address\n");
 912                 goto bad;
 913         }
 914
 915         if (AR_SREV_9285(ah))
 916                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
 917         else
 918                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
 919
 920         ath9k_init_nfcal_hist_buffer(ah);
 921
 922         return ah;
 923 bad:
 924         if (ahp)
 925                 ath9k_hw_detach((struct ath_hal *) ahp);
 926         if (status)
 927                 *status = ecode;
 928
 929         return NULL;
 930 }
 931
 932 static void ath9k_hw_init_bb(struct ath_hal *ah,
 933                              struct ath9k_channel *chan)
 934 {
 935         u32 synthDelay;
 936
 937         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 938         if (IS_CHAN_B(chan))
 939                 synthDelay = (4 * synthDelay) / 22;
 940         else
 941                 synthDelay /= 10;
 942
 943         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 944
 945         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 946 }
 947
 948 static void ath9k_hw_init_qos(struct ath_hal *ah)
 949 {
 950         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 951         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 952
 953         REG_WRITE(ah, AR_QOS_NO_ACK,
 954                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 955                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 956                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 957
 958         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 959         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 960         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 961         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 962         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 963 }
 964
 965 static void ath9k_hw_init_pll(struct ath_hal *ah,
 966                               struct ath9k_channel *chan)
 967 {
 968         u32 pll;
 969
 970         if (AR_SREV_9100(ah)) {
 971                 if (chan && IS_CHAN_5GHZ(chan))
 972                         pll = 0x1450;
 973                 else
 974                         pll = 0x1458;
 975         } else {
 976                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 977                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 978
 979                         if (chan && IS_CHAN_HALF_RATE(chan))
 980                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 981                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 982                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 983
 984                         if (chan && IS_CHAN_5GHZ(chan)) {
 985                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 986
 987
 988                                 if (AR_SREV_9280_20(ah)) {
 989                                         if (((chan->channel % 20) == 0)
 990                                             || ((chan->channel % 10) == 0))
 991                                                 pll = 0x2850;
 992                                         else
 993                                                 pll = 0x142c;
 994                                 }
 995                         } else {
 996                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 997                         }
 998
 999                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1000
1001                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1002
1003                         if (chan && IS_CHAN_HALF_RATE(chan))
1004                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1005                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1006                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1007
1008                         if (chan && IS_CHAN_5GHZ(chan))
1009                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1010                         else
1011                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1012                 } else {
1013                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1014
1015                         if (chan && IS_CHAN_HALF_RATE(chan))
1016                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1017                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1018                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1019
1020                         if (chan && IS_CHAN_5GHZ(chan))
1021                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1022                         else
1023                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1024                 }
1025         }
1026         REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1027
1028         udelay(RTC_PLL_SETTLE_DELAY);
1029
1030         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1031 }
1032
1033 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1034 {
1035         struct ath_hal_5416 *ahp = AH5416(ah);
1036         int rx_chainmask, tx_chainmask;
1037
1038         rx_chainmask = ahp->ah_rxchainmask;
1039         tx_chainmask = ahp->ah_txchainmask;
1040
1041         switch (rx_chainmask) {
1042         case 0x5:
1043                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1044                             AR_PHY_SWAP_ALT_CHAIN);
1045         case 0x3:
1046                 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1047                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1048                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1049                         break;
1050                 }
1051         case 0x1:
1052         case 0x2:
1053         case 0x7:
1054                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1055                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1056                 break;
1057         default:
1058                 break;
1059         }
1060
1061         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1062         if (tx_chainmask == 0x5) {
1063                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1064                             AR_PHY_SWAP_ALT_CHAIN);
1065         }
1066         if (AR_SREV_9100(ah))
1067                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1068                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1069 }
1070
1071 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1072                                           enum nl80211_iftype opmode)
1073 {
1074         struct ath_hal_5416 *ahp = AH5416(ah);
1075
1076         ahp->ah_maskReg = AR_IMR_TXERR |
1077                 AR_IMR_TXURN |
1078                 AR_IMR_RXERR |
1079                 AR_IMR_RXORN |
1080                 AR_IMR_BCNMISC;
1081
1082         if (ahp->ah_intrMitigation)
1083                 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1084         else
1085                 ahp->ah_maskReg |= AR_IMR_RXOK;
1086
1087         ahp->ah_maskReg |= AR_IMR_TXOK;
1088
1089         if (opmode == NL80211_IFTYPE_AP)
1090                 ahp->ah_maskReg |= AR_IMR_MIB;
1091
1092         REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1093         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1094
1095         if (!AR_SREV_9100(ah)) {
1096                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1097                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1098                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1099         }
1100 }
1101
1102 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1103 {
1104         struct ath_hal_5416 *ahp = AH5416(ah);
1105
1106         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1107                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1108                 ahp->ah_acktimeout = (u32) -1;
1109                 return false;
1110         } else {
1111                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1112                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1113                 ahp->ah_acktimeout = us;
1114                 return true;
1115         }
1116 }
1117
1118 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1119 {
1120         struct ath_hal_5416 *ahp = AH5416(ah);
1121
1122         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1123                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1124                 ahp->ah_ctstimeout = (u32) -1;
1125                 return false;
1126         } else {
1127                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1128                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1129                 ahp->ah_ctstimeout = us;
1130                 return true;
1131         }
1132 }
1133
1134 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1135 {
1136         struct ath_hal_5416 *ahp = AH5416(ah);
1137
1138         if (tu > 0xFFFF) {
1139                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1140                         "bad global tx timeout %u\n", tu);
1141                 ahp->ah_globaltxtimeout = (u32) -1;
1142                 return false;
1143         } else {
1144                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1145                 ahp->ah_globaltxtimeout = tu;
1146                 return true;
1147         }
1148 }
1149
1150 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1151 {
1152         struct ath_hal_5416 *ahp = AH5416(ah);
1153
1154         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1155                 ahp->ah_miscMode);
1156
1157         if (ahp->ah_miscMode != 0)
1158                 REG_WRITE(ah, AR_PCU_MISC,
1159                           REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1160         if (ahp->ah_slottime != (u32) -1)
1161                 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1162         if (ahp->ah_acktimeout != (u32) -1)
1163                 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1164         if (ahp->ah_ctstimeout != (u32) -1)
1165                 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1166         if (ahp->ah_globaltxtimeout != (u32) -1)
1167                 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1168 }
1169
1170 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1171 {
1172         return vendorid == ATHEROS_VENDOR_ID ?
1173                 ath9k_hw_devname(devid) : NULL;
1174 }
1175
1176 void ath9k_hw_detach(struct ath_hal *ah)
1177 {
1178         if (!AR_SREV_9100(ah))
1179                 ath9k_hw_ani_detach(ah);
1180
1181         ath9k_hw_rfdetach(ah);
1182         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1183         kfree(ah);
1184 }
1185
1186 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1187                                 void __iomem *mem, int *error)
1188 {
1189         struct ath_hal *ah = NULL;
1190
1191         switch (devid) {
1192         case AR5416_DEVID_PCI:
1193         case AR5416_DEVID_PCIE:
1194         case AR9160_DEVID_PCI:
1195         case AR9280_DEVID_PCI:
1196         case AR9280_DEVID_PCIE:
1197         case AR9285_DEVID_PCIE:
1198                 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1199                 break;
1200         default:
1201                 *error = -ENXIO;
1202                 break;
1203         }
1204
1205         return ah;
1206 }
1207
1208 /*******/
1209 /* INI */
1210 /*******/
1211
1212 static void ath9k_hw_override_ini(struct ath_hal *ah,
1213                                   struct ath9k_channel *chan)
1214 {
1215         /*
1216          * Set the RX_ABORT and RX_DIS and clear if off only after
1217          * RXE is set for MAC. This prevents frames with corrupted
1218          * descriptor status.
1219          */
1220         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1221
1222
1223         if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1224             AR_SREV_9280_10_OR_LATER(ah))
1225                 return;
1226
1227         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1228 }
1229
1230 static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1231                               struct ar5416_eeprom_def *pEepData,
1232                               u32 reg, u32 value)
1233 {
1234         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1235
1236         switch (ah->ah_devid) {
1237         case AR9280_DEVID_PCI:
1238                 if (reg == 0x7894) {
1239                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1240                                 "ini VAL: %x  EEPROM: %x\n", value,
1241                                 (pBase->version & 0xff));
1242
1243                         if ((pBase->version & 0xff) > 0x0a) {
1244                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1245                                         "PWDCLKIND: %d\n",
1246                                         pBase->pwdclkind);
1247                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1248                                 value |= AR_AN_TOP2_PWDCLKIND &
1249                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1250                         } else {
1251                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1252                                         "PWDCLKIND Earlier Rev\n");
1253                         }
1254
1255                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1256                                 "final ini VAL: %x\n", value);
1257                 }
1258                 break;
1259         }
1260
1261         return value;
1262 }
1263
1264 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1265                               struct ar5416_eeprom_def *pEepData,
1266                               u32 reg, u32 value)
1267 {
1268         struct ath_hal_5416 *ahp = AH5416(ah);
1269
1270         if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1271                 return value;
1272         else
1273                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1274 }
1275
1276 static int ath9k_hw_process_ini(struct ath_hal *ah,
1277                                 struct ath9k_channel *chan,
1278                                 enum ath9k_ht_macmode macmode)
1279 {
1280         int i, regWrites = 0;
1281         struct ath_hal_5416 *ahp = AH5416(ah);
1282         u32 modesIndex, freqIndex;
1283         int status;
1284
1285         switch (chan->chanmode) {
1286         case CHANNEL_A:
1287         case CHANNEL_A_HT20:
1288                 modesIndex = 1;
1289                 freqIndex = 1;
1290                 break;
1291         case CHANNEL_A_HT40PLUS:
1292         case CHANNEL_A_HT40MINUS:
1293                 modesIndex = 2;
1294                 freqIndex = 1;
1295                 break;
1296         case CHANNEL_G:
1297         case CHANNEL_G_HT20:
1298         case CHANNEL_B:
1299                 modesIndex = 4;
1300                 freqIndex = 2;
1301                 break;
1302         case CHANNEL_G_HT40PLUS:
1303         case CHANNEL_G_HT40MINUS:
1304                 modesIndex = 3;
1305                 freqIndex = 2;
1306                 break;
1307
1308         default:
1309                 return -EINVAL;
1310         }
1311
1312         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1313
1314         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1315
1316         ath9k_hw_set_addac(ah, chan);
1317
1318         if (AR_SREV_5416_V22_OR_LATER(ah)) {
1319                 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1320         } else {
1321                 struct ar5416IniArray temp;
1322                 u32 addacSize =
1323                         sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1324                         ahp->ah_iniAddac.ia_columns;
1325
1326                 memcpy(ahp->ah_addac5416_21,
1327                        ahp->ah_iniAddac.ia_array, addacSize);
1328
1329                 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1330
1331                 temp.ia_array = ahp->ah_addac5416_21;
1332                 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1333                 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1334                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1335         }
1336
1337         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1338
1339         for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1340                 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1341                 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1342
1343                 REG_WRITE(ah, reg, val);
1344
1345                 if (reg >= 0x7800 && reg < 0x78a0
1346                     && ah->ah_config.analog_shiftreg) {
1347                         udelay(100);
1348                 }
1349
1350                 DO_DELAY(regWrites);
1351         }
1352
1353         if (AR_SREV_9280(ah))
1354                 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1355
1356         if (AR_SREV_9280(ah))
1357                 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1358
1359         for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1360                 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1361                 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1362
1363                 REG_WRITE(ah, reg, val);
1364
1365                 if (reg >= 0x7800 && reg < 0x78a0
1366                     && ah->ah_config.analog_shiftreg) {
1367                         udelay(100);
1368                 }
1369
1370                 DO_DELAY(regWrites);
1371         }
1372
1373         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1374
1375         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1376                 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1377                                 regWrites);
1378         }
1379
1380         ath9k_hw_override_ini(ah, chan);
1381         ath9k_hw_set_regs(ah, chan, macmode);
1382         ath9k_hw_init_chain_masks(ah);
1383
1384         status = ath9k_hw_set_txpower(ah, chan,
1385                                       ath9k_regd_get_ctl(ah, chan),
1386                                       ath9k_regd_get_antenna_allowed(ah,
1387                                                                      chan),
1388                                       chan->maxRegTxPower * 2,
1389                                       min((u32) MAX_RATE_POWER,
1390                                           (u32) ah->ah_powerLimit));
1391         if (status != 0) {
1392                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1393                         "error init'ing transmit power\n");
1394                 return -EIO;
1395         }
1396
1397         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1398                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1399                         "ar5416SetRfRegs failed\n");
1400                 return -EIO;
1401         }
1402
1403         return 0;
1404 }
1405
1406 /****************************************/
1407 /* Reset and Channel Switching Routines */
1408 /****************************************/
1409
1410 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1411 {
1412         u32 rfMode = 0;
1413
1414         if (chan == NULL)
1415                 return;
1416
1417         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1418                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1419
1420         if (!AR_SREV_9280_10_OR_LATER(ah))
1421                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1422                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1423
1424         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1425                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1426
1427         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1428 }
1429
1430 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1431 {
1432         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1433 }
1434
1435 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1436 {
1437         u32 regval;
1438
1439         regval = REG_READ(ah, AR_AHB_MODE);
1440         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1441
1442         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1443         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1444
1445         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1446
1447         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1448         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1449
1450         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1451
1452         if (AR_SREV_9285(ah)) {
1453                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1454                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1455         } else {
1456                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1457                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1458         }
1459 }
1460
1461 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1462 {
1463         u32 val;
1464
1465         val = REG_READ(ah, AR_STA_ID1);
1466         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1467         switch (opmode) {
1468         case NL80211_IFTYPE_AP:
1469                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1470                           | AR_STA_ID1_KSRCH_MODE);
1471                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1472                 break;
1473         case NL80211_IFTYPE_ADHOC:
1474                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1475                           | AR_STA_ID1_KSRCH_MODE);
1476                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1477                 break;
1478         case NL80211_IFTYPE_STATION:
1479         case NL80211_IFTYPE_MONITOR:
1480                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1481                 break;
1482         }
1483 }
1484
1485 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1486                                                  u32 coef_scaled,
1487                                                  u32 *coef_mantissa,
1488                                                  u32 *coef_exponent)
1489 {
1490         u32 coef_exp, coef_man;
1491
1492         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1493                 if ((coef_scaled >> coef_exp) & 0x1)
1494                         break;
1495
1496         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1497
1498         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1499
1500         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1501         *coef_exponent = coef_exp - 16;
1502 }
1503
1504 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1505                                      struct ath9k_channel *chan)
1506 {
1507         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1508         u32 clockMhzScaled = 0x64000000;
1509         struct chan_centers centers;
1510
1511         if (IS_CHAN_HALF_RATE(chan))
1512                 clockMhzScaled = clockMhzScaled >> 1;
1513         else if (IS_CHAN_QUARTER_RATE(chan))
1514                 clockMhzScaled = clockMhzScaled >> 2;
1515
1516         ath9k_hw_get_channel_centers(ah, chan, &centers);
1517         coef_scaled = clockMhzScaled / centers.synth_center;
1518
1519         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1520                                       &ds_coef_exp);
1521
1522         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1523                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1524         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1525                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1526
1527         coef_scaled = (9 * coef_scaled) / 10;
1528
1529         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1530                                       &ds_coef_exp);
1531
1532         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1533                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1534         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1535                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1536 }
1537
1538 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1539 {
1540         u32 rst_flags;
1541         u32 tmpReg;
1542
1543         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1544                   AR_RTC_FORCE_WAKE_ON_INT);
1545
1546         if (AR_SREV_9100(ah)) {
1547                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1548                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1549         } else {
1550                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1551                 if (tmpReg &
1552                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1553                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1554                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1555                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1556                 } else {
1557                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1558                 }
1559
1560                 rst_flags = AR_RTC_RC_MAC_WARM;
1561                 if (type == ATH9K_RESET_COLD)
1562                         rst_flags |= AR_RTC_RC_MAC_COLD;
1563         }
1564
1565         REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1566         udelay(50);
1567
1568         REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1569         if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1570                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1571                         "RTC stuck in MAC reset\n");
1572                 return false;
1573         }
1574
1575         if (!AR_SREV_9100(ah))
1576                 REG_WRITE(ah, AR_RC, 0);
1577
1578         ath9k_hw_init_pll(ah, NULL);
1579
1580         if (AR_SREV_9100(ah))
1581                 udelay(50);
1582
1583         return true;
1584 }
1585
1586 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1587 {
1588         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1589                   AR_RTC_FORCE_WAKE_ON_INT);
1590
1591         REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1592         REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1593
1594         if (!ath9k_hw_wait(ah,
1595                            AR_RTC_STATUS,
1596                            AR_RTC_STATUS_M,
1597                            AR_RTC_STATUS_ON)) {
1598                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1599                 return false;
1600         }
1601
1602         ath9k_hw_read_revisions(ah);
1603
1604         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1605 }
1606
1607 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1608 {
1609         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1610                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1611
1612         switch (type) {
1613         case ATH9K_RESET_POWER_ON:
1614                 return ath9k_hw_set_reset_power_on(ah);
1615                 break;
1616         case ATH9K_RESET_WARM:
1617         case ATH9K_RESET_COLD:
1618                 return ath9k_hw_set_reset(ah, type);
1619                 break;
1620         default:
1621                 return false;
1622         }
1623 }
1624
1625 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1626                               enum ath9k_ht_macmode macmode)
1627 {
1628         u32 phymode;
1629         u32 enableDacFifo = 0;
1630         struct ath_hal_5416 *ahp = AH5416(ah);
1631
1632         if (AR_SREV_9285_10_OR_LATER(ah))
1633                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1634                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1635
1636         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1637                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1638
1639         if (IS_CHAN_HT40(chan)) {
1640                 phymode |= AR_PHY_FC_DYN2040_EN;
1641
1642                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1643                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1644                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1645
1646                 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1647                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1648         }
1649         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1650
1651         ath9k_hw_set11nmac2040(ah, macmode);
1652
1653         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1654         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1655 }
1656
1657 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1658                                 struct ath9k_channel *chan)
1659 {
1660         struct ath_hal_5416 *ahp = AH5416(ah);
1661
1662         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1663                 return false;
1664
1665         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1666                 return false;
1667
1668         ahp->ah_chipFullSleep = false;
1669
1670         ath9k_hw_init_pll(ah, chan);
1671
1672         ath9k_hw_set_rfmode(ah, chan);
1673
1674         return true;
1675 }
1676
1677 static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1678                                                  struct ath9k_channel *chan)
1679 {
1680         if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1681                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1682                         "invalid channel %u/0x%x; not marked as "
1683                         "2GHz or 5GHz\n", chan->channel, chan->channelFlags);
1684                 return NULL;
1685         }
1686
1687         if (!IS_CHAN_OFDM(chan) &&
1688             !IS_CHAN_B(chan) &&
1689             !IS_CHAN_HT20(chan) &&
1690             !IS_CHAN_HT40(chan)) {
1691                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1692                         "invalid channel %u/0x%x; not marked as "
1693                         "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1694                         chan->channel, chan->channelFlags);
1695                 return NULL;
1696         }
1697
1698         return ath9k_regd_check_channel(ah, chan);
1699 }
1700
1701 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1702                                     struct ath9k_channel *chan,
1703                                     enum ath9k_ht_macmode macmode)
1704 {
1705         u32 synthDelay, qnum;
1706
1707         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1708                 if (ath9k_hw_numtxpending(ah, qnum)) {
1709                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1710                                 "Transmit frames pending on queue %d\n", qnum);
1711                         return false;
1712                 }
1713         }
1714
1715         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1716         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1717                            AR_PHY_RFBUS_GRANT_EN)) {
1718                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1719                         "Could not kill baseband RX\n");
1720                 return false;
1721         }
1722
1723         ath9k_hw_set_regs(ah, chan, macmode);
1724
1725         if (AR_SREV_9280_10_OR_LATER(ah)) {
1726                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1727                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1728                                 "failed to set channel\n");
1729                         return false;
1730                 }
1731         } else {
1732                 if (!(ath9k_hw_set_channel(ah, chan))) {
1733                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1734                                 "failed to set channel\n");
1735                         return false;
1736                 }
1737         }
1738
1739         if (ath9k_hw_set_txpower(ah, chan,
1740                                  ath9k_regd_get_ctl(ah, chan),
1741                                  ath9k_regd_get_antenna_allowed(ah, chan),
1742                                  chan->maxRegTxPower * 2,
1743                                  min((u32) MAX_RATE_POWER,
1744                                      (u32) ah->ah_powerLimit)) != 0) {
1745                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1746                         "error init'ing transmit power\n");
1747                 return false;
1748         }
1749
1750         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1751         if (IS_CHAN_B(chan))
1752                 synthDelay = (4 * synthDelay) / 22;
1753         else
1754                 synthDelay /= 10;
1755
1756         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1757
1758         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1759
1760         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1761                 ath9k_hw_set_delta_slope(ah, chan);
1762
1763         if (AR_SREV_9280_10_OR_LATER(ah))
1764                 ath9k_hw_9280_spur_mitigate(ah, chan);
1765         else
1766                 ath9k_hw_spur_mitigate(ah, chan);
1767
1768         if (!chan->oneTimeCalsDone)
1769                 chan->oneTimeCalsDone = true;
1770
1771         return true;
1772 }
1773
1774 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1775 {
1776         int bb_spur = AR_NO_SPUR;
1777         int freq;
1778         int bin, cur_bin;
1779         int bb_spur_off, spur_subchannel_sd;
1780         int spur_freq_sd;
1781         int spur_delta_phase;
1782         int denominator;
1783         int upper, lower, cur_vit_mask;
1784         int tmp, newVal;
1785         int i;
1786         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1787                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1788         };
1789         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1790                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1791         };
1792         int inc[4] = { 0, 100, 0, 0 };
1793         struct chan_centers centers;
1794
1795         int8_t mask_m[123];
1796         int8_t mask_p[123];
1797         int8_t mask_amt;
1798         int tmp_mask;
1799         int cur_bb_spur;
1800         bool is2GHz = IS_CHAN_2GHZ(chan);
1801
1802         memset(&mask_m, 0, sizeof(int8_t) * 123);
1803         memset(&mask_p, 0, sizeof(int8_t) * 123);
1804
1805         ath9k_hw_get_channel_centers(ah, chan, &centers);
1806         freq = centers.synth_center;
1807
1808         ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1809         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1810                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1811
1812                 if (is2GHz)
1813                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1814                 else
1815                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1816
1817                 if (AR_NO_SPUR == cur_bb_spur)
1818                         break;
1819                 cur_bb_spur = cur_bb_spur - freq;
1820
1821                 if (IS_CHAN_HT40(chan)) {
1822                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1823                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1824                                 bb_spur = cur_bb_spur;
1825                                 break;
1826                         }
1827                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1828                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1829                         bb_spur = cur_bb_spur;
1830                         break;
1831                 }
1832         }
1833
1834         if (AR_NO_SPUR == bb_spur) {
1835                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1836                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1837                 return;
1838         } else {
1839                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1840                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1841         }
1842
1843         bin = bb_spur * 320;
1844
1845         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1846
1847         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1848                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1849                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1850                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1851         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1852
1853         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1854                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1855                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1856                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1857                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1858         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1859
1860         if (IS_CHAN_HT40(chan)) {
1861                 if (bb_spur < 0) {
1862                         spur_subchannel_sd = 1;
1863                         bb_spur_off = bb_spur + 10;
1864                 } else {
1865                         spur_subchannel_sd = 0;
1866                         bb_spur_off = bb_spur - 10;
1867                 }
1868         } else {
1869                 spur_subchannel_sd = 0;
1870                 bb_spur_off = bb_spur;
1871         }
1872
1873         if (IS_CHAN_HT40(chan))
1874                 spur_delta_phase =
1875                         ((bb_spur * 262144) /
1876                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1877         else
1878                 spur_delta_phase =
1879                         ((bb_spur * 524288) /
1880                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1881
1882         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1883         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1884
1885         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1886                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1887                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1888         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1889
1890         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1891         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1892
1893         cur_bin = -6000;
1894         upper = bin + 100;
1895         lower = bin - 100;
1896
1897         for (i = 0; i < 4; i++) {
1898                 int pilot_mask = 0;
1899                 int chan_mask = 0;
1900                 int bp = 0;
1901                 for (bp = 0; bp < 30; bp++) {
1902                         if ((cur_bin > lower) && (cur_bin < upper)) {
1903                                 pilot_mask = pilot_mask | 0x1 << bp;
1904                                 chan_mask = chan_mask | 0x1 << bp;
1905                         }
1906                         cur_bin += 100;
1907                 }
1908                 cur_bin += inc[i];
1909                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1910                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1911         }
1912
1913         cur_vit_mask = 6100;
1914         upper = bin + 120;
1915         lower = bin - 120;
1916
1917         for (i = 0; i < 123; i++) {
1918                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1919
1920                         /* workaround for gcc bug #37014 */
1921                         volatile int tmp = abs(cur_vit_mask - bin);
1922
1923                         if (tmp < 75)
1924                                 mask_amt = 1;
1925                         else
1926                                 mask_amt = 0;
1927                         if (cur_vit_mask < 0)
1928                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1929                         else
1930                                 mask_p[cur_vit_mask / 100] = mask_amt;
1931                 }
1932                 cur_vit_mask -= 100;
1933         }
1934
1935         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1936                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1937                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1938                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1939                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1940                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1941                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1942                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1943         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1944         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1945
1946         tmp_mask = (mask_m[31] << 28)
1947                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1948                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1949                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1950                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1951                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1952                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1953                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1954         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1955         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1956
1957         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1958                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1959                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1960                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1961                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1962                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1963                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1964                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1965         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1966         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1967
1968         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1969                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1970                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1971                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1972                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1973                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1974                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1975                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1976         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1977         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1978
1979         tmp_mask = (mask_p[15] << 28)
1980                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1981                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1982                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1983                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1984                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1985                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1986                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1987         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1988         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1989
1990         tmp_mask = (mask_p[30] << 28)
1991                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1992                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1993                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1994                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1995                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1996                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1997                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1998         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1999         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2000
2001         tmp_mask = (mask_p[45] << 28)
2002                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2003                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2004                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2005                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2006                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2007                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2008                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2009         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2010         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2011
2012         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2013                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2014                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2015                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2016                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2017                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2018                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2019                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2020         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2021         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2022 }
2023
2024 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
2025 {
2026         int bb_spur = AR_NO_SPUR;
2027         int bin, cur_bin;
2028         int spur_freq_sd;
2029         int spur_delta_phase;
2030         int denominator;
2031         int upper, lower, cur_vit_mask;
2032         int tmp, new;
2033         int i;
2034         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2035                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2036         };
2037         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2038                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2039         };
2040         int inc[4] = { 0, 100, 0, 0 };
2041
2042         int8_t mask_m[123];
2043         int8_t mask_p[123];
2044         int8_t mask_amt;
2045         int tmp_mask;
2046         int cur_bb_spur;
2047         bool is2GHz = IS_CHAN_2GHZ(chan);
2048
2049         memset(&mask_m, 0, sizeof(int8_t) * 123);
2050         memset(&mask_p, 0, sizeof(int8_t) * 123);
2051
2052         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2053                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2054                 if (AR_NO_SPUR == cur_bb_spur)
2055                         break;
2056                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2057                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2058                         bb_spur = cur_bb_spur;
2059                         break;
2060                 }
2061         }
2062
2063         if (AR_NO_SPUR == bb_spur)
2064                 return;
2065
2066         bin = bb_spur * 32;
2067
2068         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2069         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2070                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2071                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2072                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2073
2074         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2075
2076         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2077                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2078                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2079                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2080                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2081         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2082
2083         spur_delta_phase = ((bb_spur * 524288) / 100) &
2084                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2085
2086         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2087         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2088
2089         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2090                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2091                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2092         REG_WRITE(ah, AR_PHY_TIMING11, new);
2093
2094         cur_bin = -6000;
2095         upper = bin + 100;
2096         lower = bin - 100;
2097
2098         for (i = 0; i < 4; i++) {
2099                 int pilot_mask = 0;
2100                 int chan_mask = 0;
2101                 int bp = 0;
2102                 for (bp = 0; bp < 30; bp++) {
2103                         if ((cur_bin > lower) && (cur_bin < upper)) {
2104                                 pilot_mask = pilot_mask | 0x1 << bp;
2105                                 chan_mask = chan_mask | 0x1 << bp;
2106                         }
2107                         cur_bin += 100;
2108                 }
2109                 cur_bin += inc[i];
2110                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2111                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2112         }
2113
2114         cur_vit_mask = 6100;
2115         upper = bin + 120;
2116         lower = bin - 120;
2117
2118         for (i = 0; i < 123; i++) {
2119                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2120
2121                         /* workaround for gcc bug #37014 */
2122                         volatile int tmp = abs(cur_vit_mask - bin);
2123
2124                         if (tmp < 75)
2125                                 mask_amt = 1;
2126                         else
2127                                 mask_amt = 0;
2128                         if (cur_vit_mask < 0)
2129                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2130                         else
2131                                 mask_p[cur_vit_mask / 100] = mask_amt;
2132                 }
2133                 cur_vit_mask -= 100;
2134         }
2135
2136         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2137                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2138                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2139                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2140                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2141                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2142                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2143                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2144         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2145         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2146
2147         tmp_mask = (mask_m[31] << 28)
2148                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2149                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2150                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2151                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2152                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2153                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2154                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2155         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2156         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2157
2158         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2159                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2160                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2161                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2162                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2163                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2164                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2165                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2166         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2167         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2168
2169         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2170                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2171                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2172                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2173                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2174                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2175                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2176                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2177         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2178         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2179
2180         tmp_mask = (mask_p[15] << 28)
2181                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2182                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2183                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2184                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2185                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2186                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2187                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2188         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2189         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2190
2191         tmp_mask = (mask_p[30] << 28)
2192                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2193                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2194                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2195                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2196                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2197                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2198                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2199         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2200         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2201
2202         tmp_mask = (mask_p[45] << 28)
2203                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2204                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2205                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2206                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2207                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2208                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2209                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2210         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2211         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2212
2213         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2214                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2215                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2216                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2217                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2218                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2219                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2220                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2221         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2222         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2223 }
2224
2225 bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2226                     enum ath9k_ht_macmode macmode,
2227                     u8 txchainmask, u8 rxchainmask,
2228                     enum ath9k_ht_extprotspacing extprotspacing,
2229                     bool bChannelChange, int *status)
2230 {
2231         u32 saveLedState;
2232         struct ath_hal_5416 *ahp = AH5416(ah);
2233         struct ath9k_channel *curchan = ah->ah_curchan;
2234         u32 saveDefAntenna;
2235         u32 macStaId1;
2236         int ecode;
2237         int i, rx_chainmask;
2238
2239         ahp->ah_extprotspacing = extprotspacing;
2240         ahp->ah_txchainmask = txchainmask;
2241         ahp->ah_rxchainmask = rxchainmask;
2242
2243         if (AR_SREV_9280(ah)) {
2244                 ahp->ah_txchainmask &= 0x3;
2245                 ahp->ah_rxchainmask &= 0x3;
2246         }
2247
2248         if (ath9k_hw_check_chan(ah, chan) == NULL) {
2249                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2250                         "invalid channel %u/0x%x; no mapping\n",
2251                         chan->channel, chan->channelFlags);
2252                 ecode = -EINVAL;
2253                 goto bad;
2254         }
2255
2256         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
2257                 ecode = -EIO;
2258                 goto bad;
2259         }
2260
2261         if (curchan)
2262                 ath9k_hw_getnf(ah, curchan);
2263
2264         if (bChannelChange &&
2265             (ahp->ah_chipFullSleep != true) &&
2266             (ah->ah_curchan != NULL) &&
2267             (chan->channel != ah->ah_curchan->channel) &&
2268             ((chan->channelFlags & CHANNEL_ALL) ==
2269              (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2270             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2271                                    !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2272
2273                 if (ath9k_hw_channel_change(ah, chan, macmode)) {
2274                         ath9k_hw_loadnf(ah, ah->ah_curchan);
2275                         ath9k_hw_start_nfcal(ah);
2276                         return true;
2277                 }
2278         }
2279
2280         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2281         if (saveDefAntenna == 0)
2282                 saveDefAntenna = 1;
2283
2284         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2285
2286         saveLedState = REG_READ(ah, AR_CFG_LED) &
2287                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2288                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2289
2290         ath9k_hw_mark_phy_inactive(ah);
2291
2292         if (!ath9k_hw_chip_reset(ah, chan)) {
2293                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2294                 ecode = -EINVAL;
2295                 goto bad;
2296         }
2297
2298         if (AR_SREV_9280(ah)) {
2299                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2300                             AR_GPIO_JTAG_DISABLE);
2301
2302                 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2303                         if (IS_CHAN_5GHZ(chan))
2304                                 ath9k_hw_set_gpio(ah, 9, 0);
2305                         else
2306                                 ath9k_hw_set_gpio(ah, 9, 1);
2307                 }
2308                 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2309         }
2310
2311         ecode = ath9k_hw_process_ini(ah, chan, macmode);
2312         if (ecode != 0) {
2313                 ecode = -EINVAL;
2314                 goto bad;
2315         }
2316
2317         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2318                 ath9k_hw_set_delta_slope(ah, chan);
2319
2320         if (AR_SREV_9280_10_OR_LATER(ah))
2321                 ath9k_hw_9280_spur_mitigate(ah, chan);
2322         else
2323                 ath9k_hw_spur_mitigate(ah, chan);
2324
2325         if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2326                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2327                         "error setting board options\n");
2328                 ecode = -EIO;
2329                 goto bad;
2330         }
2331
2332         ath9k_hw_decrease_chain_power(ah, chan);
2333
2334         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2335         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2336                   | macStaId1
2337                   | AR_STA_ID1_RTS_USE_DEF
2338                   | (ah->ah_config.
2339                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2340                   | ahp->ah_staId1Defaults);
2341         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2342
2343         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2344         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2345
2346         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2347
2348         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2349         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2350                   ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2351
2352         REG_WRITE(ah, AR_ISR, ~0);
2353
2354         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2355
2356         if (AR_SREV_9280_10_OR_LATER(ah)) {
2357                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
2358                         ecode = -EIO;
2359                         goto bad;
2360                 }
2361         } else {
2362                 if (!(ath9k_hw_set_channel(ah, chan))) {
2363                         ecode = -EIO;
2364                         goto bad;
2365                 }
2366         }
2367
2368         for (i = 0; i < AR_NUM_DCU; i++)
2369                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2370
2371         ahp->ah_intrTxqs = 0;
2372         for (i = 0; i < ah->ah_caps.total_queues; i++)
2373                 ath9k_hw_resettxqueue(ah, i);
2374
2375         ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2376         ath9k_hw_init_qos(ah);
2377
2378 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2379         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2380                 ath9k_enable_rfkill(ah);
2381 #endif
2382         ath9k_hw_init_user_settings(ah);
2383
2384         REG_WRITE(ah, AR_STA_ID1,
2385                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2386
2387         ath9k_hw_set_dma(ah);
2388
2389         REG_WRITE(ah, AR_OBS, 8);
2390
2391         if (ahp->ah_intrMitigation) {
2392
2393                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2394                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2395         }
2396
2397         ath9k_hw_init_bb(ah, chan);
2398
2399         if (!ath9k_hw_init_cal(ah, chan)){
2400                 ecode = -EIO;;
2401                 goto bad;
2402         }
2403
2404         rx_chainmask = ahp->ah_rxchainmask;
2405         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2406                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2407                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2408         }
2409
2410         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2411
2412         if (AR_SREV_9100(ah)) {
2413                 u32 mask;
2414                 mask = REG_READ(ah, AR_CFG);
2415                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2416                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2417                                 "CFG Byte Swap Set 0x%x\n", mask);
2418                 } else {
2419                         mask =
2420                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2421                         REG_WRITE(ah, AR_CFG, mask);
2422                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2423                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2424                 }
2425         } else {
2426 #ifdef __BIG_ENDIAN
2427                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2428 #endif
2429         }
2430
2431         return true;
2432 bad:
2433         if (status)
2434                 *status = ecode;
2435         return false;
2436 }
2437
2438 /************************/
2439 /* Key Cache Management */
2440 /************************/
2441
2442 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2443 {
2444         u32 keyType;
2445
2446         if (entry >= ah->ah_caps.keycache_size) {
2447                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2448                         "entry %u out of range\n", entry);
2449                 return false;
2450         }
2451
2452         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2453
2454         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2455         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2456         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2457         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2458         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2459         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2460         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2461         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2462
2463         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2464                 u16 micentry = entry + 64;
2465
2466                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2467                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2468                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2469                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2470
2471         }
2472
2473         if (ah->ah_curchan == NULL)
2474                 return true;
2475
2476         return true;
2477 }
2478
2479 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2480 {
2481         u32 macHi, macLo;
2482
2483         if (entry >= ah->ah_caps.keycache_size) {
2484                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2485                         "entry %u out of range\n", entry);
2486                 return false;
2487         }
2488
2489         if (mac != NULL) {
2490                 macHi = (mac[5] << 8) | mac[4];
2491                 macLo = (mac[3] << 24) |
2492                         (mac[2] << 16) |
2493                         (mac[1] << 8) |
2494                         mac[0];
2495                 macLo >>= 1;
2496                 macLo |= (macHi & 1) << 31;
2497                 macHi >>= 1;
2498         } else {
2499                 macLo = macHi = 0;
2500         }
2501         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2502         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2503
2504         return true;
2505 }
2506
2507 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2508                                  const struct ath9k_keyval *k,
2509                                  const u8 *mac, int xorKey)
2510 {
2511         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2512         u32 key0, key1, key2, key3, key4;
2513         u32 keyType;
2514         u32 xorMask = xorKey ?
2515                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2516                  | ATH9K_KEY_XOR) : 0;
2517         struct ath_hal_5416 *ahp = AH5416(ah);
2518
2519         if (entry >= pCap->keycache_size) {
2520                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2521                         "entry %u out of range\n", entry);
2522                 return false;
2523         }
2524
2525         switch (k->kv_type) {
2526         case ATH9K_CIPHER_AES_OCB:
2527                 keyType = AR_KEYTABLE_TYPE_AES;
2528                 break;
2529         case ATH9K_CIPHER_AES_CCM:
2530                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2531                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2532                                 "AES-CCM not supported by mac rev 0x%x\n",
2533                                 ah->ah_macRev);
2534                         return false;
2535                 }
2536                 keyType = AR_KEYTABLE_TYPE_CCM;
2537                 break;
2538         case ATH9K_CIPHER_TKIP:
2539                 keyType = AR_KEYTABLE_TYPE_TKIP;
2540                 if (ATH9K_IS_MIC_ENABLED(ah)
2541                     && entry + 64 >= pCap->keycache_size) {
2542                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2543                                 "entry %u inappropriate for TKIP\n", entry);
2544                         return false;
2545                 }
2546                 break;
2547         case ATH9K_CIPHER_WEP:
2548                 if (k->kv_len < LEN_WEP40) {
2549                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2550                                 "WEP key length %u too small\n", k->kv_len);
2551                         return false;
2552                 }
2553                 if (k->kv_len <= LEN_WEP40)
2554                         keyType = AR_KEYTABLE_TYPE_40;
2555                 else if (k->kv_len <= LEN_WEP104)
2556                         keyType = AR_KEYTABLE_TYPE_104;
2557                 else
2558                         keyType = AR_KEYTABLE_TYPE_128;
2559                 break;
2560         case ATH9K_CIPHER_CLR:
2561                 keyType = AR_KEYTABLE_TYPE_CLR;
2562                 break;
2563         default:
2564                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2565                         "cipher %u not supported\n", k->kv_type);
2566                 return false;
2567         }
2568
2569         key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2570         key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2571         key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2572         key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2573         key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2574         if (k->kv_len <= LEN_WEP104)
2575                 key4 &= 0xff;
2576
2577         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2578                 u16 micentry = entry + 64;
2579
2580                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2581                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2582                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2583                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2584                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2585                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2586                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2587
2588                 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2589                         u32 mic0, mic1, mic2, mic3, mic4;
2590
2591                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2592                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2593                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2594                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2595                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2596                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2597                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2598                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2599                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2600                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2601                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2602                                   AR_KEYTABLE_TYPE_CLR);
2603
2604                 } else {
2605                         u32 mic0, mic2;
2606
2607                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2608                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2609                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2610                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2611                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2612                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2613                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2614                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2615                                   AR_KEYTABLE_TYPE_CLR);
2616                 }
2617                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2618                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2619                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2620                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2621         } else {
2622                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2623                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2624                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2625                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2626                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2627                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2628
2629                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2630         }
2631
2632         if (ah->ah_curchan == NULL)
2633                 return true;
2634
2635         return true;
2636 }
2637
2638 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2639 {
2640         if (entry < ah->ah_caps.keycache_size) {
2641                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2642                 if (val & AR_KEYTABLE_VALID)
2643                         return true;
2644         }
2645         return false;
2646 }
2647
2648 /******************************/
2649 /* Power Management (Chipset) */
2650 /******************************/
2651
2652 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2653 {
2654         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2655         if (setChip) {
2656                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2657                             AR_RTC_FORCE_WAKE_EN);
2658                 if (!AR_SREV_9100(ah))
2659                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2660
2661                 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2662                             AR_RTC_RESET_EN);
2663         }
2664 }
2665
2666 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2667 {
2668         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2669         if (setChip) {
2670                 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2671
2672                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2673                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2674                                   AR_RTC_FORCE_WAKE_ON_INT);
2675                 } else {
2676                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2677                                     AR_RTC_FORCE_WAKE_EN);
2678                 }
2679         }
2680 }
2681
2682 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2683                                      int setChip)
2684 {
2685         u32 val;
2686         int i;
2687
2688         if (setChip) {
2689                 if ((REG_READ(ah, AR_RTC_STATUS) &
2690                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2691                         if (ath9k_hw_set_reset_reg(ah,
2692                                            ATH9K_RESET_POWER_ON) != true) {
2693                                 return false;
2694                         }
2695                 }
2696                 if (AR_SREV_9100(ah))
2697                         REG_SET_BIT(ah, AR_RTC_RESET,
2698                                     AR_RTC_RESET_EN);
2699
2700                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2701                             AR_RTC_FORCE_WAKE_EN);
2702                 udelay(50);
2703
2704                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2705                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2706                         if (val == AR_RTC_STATUS_ON)
2707                                 break;
2708                         udelay(50);
2709                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2710                                     AR_RTC_FORCE_WAKE_EN);
2711                 }
2712                 if (i == 0) {
2713                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2714                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2715                         return false;
2716                 }
2717         }
2718
2719         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2720
2721         return true;
2722 }
2723
2724 bool ath9k_hw_setpower(struct ath_hal *ah,
2725                        enum ath9k_power_mode mode)
2726 {
2727         struct ath_hal_5416 *ahp = AH5416(ah);
2728         static const char *modes[] = {
2729                 "AWAKE",
2730                 "FULL-SLEEP",
2731                 "NETWORK SLEEP",
2732                 "UNDEFINED"
2733         };
2734         int status = true, setChip = true;
2735
2736         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2737                 modes[ahp->ah_powerMode], modes[mode],
2738                 setChip ? "set chip " : "");
2739
2740         switch (mode) {
2741         case ATH9K_PM_AWAKE:
2742                 status = ath9k_hw_set_power_awake(ah, setChip);
2743                 break;
2744         case ATH9K_PM_FULL_SLEEP:
2745                 ath9k_set_power_sleep(ah, setChip);
2746                 ahp->ah_chipFullSleep = true;
2747                 break;
2748         case ATH9K_PM_NETWORK_SLEEP:
2749                 ath9k_set_power_network_sleep(ah, setChip);
2750                 break;
2751         default:
2752                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2753                         "Unknown power mode %u\n", mode);
2754                 return false;
2755         }
2756         ahp->ah_powerMode = mode;
2757
2758         return status;
2759 }
2760
2761 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2762 {
2763         struct ath_hal_5416 *ahp = AH5416(ah);
2764         u8 i;
2765
2766         if (ah->ah_isPciExpress != true)
2767                 return;
2768
2769         if (ah->ah_config.pcie_powersave_enable == 2)
2770                 return;
2771
2772         if (restore)
2773                 return;
2774
2775         if (AR_SREV_9280_20_OR_LATER(ah)) {
2776                 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2777                         REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2778                                   INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2779                 }
2780                 udelay(1000);
2781         } else if (AR_SREV_9280(ah) &&
2782                    (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2783                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2784                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2785
2786                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2787                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2788                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2789
2790                 if (ah->ah_config.pcie_clock_req)
2791                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2792                 else
2793                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2794
2795                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2796                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2797                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2798
2799                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2800
2801                 udelay(1000);
2802         } else {
2803                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2804                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2805                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2806                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2807                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2808                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2809                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2810                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2811                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2812                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2813         }
2814
2815         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2816
2817         if (ah->ah_config.pcie_waen) {
2818                 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2819         } else {
2820                 if (AR_SREV_9285(ah))
2821                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2822                 else if (AR_SREV_9280(ah))
2823                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2824                 else
2825                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2826         }
2827
2828 }
2829
2830 /**********************/
2831 /* Interrupt Handling */
2832 /**********************/
2833
2834 bool ath9k_hw_intrpend(struct ath_hal *ah)
2835 {
2836         u32 host_isr;
2837
2838         if (AR_SREV_9100(ah))
2839                 return true;
2840
2841         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2842         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2843                 return true;
2844
2845         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2846         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2847             && (host_isr != AR_INTR_SPURIOUS))
2848                 return true;
2849
2850         return false;
2851 }
2852
2853 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2854 {
2855         u32 isr = 0;
2856         u32 mask2 = 0;
2857         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2858         u32 sync_cause = 0;
2859         bool fatal_int = false;
2860         struct ath_hal_5416 *ahp = AH5416(ah);
2861
2862         if (!AR_SREV_9100(ah)) {
2863                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2864                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2865                             == AR_RTC_STATUS_ON) {
2866                                 isr = REG_READ(ah, AR_ISR);
2867                         }
2868                 }
2869
2870                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2871                         AR_INTR_SYNC_DEFAULT;
2872
2873                 *masked = 0;
2874
2875                 if (!isr && !sync_cause)
2876                         return false;
2877         } else {
2878                 *masked = 0;
2879                 isr = REG_READ(ah, AR_ISR);
2880         }
2881
2882         if (isr) {
2883                 if (isr & AR_ISR_BCNMISC) {
2884                         u32 isr2;
2885                         isr2 = REG_READ(ah, AR_ISR_S2);
2886                         if (isr2 & AR_ISR_S2_TIM)
2887                                 mask2 |= ATH9K_INT_TIM;
2888                         if (isr2 & AR_ISR_S2_DTIM)
2889                                 mask2 |= ATH9K_INT_DTIM;
2890                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2891                                 mask2 |= ATH9K_INT_DTIMSYNC;
2892                         if (isr2 & (AR_ISR_S2_CABEND))
2893                                 mask2 |= ATH9K_INT_CABEND;
2894                         if (isr2 & AR_ISR_S2_GTT)
2895                                 mask2 |= ATH9K_INT_GTT;
2896                         if (isr2 & AR_ISR_S2_CST)
2897                                 mask2 |= ATH9K_INT_CST;
2898                 }
2899
2900                 isr = REG_READ(ah, AR_ISR_RAC);
2901                 if (isr == 0xffffffff) {
2902                         *masked = 0;
2903                         return false;
2904                 }
2905
2906                 *masked = isr & ATH9K_INT_COMMON;
2907
2908                 if (ahp->ah_intrMitigation) {
2909                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2910                                 *masked |= ATH9K_INT_RX;
2911                 }
2912
2913                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2914                         *masked |= ATH9K_INT_RX;
2915                 if (isr &
2916                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2917                      AR_ISR_TXEOL)) {
2918                         u32 s0_s, s1_s;
2919
2920                         *masked |= ATH9K_INT_TX;
2921
2922                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2923                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2924                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2925
2926                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2927                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2928                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2929                 }
2930
2931                 if (isr & AR_ISR_RXORN) {
2932                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2933                                 "receive FIFO overrun interrupt\n");
2934                 }
2935
2936                 if (!AR_SREV_9100(ah)) {
2937                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2938                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2939                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2940                                         *masked |= ATH9K_INT_TIM_TIMER;
2941                         }
2942                 }
2943
2944                 *masked |= mask2;
2945         }
2946
2947         if (AR_SREV_9100(ah))
2948                 return true;
2949
2950         if (sync_cause) {
2951                 fatal_int =
2952                         (sync_cause &
2953                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2954                         ? true : false;
2955
2956                 if (fatal_int) {
2957                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2958                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2959                                         "received PCI FATAL interrupt\n");
2960                         }
2961                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2962                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2963                                         "received PCI PERR interrupt\n");
2964                         }
2965                 }
2966                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2967                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2968                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2969                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2970                         REG_WRITE(ah, AR_RC, 0);
2971                         *masked |= ATH9K_INT_FATAL;
2972                 }
2973                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2974                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2975                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2976                 }
2977
2978                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2979                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2980         }
2981
2982         return true;
2983 }
2984
2985 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2986 {
2987         return AH5416(ah)->ah_maskReg;
2988 }
2989
2990 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2991 {
2992         struct ath_hal_5416 *ahp = AH5416(ah);
2993         u32 omask = ahp->ah_maskReg;
2994         u32 mask, mask2;
2995         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2996
2997         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2998
2999         if (omask & ATH9K_INT_GLOBAL) {
3000                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3001                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3002                 (void) REG_READ(ah, AR_IER);
3003                 if (!AR_SREV_9100(ah)) {
3004                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3005                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3006
3007                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3008                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3009                 }
3010         }
3011
3012         mask = ints & ATH9K_INT_COMMON;
3013         mask2 = 0;
3014
3015         if (ints & ATH9K_INT_TX) {
3016                 if (ahp->ah_txOkInterruptMask)
3017                         mask |= AR_IMR_TXOK;
3018                 if (ahp->ah_txDescInterruptMask)
3019                         mask |= AR_IMR_TXDESC;
3020                 if (ahp->ah_txErrInterruptMask)
3021                         mask |= AR_IMR_TXERR;
3022                 if (ahp->ah_txEolInterruptMask)
3023                         mask |= AR_IMR_TXEOL;
3024         }
3025         if (ints & ATH9K_INT_RX) {
3026                 mask |= AR_IMR_RXERR;
3027                 if (ahp->ah_intrMitigation)
3028                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3029                 else
3030                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3031                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3032                         mask |= AR_IMR_GENTMR;
3033         }
3034
3035         if (ints & (ATH9K_INT_BMISC)) {
3036                 mask |= AR_IMR_BCNMISC;
3037                 if (ints & ATH9K_INT_TIM)
3038                         mask2 |= AR_IMR_S2_TIM;
3039                 if (ints & ATH9K_INT_DTIM)
3040                         mask2 |= AR_IMR_S2_DTIM;
3041                 if (ints & ATH9K_INT_DTIMSYNC)
3042                         mask2 |= AR_IMR_S2_DTIMSYNC;
3043                 if (ints & ATH9K_INT_CABEND)
3044                         mask2 |= (AR_IMR_S2_CABEND);
3045         }
3046
3047         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3048                 mask |= AR_IMR_BCNMISC;
3049                 if (ints & ATH9K_INT_GTT)
3050                         mask2 |= AR_IMR_S2_GTT;
3051                 if (ints & ATH9K_INT_CST)
3052                         mask2 |= AR_IMR_S2_CST;
3053         }
3054
3055         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3056         REG_WRITE(ah, AR_IMR, mask);
3057         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3058                                            AR_IMR_S2_DTIM |
3059                                            AR_IMR_S2_DTIMSYNC |
3060                                            AR_IMR_S2_CABEND |
3061                                            AR_IMR_S2_CABTO |
3062                                            AR_IMR_S2_TSFOOR |
3063                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3064         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3065         ahp->ah_maskReg = ints;
3066
3067         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3068                 if (ints & ATH9K_INT_TIM_TIMER)
3069                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3070                 else
3071                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3072         }
3073
3074         if (ints & ATH9K_INT_GLOBAL) {
3075                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3076                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3077                 if (!AR_SREV_9100(ah)) {
3078                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3079                                   AR_INTR_MAC_IRQ);
3080                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3081
3082
3083                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3084                                   AR_INTR_SYNC_DEFAULT);
3085                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3086                                   AR_INTR_SYNC_DEFAULT);
3087                 }
3088                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3089                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3090         }
3091
3092         return omask;
3093 }
3094
3095 /*******************/
3096 /* Beacon Handling */
3097 /*******************/
3098
3099 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3100 {
3101         struct ath_hal_5416 *ahp = AH5416(ah);
3102         int flags = 0;
3103
3104         ahp->ah_beaconInterval = beacon_period;
3105
3106         switch (ah->ah_opmode) {
3107         case NL80211_IFTYPE_STATION:
3108         case NL80211_IFTYPE_MONITOR:
3109                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3110                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3111                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3112                 flags |= AR_TBTT_TIMER_EN;
3113                 break;
3114         case NL80211_IFTYPE_ADHOC:
3115                 REG_SET_BIT(ah, AR_TXCFG,
3116                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3117                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3118                           TU_TO_USEC(next_beacon +
3119                                      (ahp->ah_atimWindow ? ahp->
3120                                       ah_atimWindow : 1)));
3121                 flags |= AR_NDP_TIMER_EN;
3122         case NL80211_IFTYPE_AP:
3123                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3124                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3125                           TU_TO_USEC(next_beacon -
3126                                      ah->ah_config.
3127                                      dma_beacon_response_time));
3128                 REG_WRITE(ah, AR_NEXT_SWBA,
3129                           TU_TO_USEC(next_beacon -
3130                                      ah->ah_config.
3131                                      sw_beacon_response_time));
3132                 flags |=
3133                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3134                 break;
3135         default:
3136                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3137                         "%s: unsupported opmode: %d\n",
3138                         __func__, ah->ah_opmode);
3139                 return;
3140                 break;
3141         }
3142
3143         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3144         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3145         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3146         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3147
3148         beacon_period &= ~ATH9K_BEACON_ENA;
3149         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3150                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3151                 ath9k_hw_reset_tsf(ah);
3152         }
3153
3154         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3155 }
3156
3157 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3158                                     const struct ath9k_beacon_state *bs)
3159 {
3160         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3161         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3162
3163         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3164
3165         REG_WRITE(ah, AR_BEACON_PERIOD,
3166                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3167         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3168                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3169
3170         REG_RMW_FIELD(ah, AR_RSSI_THR,
3171                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3172
3173         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3174
3175         if (bs->bs_sleepduration > beaconintval)
3176                 beaconintval = bs->bs_sleepduration;
3177
3178         dtimperiod = bs->bs_dtimperiod;
3179         if (bs->bs_sleepduration > dtimperiod)
3180                 dtimperiod = bs->bs_sleepduration;
3181
3182         if (beaconintval == dtimperiod)
3183                 nextTbtt = bs->bs_nextdtim;
3184         else
3185                 nextTbtt = bs->bs_nexttbtt;
3186
3187         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3188         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3189         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3190         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3191
3192         REG_WRITE(ah, AR_NEXT_DTIM,
3193                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3194         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3195
3196         REG_WRITE(ah, AR_SLEEP1,
3197                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3198                   | AR_SLEEP1_ASSUME_DTIM);
3199
3200         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3201                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3202         else
3203                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3204
3205         REG_WRITE(ah, AR_SLEEP2,
3206                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3207
3208         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3209         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3210
3211         REG_SET_BIT(ah, AR_TIMER_MODE,
3212                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3213                     AR_DTIM_TIMER_EN);
3214
3215 }
3216
3217 /*******************/
3218 /* HW Capabilities */
3219 /*******************/
3220
3221 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3222 {
3223         struct ath_hal_5416 *ahp = AH5416(ah);
3224         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3225         u16 capField = 0, eeval;
3226
3227         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3228
3229         ah->ah_currentRD = eeval;
3230
3231         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3232         ah->ah_currentRDExt = eeval;
3233
3234         capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3235
3236         if (ah->ah_opmode != NL80211_IFTYPE_AP &&
3237             ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3238                 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3239                         ah->ah_currentRD += 5;
3240                 else if (ah->ah_currentRD == 0x41)
3241                         ah->ah_currentRD = 0x43;
3242                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3243                         "regdomain mapped to 0x%x\n", ah->ah_currentRD);
3244         }
3245
3246         eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3247         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3248
3249         if (eeval & AR5416_OPFLAGS_11A) {
3250                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3251                 if (ah->ah_config.ht_enable) {
3252                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3253                                 set_bit(ATH9K_MODE_11NA_HT20,
3254                                         pCap->wireless_modes);
3255                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3256                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3257                                         pCap->wireless_modes);
3258                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3259                                         pCap->wireless_modes);
3260                         }
3261                 }
3262         }
3263
3264         if (eeval & AR5416_OPFLAGS_11G) {
3265                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3266                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3267                 if (ah->ah_config.ht_enable) {
3268                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3269                                 set_bit(ATH9K_MODE_11NG_HT20,
3270                                         pCap->wireless_modes);
3271                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3272                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3273                                         pCap->wireless_modes);
3274                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3275                                         pCap->wireless_modes);
3276                         }
3277                 }
3278         }
3279
3280         pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3281         if ((ah->ah_isPciExpress)
3282             || (eeval & AR5416_OPFLAGS_11A)) {
3283                 pCap->rx_chainmask =
3284                         ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3285         } else {
3286                 pCap->rx_chainmask =
3287                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3288         }
3289
3290         if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3291                 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3292
3293         pCap->low_2ghz_chan = 2312;
3294         pCap->high_2ghz_chan = 2732;
3295
3296         pCap->low_5ghz_chan = 4920;
3297         pCap->high_5ghz_chan = 6100;
3298
3299         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3300         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3301         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3302
3303         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3304         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3305         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3306
3307         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3308
3309         if (ah->ah_config.ht_enable)
3310                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3311         else
3312                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3313
3314         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3315         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3316         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3317         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3318
3319         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3320                 pCap->total_queues =
3321                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3322         else
3323                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3324
3325         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3326                 pCap->keycache_size =
3327                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3328         else
3329                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3330
3331         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3332         pCap->num_mr_retries = 4;
3333         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3334
3335         if (AR_SREV_9280_10_OR_LATER(ah))
3336                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3337         else
3338                 pCap->num_gpio_pins = AR_NUM_GPIO;
3339
3340         if (AR_SREV_9280_10_OR_LATER(ah)) {
3341                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3342                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3343         } else {
3344                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3345                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3346         }
3347
3348         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3349                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3350                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3351         } else {
3352                 pCap->rts_aggr_limit = (8 * 1024);
3353         }
3354
3355         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3356
3357 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3358         ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3359         if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3360                 ah->ah_rfkill_gpio =
3361                         MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3362                 ah->ah_rfkill_polarity =
3363                         MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3364
3365                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3366         }
3367 #endif
3368
3369         if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3370             (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3371             (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3372             (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3373             (ah->ah_macVersion == AR_SREV_VERSION_9280))
3374                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3375         else
3376                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3377
3378         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3379                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3380         else
3381                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3382
3383         if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3384                 pCap->reg_cap =
3385                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3386                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3387                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3388                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3389         } else {
3390                 pCap->reg_cap =
3391                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3392                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3393         }
3394
3395         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3396
3397         pCap->num_antcfg_5ghz =
3398                 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3399         pCap->num_antcfg_2ghz =
3400                 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3401
3402         return true;
3403 }
3404
3405 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3406                             u32 capability, u32 *result)
3407 {
3408         struct ath_hal_5416 *ahp = AH5416(ah);
3409         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3410
3411         switch (type) {
3412         case ATH9K_CAP_CIPHER:
3413                 switch (capability) {
3414                 case ATH9K_CIPHER_AES_CCM:
3415                 case ATH9K_CIPHER_AES_OCB:
3416                 case ATH9K_CIPHER_TKIP:
3417                 case ATH9K_CIPHER_WEP:
3418                 case ATH9K_CIPHER_MIC:
3419                 case ATH9K_CIPHER_CLR:
3420                         return true;
3421                 default:
3422                         return false;
3423                 }
3424         case ATH9K_CAP_TKIP_MIC:
3425                 switch (capability) {
3426                 case 0:
3427                         return true;
3428                 case 1:
3429                         return (ahp->ah_staId1Defaults &
3430                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3431                         false;
3432                 }
3433         case ATH9K_CAP_TKIP_SPLIT:
3434                 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3435                         false : true;
3436         case ATH9K_CAP_WME_TKIPMIC:
3437                 return 0;
3438         case ATH9K_CAP_PHYCOUNTERS:
3439                 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3440         case ATH9K_CAP_DIVERSITY:
3441                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3442                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3443                         true : false;
3444         case ATH9K_CAP_PHYDIAG:
3445                 return true;
3446         case ATH9K_CAP_MCAST_KEYSRCH:
3447                 switch (capability) {
3448                 case 0:
3449                         return true;
3450                 case 1:
3451                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3452                                 return false;
3453                         } else {
3454                                 return (ahp->ah_staId1Defaults &
3455                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3456                                         false;
3457                         }
3458                 }
3459                 return false;
3460         case ATH9K_CAP_TSF_ADJUST:
3461                 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3462                         true : false;
3463         case ATH9K_CAP_RFSILENT:
3464                 if (capability == 3)
3465                         return false;
3466         case ATH9K_CAP_ANT_CFG_2GHZ:
3467                 *result = pCap->num_antcfg_2ghz;
3468                 return true;
3469         case ATH9K_CAP_ANT_CFG_5GHZ:
3470                 *result = pCap->num_antcfg_5ghz;
3471                 return true;
3472         case ATH9K_CAP_TXPOW:
3473                 switch (capability) {
3474                 case 0:
3475                         return 0;
3476                 case 1:
3477                         *result = ah->ah_powerLimit;
3478                         return 0;
3479                 case 2:
3480                         *result = ah->ah_maxPowerLevel;
3481                         return 0;
3482                 case 3:
3483                         *result = ah->ah_tpScale;
3484                         return 0;
3485                 }
3486                 return false;
3487         default:
3488                 return false;
3489         }
3490 }
3491
3492 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3493                             u32 capability, u32 setting, int *status)
3494 {
3495         struct ath_hal_5416 *ahp = AH5416(ah);
3496         u32 v;
3497
3498         switch (type) {
3499         case ATH9K_CAP_TKIP_MIC:
3500                 if (setting)
3501                         ahp->ah_staId1Defaults |=
3502                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3503                 else
3504                         ahp->ah_staId1Defaults &=
3505                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3506                 return true;
3507         case ATH9K_CAP_DIVERSITY:
3508                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3509                 if (setting)
3510                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3511                 else
3512                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3513                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3514                 return true;
3515         case ATH9K_CAP_MCAST_KEYSRCH:
3516                 if (setting)
3517                         ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3518                 else
3519                         ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3520                 return true;
3521         case ATH9K_CAP_TSF_ADJUST:
3522                 if (setting)
3523                         ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3524                 else
3525                         ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3526                 return true;
3527         default:
3528                 return false;
3529         }
3530 }
3531
3532 /****************************/
3533 /* GPIO / RFKILL / Antennae */
3534 /****************************/
3535
3536 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3537                                          u32 gpio, u32 type)
3538 {
3539         int addr;
3540         u32 gpio_shift, tmp;
3541
3542         if (gpio > 11)
3543                 addr = AR_GPIO_OUTPUT_MUX3;
3544         else if (gpio > 5)
3545                 addr = AR_GPIO_OUTPUT_MUX2;
3546         else
3547                 addr = AR_GPIO_OUTPUT_MUX1;
3548
3549         gpio_shift = (gpio % 6) * 5;
3550
3551         if (AR_SREV_9280_20_OR_LATER(ah)
3552             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3553                 REG_RMW(ah, addr, (type << gpio_shift),
3554                         (0x1f << gpio_shift));
3555         } else {
3556                 tmp = REG_READ(ah, addr);
3557                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3558                 tmp &= ~(0x1f << gpio_shift);
3559                 tmp |= (type << gpio_shift);
3560                 REG_WRITE(ah, addr, tmp);
3561         }
3562 }
3563
3564 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3565 {
3566         u32 gpio_shift;
3567
3568         ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3569
3570         gpio_shift = gpio << 1;
3571
3572         REG_RMW(ah,
3573                 AR_GPIO_OE_OUT,
3574                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3575                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3576 }
3577
3578 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3579 {
3580         if (gpio >= ah->ah_caps.num_gpio_pins)
3581                 return 0xffffffff;
3582
3583         if (AR_SREV_9280_10_OR_LATER(ah)) {
3584                 return (MS
3585                         (REG_READ(ah, AR_GPIO_IN_OUT),
3586                          AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
3587         } else {
3588                 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
3589                         AR_GPIO_BIT(gpio)) != 0;
3590         }
3591 }
3592
3593 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3594                          u32 ah_signal_type)
3595 {
3596         u32 gpio_shift;
3597
3598         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3599
3600         gpio_shift = 2 * gpio;
3601
3602         REG_RMW(ah,
3603                 AR_GPIO_OE_OUT,
3604                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3605                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3606 }
3607
3608 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3609 {
3610         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3611                 AR_GPIO_BIT(gpio));
3612 }
3613
3614 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3615 void ath9k_enable_rfkill(struct ath_hal *ah)
3616 {
3617         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3618                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3619
3620         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3621                     AR_GPIO_INPUT_MUX2_RFSILENT);
3622
3623         ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3624         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3625 }
3626 #endif
3627
3628 int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
3629 {
3630         struct ath9k_channel *chan = ah->ah_curchan;
3631         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3632         u16 ant_config;
3633         u32 halNumAntConfig;
3634
3635         halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3636                 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
3637
3638         if (cfg < halNumAntConfig) {
3639                 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3640                                                      cfg, &ant_config)) {
3641                         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3642                         return 0;
3643                 }
3644         }
3645
3646         return -EINVAL;
3647 }
3648
3649 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3650 {
3651         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3652 }
3653
3654 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3655 {
3656         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3657 }
3658
3659 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3660                                enum ath9k_ant_setting settings,
3661                                struct ath9k_channel *chan,
3662                                u8 *tx_chainmask,
3663                                u8 *rx_chainmask,
3664                                u8 *antenna_cfgd)
3665 {
3666         struct ath_hal_5416 *ahp = AH5416(ah);
3667         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3668
3669         if (AR_SREV_9280(ah)) {
3670                 if (!tx_chainmask_cfg) {
3671
3672                         tx_chainmask_cfg = *tx_chainmask;
3673                         rx_chainmask_cfg = *rx_chainmask;
3674                 }
3675
3676                 switch (settings) {
3677                 case ATH9K_ANT_FIXED_A:
3678                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3679                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3680                         *antenna_cfgd = true;
3681                         break;
3682                 case ATH9K_ANT_FIXED_B:
3683                         if (ah->ah_caps.tx_chainmask >
3684                             ATH9K_ANTENNA1_CHAINMASK) {
3685                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3686                         }
3687                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3688                         *antenna_cfgd = true;
3689                         break;
3690                 case ATH9K_ANT_VARIABLE:
3691                         *tx_chainmask = tx_chainmask_cfg;
3692                         *rx_chainmask = rx_chainmask_cfg;
3693                         *antenna_cfgd = true;
3694                         break;
3695                 default:
3696                         break;
3697                 }
3698         } else {
3699                 ahp->ah_diversityControl = settings;
3700         }
3701
3702         return true;
3703 }
3704
3705 /*********************/
3706 /* General Operation */
3707 /*********************/
3708
3709 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3710 {
3711         u32 bits = REG_READ(ah, AR_RX_FILTER);
3712         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3713
3714         if (phybits & AR_PHY_ERR_RADAR)
3715                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3716         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3717                 bits |= ATH9K_RX_FILTER_PHYERR;
3718
3719         return bits;
3720 }
3721
3722 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3723 {
3724         u32 phybits;
3725
3726         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3727         phybits = 0;
3728         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3729                 phybits |= AR_PHY_ERR_RADAR;
3730         if (bits & ATH9K_RX_FILTER_PHYERR)
3731                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3732         REG_WRITE(ah, AR_PHY_ERR, phybits);
3733
3734         if (phybits)
3735                 REG_WRITE(ah, AR_RXCFG,
3736                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3737         else
3738                 REG_WRITE(ah, AR_RXCFG,
3739                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3740 }
3741
3742 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3743 {
3744         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3745 }
3746
3747 bool ath9k_hw_disable(struct ath_hal *ah)
3748 {
3749         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3750                 return false;
3751
3752         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3753 }
3754
3755 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3756 {
3757         struct ath9k_channel *chan = ah->ah_curchan;
3758
3759         ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3760
3761         if (ath9k_hw_set_txpower(ah, chan,
3762                                  ath9k_regd_get_ctl(ah, chan),
3763                                  ath9k_regd_get_antenna_allowed(ah, chan),
3764                                  chan->maxRegTxPower * 2,
3765                                  min((u32) MAX_RATE_POWER,
3766                                      (u32) ah->ah_powerLimit)) != 0)
3767                 return false;
3768
3769         return true;
3770 }
3771
3772 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
3773 {
3774         struct ath_hal_5416 *ahp = AH5416(ah);
3775
3776         memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3777 }
3778
3779 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3780 {
3781         struct ath_hal_5416 *ahp = AH5416(ah);
3782
3783         memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3784
3785         return true;
3786 }
3787
3788 void ath9k_hw_setopmode(struct ath_hal *ah)
3789 {
3790         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3791 }
3792
3793 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3794 {
3795         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3796         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3797 }
3798
3799 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
3800 {
3801         struct ath_hal_5416 *ahp = AH5416(ah);
3802
3803         memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3804 }
3805
3806 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
3807 {
3808         struct ath_hal_5416 *ahp = AH5416(ah);
3809
3810         memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
3811
3812         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3813         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3814
3815         return true;
3816 }
3817
3818 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3819 {
3820         struct ath_hal_5416 *ahp = AH5416(ah);
3821
3822         memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3823         ahp->ah_assocId = assocId;
3824
3825         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3826         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3827                   ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3828 }
3829
3830 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3831 {
3832         u64 tsf;
3833
3834         tsf = REG_READ(ah, AR_TSF_U32);
3835         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3836
3837         return tsf;
3838 }
3839
3840 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3841 {
3842         int count;
3843
3844         count = 0;
3845         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3846                 count++;
3847                 if (count > 10) {
3848                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3849                                 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3850                         break;
3851                 }
3852                 udelay(10);
3853         }
3854         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3855 }
3856
3857 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3858 {
3859         struct ath_hal_5416 *ahp = AH5416(ah);
3860
3861         if (setting)
3862                 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3863         else
3864                 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3865
3866         return true;
3867 }
3868
3869 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3870 {
3871         struct ath_hal_5416 *ahp = AH5416(ah);
3872
3873         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3874                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3875                 ahp->ah_slottime = (u32) -1;
3876                 return false;
3877         } else {
3878                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3879                 ahp->ah_slottime = us;
3880                 return true;
3881         }
3882 }
3883
3884 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3885 {
3886         u32 macmode;
3887
3888         if (mode == ATH9K_HT_MACMODE_2040 &&
3889             !ah->ah_config.cwm_ignore_extcca)
3890                 macmode = AR_2040_JOINED_RX_CLEAR;
3891         else
3892                 macmode = 0;
3893
3894         REG_WRITE(ah, AR_2040_MODE, macmode);
3895 }